SRAM (Static Random Access Memory) unit, SRAM circuit and memory
By adding four MOSFETs to a 6T SRAM to form a 10T SRAM, the problems of slow read/write speed and inability to directly copy data are solved, achieving faster data read/write and copy speeds.
Patent Information
- Application Number
- CN202520403494.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-03-07
AI Technical Summary
Traditional 6T SRAM has slow read and write speeds and cannot directly copy data. In the von Neumann architecture, the data transfer time between SRAM and ALU is too long, resulting in slow data copying speed.
By adding four MOSFETs to a 6T SRAM, a 10T SRAM cell is formed. Data can be directly copied by controlling specific signal lines, eliminating the need for the ALU step.
It improves data read and write speed, enables fast data copying, and simplifies the data copying process.
Smart Images
Figure CN223828233U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of memory technology, and in particular to an SRAM cell, an SRAM circuit, and a memory. Background Technology
[0002] like Figure 1 and Figure 2 As shown, traditional memory includes 6T SRAM (6-Transistor Static Random Access Memory) and 8T SRAM (8-Transistor Static Random Access Memory). 6T SRAM and 8T SRAM only have storage and read / write functions. 6T SRAM has a slower read / write speed, while 8T SRAM has a faster read / write speed than 6T SRAM.
[0003] To enable SRAM to perform copying, the SRAM and ALU (Arithmetic Logic Unit) need to form a von Neumann architecture. In a von Neumann architecture, when copying data, the SRAM first reads the data, the ALU copies the read data, and finally, the copied data is stored. Since the SRAM and ALU are relatively separate devices, the time for data transfer between them is often hundreds or thousands of times longer than the ALU's computation time, resulting in a slow data copying speed. Utility Model Content
[0004] This invention provides an SRAM cell, an SRAM circuit, and a memory to solve the technical problems of slow read / write speed and inability to copy data in 6T SRAM.
[0005] To solve the above-mentioned technical problems, this utility model provides an SRAM cell, including 10 MOS transistors, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; M1, M3, M5, M6, M7, M8 and M10 are NMOS, and M2, M4 and M9 are PMOS;
[0006] The gate of M1 is connected to the gate of M2, the source of M4, the drain of M3, and the gate of M10, respectively. The drain of M1 is connected to the source of M8, and the source of M1 and the source of M3 are connected to the first ground terminal, respectively.
[0007] The drains of M2 and M4 are connected to the high level VDD, and the source of M2 is connected to the drain of M9.
[0008] The gate of M3 is connected to the gate of M4, the source of M9, the drain of M8, the drain of M5, and the drain of M7, respectively.
[0009] The gate of M5 is connected to the word line WL, and the source of M5 is connected to the bit line BL.
[0010] The gate of M6 is connected to the read word line RWL, the drain of M6 is connected to the read bit line RBL, and the source of M6 is connected to the drain of M10.
[0011] The gate of M7 is connected to the control signal line CA, and the source of M7 is connected to the terminal CC.
[0012] The gate of M8 is connected to the control signal line CB;
[0013] The gate of M9 is connected to the control signal line CD;
[0014] The source of M10 is connected to the second ground terminal.
[0015] Optionally, the SRAM cell is used to read data, the control signal line CA is used to input a low level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, the read word line RWL is used to input a high level, and the read bit line RBL is precharged to a high level.
[0016] Optionally, the SRAM cell is used for writing data, the control signal line CA is used to input a low level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, the word line WL is used to input a high level, and the bit line BL is precharged to a high level.
[0017] Optionally, the first grounding terminal and the second grounding terminal are the same grounding terminal.
[0018] This utility model also provides an SRAM circuit, including the two SRAM units mentioned above, namely a first unit and a second unit, wherein the terminal CC of the first unit and the terminal CC of the second unit are connected to each other.
[0019] Optionally, the first unit is used to copy data from the second unit; in the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level; in the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level.
[0020] Optionally, the second unit is used to copy the data in the first unit; in the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level; in the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level.
[0021] This utility model also provides an SRAM circuit, including two columns of the above-described SRAM cells, namely a first column and a second column. Each column includes two or more SRAM cells. The control signal lines CA of each SRAM cell in each column are interconnected, the control signal lines CB of each SRAM cell in each column are interconnected, the control signal lines CD of each SRAM cell in each column are interconnected, and the read bit lines RBL of each SRAM cell in each column are interconnected. The terminals CC of the two SRAM cells in each row are interconnected.
[0022] Optionally, the first column is used to copy data from the second column; in the first column, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and each word line WL is used to input a low level; in the second column, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and each word line WL is used to input a low level.
[0023] This invention also provides a memory, including the SRAM cell or the SRAM circuit described in any of the above claims.
[0024] This utility model provides an SRAM cell, SRAM circuit, and memory, comprising 10 MOSFETs. This SRAM cell can be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOSFETs to an existing 6T SRAM; the four added MOSFETs are M7, M8, M9, and M10. Figure 4 As shown, 10T SRAM behaves similarly to 8T SRAM when reading and writing data, but it has one less memory module than 8T SRAM. Figure 4 The MOSFETs marked with an "X" in the middle indicate that the read / write speed of 10T SRAM is slightly slower than that of 8T SRAM, but faster than that of 6T SRAM. For example... Figures 5-11As shown, after combining 10T SRAM, it can be directly used for data copying, eliminating the need for an ALU and significantly improving the data copying speed. An unexpected benefit of 10T SRAM is its improved data read and write speed; it can be used for data copying at a very fast pace. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a 6T SRAM circuit structure in the prior art.
[0026] Figure 2 This is a schematic diagram of the circuit structure of an 8T SRAM in the prior art.
[0027] Figure 3 This is a schematic diagram of the circuit structure of an SRAM cell, namely a 10T SRAM, provided in one embodiment of this utility model.
[0028] Figure 4 yes Figure 3 Equivalent circuit diagram during data reading and writing.
[0029] Figure 5 This is a schematic diagram of an SRAM circuit provided in one embodiment of the present invention, namely, a circuit structure after two SRAM cells are connected.
[0030] Figure 6 yes Figure 5 The simulation diagram of Q1 (Q1 stored as 1) on the left (first unit) is copied to Q0 (Q0 stored as 0) on the right (second unit).
[0031] Figure 7 yes Figure 5 The simulation diagram of Q1 (Q1 stored as 1) on the left (first unit) is copied to Q0 (Q0 stored as 1) on the right (second unit).
[0032] Figure 8 yes Figure 5 The simulation diagram of Q1 (Q1 stored as 0) on the left (first unit) is copied to Q0 (Q0 stored as 1) on the right (second unit).
[0033] Figure 9 yes Figure 5 The simulation diagram of Q1 (Q1 stored as 0) on the left (first unit) is copied to Q0 (Q0 stored as 0) on the right (second unit).
[0034] Figure 10 This is a schematic diagram of an SRAM circuit provided in one embodiment of the present invention, namely, a circuit structure after two columns of SRAM cells are connected.
[0035] Figure 11 yes Figure 10The simulation diagram of Q2, Q4, Q6, and Q8 in the left array (first column) is copied from the simulation diagram of Q1, Q3, Q5, and Q7 in the right array (second column). Detailed Implementation
[0036] To make the objectives, advantages, and features of this utility model clearer, the following detailed description of an SRAM cell, SRAM circuit, and memory proposed by this utility model is provided in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the explanation of the embodiments of this utility model.
[0037] In the description of this utility model, the terms "first," "second," and other qualifiers are added for convenience of description and reference, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with qualifiers such as "first" and "second" may explicitly or implicitly include one or more of that feature.
[0038] like Figure 3 As shown, this embodiment provides an SRAM cell including 10 MOS transistors, namely M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10; M1, M3, M5, M6, M7, M8, and M10 are NMOS transistors, and M2, M4, and M9 are PMOS transistors; the gate of M1 is connected to the gate of M2, the source of M4, the drain of M3, and the gate of M10, respectively; the drain of M1 is connected to the source of M8; the sources of M1 and M3 are respectively connected to a first ground terminal; the drains of M2 and M4 are respectively connected to a high level VDD, and M2... The source of M3 is connected to the drain of M9; the gate of M3 is connected to the gate of M4, the source of M9, the drain of M8, the drain of M5, and the drain of M7 respectively; the gate of M5 is connected to the word line WL, and the source of M5 is connected to the bit line BL; the gate of M6 is connected to the read word line RWL, the drain of M6 is connected to the read bit line RBL, and the source of M6 is connected to the drain of M10; the gate of M7 is connected to the control signal line CA, and the source of M7 is connected to the terminal CC; the gate of M8 is connected to the control signal line CB; the gate of M9 is connected to the control signal line CD; and the source of M10 is connected to the second ground terminal.
[0039] This embodiment provides an SRAM cell comprising 10 MOSFETs, which can be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOSFETs to an existing 6T SRAM; the four added MOSFETs are M7, M8, M9, and M10. Figure 4 As shown, 10T SRAM behaves similarly to 8T SRAM when reading and writing data, but it has one less memory module than 8T SRAM. Figure 4The MOSFETs marked with an "X" in the middle indicate that the read / write speed of 10T SRAM is slightly slower than that of 8T SRAM, but faster than that of 6T SRAM. For example... Figures 5-11 As shown, after combining 10T SRAM, it can be directly used for data copying, eliminating the need for an ALU and significantly improving the data copying speed. An unexpected benefit of 10T SRAM is its improved data read and write speed; it can be used for data copying at a very fast pace.
[0040] Optional, such as Figure 3 As shown, the SRAM cell is used for reading data. The control signal line CA is used to input a low level (low level refers to a lower voltage, which can be represented by 0), the control signal line CB is used to input a high level (high level refers to a higher voltage, which can be represented by 1), the control signal line CD is used to input a low level, the read word line RWL is used to input a high level, and the read bit line RBL is precharged to a high level. When the control signal line CA inputs a low level, M7 is off; when the control signal line CB inputs a high level, M8 is on; when the control signal line CD inputs a low level, M9 is on. At this time, the 10T SRAM is similar to the 8T SRAM, but with one less cell than the 8T SRAM. Figure 4 The MOSFET marked with an "X" is shown in the image. When reading data, assuming Q = 0 (i.e., the original data is 0) and QB = 1, M10 is turned on; the read word line RWL is high, and M6 is turned on; the read bit line RBL is pre-charged to high. Due to the voltage difference between the read bit line RBL and ground, a current flows from the read bit line RBL to ground, reducing the voltage of the read bit line RBL, thus allowing the reading of 0. Similarly, assuming Q = 1 (i.e., the original data is 1) and QB = 0, M10 is turned off, and the read bit line RBL remains high, allowing the reading of 1.
[0041] Optional, such as Figure 3 As shown, the SRAM cell is used for writing data. The control signal line CA is used to input a low level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, the word line WL is used to input a high level, and the bit line BL is pre-charged to a high level. When writing data, assuming Q = 0 (i.e., the original data is 0) and QB = 1, M1 and M4 are turned on; the word line WL is high, and M5 is turned on; the bit line BL is pre-charged to a high level. Due to the voltage difference between the bit line BL and the Q terminal, a current is formed from the bit line BL to the Q terminal, increasing the voltage at the Q terminal, making Q = 1, i.e., writing 1 at the Q terminal. Similarly, assuming Q = 1 (i.e., the original data is 1) and QB = 0, M2 and M3 are turned on; since there is no voltage difference between the bit line BL and the Q terminal, the voltage at the Q terminal remains unchanged, and the Q terminal remains at 1, equivalent to writing 1. The principle of writing 0 is the same as the principle of writing 1.
[0042] Optional, see reference Figure 3 As shown, the first ground terminal and the second ground terminal are the same ground terminal, which simplifies the structure of the SRAM cell. In other embodiments, the first ground terminal and the second ground terminal can be two separate ground terminals.
[0043] like Figure 5 As shown, based on the SRAM cell provided in the above embodiment, this embodiment provides an SRAM circuit including two SRAM cells, namely the first cell ( Figure 5 (left side) and second unit ( Figure 5 (on the right side), the terminal CC of the first unit and the terminal CC of the second unit are connected to each other.
[0044] This embodiment provides an SRAM circuit in which the CC terminals of the first and second units are interconnected. The first unit can copy data from the second unit; that is, the SRAM unit on the left can copy data from the SRAM unit on the right. In other embodiments, by setting the input signals of each signal line, the second unit can also copy data from the first unit.
[0045] Optional, such as Figures 5-9 As shown, the first unit is used to copy data from the second unit; in the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level; in the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level.
[0046] For ease of description, CD on the left is represented by CD1, CB by CB1, Q by Q1, and QB by QB1; while CD on the right is represented by CD0, CB by CB0, Q by Q0, and QB by QB0. In each simulation graph, the horizontal axis time (ns) represents time, and the vertical axis V (mV) represents voltage. Figure 5 and Figure 6As shown, when copying data 0, assuming Q0 = 0 in the second unit (i.e., the original data is 0) and QB0 = 1, then M1 and M4 in the second unit are turned on, and M2 and M3 are turned off. Making word line WL = 0 (i.e., applying a lower external voltage), M5 in both the first and second units is turned off. Making control signal line CA = 1 (i.e., applying a higher external voltage), then M7 in both the first and second units is turned on, connecting the first and second units. Making control signal line CB0 = 1 and control signal line CD0 = 0 in the second unit, then M8 and M9 are turned on. Making control signal line CB1 = 0 and control signal line CD1 = 1 in the first unit, then M8 and M9 are turned off. Assuming Q1 = 1 in the first unit (i.e., the original data is 1), due to the voltage difference between Q1 and Q0, a current path Q1→Q0→ground is formed, causing the voltage at Q1 to drop rapidly, resulting in Q1 = 0, thus achieving Q1 copying Q0. Similarly, as... Figure 9 As shown, assuming Q1 = 0 (i.e., the original data is 0), since there is no voltage difference between Q1 and Q0, no current is formed, and Q1 = 0 remains unchanged, which is equivalent to copying 0.
[0047] like Figure 5 and Figure 8 As shown, when copying data 1, assuming Q0 = 1 (i.e., the original data is 1) and QB0 = 0 in the second unit, M2 and M3 in the second unit are turned on, while M1 and M4 are turned off. Making word line WL = 0 (i.e., applying a lower external voltage) turns off M5 in both the first and second units. Making control signal line CA = 1 (i.e., applying a higher external voltage) turns on M7 in both the first and second units, connecting them. Making control signal line CB0 = 1 and control signal line CD0 = 0 in the second unit turns on M8 and M9. Making control signal line CB1 = 0 and control signal line CD1 = 1 in the first unit turns off M8 and M9. Assuming Q1 = 0 in the first unit (i.e., the original data is 0), due to the voltage difference between Q1 and Q0, a current path VDD → Q0 → Q1 is formed, causing the voltage at Q1 to rise rapidly, resulting in Q1 = 1, thus enabling Q1 to copy Q0. Similarly, as... Figure 7 As shown, assuming Q1 = 1 (i.e., the original data is 1), since there is no voltage difference between Q1 and Q0, no current is formed, and Q1 = 1 remains unchanged, which is equivalent to copying 1.
[0048] Optional, see reference Figures 5-9As shown, the second unit is used to copy data from the first unit. In the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level. In the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level. When the levels of the control signal lines and word lines in the first and second units are interchanged, the second unit can copy data from the first unit, and the principle is the same as the principle of the first unit copying data from the second unit.
[0049] like Figure 10 As shown, based on the aforementioned SRAM circuit, this embodiment provides another SRAM circuit, including two columns of SRAM cells, namely a first column and a second column, each column including two or more of the aforementioned SRAM cells, and the control signal line CA of each SRAM cell in each column (… Figure 10 To distinguish the connection relationships between the left and right columns and each endpoint, 0 or 1 is added after the letter for differentiation. The control signal lines CB of each SRAM cell in each column are interconnected, the control signal lines CD of each SRAM cell in each column are interconnected, and the read bit lines RBL of each SRAM cell in each column are interconnected. The terminals CC of the two SRAM cells in each row are interconnected.
[0050] This embodiment provides an SRAM circuit in which the first column can copy data from the second column; that is, the left column can copy data from the right column. In other embodiments, by setting the input signals of each signal line, the second column can also copy data from the first column.
[0051] Optional, such as Figure 10 and Figure 11 As shown, the first column is used to copy data from the second column; in the first column, the control signal line CA (i.e. Figure 10 CA0 in the input is used for high level, and the control signal line CB (i.e. Figure 10 CB0) is used to input a low level, and the control signal line CD (i.e. Figure 10 CD0) is used to input a high level, and each word line WL (i.e. Figure 10 WL0, WL1, and WL2 in the first column are used for inputting a low level; in the second column, the control signal line CA (i.e., Figure 10 CA1) is used to input a high level, and the control signal line CB (i.e. Figure 10 CB1) is used to input a high level, and the control signal line CD (i.e. Figure 10CD1) is used to input a low level, and each word line WL (i.e. Figure 10 WL0, WL1, and WL2 in the table are used to input low levels. The principle of copying data from the second column in the first column is the same as that of copying data from the second unit in the first unit above, and will not be repeated here.
[0052] Based on the same technical concept as the SRAM cell and SRAM circuit described above, this embodiment provides a memory including the SRAM cell or SRAM circuit described above.
[0053] This embodiment provides a memory including 10 MOS transistors, and this SRAM cell can be referred to as a 10T SRAM. A 10T SRAM is obtained by adding 4 MOS transistors to an existing 6T SRAM; the 4 added MOS transistors are M7, M8, M9, and M10. Figure 4 As shown, 10T SRAM behaves similarly to 8T SRAM when reading and writing data, but it has one less memory module than 8T SRAM. Figure 4 The MOSFET marked with an "X" indicates that the read / write speed of a 10TB SRAM is slightly slower than that of an 8TB SRAM, but faster than that of a 6TB SRAM. For example... Figures 5-11 As shown, after combining 10T SRAM, it can be directly used for data copying, eliminating the need for an ALU and significantly improving the data copying speed. An unexpected benefit of 10T SRAM is its improved data read and write speed; it can be used for data copying at a very fast pace.
[0054] In summary, this utility model provides an SRAM cell, SRAM circuit, and memory, comprising 10 MOSFETs. This SRAM cell can be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOSFETs to the existing 6T SRAM; the four added MOSFETs are M7, M8, M9, and M10. Figure 4 As shown, 10T SRAM behaves similarly to 8T SRAM when reading and writing data, but it has one less memory module than 8T SRAM. Figure 4 The MOSFETs marked with an "X" in the middle indicate that the read / write speed of 10T SRAM is slightly slower than that of 8T SRAM, but faster than that of 6T SRAM. For example... Figures 5-11 As shown, after combining 10T SRAM, it can be directly used for data copying, eliminating the need for an ALU and significantly improving the data copying speed. An unexpected benefit of 10T SRAM is its improved data read and write speed; it can be used for data copying at a very fast pace.
[0055] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present utility model.
Claims
1. An SRAM cell, characterized in that, It includes 10 MOSFETs, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; M1, M3, M5, M6, M7, M8 and M10 are NMOS, and M2, M4 and M9 are PMOS; The gate of M1 is connected to the gate of M2, the source of M4, the drain of M3, and the gate of M10, respectively. The drain of M1 is connected to the source of M8, and the source of M1 and the source of M3 are connected to the first ground terminal, respectively. The drains of M2 and M4 are connected to the high level VDD, and the source of M2 is connected to the drain of M9. The gate of M3 is connected to the gate of M4, the source of M9, the drain of M8, the drain of M5, and the drain of M7, respectively. The gate of M5 is connected to the word line WL, and the source of M5 is connected to the bit line BL. The gate of M6 is connected to the read word line RWL, the drain of M6 is connected to the read bit line RBL, and the source of M6 is connected to the drain of M10. The gate of M7 is connected to the control signal line CA, and the source of M7 is connected to the terminal CC. The gate of M8 is connected to the control signal line CB; The gate of M9 is connected to the control signal line CD; The source of M10 is connected to the second ground terminal.
2. An SRAM cell as described in claim 1, characterized in that, The SRAM cell is used to read data. The control signal line CA is used to input a low level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, the read word line RWL is used to input a high level, and the read bit line RBL is precharged to a high level.
3. An SRAM cell as described in claim 1, characterized in that, The SRAM cell is used for writing data. The control signal line CA is used to input a low level. The control signal line CB is used to input a high level. The control signal line CD is used to input a low level. The word line WL is used to input a high level. The bit line BL is precharged to a high level.
4. An SRAM cell as described in claim 1, characterized in that, The first grounding terminal and the second grounding terminal are the same grounding terminal.
5. An SRAM circuit, characterized in that, It includes two SRAM cells as described in claim 1, namely a first cell and a second cell, wherein the terminals CC of the first cell and the second cell are connected to each other.
6. An SRAM circuit as described in claim 5, characterized in that, The first unit is used to copy data from the second unit; in the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level; in the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level.
7. An SRAM circuit as described in claim 5, characterized in that, The second unit is used to copy the data in the first unit; in the first unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and the word line WL is used to input a low level; in the second unit, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and the word line WL is used to input a low level.
8. An SRAM circuit, characterized in that, The device comprises two columns of SRAM cells as described in claim 1, namely a first column and a second column. Each column includes two or more of the SRAM cells described above. The control signal lines CA of each SRAM cell in each column are interconnected. The control signal lines CB and CD of each SRAM cell in each column are interconnected. The read bit lines RBL of each SRAM cell in each column are interconnected. The terminals CC of the two SRAM cells in each row are interconnected.
9. An SRAM circuit as described in claim 8, characterized in that, The first column is used to copy the data in the second column; in the first column, the control signal line CA is used to input a high level, the control signal line CB is used to input a low level, the control signal line CD is used to input a high level, and each word line WL is used to input a low level; in the second column, the control signal line CA is used to input a high level, the control signal line CB is used to input a high level, the control signal line CD is used to input a low level, and each word line WL is used to input a low level.
10. A memory, characterized in that, It includes the SRAM cell as described in any one of claims 1-4 or the SRAM circuit as described in any one of claims 5-9.