Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, including: providing a substrate; forming a first recess in the substrate, the first recess having a bottom size smaller than a top size along a direction parallel to a surface of the substrate, and having a wall corner surface between a sidewall surface and a bottom surface of the first recess; forming a protective layer on the sidewall of the first recess, the protective layer exposing the wall corner surface and the bottom of the first recess; after forming the protective layer, performing a first etching process on the wall corner surface to form a second recess from the first recess; and forming an epitaxial layer in the second recess. The protective layer is used to reduce damage to the sidewall of the first recess, reduce lateral etching of the sidewall of the first recess, facilitate formation of a second recess with a sidewall relatively perpendicular to the bottom, optimize the morphology of the second recess, and improve the performance of the formed device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the further development of semiconductor technology, as transistor feature sizes shrink to the nanoscale, proportional scaling techniques face increasingly severe challenges, such as mobility degradation, source-drain punch-through leakage, and hot carrier effects. Among these, mobility degradation is a major obstacle affecting the speed improvement of integrated circuits. By improving the mobility of carriers within the channel, it is possible to compensate for the mobility degradation caused by factors such as Coulomb interactions due to high channel doping, increased effective electric field strength due to thinner gate dielectric, and enhanced interface scattering.

[0003] Strained silicon technology introduces strain, or stress variation, into the channel layer through device structure and material design. This alters the lattice structure of the channel layer substrate, thereby increasing carrier mobility and improving device performance. Direct epitaxy of stressed channel materials is becoming a development trend. Germanium-silicon materials, due to their high carrier mobility, improved device reliability, and compatibility with existing silicon-based processes, have become a hot research topic for novel channel materials.

[0004] However, the technology of germanium-silicon channel devices still needs continuous improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a second groove located within the substrate; a protective layer located on the sidewall of the second groove, wherein the top surface of the protective layer is flush with the surface of the substrate, and the bottom surface of the protective layer is higher than the bottom surface of the second groove; and an epitaxial layer located within the second groove.

[0007] Optionally, the material of the epitaxial layer includes germanium silicon.

[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first groove in the substrate, wherein the bottom dimension of the first groove is smaller than the top dimension along a direction parallel to the surface of the substrate, and a corner surface is formed between the sidewall surface and the bottom surface of the first groove; forming a protective layer on the sidewall of the first groove, the protective layer exposing the corner surface and the bottom of the first groove; after forming the protective layer, etching the corner surface by a first etching process to form a second groove from the first groove; and forming an epitaxial layer in the second groove.

[0009] Optionally, the material of the protective layer is different from the material of the substrate.

[0010] Optionally, the method for forming the protective layer includes: forming an initial protective layer on the surface of the first groove; and removing the initial protective layer from the bottom of the first groove and the surface of the corner using a second etching process to form the protective layer.

[0011] Optionally, the second etching process includes anisotropic dry etching; the etching gas used in the second etching process includes hydrogen-containing gas.

[0012] Optionally, the hydrogen-containing gas includes one or more of CHF3, CH2F3, and CH3F.

[0013] Optionally, the second etching process may have a selection ratio of the initial protective layer to the substrate greater than 15:1.

[0014] Optionally, the initial protective layer may be formed using a chemical vapor deposition process or an atomic layer deposition process.

[0015] Optionally, the initial protective layer is also formed on the surface of the substrate; the method for forming the protective layer further includes: removing the initial protective layer on the surface of the substrate using a second etching process.

[0016] Optionally, the initial protective layer is formed using an in-situ passivation process.

[0017] Optionally, the in-situ passivation process includes inductively coupled plasma etching.

[0018] Optionally, the process parameters of the inductively coupled plasma etching process include: the plasma gas includes oxygen or nitrogen, the power range is 100 watts to 200 watts, and no bias voltage or a bias voltage range of 20 volts to 40 volts.

[0019] Optionally, the first groove is formed using a third etching process, the third etching process including anisotropic etching processes.

[0020] Optionally, in the third etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate ranges from 0 degrees to 5 degrees.

[0021] Optionally, the first etching process includes anisotropic etching, wherein the angle between the implantation direction of the etching ions and the normal direction of the substrate is greater than 0 degrees and less than or equal to 15 degrees.

[0022] Optionally, after the protective layer is formed, before etching with the first etching process, the process further includes etching the bottom of the first groove and the corner surface with a fourth etching process.

[0023] Optionally, the fourth etching process includes anisotropic dry etching.

[0024] Optionally, in the fourth etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate ranges from 0 degrees to 5 degrees.

[0025] Optionally, the material of the epitaxial layer includes germanium silicon.

[0026] Optionally, after forming the second groove and before forming the epitaxial layer, the method further includes: removing the protective layer using a fifth etching process.

[0027] Optionally, the material of the protective layer includes silicon nitride or silicon oxide.

[0028] Optionally, the thickness of the protective layer is greater than 0.5 nanometers.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0030] In the semiconductor structure formation method provided by the present invention, a protective layer is formed on the sidewall of the first groove. The protective layer exposes the corner surface and the bottom of the first groove. After the protective layer is formed, the corner surface is etched by a first etching process. During the etching process, the protective layer is used to reduce damage to the sidewall of the first groove and reduce the lateral etching of the sidewall of the first groove, which is conducive to forming a second groove with the sidewall being more perpendicular to the bottom, optimizing the morphology of the second groove, and improving the performance of the formed device.

[0031] Furthermore, the initial protective layer formation process includes an in-situ passivation process, which can avoid the impact of impurities introduced by the off-situ formation of the initial protective layer on device performance.

[0032] Furthermore, the initial protective layer is formed using a chemical vapor deposition process or an atomic layer deposition process, which facilitates the formation of a thicker material layer to better protect the sidewalls of the first groove from etching damage during subsequent etching processes.

[0033] Furthermore, the etching gas used in the second etching process includes hydrogen-containing gas, so as to improve the selectivity of the second etching process for the protective layer and the substrate, and reduce damage to the substrate.

[0034] Furthermore, in the third etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate is between 0 and 5 degrees, which helps to reduce the lateral etching of the first groove, so as to form a second groove morphology with the sidewalls being more perpendicular to the bottom.

[0035] Furthermore, the first etching process includes anisotropic etching, wherein the angle between the implantation direction of the etching ions and the normal direction of the substrate is greater than 0 degrees and less than or equal to 15 degrees. This facilitates the lateral etching of the corner surface to remove the corner surface while reducing the etching of the first groove along the normal direction. Attached Figure Description

[0036] Figures 1 to 5 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0037] Figures 6 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0038] Figure 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0039] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0040] As described in the background section, the performance of semiconductor structures formed using existing germanium-silicon channel device technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0041] Figures 1 to 5 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0042] Please refer to Figure 1 A substrate 101 is provided, the substrate 101 including a first region I and a second region II adjacent to the first region I; a mask layer 102 is formed on the substrate 101, the mask layer 102 exposing the first region I.

[0043] Please refer to Figure 2 Using the mask layer 102 as a mask, the substrate 101 is etched using a first dry etching process to form a first groove 103 in the substrate 101. A corner surface A is formed at the bottom of the sidewall of the first groove 103.

[0044] Please refer to Figure 3The first groove 103 is further etched using a second dry etching process to remove or reduce the corner surface A to form a second groove 104; after the second groove 104 is formed, the mask layer 102 is removed.

[0045] Please refer to Figure 4 An epitaxial layer 105 is formed within the second groove 104.

[0046] Please refer to Figure 5 The epitaxial layer 105 and the substrate 101 are etched to form the first fin 106 of the first region I and the second fin 107 of the second region II.

[0047] In the above method, the first region I is used to form a P-type device, the second region II is used to form an N-type device, and a PN interface is formed between the first region I and the second region II. The first fin 106 is made of germanium-silicon, which can improve the channel electron mobility of the P-type device. The second fin 107 is made of silicon and is used to form the channel of the N-type device.

[0048] After the first dry etching process, due to the influence of the dry etching process, such as the accumulation of by-products generated during the etching process on the sidewalls of the previously etched grooves, further etching will be hindered, making it impossible to form an ideal groove with sidewalls perpendicular to the bottom. Instead, a first groove 103 with a bottom width smaller than the top width will be formed, i.e., a corner surface A will be formed (e.g., Figure 2 (As shown). The second dry etching process is used to remove or reduce the corner surface A. While corner A is being removed, the sidewalls of the first groove 103 are also etched laterally. The more corner surface A is removed, the more the sidewalls of the first groove 103 bend. (As shown) Figure 3 As shown, the corner surface B of the formed second groove 104 is significantly smaller than the corner surface A, and the difference between the widest and narrowest points of the sidewall of the second groove 104, i.e., the degree of curvature CR, is significantly larger. The second dry etching process needs to balance the consumption of the corner surface A and the lateral etching of the sidewall of the first groove 103.

[0049] When the feature size of the device is large, such as above the 10nm process node, the CR (contact fin) is controlled within 26nm, and the impact on the formed device is small. However, with the further shrinking of the feature size in CMOS technology and the further reduction of the fin spacing, near the interface between the first region I and the second region II (i.e., the PN interface), when the corner face B is large, it will cause the bottom of the first fin 106 formed in the first region I to be mixed with silicon material (such as...). Figure 5(As shown by the dashed line); When the curvature CR is large, the epitaxial layer 105 will extend laterally into the first region I, which may cause germanium-silicon material to be mixed in the second fin 107. At the same time, the poor morphology of the second groove 104 will also lead to irregular PN interface. The smaller the feature size of the device, the greater the impact on device performance. Therefore, the morphology of the second groove 104 needs to be further improved.

[0050] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. A protective layer is formed on the sidewall of a first groove, exposing the corner surface and the bottom of the first groove. After forming the protective layer, a first etching process is performed on the corner surface. During the etching process, the protective layer is used to reduce damage to the sidewall of the first groove and reduce lateral etching of the sidewall, which facilitates the formation of a second groove with a sidewall that is more perpendicular to the bottom, optimizes the morphology of the second groove, and improves the performance of the formed device.

[0051] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] Figures 6 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0053] Please refer to Figure 6 Substrate 201 is provided.

[0054] In this embodiment, the substrate 201 is made of silicon. In other embodiments, the substrate 201 may be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements may include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0055] Please refer to Figure 7 A first groove 203 is formed in the substrate 201. Along a direction parallel to the surface of the substrate 201, the bottom dimension of the first groove 203 is smaller than the top dimension, and a corner surface D is formed between the sidewall surface and the bottom surface of the first groove 203.

[0056] In this embodiment, the method for forming the first groove 203 includes: forming a mask layer 202 on the substrate 201, wherein the mask layer 202 exposes a portion of the substrate; and etching the substrate 201 using the mask layer 202 as a mask to form the first groove 203.

[0057] The mask layer 102 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the mask layer 102 is made of silicon nitride.

[0058] In this embodiment, the first groove 203 is formed using a third etching process, which includes anisotropic etching processes.

[0059] In the third etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate 201 ranges from 0 degrees to 5 degrees. The purpose of selecting this angle range is to achieve anisotropic etching, that is, the etching rate along the normal direction of the substrate 201 is much greater than the etching rate along the direction parallel to the substrate 201 (i.e., lateral etching), which helps to reduce the lateral etching of the first groove, so as to form a second groove morphology with the sidewalls being more perpendicular to the bottom.

[0060] Due to the influence of the dry etching process, if byproducts generated during the etching process accumulate on the sidewalls of the grooves formed by the first etching, they will block further etching and prevent the formation of an ideal groove with sidewalls perpendicular to the bottom. Instead, a first groove 203 with a bottom width smaller than the top width is formed, i.e., a corner surface D is formed. The corner surface needs to be removed later to form a better groove morphology.

[0061] Subsequently, a protective layer is formed on the sidewall of the first groove 203, exposing the corner surface D and the bottom of the first groove 203. For the method of forming the first groove 203, please refer to [reference needed]. Figures 8 to 9 .

[0062] Please refer to Figure 8 An initial protective layer 204 is formed on the surface of the first groove 203.

[0063] In this embodiment, the initial protective layer 204 is formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, which facilitates the formation of a thicker material layer to better protect the sidewalls of the first groove 203 from etching damage during subsequent etching processes. In another embodiment, the initial protective layer is formed using an in-situ passivation process.

[0064] In this embodiment, the initial protective layer 204 is also formed on the surface of the substrate 201. Specifically, the initial protective layer 204 is also formed on the surface of the mask layer 202.

[0065] The initial protective layer 204 is used to form a protective layer. The material of the initial protective layer 204 is different from that of the substrate 201 so that when the initial protective layer 204 is subsequently etched, an etching process with a large selectivity between the initial protective layer 204 and the substrate 201 can be selected to reduce etching damage to the substrate 201.

[0066] The initial protective layer 204 is made of silicon nitride or silicon oxide. In this embodiment, the initial protective layer 204 is made of silicon oxide.

[0067] The initial protective layer 204 has a thickness greater than 0.5 nanometers. The initial protective layer 204 is used to form the subsequent protective layer, and the thickness of the initial protective layer 204 determines the thickness of the subsequent protective layer. The reason for selecting this thickness range is to reduce the possibility of damage to the initial protective layer 204 caused by subsequent etching, which could result in poor uniformity of the thickness of the subsequently formed protective layer and render it ineffective as a protective layer.

[0068] Please refer to Figure 9 The initial protective layer 204 on the bottom of the first groove 203 and the surface of the corner D is removed by a second etching process to form the protective layer 205.

[0069] The protective layer 205 is used to protect the sidewalls of the first groove 203 from damage during subsequent etching processes and reduce the lateral expansion of the first groove 203.

[0070] The second etching process includes anisotropic dry etching; the etching gas used in the second etching process includes hydrogen-containing gas.

[0071] The hydrogen-containing gas includes one or more of CHF3, CH2F3, and CH3F. During the second etching process, the hydrogen-containing gas helps to improve the selectivity of the second etching process for the initial protective layer 204 and the substrate 201, and reduces the etching damage to the substrate 201 caused by the etching process.

[0072] The material of the protective layer 205 depends on the material of the initial protective layer 204, that is, the material of the protective layer 205 is different from the material of the substrate 201; the material of the protective layer 205 includes silicon nitride or silicon oxide; the thickness of the protective layer is greater than 0.5 nanometers. In this embodiment, the material of the protective layer 205 is silicon nitride.

[0073] In this embodiment, the method for forming the protective layer 205 further includes: removing the initial protective layer 204 on the surface of the substrate 201 using a second etching process.

[0074] The second etching process uses a selectivity ratio greater than 15:1 for the initial protective layer 204 to the substrate 201. The higher the selectivity ratio, the more beneficial it is to reduce damage to the substrate 201 when etching the initial protective layer 204.

[0075] After the protective layer 205 is formed, a first etching process is performed on the corner surface D to form a second groove from the first groove 203. In this embodiment, after the protective layer 205 is formed but before the first etching process, an initial second groove is also formed. The method for forming the initial second groove is described in [reference needed]. Figure 10 .

[0076] Please refer to Figure 10 The bottom of the first groove 203 and the corner surface D are etched using the fourth etching process.

[0077] The fourth etching process includes anisotropic dry etching processes.

[0078] In the fourth etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate 201 ranges from 0 degrees to 5 degrees. This fourth etching process further increases the depth of the initially formed second groove 206 along the normal direction of the substrate 201. That is, while protecting the sidewalls of the formed groove, multiple etching operations can be performed to form a groove with a large aspect ratio, thus avoiding excessive lateral etching of the groove sidewalls.

[0079] In this embodiment, the corner surface D is formed into corner surface E under the fourth etching process.

[0080] Please refer to Figure 11 After the protective layer 205 is formed, the corner surface D is etched by a first etching process so that the first groove 203 forms the second groove 207.

[0081] Specifically, in this embodiment, after the initial second groove 206 is formed, the corner surface E is etched using a first etching process to form the second groove 207 from the initial second groove 206.

[0082] The first etching process includes anisotropic etching, wherein the angle between the implantation direction of the etching ions and the normal direction of the substrate is greater than 0 degrees and less than or equal to 15 degrees. This etching angle range is chosen to reduce further etching of the initial second groove 206 along the normal direction of the substrate 201, while primarily performing lateral etching on the corner surface E. During the etching process, the protective layer is used to reduce damage to the sidewalls of the first groove 203 (specifically, the initial second groove 206 in this embodiment), reducing lateral etching of the sidewalls of the first groove 203 (specifically, the initial second groove 206 in this embodiment), facilitating the formation of a second groove 207 with sidewalls more perpendicular to the bottom, optimizing the morphology of the second groove 207, and improving the performance of the formed device.

[0083] Please refer to Figure 12 An epitaxial layer 208 is formed in the second groove 207.

[0084] In this embodiment, after forming the second groove 207 and before forming the epitaxial layer 208, the method further includes: removing the mask layer 202.

[0085] In this embodiment, the protective layer 205 on the sidewall of the first groove 203 is retained. In other embodiments, after forming the second groove 207 and before forming the epitaxial layer 208, the process further includes removing the protective layer 205 using a fifth etching process. The material of the protective layer 205 is different from the material of the substrate 201, and an etching process with a high selectivity ratio for both the protective layer 205 and the substrate 201 can be selected to reduce damage to the substrate 201 during the fifth etching process.

[0086] The material of the epitaxial layer 208 includes germanium and silicon.

[0087] The process for forming the epitaxial layer 208 includes an epitaxial growth process. In this embodiment, the process for forming the epitaxial layer 208 is an epitaxial growth process. The process parameters of the epitaxial growth process include: the reaction gases include SiH4, GeH4, and H2, the flow rate of SiH4 is in the range of 110 sccm to 130 sccm, the flow rate of GeH4 is in the range of 95 sccm to 115 sccm, the flow rate of H2 is in the range of 25 slm to 35 slm, and the gas pressure is in the range of 95 to 105 Torr.

[0088] The epitaxial layer 208 is made of germanium-silicon, and the substrate 201 is made of silicon. Due to the lattice mismatch between germanium and silicon, compressive stress is generated on the epitaxial layer 208. The compressive stress can reduce the effective conductivity of holes in the channel direction and improve the speed of PMOS devices.

[0089] Accordingly, another embodiment of the present invention also provides an embodiment of a semiconductor structure formed by the above-described forming method. Please refer to [the original text]. Figure 12 Includes: a substrate 201; and a second recess 207 located within the substrate 201 (e.g., ...). Figure 11 (as shown); a protective layer 205 located on the sidewall of the second groove 207, the top surface of the protective layer 205 being flush with the surface of the substrate 201, and the bottom surface of the protective layer 205 being higher than the bottom surface of the second groove 207; an epitaxial layer 208 located within the second groove 207.

[0090] In this embodiment, the epitaxial layer 208 is made of germanium-silicon. Subsequently, the epitaxial layer 208 is used to form the channel of a germanium-silicon channel device.

[0091] Figure 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0092] Please Figure 7 Continue to refer to Figure 13 An initial protective layer 301 is formed on the surface of the first groove 203.

[0093] The initial protective layer 301 is formed using an in-situ passivation process. This in-situ passivation process can prevent impurities introduced by forming the initial protective layer in an off-site manner from affecting device performance.

[0094] The in-situ passivation process includes inductively coupled plasma etching.

[0095] In this embodiment, the process parameters of the inductively coupled plasma etching process include: the plasma gas includes oxygen or nitrogen, the power range is 100 watts to 200 watts, and no bias voltage or a bias voltage range of 20 volts to 40 volts. During the inductively coupled plasma etching process, the surface of the first groove 203 reacts with the oxygen or nitrogen ion gas to form silicon oxide or silicon nitride, that is, the material of the initial protective layer 301 is silicon oxide or silicon nitride.

[0096] Subsequently, a protective layer is formed using the initial protective layer 301. For details on the formation of the protective layer and subsequent processes in this embodiment, please refer to Figures 9 to 9. Figure 12 The description will not be repeated here.

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first groove is formed in the substrate using a third etching process, the third etching process including anisotropic etching process, the first groove is U-shaped, along a direction parallel to the surface of the substrate, the bottom dimension of the first groove is smaller than the top dimension, and there is a corner surface between the sidewall surface and the bottom surface of the first groove; A protective layer is formed on the sidewall of the first groove, the protective layer exposing the corner surface and the bottom of the first groove; After the protective layer is formed, the corner surface is etched by a first etching process to form a second groove from the first groove. An epitaxial layer is formed within the second groove; The epitaxial layer is etched to form several fins.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer is different from the material of the substrate.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the protective layer includes: forming an initial protective layer on the surface of the first groove; and removing the initial protective layer from the bottom of the first groove and the surface of the corner using a second etching process to form the protective layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The second etching process includes anisotropic dry etching; the etching gas used in the second etching process includes hydrogen-containing gas.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The hydrogen-containing gas includes one or more of CHF3, CH2F3, and CH3F.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The second etching process has a selection ratio of the initial protective layer to the substrate that is greater than 15:

1.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, The initial protective layer is formed using a process including chemical vapor deposition or atomic layer deposition.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The initial protective layer is also formed on the surface of the substrate; the method for forming the protective layer further includes: removing the initial protective layer from the surface of the substrate using a second etching process.

9. The method for forming a semiconductor structure as described in claim 3, characterized in that, The initial protective layer is formed by an in-situ passivation process.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The in-situ passivation process includes inductively coupled plasma etching.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters of the inductively coupled plasma etching process include: plasma gas including oxygen or nitrogen, power range of 100 watts to 200 watts, no bias voltage or bias voltage range of 20 volts to 40 volts.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the third etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate ranges from 0 degrees to 5 degrees.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process includes anisotropic etching, wherein the angle between the implantation direction of the etching ions and the normal direction of the substrate is greater than 0 degrees and less than or equal to 15 degrees.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the protective layer is formed, before etching with the first etching process, the process further includes: etching the bottom of the first groove and the corner surface with the fourth etching process.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The fourth etching process includes anisotropic dry etching processes.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, In the fourth etching process, the angle between the implantation direction of the etching ions and the normal direction of the substrate ranges from 0 degrees to 5 degrees.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the epitaxial layer includes germanium and silicon.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the second groove is formed but before the epitaxial layer is formed, the process further includes: removing the protective layer using a fifth etching process.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes silicon nitride or silicon oxide.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer is greater than 0.5 nanometers.

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