Multiplexer and serializer comprising a multiplexer

Abstract

A multiplexer and a serializer including the multiplexer are provided. The multiplexer selects one of first to fourth data signals in response to first to fourth pulses. The first to fourth pulses correspond to the first to fourth data signals, respectively, and are sequentially switched. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse, and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0087760, filed on July 5, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure described herein relate to multiplexers included in high-speed serial communication systems and serializers including multiplexers. Background Technology

[0004] In high-speed serial link systems, data bits can be transmitted serially through a channel. When transmitting signals through channels such as coaxial cables or PCB traces, the channel bandwidth may be limited by channel load, skin effect, and dielectric loss, and high-frequency components of the signal may be attenuated at the receiver. In particular, the reliability of high-speed serial link systems can be reduced due to inter-symbol interference (ISI), a form of signal distortion where one symbol interferes with subsequent symbols.

[0005] For example, ISI can be added at the rising or falling edge of a signal whose voltage level changes rapidly at high frequencies. In this case, the signal output from the transmitter will be distorted, or the time it takes for the signal to be transmitted to the receiver will vary depending on the frequency. Summary of the Invention

[0006] Embodiments of this disclosure provide a multiplexer and a serializer including the multiplexer.

[0007] According to an embodiment, a multiplexer selects one of a first data signal to a fourth data signal in response to a first pulse to a fourth pulse, wherein the first pulse to the fourth pulse respectively correspond to the first data signal to the fourth data signal and are toggled sequentially. The multiplexer may include a NAND gate, a NOR gate, a first transistor, and a second transistor. The NAND gate outputs a first gating signal in response to receiving the first data signal, a fourth complementary data signal (which is a complementary signal to the fourth data signal), and the first pulse. The NOR gate outputs a second gating signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse. The first transistor includes a first terminal to which a first power supply voltage is applied, a gate to which the first gating signal is received, and a second terminal connected to the output of the multiplexer. The second transistor includes a first terminal connected to the output of the multiplexer, a gate to which the second gating signal is received, and a second terminal to which a ground voltage is applied. The first data signal may correspond to the rising edge of the first pulse, and the fourth complementary data signal may correspond to the rising edge of the fourth pulse.

[0008] According to an embodiment, a serializer may include a clock multiplexer and a multiplexer. The clock multiplexer generates first pulses to fourth pulses based on a first clock to a fourth clock. The first clock to the fourth clock have a 90-degree phase difference from each other, and the first pulses to the fourth pulses are switched sequentially. The multiplexer outputs an output signal based on a first data signal to a fourth data signal in response to the first pulses to the fourth pulses and a first complementary pulse to a fourth complementary pulse, which are respectively complementary to the first pulses to the fourth pulses. The first data signal to the fourth data signal corresponds to the first pulses to the fourth pulse. The multiplexer may include a NAND gate and a NOR gate. The NAND gate outputs a first gating signal in response to receiving the first data signal, a fourth complementary data signal complementary to the fourth data signal, and the first pulse. The NOR gate outputs a second gating signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse. The level of the output signal may be based on the first gating signal and the second gating signal.

[0009] According to an embodiment, a serializer may include a clock multiplexer and a multiplexer. The clock multiplexer generates first pulses to fourth pulses based on a first clock to a fourth clock, the first clock to the fourth clock having a 90-degree phase difference from each other, and the first pulses to the fourth pulses are switched sequentially. The multiplexer, in response to the first pulses to the fourth pulses and first complementary pulses to fourth complementary pulses respectively complementary to the first pulses to the fourth pulses, outputs an output signal based on a first data signal to a fourth data signal. The first data signal to the fourth data signal corresponds to the first pulses to the fourth pulses, respectively. The multiplexer may include a NAND gate, a NOR gate, a first transistor, and a second transistor. The NAND gate, in response to receiving the first data signal, a fourth complementary data signal (which is a complementary signal to the fourth data signal), and the first pulse, outputs a first gating signal. The NOR gate, in response to receiving the first data signal, the fourth complementary data signal, and the first complementary pulse complementary to the first pulse, outputs a second gating signal. The first transistor includes: a first terminal to which a first power supply voltage is applied, a gate to receive the first gating signal, and a second terminal connected to the output of the multiplexer. The second transistor includes a first terminal connected to the output of the multiplexer, a gate to receive the second gating signal, and a second terminal to which a ground voltage is applied. The first data signal may correspond to the rising edge of the first pulse, and the fourth complementary data signal may correspond to the rising edge of the fourth pulse. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 A block diagram of a communication system according to some embodiments of the present disclosure is shown.

[0012] Figure 2 A block diagram of a serializer according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A block diagram of a serializer according to some embodiments of the present disclosure is shown in detail.

[0014] Figure 4 Timing diagrams of clocks and pulses used in a serializer according to some embodiments of the present disclosure are shown.

[0015] Figure 5 A circuit diagram of the NAND gate of a multiplexer according to some embodiments of the present disclosure is shown.

[0016] Figure 6Aand Figure 6B The operation of the NAND gate of a multiplexer according to some embodiments of the present disclosure is illustrated.

[0017] Figure 7 A circuit diagram of the NOR (or NOT) gate of a multiplexer according to some embodiments of the present disclosure is shown.

[0018] Figure 8A and Figure 8B The operation of the NOR gate of a multiplexer according to some embodiments of this disclosure is illustrated.

[0019] Figure 9 A block diagram of a serializer according to some embodiments of the present disclosure is shown.

[0020] Figure 10 A block diagram of a system according to some embodiments of the present disclosure is shown.

[0021] Figure 11 A block diagram of a memory according to some embodiments of the present disclosure is shown. Detailed Implementation

[0022] The embodiments of this disclosure will now be described in detail and clearly to enable those skilled in the art to implement this disclosure.

[0023] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In describing the present disclosure, to facilitate overall understanding, the same parts / elements will be labeled with the same reference numerals / numbers in the drawings, and therefore additional descriptions will be omitted to avoid redundancy.

[0024] Figure 1 A block diagram of a communication system 10 according to some embodiments of the present disclosure is shown. The communication system 10 may include a transmitter 11 and a receiver 12 communicating with each other via a channel 13. In some embodiments, the communication system 10 may be referred to as a "transceiver", a "data transmission / reception circuit", or a "high-speed data transmission system".

[0025] Transmitter 11 can transmit data-based transmission signals to receiver 12 via channel 13. Channel 13, the number of pins of the integrated circuit implementing transmitter 11, and the number of pins of the integrated circuit implementing receiver 12 increase the cost required to implement communication system 10. To reduce the cost required to implement the above components, transmitter 11 can transmit signals including serialized data bits. Transmitter 11 may include a serializer (SER) 100 for serializing data.

[0026] Channel 13 can be a physical or electrical path connecting transmitter 11 and receiver 12. For example, channel 13 can be implemented using traces on a printed circuit board (PCB) or a coaxial cable. Skin effect, dielectric loss, etc., of channel 13 can attenuate the high-frequency components of data transmitted via channel 13. Channel loss occurs at receiver 12 when a signal is transmitted via channel 13. In addition, impedance discontinuities (or mismatches) can occur on channel 13 due to connectors between the PCB and the cable, as well as any other physical interfaces. Impedance discontinuities in channel 13 may manifest as notches in the frequency response of channel 13 and may cause reflected noise at receiver 12. Each data bit passing through channel 13 may impede subsequent (one or more) bits due to channel loss or bandwidth limitations, and an increase in the bit error rate may occur due to adjacent symbol overlap (i.e., inter-symbol interference (ISI)).

[0027] Receiver 12 can receive signals from transmitter 11 via channel 13. Receiver 12 may include a deserializer (DES) 14 for deserializing transmitted signals. Receiver 12 can deserialize transmitted signals by using deserializer 14.

[0028] Figure 2 A block diagram of a serializer 100 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 1 and Figure 2 The serializer 100 may include a multiplexer (4:1 MUX) 110 and a clock multiplexer (CLK MUX) 120. The multiplexer 110 may receive data D0 to D3, pulses PL0 to PL3, and complementary pulses PL0B to PL3B. The multiplexer 110 may output a data signal DQ based on pulses PL0 to PL3, complementary pulses PL0B to PL3B, and data D0 to D3. For example, the data signal DQ output from the multiplexer 110 may correspond to a signal that serializes data D0 to D3 sequentially.

[0029] Clock multiplexer 120 can receive clocks WCK0, WCK90, WCK180, and WCK270. Clocks WCK0, WCK90, WCK180, and WCK270 can be generated by a processor (not shown) or a signal generator (not shown) of transmitter 11 for use in clock multiplexer 120. Clock multiplexer 120 can generate pulses PL0 to PL3 and complementary pulses PL0B to PL3B based on clocks WCK0, WCK90, WCK180, and WCK270. Pulses PL0 to PL3 can be complementary to the complementary pulses PL0B to PL3B, respectively.

[0030] Figure 3 A block diagram of a serializer 100 according to some embodiments of the present disclosure is shown in detail. (Refer to...) Figure 2 and Figure 3 The serializer 100 may include a multiplexer 110 and a clock multiplexer 120, and the multiplexer 110 may include blocks 111 to 114 corresponding to data D0 to D3, respectively. For example, block 111 may correspond to data D0. Blocks 111 to 114 may receive pulses PL0 to PL3, complementary pulses PL0B to PL3B, data (or data signals) D0 to D3, and complementary data (e.g., complementary data D3B in block 111), and may output a data signal DQ. Blocks 111 to 114 may sample data D0 to D3 in response to pulses PL0 to PL3 and complementary pulses PL0B to PL3B.

[0031] Blocks 111 to 114 can all receive data complementary to the data sampled at the preceding pulse (or data sampled in response to the preceding pulse). For example, on a pulse sequence, block 111 can receive complementary data D3B complementary to the data D3 sampled at the preceding pulse PL3 (or data sampled in response to pulse PL3) of the corresponding pulse PL0. Blocks 111 to 113 can all equalize the edges of the data signal DQ to be output from multiplexer 110 based on the received complementary data. For example, blocks 111 to 113 can all improve the transition speed of the data signal DQ by pre-pulling down or up gating signals SG1 and SG2 based on the received complementary data.

[0032] Clock multiplexer 120 can receive clocks WCK0, WCK90, WCK180, and WCK270, and can generate pulses PL0 to PL3 and complementary pulses PL0B to PL3B based on clocks WCK0, WCK90, WCK180, and WCK270. Clock multiplexer 120 can generate pulses PL0 and complementary pulses PL0B by using clock WCK0 as a reference clock. For example, clock multiplexer 120 may include NAND gates 121 and 125 and inverters 122, 123, and 124 for generating pulses PL0 and complementary pulses PL0B.

[0033] NAND gate 121 may include an input for receiving clocks WCK0 and WCK270 and an output connected to the input of inverter 122. Inverter 122 may include an input connected to the output of NAND gate 121 and an output for outputting pulse PL0.

[0034] Inverter 123 may include an input for receiving clock WCK90 and an output connected to NAND gate 125. Inverter 124 may include an input for receiving clock WCK180 and an output connected to NAND gate 125. NAND gate 125 may include an input connected to the outputs of inverters 123 and 124 respectively, and an output for outputting a complementary pulse PL0B.

[0035] exist Figure 3 In the illustrated embodiment, clock multiplexer 120 may include components for generating pulses PL0 and complementary pulses PL0B, but the configuration of clock multiplexer 120 is not limited thereto. For example, clock multiplexer 120 may also include components for generating pulses PL1 to PL3 and complementary pulses PL1B to PL3B. The components for generating pulses PL1 to PL3 can generate pulses PL1 to PL3 and complementary pulses PL1B to PL3B by using clocks WCK90, WCK180, and WCK270 as reference clocks.

[0036] For example, clock multiplexer 120 may include a NAND gate and an inverter for generating pulse PL1. The NAND gate for generating pulse PL1 may receive clocks WCK0 and WCK90 instead of clocks WCK0 and WCK270, and may be implemented similarly to NAND gate 121. The inverter for generating pulse PL1 may include an input connected to the NAND gate for generating pulse PL1, and may be implemented similarly to inverter 122. Clock multiplexer 120 may include a first inverter, a second inverter, and a NAND gate for generating complementary pulse PL1B. The first inverter for generating complementary pulse PL1B may receive clock WCK180 instead of clock WCK90, and may be implemented similarly to inverter 123. The second inverter for generating complementary pulse PL1B may receive clock WCK270 instead of clock WCK180, and may be implemented similarly to inverter 124. The NAND gate used to generate the complementary pulse PL1B may include inputs connected to a first inverter and a second inverter used to generate the complementary pulse PL1B, and may be implemented similarly to NAND gate 125.

[0037] As described above, clock multiplexer 120 may include a NAND gate and an inverter for generating pulse PL2. For example, the NAND gate for generating pulse PL2 may receive clocks WCK180 and WCK90 instead of clocks WCK0 and WCK270, and may be implemented similarly to NAND gate 121. The inverter for generating pulse PL2 may include an input connected to the NAND gate for generating pulse PL2, and may be implemented similarly to inverter 122. Clock multiplexer 120 may include a first inverter, a second inverter, and a NAND gate for generating complementary pulse PL2B. The first inverter for generating complementary pulse PL2B may receive clock WCK270 instead of clock WCK90, and may be implemented similarly to inverter 123. The second inverter for generating complementary pulse PL2B may receive clock WCK0 instead of clock WCK180, and may be implemented similarly to inverter 124. The NAND gate used to generate the complementary pulse PL2B may include inputs connected to a first inverter and a second inverter used to generate the complementary pulse PL2B, and may be implemented similarly to NAND gate 125.

[0038] As described above, clock multiplexer 120 may include a NAND gate and an inverter for generating pulse PL3. For example, the NAND gate for generating pulse PL3 may receive clocks WCK180 and WCK270 instead of clocks WCK0 and WCK270, and may be implemented similarly to NAND gate 121. The inverter for generating pulse PL3 may include an input connected to the NAND gate for generating pulse PL3, and may be implemented similarly to inverter 122. Clock multiplexer 120 may include a first inverter, a second inverter, and a NAND gate for generating complementary pulse PL3B. The first inverter for generating complementary pulse PL3B may receive clock WCK0 instead of clock WCK90, and may be implemented similarly to inverter 123. The second inverter for generating complementary pulse PL3B may receive clock WCK90 instead of clock WCK180, and may be implemented similarly to inverter 124. The NAND gate used to generate the complementary pulse PL3B may include inputs connected to a first inverter and a second inverter used to generate the complementary pulse PL3B, and may be implemented similarly to NAND gate 125.

[0039] Block 111 may include NAND gate 210, NOR gate 220, and transistors M1 and M2. NAND gate 210 may include inputs for receiving data D0 and pulse PL0, respectively, and an output connected to the gate of transistor M1. NAND gate 210 may also receive complementary data D3B. Complementary data D3B may be complementary to data D3, which is sampled (or will be sampled) in response to pulse PL3 being the pulse immediately preceding the toggle before pulse PL0. NAND gate 210 may output a gating signal SG1 to transistor M1 based on data D0, pulse PL0, and complementary data D3B.

[0040] NOR gate 220 may include input terminals for receiving data D0 and complementary pulse PL0B respectively, and an output terminal connected to the gate of transistor M2. NOR gate 220 may also receive complementary data D3B. NOR gate 220 may output a gating signal SG2 to transistor M2 based on data D0, complementary pulse PL0B and complementary data D3B.

[0041] Transistor M1 may include a first terminal to which a voltage VDD is applied, a gate connected to the output terminal of NAND gate 210, and a second terminal connected to the first terminal of transistor M2. Transistor M1 may be turned on or off in response to a gating signal SG1. Transistor M2 may include a first terminal connected to the second terminal of transistor M1, a gate connected to the output terminal of NOR gate 220, and a second terminal to which a ground voltage is applied. Transistor M2 may be turned on or off in response to a gating signal SG2. The second terminal of transistor M1 and the first terminal of transistor M2 may be connected to the output terminal of the output data signal DQ of multiplexer 110.

[0042] The configuration and operation of blocks 112, 113, and 114 can be similar to the configuration and operation of block 111. Each of blocks 112, 113, and 114 can be implemented to correspond to the relevant data. For example, block 112 corresponding to data D1 may include NAND gates and NOR gates as follows: the NAND gate receives data D1, pulse PL1, and complementary data D0B instead of data D0, pulse PL0, and complementary data D3B and is implemented similarly to NAND gate 210; the NOR gate receives data D1, complementary pulse PL1B, and complementary data D0B instead of data D0, complementary pulse PL0B, and complementary data D3B and is implemented similarly to NOR gate 220. As described above, block 113 can be implemented to correspond to data D2, pulse PL2, and complementary data D1B, and block 114 can be implemented to correspond to data D3, pulse PL3, and complementary data D2B.

[0043] Figure 4Timing diagrams are shown of clocks WCK0, WCK90, WCK180, and WCK270, and pulses PL0, PL1, PL2, and PL3 used in a serializer 100 according to some embodiments of the present disclosure. (Refer to...) Figures 2 to 4 The clock signals WCK90, WCK180, and WCK270 input to the clock multiplexer 120 can be signals with a phase difference of a multiple of 90 degrees from clock WCK0. For example, clock WCK0 and clock WCK90 can have a 90-degree phase difference. Clock WCK0 and clock WCK180 can have a 180-degree phase difference. Clock WCK0 and clock WCK270 can have a 270-degree phase difference.

[0044] Data D0, D1, D2, and D3 can be input to multiplexer 110 synchronously with clocks WCK0, WCK90, WCK180, and WCK270. For example, data D0 can be input to multiplexer 110 synchronously with the rising edge of clock WCK0 (e.g., time points tc1, tc5, and tc9). Data D1 can be input to multiplexer 110 synchronously with the rising edge of clock WCK90 (e.g., time points tc2 and tc6). Data D2 can be input to multiplexer 110 synchronously with the rising edge of clock WCK180 (e.g., time points tc3 and tc7). Data D3 can be input to multiplexer 110 synchronously with the rising edge of clock WCK270 (e.g., time points tc4 and tc8).

[0045] Pulses PL0, PL1, PL2, and PL3 can switch in response to the rising edges of clocks WCK0, WCK90, WCK180, and WCK270, respectively. For example, pulse PL0 can switch in response to the rising edge of clock WCK0 (e.g., time points tc1, tc5, and tc9). Pulse PL1 can switch in response to the rising edge of clock WCK90 (e.g., time points tc2 and tc6). Pulse PL2 can switch in response to the rising edge of clock WCK180 (e.g., time points tc3 and tc7). Pulse PL3 can switch in response to the rising edge of clock WCK270 (e.g., time points tc4 and tc8). Clock multiplexer 120 can provide pulses PL0, PL1, PL2 and PL3 to multiplexer 110, and multiplexer 110 can sample data D0, D1, D2 and D3 in response to the rising edge of pulses PL0, PL1, PL2 and PL3.

[0046] In this disclosure, the preceding pulse of any pulse can indicate the pulse that switches immediately before the arbitrary pulse on the pulse sequence. For example, the preceding pulse of pulse PL0 can be pulse PL3; the preceding pulse of pulse PL1 can be pulse PL0; the preceding pulse of pulse PL2 can be pulse PL1; and the preceding pulse of pulse PL3 can be pulse PL2.

[0047] In this disclosure, data input before any data can indicate data input immediately preceding the arbitrary data on a pulse sequence, or data input before any data can indicate data input in response to the pulse corresponding to the arbitrary data. For example, data input to multiplexer 110 before data D1 input at time point tc2 can be data D0 input at time point tc1. Data input to multiplexer 110 before data D2 input at time point tc3 can be data D1 input at time point tc2. Data input to multiplexer 110 before data D3 input at time point tc4 can be data D2 input at time point tc3. Data input to multiplexer 110 before data D0 input at time point tc5 can be data D3 input at time point tc4.

[0048] Figure 5 A circuit diagram of the NAND gate 210 of a multiplexer 110 according to some embodiments of the present disclosure is shown. (Refer to...) Figures 2 to 5 Block 111 includes NAND gate 210, which may include transistors MND1, MND2, MND3, and MND4, as well as circuit 211. Transistors MND1 and MND2 may be implemented as PMOS transistors, and transistors MND3 and MND4 may be implemented as NMOS transistors.

[0049] Transistor MND1 may include a first terminal for which a voltage VDD1 is applied, a gate for which a pulse PL0 is applied, and a second terminal connected to the gate of transistor M1. Transistor MND2 may include a first terminal for which a voltage VDD2 is applied, a gate for which data D0 is applied, and a second terminal connected to the gate of transistor M1. Transistor MND3 may include a first terminal connected to the gate of transistor M1, a gate for which a pulse PL0 is applied, and a second terminal connected to node ND1. Transistor MND4 may include a first terminal connected to node ND1, a gate for which data D0 is applied, and a second terminal for which a ground voltage is applied.

[0050] Circuit 211 may include transistors MND5 and MND6. Transistor MND5 may include a first terminal for which an applied voltage VDD3 is applied, a gate for which data D0 is applied, and a second terminal connected to node ND1. Transistor MND6 may include a first terminal connected to node ND1, a gate for which data D3B is applied, and a second terminal for which a ground voltage is applied. Transistor MND5 may be implemented as a PMOS transistor, and transistor MND6 may be implemented as an NMOS transistor. When data D3 is sampled in block 114 in response to a rising edge pulse PL3 (or when data D3 is input to block 114), complementary data D3B may be input to block 111.

[0051] Circuit 211 can pull down the voltage level of node ND1 by a given level (e.g., to ground or close to ground) before the rising edge of pulse PL0 by using data D3 (or data D3B complementary to data D3) corresponding to pulse PL3, which is the preceding pulse of pulse PL0. This reduces the time required to lower the level of gate signal SG1 below the threshold voltage of transistor M1 in response to the next rising edge pulse PL0 and the corresponding data D0. This can mean that the transition speed of data signal DQ is faster. Consequently, inter-symbol interference (ISI) caused by the rising edge of data input from serializer 100 can be reduced.

[0052] Figure 6A and Figure 6B The operation of NAND gate 210 of multiplexer 110 according to some embodiments of the present disclosure is illustrated. (Refer to...) Figures 2 to 5 , Figure 6A and Figure 6B NAND gate 210 can output a gating signal SG1 corresponding to pulse PL0 and data D0 based on complementary data (i.e., data D3B) of data D3 corresponding to the preceding pulse PL3 of pulse PL0.

[0053] exist Figure 6A In the illustrated embodiment, data input to the serializer 100 can change at the rising edge of pulse PL0. For example, when data D3 input in response to the rising edge of the previous pulse PL3 corresponds to logic low, data D0 input in response to the rising edge of pulse PL0 can correspond to logic high.

[0054] The data D3B corresponding to logic high (i.e., "1") can be pre-applied to the gate of transistor MND6 in response to the preceding pulse PL3 of pulse PL0. Transistor MND6 can then be turned on in response to the data D3B corresponding to logic high. The voltage at node ND1 can be pulled down in response to transistor MND6 being turned on. In other words, NAND gate 210 can be understood as being pre-activated by the previous data D3.

[0055] Subsequently, a logic high pulse PL0 (or rising edge pulse PL0) can be applied to transistors MND1 and MND3, and a logic high data D0 (i.e., "1") can be applied to the gates of transistors MND2, MND4, and MND5. This allows transistors MND1, MND2, and MND5 to be turned off, while transistors MND3 and MND4 can be turned on. As a result, the level of the gate signal SG1 applied to the gate of transistor M1 can drop faster due to the voltage of the previously pulled-down node ND1 (e.g., faster than when NAND gate 210 is not pre-activated).

[0056] The level of the gate signal SG1 applied to the gate of transistor M1 can drop more quickly due to the data D3B applied to transistor MND6, thus reducing the time it takes for transistor M1 to turn on in response to data D0. As a result, the transition speed of the data signal DQ output from serializer 100 can be increased. In other words, the transition speed of the signal output from serializer 100 in response to the transition of data input to serializer 100 can be increased by circuit 211. Inter-symbol interference caused by the rising edge of the input data can be mitigated.

[0057] exist Figure 6B In the illustrated embodiment, the data input to the serializer 100 may not change at the rising edge of pulse PL0. For example, when data D3 input in response to the rising edge of the previous pulse PL3 corresponds to logic low, data D0 input in response to the rising edge of pulse PL0 may correspond to logic low.

[0058] The data D3B corresponding to logic high (i.e., "1") can be applied to the gate of transistor MND6 in advance in response to the preceding pulse PL3 of pulse PL0. Transistor MND6 can then be turned on in response to the data D3B corresponding to logic high.

[0059] Subsequently, a logic high pulse PL0 (or rising edge pulse PL0) can be applied to transistors MND1 and MND3, and a logic low data D0 (i.e., "0") can be applied to the gates of transistors MND2, MND4, and MND5. This allows transistors MND1 and MND4 to turn off, while transistors MND2, MND3, and MND5 can turn on. Due to the conduction of transistor MND5, the voltage at node ND1 can rise to a given level. As the voltage at node ND1 increases, transistor MND3 can turn off, or the magnitude of the current flowing through transistor MND3 to node ND1 can decrease. This prevents the level of the gate signal SG1 output from NAND gate 210 from falling below the threshold voltage of transistor M1. In other words, transistor MND5 can prevent abnormal operation of NAND gate 210 due to complementary data D3B and can prevent glitches.

[0060] Figure 7 A circuit diagram of the NOR gate 220 of a multiplexer 110 according to some embodiments of the present disclosure is shown. (Refer to...) Figures 2 to 4 and Figure 7 Block 111 includes NOR gate 220, which may include transistors MNR1, MNR2, MNR3, and MNR4, as well as circuit 221. Transistors MNR1 and MNR2 can be implemented as PMOS transistors, and transistors MNR3 and MNR4 can be implemented as NMOS transistors.

[0061] Transistor MNR1 may include a first terminal for which a voltage VDD4 is applied, a gate for which data D0 is applied, and a second terminal connected to node ND2. Transistor MNR2 may include a first terminal connected to node ND2, a gate for which a complementary pulse PL0B is applied, and a second terminal connected to the gate of transistor M2. Transistor MNR3 may include a first terminal connected to the gate of transistor M2, a gate for which a complementary pulse PL0B is applied, and a second terminal for which a ground voltage is applied. Transistor MNR4 may include a first terminal connected to the gate of transistor M2, a gate for which data D0 is applied, and a second terminal for which a ground voltage is applied.

[0062] Circuit 221 may include transistors MNR5 and MNR6. Transistor MNR5 may include a first terminal connected to node ND2, a gate for which data D0 is applied, and a second terminal for which a ground voltage is applied. Transistor MNR6 may include a first terminal for which voltage VDD5 is applied, a gate for which complementary data D3B is applied, and a second terminal connected to node ND2. Transistor MNR5 may be implemented as an NMOS transistor, and transistor MNR6 may be implemented as a PMOS transistor. When data D3 is sampled in block 114 in response to rising edge pulse PL3 (or when data D3 is input to block 114), complementary data D3B may be input to block 111.

[0063] Circuit 221 can pull up the voltage level of node ND2 to a given level (e.g., to voltage VDD5 or close to voltage VDD5) before the falling edge of pulse PL0B (or before the rising edge of pulse PL0) by using data D3 (or data D3B complementary to data D3) corresponding to pulse PL3, which is the preceding pulse of pulse PL0. This reduces the time required to increase the level of the gate signal SG2 above the threshold voltage of transistor M2 in response to the falling edge of pulse PL0B and the corresponding data D0. This results in a faster transition speed for the data signal DQ. Consequently, inter-symbol interference (ISI) based on the falling edge of the data input from serializer 100 can be reduced.

[0064] Figure 8A and Figure 8B The operation of the NOR gate 220 of a multiplexer 110 according to some embodiments of the present disclosure is illustrated. (Refer to...) Figures 2 to 4 , Figure 8A and Figure 8B The NOR gate 220 can output a gated signal SG2 corresponding to the complementary pulse PL0B and the data D0 based on the complementary data (i.e., data D3B) of data D3 corresponding to the preceding pulse PL3 of pulse PL0.

[0065] exist Figure 8A In the illustrated embodiment, data input to the serializer 100 can transition at the falling edge of the complementary pulse PL0B. For example, when data D3 input in response to the rising edge of the previous pulse PL3 corresponds to logic high, data D0 input in response to the falling edge of the complementary pulse PL0B can correspond to logic low.

[0066] The data D3B corresponding to logic low (i.e., "0") can be pre-applied to the gate of transistor MNR6 in response to the preceding complementary pulse PL3B. Transistor MNR6 can then be turned on in response to the data D3B corresponding to logic low. The voltage at node ND2 can be pulled up in response to transistor MNR6 being turned on. In other words, NOR gate 220 can be understood as being pre-activated by the previous data D3.

[0067] Subsequently, a complementary pulse PL0B (or a falling edge complementary pulse PL0B) corresponding to logic low can be applied to transistors MNR2 and MNR3, and data D0 (i.e., "0") corresponding to logic low can be applied to the gates of transistors MNR1, MNR4, and MNR5. This turns on transistors MNR1 and MNR2, while turning off transistors MNR3, MNR4, and MNR5. As a result, the level of the gate signal SG2 applied to the gate of transistor M2 can rise faster due to the voltage of the previously pulled-up node ND2 (e.g., faster than when NOR gate 220 is not pre-activated).

[0068] The level of the gate signal SG2 applied to the gate of transistor M2 can rise faster due to the data D3B applied to transistor MNR6, thus reducing the time required for transistor M2 to turn on in response to data D0. As a result, the transition speed of the data signal DQ output from serializer 100 can be increased. In other words, the transition speed of the signal output from serializer 100 in response to the transition of data input to serializer 100 can be increased by circuit 221. Therefore, inter-symbol interference caused by the falling edge of the input data can be improved.

[0069] exist Figure 8B In the illustrated embodiment, the data input to the serializer 100 may not change at the falling edge of the complementary pulse PL0B. For example, when data D3 input in response to the rising edge of the previous pulse PL3 corresponds to logic high, data D0 input in response to the falling edge of the complementary pulse PL0B may correspond to logic high.

[0070] The data D3B corresponding to logic low (i.e., "0") can be applied to the gate of transistor MNR6 in response to the preceding complementary pulse PL3B. Transistor MNR6 can then be turned on in response to the data D3B corresponding to logic low.

[0071] Subsequently, a complementary pulse PL0B corresponding to logic low (or a falling edge complementary pulse PL0B) can be applied to transistors MNR2 and MNR3, and data D0 (i.e., "1") corresponding to logic high can be applied to the gates of transistors MNR1, MNR4, and MNR5. This turns off transistors MNR1 and MNR3, while turning on transistors MNR2, MNR4, and MNR5. The voltage at node ND2 can drop by a given level due to the conducting transistor MNR5. As the voltage at node ND2 decreases, transistor MNR1 can turn on, or the current flowing through transistor MNR1 to node ND2 can increase. This prevents the level of the gate signal SG2 output from NOR gate 220 from exceeding the threshold voltage of transistor M2. In other words, transistor MNR5 can prevent abnormal operation of NOR gate 220 due to complementary data D3B and can prevent glitches.

[0072] Figure 9 A block diagram of a serializer 100a according to some embodiments of the present disclosure is shown. (Refer to...) Figure 1 , Figure 2 and Figure 9 The serializer 100a includes, in addition to Figure 2 In addition to the multiplexer 110 and the clock multiplexer 120, it may also include pre-drivers 112A and 113A, a main driver 112B, a de-emphasis driver 113B, and a delay circuit 113C.

[0073] The pre-driver 112A can be connected to the output of the multiplexer 110. The pre-driver 112A can preprocess the signal output from the multiplexer 110 and can transmit the preprocessed signal to the main driver 112B. The main driver 112B can transmit a signal to the output of the serializer 100a based on the signal transmitted from the multiplexer 110 through the pre-driver 112A.

[0074] Delay circuit 113C can be connected to the output of multiplexer 110. Delay circuit 113C can delay the signal output from multiplexer 110 by a unit time. For example, delay circuit 113C can delay the signal output from multiplexer 110 by the duration of the rising edge of pulse PL0 (or the duty cycle of pulse PL0). Pre-driver 113A can preprocess the signal output from delay circuit 113C and can transmit the preprocessed signal to de-emphasis driver 113B. The configuration and operation of pre-driver 113A can be similar to the configuration and operation of pre-driver 112A. De-emphasis driver 113B can attenuate the magnitude of the signal output from pre-driver 113A. For example, de-emphasis driver 113B can reduce the magnitude of the signal output from pre-driver 113A by a given ratio. In this way, the swing width of the voltage output from pre-driver 113A can be reduced. De-emphasis driver 113B can transmit the attenuated (or amplified) signal to the output of serializer 100a.

[0075] The data signal DQ output from the serializer 100a can correspond to the sum of the signals output from the master driver 112B and the deemphasis driver 113B. The magnitude of the edge of the data signal DQ (corresponding to the edge of the input data of the serializer 100a) can be increased by the signal output from the deemphasis driver 113B, thus preventing inter-symbol interference caused by the edge. However, the attenuation operation of the deemphasis driver 113B may increase the jitter (PSIJ) introduced into the data signal DQ due to power supply noise. Furthermore, since the signal output from the multiplexer 110 further passes through the delay circuit 113C, the pre-driver 113A, and the deemphasis driver 113B, the operating speed of the serializer 100a may slow down. Since the deemphasis driver 113B operates in response to clocks WCK0 to WCK270, the deemphasis driver 113B may be affected by the frequency of clocks WCK0 to WCK270 and may cause an increase in the load on clocks WCK0 to WCK270.

[0076] In some embodiments, since the serializer 100a includes a reference Figures 3 to 8B The described multiplexer 110 thus prevents inter-symbol interference and eliminates the need to strengthen the operation of driver 113B. Therefore, with Figure 9 The serializer 100a is different. Figure 2 The serializer 100 may not include the delay circuit 113C, the pre-driver 113A, and the de-emphasis driver 113B. As a result, Figure 2 The serializer 100 can have more than Figure 9 The serializer 100a has small jitter and can also be smaller than... Figure 9The serializer 100a operates quickly. Furthermore, since the operation of the multiplexer 110 is not responsive to clocks WCK0 to WCK270, the impact of clocks WCK0 to WCK270 on the output signal of the multiplexer 110 can be reduced.

[0077] Figure 10 This is a diagram of a system 1000 that utilizes a storage device according to an embodiment. Figure 10 System 1000 can fundamentally be a mobile system such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 10 The system 1000 is not necessarily limited to mobile systems, but can be a PC, laptop computer, server, media player, or automotive equipment (e.g., navigation device).

[0078] Reference Figure 10 System 1000 may include a main processor 1100, memory (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). Furthermore, system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0079] In some embodiments, at least one component of system 1000 may include Figure 1 The transmitter 11 is used to communicate with any other component of the system 1000. For example, at least one component of the system 1000 (e.g., main processor 1100, memories 1200a and 1200b, storage devices 1300a and 1300b, communication device 1440, or connection interface 1480) may include the transmitter 11, which includes... Figure 2 A serializer 100 for serializing signals generated by at least one component.

[0080] The main processor 1100 can control all operations of the system 1000, and more specifically, can control the operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0081] The main processor 1100 may include at least one CPU core 1110 and a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented using a separate chip physically independent of any other component of the main processor 1100.

[0082] Memory 1200a and 1200b can be used as the primary storage devices of system 1000. While both memory 1200a and 1200b may include volatile memory such as static random access memory (SRAM) and / or dynamic RAM (DRAM), both memory 1200a and 1200b may also include non-volatile memory such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 1200a and 1200b can be implemented in the same package as the main processor 1100.

[0083] Storage devices 1300a and 1300b can be used as non-volatile storage devices configured to store data regardless of whether power is supplied to them, and have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may each include storage controllers (STRG CTRL) 1310a and 1310b and NVMs 1320a and 1320b configured to store data via the control of storage controllers 1310a and 1310b. Although NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0084] Storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or implemented in the same package as the main processor 1100. Furthermore, storage devices 1300a and 1300b may be of the type of solid-state drive (SSD) or memory card and may be removably combined with other components of the system 100 via an interface (such as connection interface 1480 described below). Storage devices 1300a and 1300b may be devices that apply standard protocols (such as Universal Flash Memory (UFS), embedded multimedia card (eMMC), or high-speed non-volatile memory (NVMe)), but are not limited to these.

[0085] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include a camera, a portable video camera, and / or a webcam.

[0086] User input device 1420 can receive various types of data input by the user of system 1000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0087] Sensor 1430 can detect various types of physical quantities that can be acquired from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0088] Communication device 1440 can send and receive signals between other devices outside system 1000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0089] In some embodiments, the communication device 1440 may include Figure 1 The transmitter 11. For example, the communication device 1140 may include a transmitter 11 that includes: Figure 2 A serializer 100 is used to serialize signals generated in system 1000.

[0090] The display 1450 and the speaker 1460 can be used as output devices configured to output visual and auditory information to the user of the system 1000, respectively.

[0091] The power supply device 1470 can appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0092] Connection interface 1480 provides connectivity between system 1000 and external devices that are connected to system 1000 and capable of sending and receiving data from system 1000. Connection interface 1480 can be implemented using various interface schemes such as: Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0093] Figure 11 A block diagram of a memory 1200a according to some embodiments of the present disclosure is shown. (Refer to...) Figure 1 , Figure 2 , Figure 10 and Figure 11 ,include Figure 2 The transmitter 11 of the serializer 100 can be included in a semiconductor memory device such as memory 1200a.

[0094] Memory 1200a may include a memory controller 1210 and n DRAMs DRAM1 to DRAMn (n is a natural number). DRAMs DRAM1 to DRAMn can communicate with memory 1200a via a channel (e.g., 1221). Memory controller 1210 and DRAMs DRAM1 to DRAMn may include [missing information - likely related to a specific interface or feature]. Figure 2 The transmitter 11 of the serializer 100. In this way, the quality of serial communication between DRAMs DRAM1 to DRAMn in the memory 1200a can be improved. For example, inter-symbol interference of data signals output from each of DRAMs DRAM1 to DRAMn can be prevented.

[0095] According to some embodiments of this disclosure, a multiplexer can pre-adjust the voltage level of a node electrically connected to the output of the multiplexer based on second data corresponding to the preceding pulse of the first pulse and first data corresponding to the first pulse. Therefore, the switching speed of the output signal can be improved and inter-symbol interference can be reduced.

[0096] As is conventional in the art, embodiments can be described and illustrated based on blocks that perform one or more described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuitry may be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of this disclosure, each block of an embodiment may be physically separated into two or more interactive and discrete blocks. Similarly, without departing from the scope of this disclosure, the blocks of an embodiment may be physically combined into more complex blocks. One aspect of an embodiment may be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0097] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A multiplexer, comprising: The NAND gate has a pull-down switch that, based on a previous data signal input to the NAND gate and before the NAND gate receives a next clock signal and a next data signal, begins to cause the output of the NAND gate to transition from a first state to a second state, the next clock signal and the next data signal being used to determine the next output state of the NAND gate; as well as An inverter that inverts the next output state. The NAND gate includes an input terminal for receiving data and a pulse, and an output terminal. The NAND gate can output a gating signal based on the data, the pulse, and complementary data. The NAND gate includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a circuit, wherein the circuit includes a fifth transistor and a sixth transistor; The first transistor includes a first terminal to which a first voltage is applied, a gate to which the pulse is applied, and a second terminal connected to the output terminal of the NAND gate; The second transistor includes a first terminal to which a second voltage is applied, a gate to which the data is applied, and a second terminal connected to the output terminal of the NAND gate; The third transistor includes a first terminal connected to the output terminal of the NAND gate, a gate to which the pulse is applied, and a second terminal connected to the node; The fourth transistor includes a first terminal connected to the node, a gate to which the data is applied, and a second terminal to which a ground voltage is applied. The fifth transistor includes a first terminal to which a third voltage is applied, a gate to which the data is applied, and a second terminal connected to the node; and The sixth transistor includes a first terminal connected to the node, a gate to which the complementary data is applied, and a second terminal to which a ground voltage is applied.

2. The multiplexer according to claim 1, wherein, In response to the next data signal and the previous data signal having the same state and the next clock signal changing to the same state as the previous data signal, the output of the NAND gate completes the transition to the second state.

3. The multiplexer according to claim 1, wherein, The NAND gate also includes a pull-up switch, which prevents the output of the NAND gate from completing the transition to the second state in response to the next data signal having a second state when the next clock signal transitions to the first state.

4. The multiplexer according to claim 1, wherein, The pull-down switch initiates the transition of the NAND gate output from the first state to the second state by reducing the first voltage present at the node between the series-connected first and second switches. The first switch receives the next clock signal at its active terminal, and the second switch receives the next data signal at its active terminal.

5. The multiplexer according to claim 4, wherein, The pull-down switch is connected in parallel with the second switch.

6. The multiplexer according to claim 4, wherein, In response to the next clock signal activating the first switch to create a current path through both the first switch and the pull-down switch, the output of the NAND gate completes the transition to the second state.

7. The multiplexer according to claim 6, wherein, The current path extends between the output of the NAND gate and the voltage having the second state.

8. The multiplexer of claim 4, further comprising a pull-up switch, the pull-up switch responsive to the next data signal having the second state when the next clock signal transitions to the first state, pulling up the first voltage present at the node between the series-connected first switch and the second switch to prevent the output of the NAND gate from completing the transition to the second state.

9. The multiplexer according to claim 8, wherein, The pull-up switch and the pull-down switch are electrically connected in series between the voltage having the first state and the voltage having the second state.

10. The multiplexer of claim 1, further comprising a NOR gate with a pull-up switch, the pull-up switch initiating a transition of the output of the NOR gate from the second state to the first state based on a previous data signal input to the NOR gate and before the NOR gate receives a next inverted clock signal and the next data signal, the next inverted clock signal and the next data signal being used to determine the next output state of the NOR gate.

11. The multiplexer according to claim 10, wherein, In response to the next data signal and the previous data signal having the same state and the next inverted clock signal changing to the same state as the previous data signal, the output of the NOR gate completes the transition to the first state.

12. The multiplexer according to claim 10, wherein, The NOR gate also includes a pull-down switch, which prevents the output of the NOR gate from completing the transition to the first state when the next inverted clock signal has the first state.

13. The multiplexer according to claim 10, wherein, The pull-up switch initiates the transition of the output of the NOR gate from the second state to the first state by increasing a first voltage present at the node between the first and second switches connected in series. The first switch receives the next inverted clock signal at its active terminal, and the second switch receives the next data signal at its active terminal.

14. The multiplexer according to claim 13, wherein, In response to the next inverted clock signal activating the first switch to create a current path through both the first switch and the pull-up switch, the output of the NOR gate completes the transition to the first state.

15. The multiplexer according to claim 14, wherein, The current path extends between the output of the NOR gate and the voltage having the first state.

16. The multiplexer of claim 13, further comprising a pull-down switch, wherein the pull-down switch pulls down a first voltage present at a node between the series-connected first switch and the second switch in response to the next data signal having the first state when the next inverted clock signal transitions to the second state, to prevent the output of the NOR gate from completing the transition to the first state.

17. The multiplexer according to claim 16, wherein, The pull-down switch and the pull-up switch are electrically connected in series between the voltage having the first state and the voltage having the second state.

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