A multi-sampling rate channel synchronization system and method based on FPGA

Abstract

The present invention relates to an FPGA-based multi-sampling rate channel synchronization system and method, belonging to the field of software radio technology. The system solves the existing problems of data latency and distortion caused by data synchronization. The system primarily obtains user target parameter information and baseband signal information through a host computer's human-computer interaction interface and transmits at least two baseband signals to be synchronized. The system then uses a DSP to modulate the signals and delay them accordingly based on a delay time signal fed back by the FPGA to form at least two initial synchronization signals. The FPGA then calculates, adjusts, and synthesizes the signals, and finally outputs the resulting synchronization signals through a DA chip. This achieves zero-distortion and zero-delay output without consuming additional hardware resources.

Description

Technical Field

[0001] The present invention relates to the technical field of software radio, and in particular to a multi-sampling rate channel synchronization system and method based on FPGA. Background Art

[0002] Software-defined radios (SDRs) are wireless devices with a reconfigurable hardware platform that can operate across multiple communication standards. Due to their lower cost, greater flexibility, and higher performance, SDRs have rapidly become the de facto standard in military, public safety, and commercial wireless applications. Signal processing in SDRs typically requires an FPGA, which handles the computationally intensive signal processing data paths and control, minimizing system latency. When switching from one standard to another, the FPGA's reconfigurability allows for full reconfiguration to implement the data paths for a specific standard.

[0003] Multi-rate signal processing is key to achieving digital signal processing in software-defined radio (SDR). Increasing the sampling rate improves the signal-to-noise ratio (SNR) of the sampled quantization, but the high rate of the post-sampling data stream can hinder subsequent signal processing. In particular, for some synchronous demodulation algorithms, computationally intensive, high data throughput makes it difficult to meet real-time requirements. Therefore, it is necessary to reduce the data stream speed after the DA chip. Multi-rate signal processing technology provides the theoretical basis for implementing this reduction. However, multi-rate signal processing involves the issue of synchronization between signals with different sampling rates.

[0004] Generally, multi-rate signals are completely independent and do not affect each other. However, differences in sampling rate, modulation method, processor processing delay, and path delay can lead to significant delay differences between different signals. To address this issue, the current method is to estimate a maximum delay, discard the data from the remaining signals that are output first, and then output it together with the signal with the maximum delay. However, this approach comes with two problems: 1. Data loss causes distortion; 2. The maximum delay is estimated, and each adjustment to the sampling rate and modulation method will cause a change in delay. Therefore, the delay needs to be reserved according to the maximum, which in turn leads to greater data distortion. Therefore, a method that can guarantee both zero delay and zero distortion is urgently needed. Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide an FPGA-based multi-sampling channel synchronization system and method to solve the existing problem of achieving zero-distortion and zero-delay output without consuming additional hardware resources.

[0006] On the one hand, an embodiment of the present invention provides a multi-sampling rate channel synchronization system based on FPGA, comprising: a host computer, a DSP, an FPGA, and a DA chip;

[0007] The host computer is used to obtain target parameter information and baseband signal information input by the user through the human-computer interaction interface and send down at least two baseband signals to be synchronized;

[0008] A DSP, configured to modulate at least two of the baseband signals based on the baseband signal information to obtain modulated signals, and to delay the at least two baseband signals accordingly based on the delay time signal fed back by the FPGA to form at least two initial synchronization signals;

[0009] FPGA, configured to obtain a delay time signal between at least two baseband signals according to the modulated signal; and adjust at least two initial synchronization signals based on the target parameter information to obtain at least two target synchronization signals and perform signal synthesis;

[0010] The DA chip is used to convert the synthesized signal into an analog signal for output.

[0011] Based on the above solution, the embodiment of the present invention further makes the following improvements:

[0012] Optionally, the baseband signal information includes modulation mode information of the baseband signal;

[0013] The DSP performs the following process to modulate at least two baseband signals based on the baseband signal information to obtain modulated signals:

[0014] Taking a small segment from at least two baseband signals to obtain a microsecond level signal;

[0015] The modulated signal is obtained by modulating a microsecond signal obtained by taking any small segment thereof based on the modulation mode information.

[0016] Optionally, the FPGA executes the following process to obtain a delay time signal between at least two baseband signals based on the modulated signal, specifically including:

[0017] The FPGA starts timing at the first point of receiving the first signal, stops timing at the first point of receiving the second signal, and latches the result to obtain the time difference t2,1 between the first and second signals.

[0018] Start timing at the first point when the i-1th signal is received, stop timing at the first point when the i-th signal is received, and obtain the time difference between the i-th and i-1th signals; where i ranges from 2 to n, and n is the number of baseband signals;

[0019] Based on the time difference, the delay time of the first signal is calculated using a formula;

[0020] Among them, the first, second, ..., i, ..., n-way signals are obtained in sequence according to the time when the FPGA receives the first point of the modulated signal.

[0021] Optionally, the DSP executes the following process to delay at least two baseband signals accordingly based on the delay time signal fed back by the FPGA to form at least two initial synchronization signals, specifically including:

[0022] The DSP directly generates the first channel initial synchronization signal according to the baseband signal corresponding to the first channel signal;

[0023] Based on the delay time of the i-th signal, the baseband signal corresponding to the i-th signal is delayed by a corresponding time to obtain the i-th initial synchronization signal.

[0024] Optionally, the target parameter information includes: a target sampling rate; the target sampling rate is consistent with a fixed sampling rate of the DA chip;

[0025] The FPGA executes the following process to adjust at least two of the initial synchronization signals based on the target parameter information:

[0026] Obtaining an interpolation multiple according to the initial sampling rate of the modulated signal and the target sampling rate;

[0027] The initial synchronization signal is interpolated and filtered using the interpolation multiple.

[0028] Optionally, the interpolation factor = target sampling rate ÷ initial sampling rate.

[0029] Optionally, the target parameter information further includes a target amplitude and a target frequency;

[0030] The FPGA executes the following process to adjust at least two of the initial synchronization signals based on the target parameter information:

[0031] Frequency shifting and amplitude modulation are performed on each signal after interpolation filtering based on the target amplitude and the target frequency to obtain at least two target synchronization signals, and the obtained target synchronization signals are synthesized.

[0032] On the other hand, an embodiment of the present invention further provides a multi-sampling rate channel synchronization method based on FPGA, specifically comprising:

[0033] S1: Check the normal operation of the circuit and the operation status of the FPGA chip, obtain target parameter information and baseband signal information through the host computer, and send at least two baseband signals to be synchronized and the above information to the DSP through the host computer;

[0034] S2: The DSP modulates at least two baseband signals to obtain modulated signals; and sends the modulated signals and the received target parameter information to the FPGA;

[0035] S3: FPGA calculates the difference between the above modulated signals to obtain the delay time;

[0036] S4: The DSP generates an initial synchronization signal based on the delay times of the above-mentioned respective paths and at least two baseband signals;

[0037] S5: FPGA adjusts the initial synchronization signal based on the target parameter information to obtain the target synchronization signal, and synthesizes the target synchronization signal into one channel;

[0038] S6: DA chip output signal.

[0039] Optionally, the FPGA executes the following process to obtain a delay time signal between at least two baseband signals based on the modulated signal, specifically including:

[0040] The FPGA starts timing at the first point of receiving the first signal, stops timing at the first point of receiving the second signal, and latches the result to obtain the time difference t2,1 between the first and second signals.

[0041] Start timing at the first point when the i-1th signal is received, stop timing at the first point when the i-th signal is received, and obtain the time difference between the i-th and i-1th signals; where i ranges from 2 to n, and n is the number of baseband signals;

[0042] Based on the time difference, the delay time of the first signal is calculated using a formula;

[0043] Among them, the first, second, ..., i, ..., n-way signals are obtained in sequence according to the time when the FPGA receives the first point of the modulated signal.

[0044] Optionally, the target parameter information includes a target sampling rate; and the adjusting the initial synchronization signal based on the target parameter information in S5 includes:

[0045] Obtaining an interpolation multiple according to the initial sampling rate of the modulated signal and the target sampling rate;

[0046] Performing interpolation filtering on the initial synchronization signal using the interpolation multiple;

[0047] Where, interpolation factor = target sampling rate ÷ initial sampling rate.

[0048] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0049] 1. Difference calculation and interpolation filtering can be achieved only through FPGA, without consuming processor computing resources or additional hardware resources.

[0050] 2. By modulating a small segment (microsecond level) of at least two selected baseband signals and performing other information processing, each modulated signal is relatively short, which can ensure that the FPGA can calculate the delay time signal in a relatively short time, saving computing time and computing resources, and thus achieving the goal of zero distortion and zero delay output.

[0051] 3. The delay is calculated by the time difference between the first points of each modulated signal. The calculation method is simple and efficient.

[0052] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0054] Figure 1 This is a structural diagram of the prior art system;

[0055] Figure 2 It is a flow chart of signal processing in the prior art;

[0056] Figure 3 The figure is a schematic structural diagram of a multi-sampling rate channel synchronization system based on FPGA according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0058] like Figure 1-2 As shown, the system structure diagram in the prior art and the signal processing flow chart in the prior art.

[0059] A specific embodiment of the present invention discloses a multi-sampling rate channel synchronization system based on FPGA, such as Figure 3 As shown. Specifically including: host computer, digital signal processor, FPGA, DA chip. Among them,

[0060] The host computer obtains the target parameter information and baseband signal information input by the user through the human-computer interaction interface and sends at least two baseband signals to be synchronized to the DSP. Specifically, the target parameter information input by the user includes the target sampling rate, target amplitude and target frequency; the baseband signal information includes the modulation method corresponding to the baseband signal. The target sampling rate is consistent with the fixed sampling rate of the DA chip. The target amplitude refers to the amplitude after signal synchronization, and the target frequency refers to the frequency after signal synchronization; there can be many modulation methods corresponding to the baseband signal, such as amplitude modulation, phase modulation, and frequency modulation, and any modulation method can be applied. The initial sampling rate of the above-mentioned at least two baseband signals is generally less than 100M. For DSP, the lower the sampling rate, the better, because the higher the sampling rate, the slower the DSP modulation and the more resources it needs to consume; the target sampling rate required is generally higher, and the initial sampling rate here is much lower than the target sampling rate. The initial sampling rate is the sampling rate of the baseband signal.

[0061] The DSP (digital signal processor) is used to modulate a small segment of each baseband signal according to the baseband signal and modulation method sent by the host computer to obtain the modulated signals, namely the modulated signals.

[0062] Specifically, for at least two baseband signals to be synchronized, only a small segment of the baseband signal (microsecond level) in each signal needs to be modulated, because it takes a long time for the DSP to process all the signals, so selecting a small segment of the baseband signal is sufficient.

[0063] The DSP is also used to send each modulation signal, target sampling rate, target amplitude, and target frequency to the FPGA. The sent modulation signals are used by the FPGA to calculate the delay time signal. The shortness of each modulation signal ensures that the FPGA can calculate the delay time signal in a relatively short time, saving computing time and resources.

[0064] The DSP is used to generate an initial synchronization signal based on at least two baseband signals and send it to the FPGA after receiving the delay time signal fed back by the FPGA. The delay time signal is calculated by the FPGA based on the time difference of each signal received.

[0065] FPGA is used to calculate the difference based on the time difference of each modulated signal received, and obtain the delayed time signal to feed back to DSP.

[0066] Specifically, when the FPGA performs difference calculations, it needs to know the frequency of the FPGA system clock. T max is the period of the system clock; at the same time, we also need to know the time difference between the various signals, and then use the formula T i =ti,i-1 ×F max Calculate the delay time; where T i Refers to the delay time of the i-th signal, t i,i-1 is the time difference between the i-th and i-1-th signals, where i ranges from 2 to n, and n is the total number of baseband signals. The time difference between the i-th and i-1-th signals is calculated as follows: the FPGA starts timing at the first point when it receives any signal, and takes the signal corresponding to the first point as the first signal. When the first point of the second signal is received, the counter is stopped and the result is latched. This is the time difference between the first and second signals. This can be deduced by analogy. If there are n signals, there will be n-1 signal time differences.

[0067] The delayed time signal is fed back to the DSP, and the DSP directly generates the first signal. Since the newly generated signals are all based on the first signal, the first signal has no delay, that is, the newly generated first signal is the original baseband signal.

[0068] The second path starts to have a time delay. The second to nth path signals are generated according to the time difference between the second path and the first path and the frequency of the system clock. The calculation method is: T i =t i,i-1 ×F max Based on this, the 3rd to 5th delayed signals are generated in sequence. At this time, the generated n signals are synchronized, which is the above-mentioned initial synchronization signal.

[0069] The FPGA is also used to receive the target sampling rate, target amplitude, target frequency, and initial synchronization signal issued by the DSP, and adjust the initial synchronization signal to obtain a target synchronization signal. At this time, the sampling rate, amplitude, and frequency of the target synchronization signal are consistent with the target sampling rate, target amplitude, and target frequency input by the user.

[0070] Specifically, since the initial sampling rate is very different from the target sampling rate, the initial synchronization signal needs to be interpolated and filtered. The interpolation factor is calculated according to the following formula:

[0071] It is worth noting that: because the final target sampling rate is fixed, the target sampling rate determines the selection of DA chip to some extent.

[0072] After obtaining the interpolated n synchronous signals, they are fine-tuned based on the target amplitude and frequency. This fine-tuning process yields n target synchronous signals whose amplitude and frequency meet the user's initial requirements. These n target synchronous signals are then synthesized into one signal, which is then transmitted to the DA chip. This synthesis is done because the DA chip has only one input and output. The DA chip then converts the signal into an analog signal for output.

[0073] Specifically, if the target sampling rate is 3GHz, a 3GHz DA chip is selected. If the low-sampling-rate signal after DSP modulation is 10M sampling rate, 300x interpolation filtering is required. The FPGA frequency-shifts and amplitude-modulates the interpolated n synchronous signals according to the target frequency and amplitude. These signals are then combined into a single signal and output to the DA chip, which converts the signal into an analog signal for output.

[0074] For example, taking 5-way signals as an example, the FPGA starts counting after receiving the 5-way signals modulated by the DSP. Specifically, it starts counting after receiving the first point of the first signal of the 5-way signal (any of the 5-way signals can arrive first). When the first point of the second signal is received, the counter result A is latched. When the first point of the third signal is received, the counter result B is latched. And so on. The 5-way signals can obtain four counter results A, B, C, and D, that is, the 5-way signals obtain 4 time intervals.

[0075] After obtaining the four counter results, we calculate the delays of the five signals. Specifically, assuming the FPGA system clock is 100MHz, one counter tick represents 10ns. This gives us the delay differences between the five signals: the delay between the first and second signals is Ax10ns; the delay between the second and third signals is (BA)x10ns; the delay between the third and fourth signals is (CB)x10ns; and the delay between the fourth and fifth signals is (DC)x10ns.

[0076] The feedback delay signal is the delayed signal calculated by the FPGA and fed back to the DSP. Upon receiving the delayed signal from the FPGA, the DSP immediately generates the first signal. It then generates a new second signal based on the time difference A x 10ns between the first and second signals. Similarly, a new third signal is generated by delaying (BA) x 10ns, a new fourth signal by delaying (CB) x 10ns, and a new fifth signal by delaying (DC) x 10ns.

[0077] After generating 5 initial synchronization signals, they are adjusted according to the frequency and amplitude values sent by the host computer. The 5 target synchronization signals with adjusted frequency and amplitude are synthesized into one signal and output to the DA chip.

[0078] After passing through the DA chip, the 5-channel target synchronization signals are converted from digital signals to analog signals and finally output.

[0079] Another embodiment of the present invention discloses a multi-sampling rate channel synchronization method based on FPGA, which specifically includes:

[0080] S1: Check the normal operation of the circuit and the operation status of the FPGA chip, obtain target parameter information and baseband signal information through the host computer, and send at least two baseband signals to be synchronized and the above information to the DSP through the host computer.

[0081] The host computer obtains the target parameter information and baseband signal information input by the user through the human-computer interaction interface and sends at least two baseband signals to be synchronized to the DSP. Specifically, the target parameter information input by the user includes the target sampling rate, target amplitude and target frequency; the baseband signal information includes the modulation method corresponding to the baseband signal. The target sampling rate is consistent with the fixed sampling rate of the DA chip. The target amplitude refers to the amplitude after signal synchronization, and the target frequency refers to the frequency after signal synchronization; there can be many modulation methods corresponding to the baseband signal, such as amplitude modulation, phase modulation, and frequency modulation, and any modulation method can be applied. The initial sampling rate of the above-mentioned at least two baseband signals is generally less than 100M. For DSP, the lower the sampling rate, the better, because the higher the sampling rate, the slower the DSP modulation and the more resources it needs to consume; the target sampling rate required is generally higher, and the initial sampling rate here is much lower than the target sampling rate. The initial sampling rate is the sampling rate of the baseband signal.

[0082] S2: The DSP modulates at least two baseband signals to obtain modulated signals; and sends the modulated signals and the received target parameter information to the FPGA.

[0083] The DSP modulates a small segment of each baseband signal according to the baseband signal and modulation method sent by the host computer to obtain the modulated signals, namely the modulated signals.

[0084] Specifically, for at least two synchronized baseband signals sent down, only a small segment of baseband signal (microsecond level) from each signal needs to be selected for modulation, because it takes a long time for DSP to process all signals, so selecting a small segment of baseband signal is sufficient.

[0085] The DSP is also used to send each modulation signal, target sampling rate, target amplitude, and target frequency to the FPGA;

[0086] S3: FPGA calculates the difference based on the above modulated signals to obtain the delay time.

[0087] FPGA is used to calculate the difference based on the time difference of each modulated signal received, and obtain the delayed time signal to feed back to DSP.

[0088] Specifically, when the FPGA performs difference calculations, it needs to know the frequency of the FPGA system clock. T max is the period of the system clock; at the same time, we also need to know the time difference between each signal, Ti =t i,i-1 ×F max Among them, T i Refers to the delay time of the i-th signal, t i,i-1 is the time difference between the i-th and i-1-th signals, i ranges from 2 to n, and n is the total number of baseband signals; the time difference between the i-th and i-1-th signals is calculated as follows: the FPGA starts timing at the first point when it receives any signal, stops the counter when it receives the first point of the second signal, and latches the result, which is the time difference between the first and second channels. And so on, if there are n signals, there will be n-1 signal time differences.

[0089] S4: The DSP generates an initial synchronization signal based on the delay times of the above-mentioned respective paths and at least two baseband signals.

[0090] After receiving the feedback delay time signal, the DSP generates an initial synchronization signal based on at least two baseband signals and sends it to the FPGA.

[0091] The delayed time signal is fed back to the DSP, and the DSP directly generates the first signal. Since the newly generated signals are all based on the first signal, the first signal has no delay, that is, the newly generated first signal is the original baseband signal.

[0092] The second path starts to have a time delay. The second to nth path signals are generated according to the time difference between the second path and the first path and the frequency of the system clock. The calculation method is: T i =t i,i-1 ×F max Based on this, the 3rd to 5th delayed signals are generated in sequence. At this time, the generated n signals are synchronized with each other and are the initial synchronization signals.

[0093] S5: The FPGA interpolates and filters the initial synchronization signal based on the target parameter information, adjusts it, and obtains the target synchronization signal, which is then synthesized into one channel. This adjustment includes interpolation filtering, frequency shifting, and amplitude modulation based on the target sampling rate, target frequency, and target amplitude.

[0094] The FPGA receives the initial synchronization signal from the DSP. However, since the initial sampling rate is significantly different from the target sampling rate, an interpolation filter calculation is performed on the initial synchronization signal. The interpolation factor is calculated using the following formula:

[0095] Interpolation multiple = fixed sampling rate of DA chip ÷ initial sampling rate

[0096] It is worth noting that: because the final target sampling rate is fixed, the target sampling rate determines the selection of DA chip to some extent.

[0097] After obtaining the interpolated n-channel synchronization signals, the above signals are fine-tuned according to the target amplitude and target frequency, and the n-channel target synchronization signals whose amplitude and frequency meet the user's initial requirements are obtained through fine-tuning.

[0098] Since the DA chip has only one input and output, the n-way target synchronization signals after fine-tuning are synthesized and then transmitted to the DA chip after synthesizing one signal.

[0099] S6: DA chip output signal.

[0100] Finally, the DA chip is used to convert the signal into an analog signal and output it.

[0101] In the above embodiment, the DSP pre-modulates the baseband signal to generate a microsecond-level signal, allowing calculation of the delay time for each channel. This enables automatic alignment of signals with different sampling rates, saving computation time and resources. Furthermore, after initial synchronization of the baseband signal, the signal can be automatically adjusted according to the preset target sampling rate, target frequency, and target amplitude. The present invention only requires microseconds of time during FPGA initialization to calculate the different delays for different signals, which is completely negligible.

[0102] Secondly, the desired sampling rate is fixed, but the initial sampling rate is not. Therefore, depending on the actual application requirements, the DSP will generate signals at different sampling rates. When performing interpolation filtering, the signal must be interpolated at multiples of the initial sampling rate. The interpolated value is typically zero, with the number of interpolated values being zero. After interpolation, a filter is then applied to remove the image, completing the final sampling rate conversion. (The interpolated value can also be other numbers, such as the average, but the standard approach is to interpolate zeros.)

[0103] Compared with the prior art, because signals of different rates in the same system have different delays, if they are not synchronized, they will be output sequentially, resulting in asynchronous system output. For example, when several voice, text, and image signals are transmitted simultaneously, they are originally input into the system, but due to the different modulation schemes (AM, FM, ASK, etc.) used by these signals, the output becomes asynchronous. Therefore, the present embodiment provides an FPGA-based multi-sampling rate channel synchronization method. This method provides a synchronization method for signals of different sampling rates in FPGA-based multi-sampling rate signal processing. This method does not require data loss, processor computing resources, or additional hardware resources, and achieves automated synchronization between different sampling rates, with zero distortion and zero delay, and only adds microseconds of additional time during initialization. This method consumes few hardware resources, is simple to implement, and has strong portability.

[0104] In order to achieve signal synchronization of different sampling frequencies, the present invention specifically relates to a system for synchronously outputting different sampling rate signals in a multi-sampling rate signal based on FPGA. In multi-sampling rate signal processing applications, the processing delays of signals of different sampling rates are different. If not processed, the delay differences of the output signals will be obvious. If processed, distortion will be generated or a large amount of resource consumption will be caused. In the present invention, the FPGA automatically calculates the delay of each sampling rate signal and feeds the delay back to the processor. In the case where the modulation mode is changed or the sampling rate is changed, resulting in a change in the delay, the present invention can also calculate the changed delay and feed it back. The processor can simply delay different signals according to the delay fed back by the FPGA to achieve zero delay and zero distortion between the output signals of each sampling rate, while also avoiding the use of a large amount of hardware resources.

[0105] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0106] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A multi-sampling rate channel synchronization system based on FPGA, characterized in that: include: Host computer, DSP, FPGA, DA chip; The host computer is used to obtain target parameter information and baseband signal information input by the user through the human-computer interaction interface and send down at least two baseband signals to be synchronized; A DSP, configured to modulate at least two of the baseband signals based on the baseband signal information to obtain modulated signals, and to delay the at least two baseband signals accordingly based on the delay time signal fed back by the FPGA to form at least two initial synchronization signals; An FPGA is configured to obtain a delay time signal between at least two baseband signals based on the modulated signal; and to adjust at least two initial synchronization signals based on the target parameter information to obtain at least two target synchronization signals and perform signal synthesis; wherein the target parameter information includes a target sampling rate, a target amplitude, and a target frequency, and the target sampling rate is consistent with the fixed sampling rate of the DA chip; an interpolation multiple is obtained based on the initial sampling rate and the target sampling rate of the modulated signal; the initial synchronization signal is interpolated and filtered using the interpolation multiple; and each signal after the interpolation and filtering is frequency shifted and amplitude modulated based on the target amplitude and the target frequency to obtain at least two target synchronization signals, and the obtained target synchronization signals are synthesized; The DA chip is used to convert the synthesized signal into an analog signal for output.

2. The FPGA-based multi-sampling rate channel synchronization system according to claim 1, characterized in that: The baseband signal information includes modulation mode information of the baseband signal; The DSP performs the following process to modulate at least two baseband signals based on the baseband signal information to obtain modulated signals: Taking a small segment from at least two baseband signals to obtain a microsecond level signal; The modulated signal is obtained by modulating a microsecond signal obtained by taking any small segment thereof based on the modulation mode information.

3. The FPGA-based multi-sampling rate channel synchronization system according to any one of claims 1-2, characterized in that: The FPGA executes the following process to obtain a delay time signal between at least two baseband signals based on the modulated signal, specifically including: FPGA starts timing at the first point of receiving the first signal, stops timing at the first point of receiving the second signal, and latches the result to obtain the time difference t between the first and second channels. 2,1 ; Start timing at the first point when the i-1th signal is received, and stop timing at the first point when the i-th signal is received. The time difference t between the i-th and i-1th signals is obtained. i,i-1 ; Wherein, i ranges from 2 to n, and n is the number of baseband signals; Based on the time difference t i,i-1 , using the formula T i =t i,i-1 ×F max Calculate the delay time T of the i-th signal i ; Among them, the first, second, ..., i, ..., n-way signals are obtained in sequence according to the time when the FPGA receives the first point of the modulated signal.

4. The FPGA-based multi-sampling rate channel synchronization system according to claim 3, characterized in that: The DSP executes the following process to delay at least two baseband signals accordingly based on the delay time signal fed back by the FPGA to form at least two initial synchronization signals, specifically including: The DSP directly generates the first channel initial synchronization signal according to the baseband signal corresponding to the first channel signal; Based on the delay time T of the i-th signal i The baseband signal corresponding to the i-th signal is delayed by a corresponding time to obtain the i-th initial synchronization signal.

5. The FPGA-based multi-sampling rate channel synchronization system according to claim 1, characterized in that: Interpolation factor = target sampling rate ÷ initial sampling rate.

6. A multi-sampling rate channel synchronization method based on FPGA, characterized in that: Specifically include: S1: Check the normal operation of the circuit and the operation status of the FPGA chip, obtain target parameter information and baseband signal information through the host computer, and send at least two baseband signals to be synchronized and the above information to the DSP through the host computer; S2: The DSP modulates at least two baseband signals to obtain modulated signals; and sends the modulated signals and the received target parameter information to the FPGA; S3: FPGA calculates the difference between the above modulated signals to obtain the delay time; S4: The DSP generates an initial synchronization signal based on the delay times of the above-mentioned respective paths and at least two baseband signals; S5: The FPGA performs interpolation filtering and adjustment on the initial synchronization signal based on the target parameter information to obtain a target synchronization signal, and synthesizes the target synchronization signals into one channel; the target parameter information includes a target sampling rate, a target amplitude, and a target frequency, and the target sampling rate is consistent with the fixed sampling rate of the DA chip. An interpolation multiple is obtained according to the initial sampling rate of the modulated signal and the target sampling rate, and the initial synchronization signal is interpolated and filtered using the interpolation multiple. Based on the target amplitude and the target frequency, each signal after the interpolation filtering is frequency shifted and amplitude modulated to obtain at least two channels of the target synchronization signals, and the obtained target synchronization signals are synthesized; S6: DA chip output signal.

7. The FPGA-based multi-sampling rate channel synchronization method according to claim 6, characterized in that: The FPGA executes the following process to obtain a delay time signal between at least two baseband signals based on the modulated signal, specifically including: FPGA starts timing at the first point of receiving the first signal, stops timing at the first point of receiving the second signal, and latches the result to obtain the time difference t between the first and second channels. 2,1 ; Start timing at the first point when the i-1th signal is received, and stop timing at the first point when the i-th signal is received. The time difference t between the i-th and i-1th signals is obtained. i,i-1 ; Wherein, i ranges from 2 to n, and n is the number of baseband signals; Based on the time difference t i,i-1 , using the formula T i =t i,i-1 ×F max Calculate the delay time T of the i-th signal i ; Among them, the first, second, ..., i, ..., n-way signals are obtained in sequence according to the time when the FPGA receives the first point of the modulated signal.

8. The FPGA-based multi-sampling rate channel synchronization method according to claim 6, characterized in that: The interpolation multiple in S5 = target sampling rate ÷ initial sampling rate.

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