Solid-state imaging device, driving method of solid-state imaging device, and electronic equipment

Abstract

A solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device are provided that can read signals having different conversion gains and different signal directions. A pixel signal processing unit 400 includes a first reading unit 410 that inverts the signal direction of a first conversion gain signal (HCGRST, HCGSIG) among the pixel signals PIXOUT input to an input node ND401 and inputs the inverted first conversion gain signal (HCGRST, HCGSIG) after inversion and amplification processing to an AD converter 430 via a connection node ND402. A second reading unit 420 maintains the signal direction of a second conversion gain signal (LCGSIG, LCGRST) among the pixel signals PIXOUT input to the input node ND401 and inputs the non-inverted second conversion gain signal (LCGSIG, LCGRST) to the AD converter 430 via a connection node ND402.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and electronic equipment. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors have been put into practical use as solid-state imaging devices (image sensors) using photoelectric conversion elements that detect light and generate electric charges.

[0003] CMOS image sensors are widely used as a part of various electronic devices including digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0004] CMOS image sensors have an FD amplifier in each pixel, including a photodiode (photoelectric conversion element) and a floating diffusion layer (FD). The mainstream reading type of this CMOS image sensor is column-parallel output, that is, a row in the pixel array is selected and read simultaneously in the column output direction.

[0005] In addition, each pixel of the solid-state imaging device (CMOS image sensor) can be a basic pixel composed of 4 transistors (4Tr), for example, corresponding to 1 photodiode (photoelectric conversion element), each having a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element, and a selection transistor as a selection element.

[0006] The transfer transistor is selected and turned on during a predetermined transfer period, and transfers the charges (electrons) photoelectrically converted and accumulated by the photodiode to the floating diffusion layer FD.

[0007] The reset transistor is selected and turned on during a predetermined reset period, thereby resetting the floating diffusion layer FD to the potential of the power supply line.

[0008] The selection transistor is selected and turned on during read scanning, thereby causing the source follower transistor to output the column output read signal converted into a voltage signal by the floating diffusion layer FD to the vertical signal line.

[0009] For example, during a read scan, after the floating diffusion layer FD is reset to, for example, the potential of a power line (reference potential) during a reset period, the charge of the floating diffusion layer FD has a gain corresponding to the FD capacitance and is converted into a voltage signal, which is output to the vertical signal line as a read reset signal (reference level signal) Vrst of a reference level.

[0010] Next, during a predetermined transfer period, the charge (electrons) photoelectrically converted and accumulated in the photodiode is transferred to the floating diffusion layer FD. The charge in the floating diffusion layer FD is then converted into a voltage signal with a gain corresponding to the FD capacitance, and output to the vertical signal line as a read signal (signal at a signal level) Vsig.

[0011] The output signal of the pixel is processed as a difference signal (Vsig-Vrst) by CDS (Correlated Double Sampling) in the column reading circuit.

[0012] As described above, a normal pixel read signal (hereinafter also referred to as a pixel signal) PS is formed by a read reset signal Vrst of a reference level and a read signal Vsig of a signal level.

[0013] In order to improve the performance thereof, various methods have been proposed for realizing a high-quality solid-state imaging device (CMOS image sensor) having a high dynamic range (HDR).

[0014] One method of increasing the dynamic range is to use a lateral overflow integration capacitor (LOFIC) structure (see, for example, Patent Document 1).

[0015] The pixel of the LOFIC structure adds an accumulation capacitor and an accumulation transistor to the above basic structure. The supersaturated charge overflowing from the photodiode during the same exposure time is not discarded but accumulated in the accumulation capacitor.

[0016] This LOFIC pixel can have two types of conversion gains: a conversion gain based on the capacitance Cfd1 of the floating diffusion layer (high gain side: proportional to 1 / Cfd1), and a conversion gain based on the LOFIC capacitance Clofic of the capacitance Cfd1 of the floating diffusion layer plus the accumulation capacitance C2 (low gain side: proportional to 1 / (Cfd1+Cloric)).

[0017] In other words, in a LOFIC pixel, a low conversion gain (LCG) signal and a high conversion gain (HCG) signal are used to achieve large saturation and small dark noise, respectively.

[0018] Prior art literature

[0019] Patent Literature

[0020] Patent Document 1: Japanese Patent Application Laid-Open No. 2005-328493

[0021] Patent Document 2: Japanese Patent Application Laid-Open No. 2020-115603 Summary of the Invention

[0022] Technical problems to be solved by the present invention

[0023] However, LOFIC has a significant problem in that the SNR is degraded at the junction (junction) of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal.

[0024] In other words, the kTC noise of the LCG signal cannot be eliminated by the LOFIC configuration alone, so the SNR at the junction of the HCG signal and the LCG signal is reduced.

[0025] For example, Patent Document 2 proposes a specific circuit structure of a pixel signal processing unit in a reading circuit of a solid-state imaging device. Although it is not targeted at LOFIC, it can eliminate the noise gap at the junction of low conversion gain data and high conversion gain data, suppress the increase in power consumption and circuit area, and achieve a high dynamic range.

[0026] In addition, in a CMOS image sensor with a LOFIC structure, the signal directions of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, that is, the level transition directions of each other are opposite, so a dual readout circuit is required.

[0027] However, the pixel signal processing unit in the reading circuit described in the above-mentioned patent document 2 is difficult to directly apply to a CMOS image sensor with a LOFIC structure because it can read both the HCG signal and the LCG signal generated by a single exposure HDR (SEHDR) pixel with the same signal direction.

[0028] In addition, in order to realize a dual readout circuit applicable to a CMOS image sensor having a LOFIC structure, in order to reduce chip costs, a readout circuit that can process both LCG and HCG signals with minimal circuit overhead and achieve low power consumption is required.

[0029] The present invention provides a solid-state imaging device capable of reading signals having different conversion gains and mutually different signal directions, a driving method of the solid-state imaging device, and electronic equipment.

[0030] The present invention provides a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device, which can not only read signals with different conversion gains and different signal directions, but also suppress the increase in power consumption and circuit area, and can achieve a high dynamic range and high image quality.

[0031] Solutions to the Problem

[0032] A solid-state imaging device according to a first aspect of the present invention includes: a pixel reading unit that performs photoelectric conversion and can read a first conversion gain signal and a second conversion gain signal having opposite signal directions corresponding to at least two conversion gains as pixel signals; and a pixel signal processing unit that processes the pixel signal read from the reading pixel; the pixel signal processing unit includes: an input node that inputs the pixel signal read from the reading pixel; a connecting node that is connected to a secondary circuit; a first reading unit that inverts the signal direction of the first conversion gain signal among the pixel signals input to the input node and outputs the inverted first conversion gain signal to the connecting node; and a second reading unit that maintains the signal direction of the second conversion gain signal among the pixel signals input to the input node and outputs the non-inverted second conversion gain signal to the connecting node.

[0033] A second aspect of the present invention is a method for driving a solid-state imaging device, the solid-state imaging device comprising: a pixel reading unit that performs photoelectric conversion and can read a first conversion gain signal and a second conversion gain signal having signal directions in opposite directions corresponding to at least two conversion gains as pixel signals; and a pixel signal processing unit that processes the pixel signal read from the reading pixel; the pixel signal processing unit comprising: an input node that inputs the pixel signal read from the reading pixel; a connection node that is connected to a secondary circuit; a first reading unit that inverts the signal direction of the first conversion gain signal among the pixel signals input to the input node and outputs the inverted first conversion gain signal to the A connecting node; a second reading unit, which maintains the signal direction of the second conversion gain signal among the pixel signals input to the input node, and outputs the non-inverted second conversion gain signal to the connecting node, the driving method comprising: in a first conversion gain signal reading mode, in the first reading unit, performing an inverted reading of the first reading reset signal with the first conversion gain, and then performing an inverted reading of the first reading brightness signal with the first conversion gain; in a second conversion gain signal reading mode, in the second reading unit, performing a non-inverted reading of the second reading brightness signal with the second conversion gain, and then performing a non-inverted reading of the second reading reset signal with the second conversion gain.

[0034] An electronic device according to a third aspect of the present invention comprises: a solid-state imaging device; and an optical system for imaging an image of a subject on the solid-state imaging device; the solid-state imaging device comprises: a reading pixel, performing photoelectric conversion, capable of reading a first conversion gain signal and a second conversion gain signal having opposite signal directions corresponding to at least two conversion gains as pixel signals; and a pixel signal processing unit for processing the pixel signal read from the reading pixel; the pixel signal processing unit comprises: an input node for inputting the pixel signal read from the reading pixel; a connecting node for connecting to a secondary circuit; a first reading unit for inverting the signal direction of the first conversion gain signal among the pixel signals input to the input node, and outputting the inverted first conversion gain signal to the connecting node; a second reading unit for maintaining the signal direction of the second conversion gain signal among the pixel signals input to the input node, and outputting the non-inverted second conversion gain signal to the connecting node.

[0035] Effects of the Invention

[0036] According to the present invention, signals with different conversion gains and different signal directions can be read.

[0037] Furthermore, according to the present invention, not only can signals with different conversion gains and directions be read, but also increases in power consumption and circuit area can be suppressed, a high dynamic range can be achieved, and higher image quality can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention.

[0039] Figure 2 This is a circuit diagram showing an example of a read pixel according to the first embodiment.

[0040] Figure 3 This is a timing chart showing an example of a readout sequence for reading out pixels in the solid-state imaging device according to the first embodiment of the present invention.

[0041] Figure 4 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to the first embodiment of the present invention.

[0042] Figure 5 This is a timing chart for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the first embodiment.

[0043] Figure 6 This is a circuit diagram showing a configuration example of a main portion of a pixel signal processing unit according to a second embodiment of the present invention.

[0044] Figure 7This is a timing chart for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the second embodiment.

[0045] Figure 8 This is a circuit diagram showing a configuration example of a main portion of a pixel signal processing unit according to a third embodiment of the present invention.

[0046] Figure 9 This is a timing chart for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the third embodiment.

[0047] Figure 10 This is a block diagram showing an example of the configuration of a main portion of a pixel signal processing unit and an example of a stacked structure of pixels and the pixel signal processing unit according to a fourth embodiment of the present invention.

[0048] Figure 11 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to a fifth embodiment of the present invention.

[0049] Figure 12 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a first conversion gain signal reading mode according to a fifth embodiment of the present invention.

[0050] Figure 13 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a second conversion gain signal reading mode according to a fifth embodiment of the present invention.

[0051] Figure 14 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to a sixth embodiment of the present invention.

[0052] Figure 15 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a first conversion gain signal reading mode according to a sixth embodiment of the present invention.

[0053] Figure 16 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a second conversion gain signal reading mode according to a sixth embodiment of the present invention.

[0054] Figure 17 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to the seventh embodiment of the present invention.

[0055] Figure 18 This is a timing chart for explaining the operation of reading pixel signals from read pixels in the conversion gain read mode of the solid-state imaging device according to the seventh embodiment.

[0056] Figure 19These are diagrams showing an operation sequence and potential transition for explaining the operation of the conversion gain read mode of the solid-state imaging device according to the seventh embodiment under low illuminance, medium illuminance, and high illuminance.

[0057] Figure 20 This is a diagram showing an example of the configuration of an electronic device to which the solid-state imaging device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION

[0058] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0059] (First embodiment)

[0060] Figure 1 This is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention.

[0061] Figure 2 This is a circuit diagram showing a configuration example of a readout pixel in the solid-state imaging device according to the first embodiment of the present invention.

[0062] Figure 3 (A) to (E) are timing charts showing an example of a readout sequence for reading out pixels in the solid-state imaging device according to the first embodiment of the present invention.

[0063] In this embodiment, the solid-state imaging device 10 is configured by, for example, a CMOS image sensor.

[0064] like Figure 1 As shown, the solid-state imaging device 10 includes the following main components: a pixel unit 20 serving as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40 including a pixel signal processing unit 400, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Among these components, for example, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal reading unit 70.

[0065] In the first embodiment, the read pixels 200 arranged in rows and columns in the pixel section 20 basically have the following structure: Figure 2 The composition shown.

[0066] In other words, the read pixel 200 is configured to include: a floating diffusion layer FD (Floating Diffusion) 11 that holds transferred charge so as to read it as a voltage signal; a photodiode PD11 that serves as a photoelectric conversion element and accumulates charge corresponding to the amount of incident light during an exposure period PEXP; a transfer transistor TG11-Tr that serves as a transfer element and is maintained in a non-conductive state during the exposure period PEXP but is maintained in a conductive state during a transfer period and transfers the charge accumulated in the photodiode PD11, which serves as a photoelectric conversion element, to the floating diffusion layer FD11; and a reset transistor RST11-Tr that serves as a reset element that can perform a reset process for discharging the accumulated charge in the floating diffusion layer FD11.

[0067] The read pixel 200 includes an accumulation capacitor CS11 that is an accumulation capacitor element capable of accumulating overflow charges from the photodiode PD11 that is a photoelectric conversion element, and an accumulation transistor SG11-Tr that is an accumulation connection element that selectively connects the floating diffusion layer FD11 to the accumulation capacitor CS11 that is an accumulation capacitor element.

[0068] Furthermore, in the read pixel 200, an overflow path OVFP is formed, allowing charge overflowing from the photodiode PD11, serving as the photoelectric conversion element, and then flowing through the transfer transistor TG11-Tr to the floating diffusion layer FD11, to flow toward the region where the storage capacitor CS11, serving as the storage capacitor, is formed. The storage capacitor CS11 is connected between the storage node NDS11 and the reference potential VSS in a predetermined region formed within the overflow path OVFP. The storage transistor SG11-Tr is connected between the storage node NDS11 and the floating diffusion layer FD11. The reset transistor RST11-Tr is connected between the power supply potential VAAPIX and the storage node NDS11.

[0069] The read pixel 200 is configured to include a source follower transistor SF11 -Tr as a source follower element that outputs a voltage signal converted in the floating diffusion layer FD11 , and a selection transistor SEL11 -Tr as a selection element.

[0070] The reading pixel 200 of this embodiment selectively connects the floating diffusion layer FD11 to the accumulation capacitor CS11, which serves as an accumulation capacitor element, through the accumulation transistor SG11-Tr, which serves as an accumulation connection element, under the control of the reading unit 70. This allows the capacitance of the floating diffusion layer FD11 to be changed to the first capacitance or the second capacitance and switches the conversion gain to the first conversion gain (e.g., high conversion gain: HCG) determined by the first capacitance or the second conversion gain (e.g., low conversion gain: LCG) determined by the second capacitance.

[0071] Like this, such as Figure 3 As shown, the solid-state imaging device 10 is configured to be able to perform, under the control of the reading section 70,: first conversion gain mode reading in which pixel signals are read with a first conversion gain (high conversion gain: HCG) corresponding to a first capacitor during a specified dual conversion gain reading mode; and second conversion gain mode reading in which pixel signals are read with a second conversion gain (low conversion gain: LCG) corresponding to a second capacitor (different from the first capacitor).

[0072] The reading pixel 200 is provided with a structure such as a lateral overflow integration capacitor (hereinafter referred to as "LOFIC" (Lateral Overflow Integration Capacitor)), and under the control of the reading unit 70, performs a two-sampling reading mode (LOFIC mode) operation under low illumination conditions using the accumulated charge of the photoelectric conversion element, i.e., the photodiode PD11, and the second conversion gain related to the overflow charge.

[0073] In the first embodiment, the read pixel 200 performs dual conversion gain signal reading, that is, the first conversion gain signal reading is performed with the first conversion gain corresponding to the first capacitor (for example, high conversion gain: HCG); and the second conversion gain signal reading is performed with the second conversion gain corresponding to the second capacitor (different from the first capacitor) (for example, low conversion gain: LCG). In the first embodiment, the reading process for the read pixel 200 is as follows: Figure 3 As shown, first, in the first conversion gain signal reading mode, the first read reset signal HCGRST is read, and then the first read luminance signal HCGSIG is read.

[0074] Next, in the second conversion gain signal read mode, the second read luminance signal LCGSIG is read, and then the second read reset signal LCGRST is read.

[0075] In this manner, the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST) are read as the pixel signal PXLOUT from the read pixel 200 , and signals having opposite signal directions (level transition directions) are formed.

[0076] (Specific Circuit Configuration of Pixel 200)

[0077] Here, it is explained Figure 2 The specific circuit structure of the reading pixel 200.

[0078] Here, a configuration example of a reading pixel 200 having a LOFIC structure is described.

[0079] In the pixel unit 20 , read pixels 200 including photodiodes (photoelectric conversion elements) and in-pixel amplifiers are arranged in a two-dimensional matrix of N rows×M columns.

[0080] For example Figure 2 As shown, this reading pixel 200 is constructed to include: a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a transfer element, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, an accumulation transistor SG11-Tr as an accumulation connection element, an accumulation capacitor CS11 as an accumulation capacitor element, a floating diffusion layer FD11, and an accumulation node NDS11 connected to the accumulation capacitor CS11.

[0081] In addition, in the read pixel 200 , the capacitance CFD of the floating diffusion layer FD11 is formed to be very small in order to achieve low noise.

[0082] The capacitance CS1 of the accumulation capacitor CS11 is set to a very large capacitance (electrostatic capacitance) for high FWC (Full Well Capacity). The capacitance CS1 of the accumulation capacitor CS11 is larger than the capacitance CFD of the floating diffusion layer FD11. Furthermore, while the capacitance CFD of the floating diffusion layer FD11 is primarily used for high conversion gain, the capacitance CS1 of the accumulation capacitor CS11 is also used for low conversion gain.

[0083] The photodiode PD11 generates and accumulates signal charges (electrons in this case) in an amount corresponding to the amount of incident light.

[0084] The following description will focus on a case where the signal charges are electrons and each transistor is an n-type transistor. However, the signal charges may be holes and each transistor may be a p-type transistor.

[0085] In each reading pixel 200 , a embedded photodiode (PPD) is used as the photodiode (PD).

[0086] On the surface of the substrate forming the photodiode (PD), there are interface states caused by defects such as dangling bonds. Therefore, a large amount of charge (dark current) is generated due to thermal energy, making it impossible to read correct signals.

[0087] In embedded photodiodes (PPDs), the charge accumulation section of the photodiode (PD) is embedded within the substrate, reducing the amount of dark current mixed into the signal.

[0088] The transfer transistor TG11 -Tr is connected between the photodiode PD11 and the floating diffusion layer FD11 , and is controlled by a control signal TG.

[0089] The transfer transistor TG11 -Tr is selected and turned on while the control signal TG is at a high level (H), and transfers the charges (electrons) photoelectrically converted by the photodiode PD11 and accumulated in the accumulation node to the floating diffusion layer FD11 .

[0090] Reset transistor RST11-Tr, in Figure 2 In the example, it is connected between the power supply potential VAAPIX and the accumulation node NDS11 and is controlled by the control signal RST.

[0091] The reset transistor RST11-Tr is selected and turned on while the control signal RST is at H level. When the accumulation transistor SG11-Tr is kept on, the floating diffusion FD11 (and the accumulation capacitor CS11) are reset to the power supply potential VAAPIX.

[0092] In the first embodiment, the reset transistor RST11 -Tr, the accumulation transistor SG11 -Tr, and the transfer transistor TG11 -Tr are kept in an on state, and the floating diffusion layer FD11 and the photodiode PD11 are reset.

[0093] In the first embodiment, the reset transistor RST11 -Tr and the accumulation transistor SG11 -Tr are kept in an on state, and the floating diffusion layer FD11 and the accumulation capacitor CS11 are reset.

[0094] The accumulation transistor SG11 -Tr is connected between the floating diffusion layer FD11 (and the reset transistor RST11 -Tr) and the accumulation capacitor CS11 via the accumulation node NDS11 .

[0095] The accumulation transistor SG11-Tr is controlled by a control signal SG applied to a gate via a control line.

[0096] The accumulation transistor SG11 -Tr is selected and turned on while the control signal SG is at the H level, connecting the floating diffusion FD11 (and the reset transistor RST11 -Tr) to the accumulation capacitor CS11 .

[0097] In the first embodiment, as described above, the reset transistor RST11 -Tr and the accumulation transistor SG11 -Tr are kept in the on state, and the floating diffusion layer FD11 and the accumulation capacitor CS11 are reset.

[0098] Furthermore, if Figure 2 As shown, in this first embodiment, the overflow path OVFP is formed as a path (solid arrow) that enables the overflow charge of the photodiode PD11 to be transferred to the accumulation capacitor CS11 through the floating diffusion layer FD11, the accumulation transistor SG11-Tr, and the accumulation node NDS11, and further, a path (dashed arrow) is formed that enables the overflow charge of the accumulation capacitor CS11 to be transferred to the power supply potential VAAPIX through the accumulation node NDS11 and the reset transistor RST11-Tr.

[0099] The source follower transistor SF11 -Tr and the selection transistor SEL11 -Tr are connected in series between the power supply potential VAAPIX and the vertical signal line LSGN11 .

[0100] The gate of the source follower transistor SF11 -Tr is connected to the floating diffusion layer FD11 , and the selection transistor SEL11 -Tr is controlled by a control signal SEL applied to the gate via a control line.

[0101] The selection transistor SEL11-Tr is selected and turned on during the selection period when the control signal SEL is at H level. As a result, the source follower transistor SF11-Tr outputs the column output read voltage signal (VRST1, VSIG1) converted by the FD11 to a voltage signal to the vertical signal line LSGN11.

[0102] In the pixel portion 20 , the read pixels 200 are arranged in N rows×M columns, and therefore, there are N control lines and M vertical signal lines.

[0103] exist Figure 1 In FIG, each control line is represented as one row scanning control line.

[0104] The vertical scanning circuit 30 drives pixels in the shutter row and the reading row through the row scanning control lines in response to the control of the timing control circuit 60 .

[0105] Furthermore, the vertical scanning circuit 30 outputs a row selection signal of a row address for a read row for reading a signal and a shutter row for resetting the charge accumulated in the photodiode PD11 based on the address signal.

[0106] The reading circuit 40 may be configured as a pixel signal processing unit 400 including a plurality of column signal processing circuits (not shown) arranged corresponding to the column outputs of the pixel unit 20 , and can perform column-parallel processing using the plurality of column signal processing circuits.

[0107] In the reading circuit 40, the pixel signal processing unit 400 has the following function: forming a signal with the opposite signal direction, that is, the level migration direction, and reading a conversion gain signal of either the first conversion gain signal (HCGRST, HCGSIG) or the second conversion gain signal (LCGSIG, LCGRST) as the pixel signal PXLOUT from the reading pixel 200, specifically, inverting the first conversion gain signal.

[0108] Furthermore, the pixel signal processing section 400 has an analog-to-digital (AD) conversion function for converting the first conversion gain signal and the second conversion gain signal from analog signals to digital signals after aligning the signal directions (level transition directions).

[0109] In addition, a specific circuit configuration example of the pixel signal processing unit will be described in detail later.

[0110] The horizontal scanning circuit 50 scans and transmits the signals processed by the plurality of pixel signal processing units 400 of the reading circuit 40 in the horizontal direction, and outputs the scanned signals to a signal processing circuit (not shown).

[0111] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel unit 20 , the vertical scanning circuit 30 , the reading circuit 40 , the horizontal scanning circuit 50 , and the like.

[0112] When the dual conversion gain read mode MDCG is designated, the read unit 70 executes a first conversion gain reset read process HCGRRD, a first conversion gain read process HCGSRD, a second conversion gain read process LCGSRD, and a second conversion gain reset read process LCGRRD.

[0113] In the first embodiment, the reading section 70 executes a reading process in the dual conversion gain reading mode MDCG as a reading mode process after starting the exposure period PEXP.

[0114] For example, Figure 3As shown, the reading unit 70 keeps the reset transistor RST11-Tr, the accumulation transistor SG11-Tr, and the transfer transistor TG11-Tr in the on state for a specified period, resets the photodiode PD11, the floating diffusion layer FD11, and the accumulation capacitor CS11 and performs shutter processing, so that the transfer transistor TG11-Tr is in the non-conducting state and starts the exposure period PEXP.

[0115] Moreover, after starting the exposure period PEXP, the reading unit 70 sequentially performs the first conversion gain reset reading process HCGRRD, the first conversion gain reading process HCGSRD, the second conversion gain reading process LCGSRD, and the second conversion gain reset reading process LCGRRD as processing of the dual conversion gain reading mode DMCG.

[0116] The above is a description of the outline of the configuration and function of each component of the solid-state imaging device 10 .

[0117] Next, the configuration of the pixel signal processing unit 400 , which is a column processing system of the reading unit 70 according to the first embodiment, and related reading processing and the like will be described in detail.

[0118] Figure 4 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to the first embodiment of the present invention.

[0119] The pixel signal processing unit 400 can amplify and perform AD conversion on a plurality of pixel signals read from the read pixel 200. Figure 4 As shown, the structure includes an input node ND401 , a connection node ND402 , a first reading section 410 , a second reading section 420 , and an AD conversion section 430 .

[0120] The input node ND401 inputs the first conversion gain signal (HCGRST, HCGSIG) and the second conversion gain signal (LCGSIG, LCGRST) read from the read pixel 200 to the vertical signal line LSGN11 as the pixel signal PXLOUT, and provides the input signals to the first reading unit 410 and the second reading unit 420.

[0121] The connection node ND402 is connected to the output terminal of the first reading section 410 and the output terminal of the second reading section 320 , and is also connected to the input terminal of the AD converter 430 in the next stage.

[0122] The connection node ND402 supplies the first conversion gain signal inverted by the first reading section 410 and the second conversion gain signal processed by the second reading section 420 to the AD converter 430 .

[0123] The first reading section 410 inverts the signal direction (level transition direction) of the first conversion gain signal (HCGRST, HCGSIG) among the pixel signals PIXOUT input to the input node ND401 , and outputs the inverted first conversion gain signal to the connection node ND402 .

[0124] The second reading section 420 maintains the signal direction (level transition direction) of the second conversion gain signal (LCGSIG, LCGRST) among the pixel signals PIXOUT input to the input node ND401 , and outputs the non-inverted second conversion gain signal to the connection node ND402 .

[0125] Here, refer to Figure 4 A specific configuration example of the first reading unit 410 and the second reading unit 420 according to the first embodiment will be described.

[0126] (Configuration Example of the First Reading Unit 410)

[0127] The first reading section 410 includes a first operational amplifier (amplifier) ​​411 , an inverting input terminal (−) of which is connected to a signal supply line from the input node ND401 .

[0128] In the amplifier 411 , an inverting input terminal (−) connected to a signal supply line from the input node ND401 is connected to a first node ND411 , an output terminal is connected to a second node ND412 , and a non-inverting input terminal (+) is connected to a third node ND413 .

[0129] A first input switch 412 and a first sampling capacitor CS411 are connected in series between the input node ND401 and the first node ND411 .

[0130] A feedback capacitor CF411 is connected between the second node ND412 and the first node ND411 .

[0131] A first reset switch RST411 is connected between the second node ND412 and the first node ND411 in parallel with the feedback capacitor CF411 .

[0132] An output switch 413 is connected between the second node ND412 and the connection node ND402 .

[0133] Furthermore, the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411 is connected to the reference potential V B .

[0134] The first input switch 412 is formed of, for example, a MOS transistor, and is controlled by a control signal It is switched between a conducting state and a non-conducting state.

[0135] The first input switch 412 controls the signal in the first conversion gain signal reading mode. The first conversion gain signal (HCGRST, HCGSIG) input to the input node ND401 is input to the inverting input terminal (−) of the amplifier 411 through the first sampling capacitor CS411 and maintained in an on state by being supplied at a high level, for example.

[0136] The output switch 413 is formed of, for example, a MOS transistor, and is controlled by a control signal It is switched between a conducting state and a non-conducting state.

[0137] Output switch 413 controls the signal in the first conversion gain signal reading mode The inverted first conversion gain signal (HCGRST, HCGSIG) after the inverting amplification process by the amplifier 411 is input to the AD converter 430 through the connection node ND402 , for example, by being supplied at a high level and being kept in an on state.

[0138] The first reset switch RST411 is switched between a conducting state and a non-conducting state according to the control signal RST_HCG.

[0139] The first reset switch RST411 is kept in an on state by supplying the control signal RST_HCG at, for example, a high level during a predetermined start period of the first conversion gain signal read mode, and the amplifier 411 is initialized.

[0140] (Configuration Example of Second Reading Unit 420)

[0141] The second reading unit 420 includes a second input switch 421 connected to a signal transmission line LS421 between the input node ND401 and the connection node ND402 .

[0142] The second input switch 421 is formed of, for example, a MOS transistor, and is controlled by a control signal It is switched between a conducting state and a non-conducting state.

[0143] The second input switch 421 controls the signal in the second conversion gain signal reading mode. The second conversion gain signal (LCGSIG, LCGRST) input to the input node ND401 is input to the AD converter 430 through the connection node ND402 , for example, by being supplied at a high level and maintained in an on state.

[0144] (Configuration Example of AD Converter 430)

[0145] The AD converter 430 includes a second operational amplifier (amplifier) ​​431 having an inverting input terminal (−) connected to a signal supply line from the connection node ND402 .

[0146] In amplifier 431 , the inverting input terminal (−) connected to the signal supply line from ND402 is connected to input node ND431 , the output terminal is connected to output node ND432 , and the non-inverting input terminal (+) is connected to the output side of reference potential control circuit 432 .

[0147] A sampling capacitor CC431 serving as an input capacitor is connected between the connection node ND402 and the input node ND431 .

[0148] A third reset switch RST431 is connected between the output node ND432 and the input node ND431. A third switch 433 and a sampling capacitor CSH431 are connected in series between the third node ND431 connected to the inverting input terminal (-) of the amplifier 431 and the reference potential VSS.

[0149] The third input switch 433 is formed of, for example, a MOS transistor, and is controlled by a control signal It is switched between a conducting state and a non-conducting state.

[0150] The third input switch 433 connects the sampling capacitor CC431 to the sampling capacitor CSH431 via the input node ND431 in the second conversion gain signal read mode.

[0151] By providing the sampling capacitor CSH431 , the amplitude of the pixel signal is adjusted, and in particular, the amplitude of a high-amplitude pixel signal is reduced (adjusted) to a level that can be AD-converted, thereby expanding the dynamic range.

[0152] The third reset switch RST431 is switched between a conducting state and a non-conducting state according to the control signal RST_LCG.

[0153] The third reset switch RST431 is maintained in an on state by supplying the control signal RST_LCG at, for example, a high level during a predetermined start period of the first conversion gain signal read mode, thereby initializing the amplifier 431 .

[0154] (Reading Operation of Solid-State Imaging Device 10)

[0155] The characteristic configuration and function of each unit of the solid-state imaging device 10 have been described above.

[0156] Next, the pixel signal reading operation of the solid-state imaging device 10 according to the first embodiment will be described in detail.

[0157] Figure 5(A) to (G) are timing charts for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the first embodiment.

[0158] Figure 5 (A) represents the control signal RST of the reset transistor RST11-Tr of the pixel 200, Figure 5 (B) represents the control signal SG for reading the accumulation transistor SG11-Tr of the pixel 200, Figure 5 (C) represents the control signal TG for reading the transfer transistor TG11 -Tr of the pixel 200 .

[0159] Figure 5 (D) represents the control signal of the first input switch 412 and the output switch 413 of the first reading section 410 of the pixel signal processing section 400. and the control signals of the second input switch 421 of the second reading unit 420 and the third input switch 433 of the AD conversion unit 430.

[0160] Figure 5 (E) shows the control signal RST_HCG of the first reset switch RST411 of the first reading section 410 of the pixel signal processing section 400 and the control signal RST_LCG of the second reset switch RST431 of the AD conversion section 430 .

[0161] Figure 5 (F) represents the pixel signal PIXOUT read from the read pixel 200, Figure 5 (G) shows the amplified output signal AMPOUT of the first reading section 410 and the second reading section 420 of the pixel signal processing section 400 .

[0162] Before the dual conversion gain read mode MDCG starts, the control signals RST, SG, and TG are set to high level for a predetermined period, and the reset transistor RST11-Tr, the accumulation transistor SG11-Tr, and the transfer transistor TG11-Tr are kept in an on state for the predetermined period.

[0163] As a result, the photodiode PD11, the floating diffusion layer FD11, and the storage capacitor CS11 are reset to the fixed potential VAAPIX. That is, the shutter operation ( Figure 5 (A)~(C)).

[0164] (Reading Process in the First Conversion Gain Signal Reading Mode)

[0165] Then, when the transfer transistor TG11 -Tr is switched from the conductive state to the non-conductive state, the exposure time PEXP starts, and the reading process is performed according to the first conversion gain signal reading mode.

[0166] After a certain period of time has passed since the start of the exposure period PEXP, the control signal SG is switched to a high level for only a predetermined period, and then the reading period of the first reading reset signal (HCGRST) begins.

[0167] At this time, the control signal SG is still maintained at a low level, and the accumulation transistor SG11-Tr is in a non-conducting state. Therefore, the charge of the floating diffusion layer FD11 and the charge of the accumulation capacitor CS11 are separated, and the gain of the floating diffusion layer FD11 is maintained at the first conversion gain HCG determined by the first capacitance including the capacitance CFD of the floating diffusion layer FD11.

[0168] Then, during the first reset signal read period after the reset processing, the first conversion gain reset read processing HCGRRD is performed, and the first read reset signal HCGRST converted according to the first conversion gain HCG determined by the first capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr to the vertical signal line LSGN11, and the prescribed processing is performed on this first read reset signal HCGRST in the column processing circuit, i.e., the read circuit 40.

[0169] Next, during the first transfer period following the first reset signal read period, control signal TG is switched to a high level, and transfer transistor TG11-Tr remains in the on state, transferring the accumulated charge in photodiode PD11 to floating diffusion FD11. After the first transfer period, control signal TG is switched to a low level, and transfer transistor TG11-Tr is switched to a non-conductive state.

[0170] Next, during the first signal read period following the first transmission period, the first conversion gain read processing HCGSRD is performed, and the first read signal HCGSIG converted according to the first conversion gain determined by the first capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr to the vertical signal line LSGN11. Specified processing is performed on this first read signal HCGSIG in the column processing circuit, i.e., the read circuit 40.

[0171] Then, hold the reset level (VHCGRST, V RH ) and signal levels (VHCGSIG, V SH ), or, performing digital CDS calculation based on the difference between the reset level and the signal level.

[0172] In the first conversion gain signal reading mode, the following processing is performed by the reading circuit 40. In the first conversion gain signal reading mode, the control signal The active high level is supplied to the first input switch 412 and the output switch 413 in the first reading section 410 of the pixel signal processing section 400 of the reading circuit 40 .

[0173] On the other hand, in the first conversion gain signal reading mode, the control signal The second input switch 421 in the second reading section 420 of the pixel signal processing section 400 of the reading circuit 40 is held at an inactive low level.

[0174] Therefore, in the first conversion gain signal reading mode, the first reading section 410 of the pixel signal processing section 400 is in an active state, and the second reading section 420 is in an inactive state.

[0175] Furthermore, in the first reading section 410 , during a predetermined start period of the first conversion gain signal reading mode, the control signal RST_HCG is supplied at, for example, a high level, and the first reset switch RST411 is switched to an on state, thereby initializing the amplifier 411 .

[0176] Then, in the first conversion gain signal reading mode, the first conversion gain signal, namely the first reading reset signal HCGRST (potential V RH ) is input, and then the first read reset signal HCGRST is inverted in the amplifier 411.

[0177] In the first conversion gain signal reading mode, the AD converter 430 uses the inactive control signal RST_LCG is supplied to the third input switch 433 and the second reset switch RST431, thereby performing AD conversion by comparing the output signal AMPOUT of the first reading unit 410 supplied to the inverting input terminal (-) of the amplifier 431 with a specified potential supplied to the non-inverting input terminal (+).

[0178] In the first conversion gain signal reading mode, the first reading reset signal HCGRST (potential V RH ), and then supplies the first read brightness signal HCGSIG (potential V SH ).

[0179] Then, the first read reset signal HCGRST (potential V RH), and then the first read reset signal HCGRST is inverted and amplified in the amplifier 411 and is output to the AD converter 430 of the next stage.

[0180] The output signal AMPOUT of the amplifier 411 of the first reading unit 410 is a reference potential V B As a reference, the first read reset signal HCGRST (potential V RH ) and the low potential reading brightness signal HCGSIG (V SH ) multiplied by the capacitance ratio G(C S / C F ) after the level is amplified (V B +G*(V RH -V SH )).

[0181] (Reading Process in Second Conversion Gain Signal Reading Mode)

[0182] Next, after the first conversion gain read process HCGSRD, the control signal SG is switched from a low level to a high level, and the accumulation transistor SG11 -Tr is switched to an on state to connect the accumulation capacitor CS11 to the floating diffusion FD11 .

[0183] As a result, the charge of the floating diffusion FD11 is shared with the charge of the storage capacitor CS11 , and the gain of the floating diffusion FD11 is switched to the second conversion gain LCG determined by the second capacitor.

[0184] As a result, the reading process is switched from the first conversion gain signal reading mode to the reading process in the second conversion gain signal reading mode.

[0185] Next, during the second transfer period following the first signal read period, the control signal TG is switched to a high level, and the transfer transistor TG11-Tr remains in the on state, transferring the accumulated charge in the photodiode PD11 to the floating diffusion layer FD11. After the second transfer period, the control signal TG is switched to a low level, and the transfer transistor TG11-Tr is switched to a non-conductive state.

[0186] Then, during the second signal reading period following the second transmission period after the first signal reading period, the second conversion gain reading process LCGSRD is performed, and the second reading signal LCGSIG converted according to the second conversion gain LCG determined by the second capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr to the vertical signal line LSGN11, and the prescribed processing is performed on this second reading signal LCGSIG in the column processing circuit, i.e., the reading circuit 40.

[0187] Next, after the second signal reading period has elapsed, the control signal RST is switched to a high level, the reset transistor RST11 -Tr is switched to an on state, and the second reset signal reading period begins.

[0188] Then, during the second reset signal reading period, the second conversion gain reset read processing HCGRRD is performed, and the second read reset signal LCGRST converted according to the second conversion gain LCG determined by the second capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr to the vertical signal line LSGN11, and the prescribed processing is performed on this second read reset signal LCGRST in the column processing circuit, i.e., the read circuit 40.

[0189] Then, hold the reset level (LCGRST, V RL ) and signal levels (LCGSIG, V SL ), or, depending on the reset level LCGRST (V RL ) and signal level LCGSIG (V SL ) to perform offset noise cancellation.

[0190] In the second conversion gain signal reading mode, the following processing is performed in the reading circuit 40. In the second conversion gain signal reading mode, the control signal The inactive low level is supplied to the first input switch 412 and the output switch 413 in the first reading section 410 of the pixel signal processing section 400 of the reading circuit 40 .

[0191] On the other hand, in the second conversion gain signal reading mode, the control signal The second input switch 421 in the second reading section 420 of the pixel signal processing section 400 of the reading circuit 40 is held at an active high level. Therefore, in the second conversion gain signal reading mode, the first reading section 410 of the pixel signal processing section 400 is in an inactive state, and the second reading section 420 is in an active state.

[0192] Furthermore, in the second conversion gain signal reading mode, the power supply of the amplifier 411 of the first reading unit 410 can be turned off, thereby reducing power consumption.

[0193] In the second conversion gain signal reading mode, the AD converter 430 uses the valid control signal RST_LCG is supplied to the third input switch 433 and the second reset switch RST431 , and thus the output signal AMPOUT of the second reading unit 420 supplied to the inverting input terminal (−) of the amplifier 431 is processed as follows.

[0194] In the second conversion gain signal reading mode, the second reading section 420 and the amplifier 431 of the AD conversion section 430 functioning as an attenuator are not subjected to an inversion effect and the second read luminance signal LCGSIG (potential V SL ), then the second read reset signal LCGRST (potential V RL ).

[0195] Then, the output signal AMPOUT of the amplifier 431 of the AD conversion unit 430 is a reference potential V B As a reference, the second read brightness signal LCGSIG (potential V SL ), then the second read reset signal LCGRST (potential V RL ) multiplied by the capacitance ratio G(C C / (C C +C SH )) after the level of the attenuated signal (V B +G*(V RL -V SL )).

[0196] As described above, according to the first embodiment, the pixel signal processing unit 400 that can perform AD conversion processing, etc., Figure 4 As shown, the structure includes an input node ND401 , a connection node ND402 , a first reading section 410 , a second reading section 420 , and an AD conversion section 430 .

[0197] The first reading unit 410 reverses the signal direction (level migration direction) of the first conversion gain signal (HCGRST, HCGSIG) in the pixel signal PIXOUT input to the input node ND401, and inputs the inverted first conversion gain signal (HCGRST, HCGSIG) subjected to the inverted amplification processing to the AD conversion unit 430 through the connection node ND402.

[0198] The second reader 420 maintains the signal direction (level shift direction) of the second conversion gain signal (LCGSIG, LCGRST) within the pixel signal PIXOUT input to the input node ND401, and inputs the non-inverted second conversion gain signal (LCGSIG, LCGRST) to the AD converter 430 via the connection node ND402. Furthermore, the AD converter 430, by providing a sampling capacitor CSH431, adjusts the amplitude of the pixel signal, particularly reducing (adjusting) the amplitude of high-amplitude pixel signals to a level suitable for AD conversion, thereby expanding the dynamic range.

[0199] Therefore, according to the first embodiment, signals having different conversion gains and different signal directions can be read.

[0200] Furthermore, according to the first embodiment, signals having different conversion gains and directions can be read, while increases in power consumption and circuit area can be suppressed, and a high dynamic range can be achieved, thereby achieving high image quality.

[0201] In the second conversion gain signal reading mode, the first reading section 410 of the pixel signal processing section 400 is in an inactive state, and the second reading section 420 is in an active state.

[0202] At the same time, in the second conversion gain signal reading mode, the power supply of the amplifier 411 of the first reading unit 410 can be turned off, thereby reducing power consumption.

[0203] In addition, the AD conversion unit 430 can input an inverted first conversion gain signal and a non-inverted second conversion gain signal in the same direction, and can convert the input inverted first conversion gain signal and the non-inverted second conversion gain signal into each other through an existing ADC without circuit consumption, thereby reducing the cost of the camera system to which it is applied.

[0204] (Second embodiment)

[0205] Figure 6 This is a circuit diagram showing an example of the configuration of a main portion of a pixel signal processing unit according to a second embodiment of the present invention.

[0206] Figure 7 (A) to (H) are timing charts for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the second embodiment.

[0207] Figure 7 (A) represents the control signal RST of the reset transistor RST11-Tr of the pixel 200, Figure 7 (B) represents the control signal SG for reading the accumulation transistor SG11-Tr of the pixel 200, Figure 7 (C) represents the control signal TG for reading the transfer transistor TG11 -Tr of the pixel 200 .

[0208] Figure 7 (D) represents the control signal of the first input switch 412 of the first reading unit 410 of the pixel signal processing unit 400 The control signal of the second input switch 421 of the second reading unit 420

[0209] Figure 7 (E) represents the control signal RST_HCG of the first reset switch RST411 of the first reading section 410 of the pixel signal processing section 400, Figure 7(F) shows the control signal RST_LCG of the second reset switch RST412 of the AD converter 430 .

[0210] Figure 7 (G) represents the pixel signal PIXOUT read from the read pixel 200, Figure 7 (H) shows the amplified output signal AMPOUT of the first reading section 410 and the second reading section 420 of the pixel signal processing section 400 .

[0211] The pixel signal processing section 400A of the second embodiment differs from the pixel signal processing section 400 of the first embodiment in the following points.

[0212] In the pixel signal processing unit 400 of the first embodiment, the first reading unit 410 has the amplifier 411 , while the second reading unit 420 does not have an amplifier. The signal transmission line LS421 connected to the second input switch 421 is connected to the connection node ND402 and functions as an attenuator.

[0213] Furthermore, the first reading unit 410 and the second reading unit 420 do not share the amplifier 411 but independently perform inversion amplification processing on the first conversion gain signal (HCGRST, HCGSIG) to be processed and perform non-inversion attenuation processing on the second conversion gain signal (LCGSIG, LCGRST).

[0214] In contrast, in the pixel signal processing section 400A of the second embodiment, the amplifier 411A is shared by the first reading section 410A and the second reading section 420A.

[0215] Specifically, in the second reading section 410A, the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411A and the reference potential V B A fourth input switch 414 is connected therebetween.

[0216] On the other hand, in the second reading section 420A, the signal transmission line SL421 connected to the second input switch 421 is connected not to the connection node ND402 but to the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411A.

[0217] In the second reading section 420A, a second sampling capacitor CC421 is connected between the second input switch 421 and the third node ND413. Furthermore, an attenuation capacitor CSH421 is connected between the fifth node ND421, which is the connection node between the third node ND413 and the second sampling capacitor CC421, and the reference potential VSS.

[0218] The fourth input switch 414 is formed of, for example, a MOS transistor, and is controlled by a control signal It is switched between a conducting state and a non-conducting state.

[0219] The fourth input switch 414 controls the signal φ1 in a predetermined start period of the first conversion gain signal reading mode or the second conversion gain signal reading mode. For example, the reference potential V B Connected to the non-inverting input terminal (+) of the amplifier 411A.

[0220] According to the second embodiment, in the second conversion gain signal read mode, the second sampling capacitor CC421 and the attenuation capacitor CSH421 function as an attenuator that attenuates the second conversion gain signal (LCGSIG, LCGRST).

[0221] Then, this attenuator output is supplied to the non-inverting input terminal (+) of the amplifier 411A, and is buffered by the non-inverting unit gain amplifier on the non-inverting input terminal (+) side.

[0222] In addition, according to this second embodiment, as in the above-mentioned first embodiment, not only can signals with different conversion gains and different signal directions be read, but also the increase in power consumption and circuit area can be suppressed, and a high dynamic range can be achieved, thereby achieving high image quality.

[0223] (Third embodiment)

[0224] Figure 8 This is a circuit diagram showing an example of the configuration of a main portion of a pixel signal processing unit according to a third embodiment of the present invention.

[0225] Figure 9 (A) to (H) are timing charts for explaining the operation of reading pixel signals from read pixels in the dual conversion gain read mode of the solid-state imaging device according to the third embodiment.

[0226] Figure 9 (A) represents the control signal RST of the reset transistor RST11-Tr of the pixel 200, Figure 9 (B) represents the control signal of the accumulation transistor SG11-Tr of the reading pixel 200, Figure 9 (C) represents the control signal TG for reading the transfer transistor TG11 -Tr of the pixel 200 .

[0227] Figure 9 (D) represents the control signal of the first input switch 411 of the first reading unit 410B of the pixel signal processing unit 400B The control signal of the second input switch 421B of the second reading unit 420B Figure 9(E) represents the control signal of the fourth switch 414 of the first reading unit 410B of the pixel signal processing unit 400B

[0228] Figure 9 (F) shows the control signal RST_HCG of the first reset switch RST421 of the first reading section 410 of the pixel signal processing section 400B.

[0229] Figure 9 (G) represents the pixel signal PIXOUT read from the read pixel 200, Figure 9 (H) shows the amplified output signal AMPOUT of the first reading section 410B and the second reading section 420B of the pixel signal processing section 400B.

[0230] The pixel signal processing section 400B of the third embodiment differs from the pixel signal processing section 400A of the second embodiment in the following points.

[0231] In the pixel signal processing unit 400B of the third embodiment, during the reading process of the first conversion gain signal reading mode, the signal transmission line LS421 of the second reading unit 420B is connected to the reference potential VSS of the pixel ground, so that the input capacitance on the non-inverting input terminal (+) side of the amplifier 411B is the capacitance (CC+CSH) obtained by adding the capacitances of the sampling capacitor CC421 and the attenuation capacitor CSH421, and is balanced with the capacitance CS of the first sampling CS421 connected to the inverting input terminal (-) side.

[0232] In the pixel signal processing unit 400B of the third embodiment, the second input switch 421B has a terminal a connected to the terminal input node ND401, a terminal b connected to the reference potential VSS, and a terminal c connected to the signal transmission line LS421. When the voltage is high, connect terminal c to terminal a; when the voltage is low, connect terminal c to terminal b.

[0233] According to this third embodiment, when operating in the first conversion gain signal reading mode, the input capacitance on the non-inverting input terminal (+) side is set to be approximately equal to the capacitance (CC + CSH) in order to maintain balance with CS, and the fluctuation of the pixel grounding is offset by the differential action of the amplifier 411B.

[0234] In the pixel signal processing unit 400B of the third embodiment, during the reading process according to the first conversion gain signal reading mode, the signal transmission line LS421 of the second reading unit 420B is connected to the reference potential VSS serving as the pixel ground, so that the input capacitance on the non-inverting input terminal (+) side of the amplifier 411B is the capacitance (CC+CSH) obtained by adding the capacitances of the sampling capacitor CC421 and the attenuation capacitor CSH421, and is balanced with the capacitance CS of the first sampling CS421 connected to the inverting input terminal (-) side.

[0235] On the other hand, in the second conversion gain signal reading mode, the signal transmission line LS421 of the second reading unit 420B is connected to the input node ND401, and the second sampling capacitor CC421 and the attenuation capacitor CSH421 connected to the reference potential as the analog ground function as an attenuator to attenuate the second conversion gain signal (LCGSIG, LCGRST).

[0236] Then, this attenuator output is supplied to the non-inverting input terminal (+) of the amplifier 411B, and is buffered by the non-inverting unit gain amplifier applied on the non-inverting input terminal (+) side.

[0237] According to the third embodiment, in addition to achieving the effects of the second embodiment, the signal input to the so-called pixel ground noise cancellation circuit is supplied to the non-inverting input terminal (+) side of the amplifier 411B via the sampling capacitor CSH421. This eliminates, for example, the ground (GND) floating of each column, thereby reducing noise such as shadows. This achieves so-called ground bounce cancellation (GBC).

[0238] (Fourth embodiment)

[0239] Figure 10 This is a block diagram showing an example of the configuration of a main portion of a pixel signal processing unit and an example of a stacked structure of pixels and the pixel signal processing unit according to a fourth embodiment of the present invention.

[0240] The pixel signal processing section 400C of the fourth embodiment differs from the pixel signal processing section 400A of the second embodiment in the following points.

[0241] In the pixel signal processing unit 400C of the fourth embodiment, a fifth switch 422 is connected between a third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411C and a fifth node ND421 connected to the capacitors CC421 and CSH421 .

[0242] The fifth switch 422 is controlled by the signal Its conduction state is controlled.

[0243] In the pixel signal processing unit 400C of this fourth embodiment, during the reading process of the first conversion gain signal reading mode, the signal transmission line SL421 of the second reading unit 420C is connected to the reference potential, so that the input capacitance on the inverting input terminal (+) side of the amplifier 411C is the capacitance (CC+CSH) obtained by adding the capacitances of the fourth sampling capacitor CC421 and the attenuation capacitor CSH421, and is balanced with the capacitance CS of the first sampling CS421 connected to the inverting input terminal (-) side.

[0244] According to this fourth embodiment, the input capacitance on the non-inverting input terminal (+) side operating in the first conversion gain signal reading mode is set to be approximately equal to the capacitance (CC + CSH) in order to maintain balance with CS, and the fluctuation of the pixel ground is offset by the differential action of the amplifier 411B.

[0245] In the pixel signal processing unit 400C of the fourth embodiment, during the reading process according to the first conversion gain signal reading mode, the signal transmission line LS421 of the second reading unit 420C is connected to the reference potential VSS serving as the pixel ground, so that the input capacitance on the non-inverting input terminal (+) side of the amplifier 411C is the capacitance (CC+CSH) obtained by adding the capacitances of the sampling capacitor CC421 and the attenuation capacitor CSH421, and is balanced with the capacitance CS of the first sampling CS421 connected to the inverting input terminal (-) side.

[0246] On the other hand, in the second conversion gain signal reading mode, the signal transmission line LS421 of the second reading unit 420C is connected to the input node ND401, and the second sampling capacitor CC421 and the attenuation capacitor CSH421 connected to the reference potential as the analog ground function as an attenuator to attenuate the second conversion gain signal (LCGSIG, LCGRST).

[0247] Then, this attenuator output is supplied to the non-inverting input terminal (+) of the amplifier 411C, and is buffered by the non-inverting unit gain amplifier applied on the non-inverting input terminal (+) side.

[0248] According to the fourth embodiment, in addition to achieving the effects of the second embodiment, the signal input to the pixel ground noise cancellation circuit is supplied to the non-inverting input terminal (+) of the amplifier 411C via the attenuation capacitor CSH421. This eliminates, for example, the ground (GND) floating of each column, thereby reducing noise such as shadows. This achieves so-called ground bounce cancellation (GBC).

[0249] In the fourth embodiment, the AD converter 430C is composed of a single-slope ADC including a comparator 435 , a counter 436 , and a memory 437 .

[0250] The comparator 435 compares the output signal of the amplifier 411C of the first reading unit 410C with the ramp signal RAMP having a slope waveform that changes linearly with a constant slope, and outputs a high-level signal, for example, until the two signals intersect.

[0251] In the AD conversion unit 430C, AD conversion is performed while the counter 436 holds this high level.

[0252] (Stacked Structure of Pixels and Pixel Signal Processing Unit)

[0253] Furthermore, the solid-state imaging device 10C according to the fourth embodiment has a stacked structure of the reading pixels 200 and the pixel signal processing unit 400C.

[0254] The solid-state imaging device 10C according to the fourth embodiment has a stacked structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120 .

[0255] The solid-state imaging device 10C is formed as an imaging device having a stacked structure, for example, by laminating the wafers at a wafer level and then cutting the wafers by dicing.

[0256] In this example, the first substrate 110 is stacked on the second substrate 120 .

[0257] The reading pixels 200 are formed on the first substrate 110 , and the pixel signal processing unit 400C is formed on the second substrate 120 .

[0258] In such a stacked structure, the output node of the read pixel 200 of the first substrate 110 and the input node ND401 of the pixel signal processing unit 400C of the second substrate 120 are connected to each other. Figure 10 As shown, through-holes (Die-to-Die Via) or micro bumps are used for electrical connection.

[0259] (Fifth embodiment)

[0260] Figure 11 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to a fifth embodiment of the present invention.

[0261] Figure 12 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a first conversion gain signal reading mode according to a fifth embodiment of the present invention.

[0262] Figure 13This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a second conversion gain signal reading mode according to a fifth embodiment of the present invention.

[0263] The pixel signal processing section 400D of the fifth embodiment differs from the pixel signal processing section 400A of the second embodiment in the following points.

[0264] In the pixel signal processing section 400D of the fifth embodiment, the first and second reading sections 410D and 420D share the first and second sampling capacitors CS411 and CC421 , and also share the feedback capacitor CF411 and the attenuation capacitor.

[0265] In this example, a first sampling capacitor CS411 and a feedback capacitor CF411 are used.

[0266] The components of the pixel signal processing unit 400D according to the fifth embodiment are connected as follows.

[0267] In the pixel signal processing unit 400D, a sampling capacitor CS411 is connected to the input node ND401, a first input switch 412 is connected between the sampling capacitor CS411 and the first node ND411 connected to the inverting input terminal (-) of the first operational amplifier, i.e., the amplifier 411D, and a second input switch 421 is connected between the sampling capacitor CS411 and the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411D.

[0268] A feedback capacitor CF411 is connected between the second node ND412 connected to the output terminal of the amplifier 411D and the first node ND411 connected to the inverting input terminal (-), and a reset switch RST411 is connected between the second node ND412 connected to the output terminal of the amplifier 411D and the first node ND411 connected to the inverting input terminal (-).

[0269] A sixth switch 416 is connected between the electrode side of one side of the feedback capacitor CF411 and the first node ND411 connected to the inverting input terminal (-) of the amplifier 411D, a seventh switch 417 is connected between the electrode side of the other side of the feedback capacitor CF411 and the second node ND412 connected to the output terminal of the amplifier 411D, an eighth switch 418 is connected between the electrode side of one side of the feedback capacitor CF411 and the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411D, a ninth switch 419 is connected between the electrode side of the other side of the feedback capacitor CF411 and the reference potential VSS, and a ninth switch 419 is connected between the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411D and the reference potential V BA third switch 414 is connected therebetween.

[0270] In the above configuration, in the first conversion gain signal reading mode, as shown in FIG. Figure 12 As shown, the first input switch 412 , the third switch 414 , the sixth switch 416 , and the seventh switch 417 are kept in the on state.

[0271] On the other hand, the second input switch 421 , the reset switch RST411 , the eighth switch 418 , and the ninth switch 419 are maintained in a non-conductive state.

[0272] In the 2nd conversion gain signal reading mode, if Figure 13 As shown, the first input switch 412 , the third switch 414 , the sixth switch 416 , and the seventh switch 417 are maintained in a non-conductive state.

[0273] On the other hand, the second input switch 421 , the reset switch RST411 , the eighth switch 418 , and the ninth switch 419 are maintained in the on state.

[0274] According to the fifth embodiment, not only can the same effects as those of the second embodiment be obtained, but the number of components can be reduced, the pixel size can be miniaturized, and the stacking structure can be simplified.

[0275] For example, in a stacked structure, when one of the sampling capacitor CS411 or the feedback capacitor CF411 is configured on the upper first substrate 110 side, only one of the remaining feedback capacitor CF411 or the sampling capacitor CS411 needs to be configured on the lower second substrate 129.

[0276] (Sixth embodiment)

[0277] Figure 14 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to a sixth embodiment of the present invention.

[0278] Figure 15 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a first conversion gain signal reading mode according to a sixth embodiment of the present invention.

[0279] Figure 16 This is a circuit diagram for explaining an active system circuit of a pixel signal processing unit in a second conversion gain signal reading mode according to a sixth embodiment of the present invention.

[0280] The pixel signal processing section 400E of the sixth embodiment differs from the pixel signal processing section 400A of the second embodiment in the following points.

[0281] In the pixel signal processing section 400E of the sixth embodiment, the first sampling capacitor CS411 and the second sampling capacitor CC421 are shared by the first reading section 410E and the second reading section 420E.

[0282] In this example, the first sampling capacitor CS411 is used.

[0283] The components of the pixel signal processing unit 400E according to the sixth embodiment are connected as follows.

[0284] In the pixel signal processing unit 400E, a sampling capacitor CS411 is connected to the input node ND401, a first input switch 412 is connected between the sampling capacitor CS411 and the first node ND411 connected to the inverting input terminal (-) of the first operational amplifier, i.e., the amplifier 411E, and a second input switch 421 is connected between the sampling capacitor CS411 and the third node ND413 connected to the non-inverting input terminal (+) of the amplifier 411E.

[0285] A feedback capacitor CF411 is connected between the output terminal of the amplifier 411E and the first node ND411 connected to the inverting input terminal (-). A reset switch RST411 is connected between the second node ND412 connected to the output terminal of the amplifier 411E and the first node ND411 connected to the inverting input terminal (-). A tenth switch 4110 is connected between the electrode side of one side of the sampling capacitor CS411 and the connection node ND403 of the first input switch 412 and the second input switch 421 and the attenuation capacitor CSH421. A third switch 414 is connected between the non-inverting input terminal (+) of the amplifier 411E and the reference potential VB.

[0286] In the above configuration, in the first conversion gain signal reading mode, as shown in FIG. Figure 15 As shown, the first input switch 412 and the third switch 414 are kept in the on state.

[0287] On the other hand, the reset switch RST411, the tenth switch 4110, and the second input switch 421 are maintained in a non-conductive state.

[0288] In the second conversion gain signal reading mode, the first input switch 412 and the third switch 414 are kept in a non-conductive state.

[0289] On the other hand, the reset switch, RST 411 , the tenth switch 4110 , and the second input switch 421 are maintained in the on state.

[0290] According to the sixth embodiment, not only can the same effects as those of the second embodiment be obtained, but the number of components can be reduced, the pixel size can be miniaturized, and the stacking structure can be simplified.

[0291] For example, in a stacked structure, when one of the sampling capacitor CS411 or the feedback capacitor CF411 is arranged on the upper first substrate 110 side, only one of the remaining feedback capacitor CF411 or the sampling capacitor CS411 needs to be arranged on the lower second substrate 129.

[0292] Furthermore, according to the sixth embodiment, the number of switches can be reduced compared to the fifth embodiment, and gain adjustment becomes easier.

[0293] (Seventh embodiment)

[0294] Figure 17 This is a circuit diagram showing a configuration example of a pixel signal processing unit according to the seventh embodiment of the present invention.

[0295] The pixel signal processing section 400F of the seventh embodiment differs from the pixel signal processing section 400 of the first embodiment in the following points.

[0296] The pixel signal processing unit 400 of the first embodiment reads two types of dual-conversion-gain signals, whereas the pixel signal processing unit 400F of the seventh embodiment reads multiple types of signals, three types of triple-conversion-gain signals.

[0297] In the first reading section 410F of the pixel signal processing section 400F of the seventh embodiment, the first operational amplifier, namely, the amplifier 411F, is configured to have one to two input channels.

[0298] Specifically, the inverting input terminal (-) of the amplifier 411F is increased to 2 channels. In other words, the inverting input terminal (-) of the amplifier 411F is increased to 2 channels. Figure 4 In addition to the first inverting input terminal, it also includes a second inverting input terminal (-)2.

[0299] Moreover, the first reading unit 410F also includes: a third input switch 412-2 and a third sampling capacitor CS412 connected in series between the second inverting input terminal (-)2 of the amplifier 411F and the input node ND401; a second feedback capacitor CF412 connected between the output terminal of the amplifier 411F connected to the connection node ND402 and the second inverting input terminal (-)2; a second reset switch RST412 connected between the output terminal of the amplifier 411F connected to the connection node ND402 and the inverting input terminal (-)2; and the non-inverting input terminal (+) of the amplifier 411F is connected to the reference potential VSS.

[0300] In the pixel signal processing section 400F, the first input switch 412 is kept in the on state in the first conversion gain signal reading mode.

[0301] The second input switch 421 is kept in the on state in the second conversion gain signal reading mode.

[0302] The third input switch 412 - 2 is kept in an on state in the third conversion gain signal reading mode which is between the first conversion gain and the second conversion gain.

[0303] Furthermore, the reading pixel 200F of this seventh embodiment is configured to, for example, under the control of the reading unit 70, during a specified dual conversion gain reading mode, be able to perform a first conversion gain mode reading in which pixel signals are read with a first conversion gain (high conversion gain: HCG) corresponding to the first capacitor; and a second conversion gain mode reading in which pixel signals are read with a second conversion gain (low conversion gain: LCG) corresponding to the second capacitor.

[0304] Furthermore, in the circuit system of the pixel signal processing section 400F, inversion high gain processing (I-HCG), inversion low gain processing (I-LCG), and non-inversion attenuation processing (N-ATT) are executed.

[0305] In this seventh embodiment, in the circuit system of the pixel signal processing unit 400F, pixel signal reading is performed with a third conversion gain (medium conversion gain: MCG) corresponding to a third capacitor (different from the first capacitor and the second capacitor) having an intermediate value between the first conversion gain (high conversion gain: HCG) corresponding to the first capacitor and the second conversion gain (low conversion gain: LCG) corresponding to the second capacitor.

[0306] As described above, according to the seventh embodiment, by inserting the third conversion gain (medium conversion gain) MCG between the first conversion gain (high conversion gain) HCG and the second conversion gain (low conversion gain) LCG, the first conversion gain (high conversion gain) HCG and the third conversion gain (medium conversion gain) MCG can minimize the SNR degradation of the joint through CDS action. Moreover, although the second conversion gain (low conversion gain) LCG is a DDS action, by being connected from the third conversion gain (medium conversion gain) MCG, mode migration can be performed in an area with large signal amount (= area with high SNR), thereby minimizing the SNR degradation.

[0307] Figure 18 (A) to (G) are timing charts for explaining the operation of reading pixel signals from read pixels in the conversion gain read mode of the solid-state imaging device according to the seventh embodiment.

[0308] Figure 19 (A) to (C) are diagrams showing an operation sequence and potential transition for explaining the operation of the conversion gain read mode of the solid-state imaging device according to the seventh embodiment under low illumination, medium illumination, and high illumination.

[0309] Figure 18 (A) represents the control signal RST of the reset transistor RST11-Tr of the reading pixel 200F, Figure 18 (B) represents the control signal SG of the accumulation transistor SG11-Tr of the reading pixel 200F, Figure 18 (C) represents the control signal TG for reading the transfer transistor TG11 -Tr of the pixel 200F.

[0310] Figure 18 (D) represents the control signal of the first input switch 412 and the output switch 413 of the first reading section 410F of the pixel signal processing section 400F. The control signal of the second input switch 421 of the second reading unit 420 and the control signal of the third input switch 433 of the AD conversion unit 430

[0311] Figure 18 (E) shows the control signal RST_HCG of the first reset switch RST411 of the first reading section 410F of the pixel signal processing section 400F and the control signal RST_LCG of the second reset switch RST431 of the AD conversion section 430 .

[0312] Figure 18 (F) represents the pixel signal PIXOUT read from the read pixel 200F, Figure 18(G) shows the amplified output signal AMPOUT of the first reading section 410F and the second reading section 420F of the pixel signal processing section 400F.

[0313] The pixel signal processing unit 400F performs conversion gain signal reading processing as follows: The pixel 200F is read, and a first conversion gain signal (HCGRST, HCGSIG) and a second conversion gain signal (LCGRST, LCGSIG) corresponding to two conversion gains, whose signal directions (level transition directions) are opposite, can be read as pixel signals.

[0314] Then, the pixel signal processing unit 400F first performs inverted reading (LCGx I-LCG) of the third read reset signal MCGRST in the first read unit 410F using the third conversion gain MCG having an intermediate value between the first conversion gain HCG and the second conversion gain LCG.

[0315] Next, in the first reading section 410F, inverted reading of the first read reset signal HCGRST is performed with the first conversion gain HCG (HCG×1−HCG).

[0316] Next, in the first reading section 410F, inversion reading (HCG x I - HCG) of the first read luminance signal HCGSIG is performed with the first conversion gain HCG.

[0317] Next, in the first reading section 410F, inversion reading (LCG×I−LCG) of the third read luminance signal MCGSIG is performed with the third conversion gain MCG.

[0318] Then, in the second reading section 420F, non-inverting reading (LCG x N-AT) of the second read luminance signal LCGSIG is performed with the second conversion gain LCG.

[0319] Next, in the second reading section 420F, non-inverted reading (LCG x N-AT) of the second reading reset signal LCG is performed with the second conversion gain LCG.

[0320] According to the seventh embodiment, the same effects as those of the above-mentioned first embodiment can be obtained.

[0321] Moreover, according to this seventh embodiment, by inserting the third conversion gain (medium conversion gain) MCG between the first conversion gain (high conversion gain) HCG and the second conversion gain (low conversion gain) LCG, the first conversion gain (high conversion gain) HCG and the third conversion gain (medium conversion gain) MCG can minimize the SNR degradation of the connection through CDS action. Moreover, although the second conversion gain (low conversion gain) LCG is a DDS action, by being connected from the third conversion gain (medium conversion gain) MCG, mode migration can be performed in an area with large signal amount (= area with high SNR), thereby minimizing the SNR degradation.

[0322] The solid-state imaging devices 10 and 10A to 10F described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, portable terminals, surveillance cameras, and medical endoscope cameras.

[0323] Figure 20 This is a diagram showing an example of the configuration of an electronic device incorporating an imaging system to which the solid-state imaging device according to an embodiment of the present invention is applied.

[0324] like Figure 20 As shown, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging devices 10 , 10A, 10B, 10C, and 10D of the present embodiment can be applied.

[0325] Furthermore, the electronic device 300 includes an optical system (lens, etc.) 420 that guides incident light to the pixel region of the CMOS image sensor 310 (to form an image of a subject).

[0326] The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal of the CMOS image sensor 310 .

[0327] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310 .

[0328] The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display, or can be output to a printer. In addition, it can adopt various forms, such as being directly recorded on a storage medium such as a memory card.

[0329] As described above, by mounting the solid-state imaging devices 10 , 10A, 10B, 10C, 10D, 10E, and 10F as the CMOS image sensor 310 , a high-performance, compact, and low-cost imaging system can be provided.

[0330] Furthermore, the present invention can be used in electronic devices such as surveillance cameras and medical endoscope cameras, which have limitations on camera installation conditions such as installation size, number of connectable cables, cable length, and installation height.

[0331] Description of main component symbols

[0332] 10, 10A~10F: Solid-state imaging device

[0333] 20: Pixel Department

[0334] 200, 200F: Read pixels

[0335] PD11: Photodiode

[0336] FD11: floating diffusion layer

[0337] TG11-Tr: Pass transistor

[0338] RST11-Tr: reset transistor

[0339] SF11-Tr: Source follower transistor

[0340] SG11-Tr: Accumulation transistor

[0341] CS11: Accumulation Capacitance

[0342] 30: Vertical scanning circuit

[0343] 40: Read circuit

[0344] 400, 400A~400F: Pixel signal processing unit

[0345] 410, 410A to 410F: First reading unit

[0346] 411, 411A to 411F: Amplifier (first operational amplifier)

[0347] ND401: Input Node

[0348] ND402: Connecting Nodes

[0349] 420, 420A to 420F: Second reading unit

[0350] 421: Second input node

[0351] 430: AD conversion unit

[0352] 431: Amplifier (second operational amplifier)

[0353] 50: Horizontal scanning circuit

[0354] 60: Timing control circuit

[0355] 70: Reading unit

[0356] 300: Electronic equipment

[0357] 310: CMOS image sensor

[0358] 320: Optical System

[0359] 330: Signal Processing Circuit (PRC)

Claims

1. A solid-state imaging device, characterized in that include: Reading the pixel, performing photoelectric conversion, and being capable of reading a first conversion gain signal and a second conversion gain signal corresponding to at least two conversion gains, the signal directions of which are opposite to each other, as pixel signals; and a pixel signal processing unit for processing the pixel signal read from the reading pixel; The pixel signal processing unit includes: An input node for inputting a pixel signal read from the read pixel; Connecting nodes, connected to the secondary circuit; a first reading section configured to invert a signal direction of the first conversion gain signal among pixel signals input to the input node and output the inverted first conversion gain signal to the connection node, the first reading section comprising a first operational amplifier having an inverting input terminal connected to the input node, a first input switch connected in series between the inverting input terminal of the first operational amplifier and the input node, and a first sampling capacitor; a feedback capacitor connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; a reset switch connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; The first input switch is kept in an on state in the first conversion gain signal reading mode; The non-inverting input terminal of the first operational amplifier is connectable to at least a reference potential; The second reading section maintains the signal direction of the second conversion gain signal among the pixel signals input to the input node, and outputs the non-inverted second conversion gain signal to the connection node.

2. The solid-state imaging device according to claim 1, characterized in that The second reading unit includes: a second input switch connected between the input node and the connection node, The second input switch is maintained in an on state in the second conversion gain signal reading mode.

3. The solid-state imaging device according to claim 1, characterized in that The pixel signal processing unit includes: a first operational amplifier shared by the first reading section and the second reading section, and The first reading unit includes: a first input switch and a first sampling capacitor connected in series between the inverting input terminal of the first operational amplifier and the input node; a feedback capacitor connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; a reset switch connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; a third switch for selectively connecting the non-inverting input terminal to a reference potential; The second reading unit includes: a second input switch and a second sampling capacitor connected in series between the input node and the non-inverting input terminal; as well as an attenuation capacitor connected between the non-inverting input terminal and a reference potential; The first input switch and the third switch are kept in an on state in a first conversion gain signal reading mode; The second input switch and the reset switch are maintained in an on state in a second conversion gain signal reading mode.

4. The solid-state imaging device according to claim 3, wherein The second reading unit includes: The fourth switch can connect at least a connection signal line between the second input switch and the non-inverting input terminal to a reference potential in the first conversion gain signal reading mode.

5. The solid-state imaging device according to claim 3, wherein include: The fifth switch can selectively connect the non-inverting input terminal to a connection node between the second sampling capacitor and the attenuation capacitor.

6. The solid-state imaging device according to claim 3, wherein In the first reading unit and the second reading unit, The first sampling capacitor and the second sampling capacitor are shared. The feedback capacitor and the attenuation capacitor are shared.

7. The solid-state imaging device according to claim 6, wherein The sampling capacitor is connected to the input node. The first input switch is connected between the sampling capacitor and the inverting input terminal of the first operational amplifier. The second input switch is connected between the sampling capacitor and the non-inverting input terminal of the first operational amplifier. The feedback capacitor is connected between the output terminal of the first operational amplifier connected to the connection node and the inverting input terminal. The reset switch is connected between the output terminal of the first operational amplifier connected to the connection node and the inverting input terminal. A sixth switch is connected between one electrode side of the feedback capacitor and the inverting input terminal of the first operational amplifier. A seventh switch is connected between the other electrode side of the feedback capacitor and the output terminal of the first operational amplifier. An eighth switch is connected between one electrode side of the feedback capacitor and the non-inverting input terminal of the first operational amplifier. A ninth switch is connected between the other electrode side of the feedback capacitor and the reference potential. The third switch is connected between the non-inverting input terminal of the first operational amplifier and the reference potential.

8. The solid-state imaging device according to claim 7, wherein In the first conversion gain signal reading mode, The first input switch, the third switch, the sixth switch, and the seventh switch are kept in an on state. The second input switch, the reset switch, the eighth switch, and the ninth switch are kept in a non-conductive state. In the second conversion gain signal reading mode, The first input switch, the third switch, the sixth switch, and the seventh switch are maintained in a non-conductive state. The second input switch, the reset switch, the eighth switch, and the ninth switch are maintained in an on state.

9. The solid-state imaging device according to claim 3, wherein In the first reading unit and the second reading unit, The first sampling capacitor and the second sampling capacitor are shared.

10. The solid-state imaging device according to claim 9, wherein The sampling capacitor is connected to the input node. The first input switch is connected between the sampling capacitor and the inverting input terminal of the first operational amplifier. The second input switch is connected between the sampling capacitor and the non-inverting input terminal of the first operational amplifier. The feedback capacitor is connected between the output terminal of the first operational amplifier connected to the connection node and the inverting input terminal. The reset switch is connected between the output terminal of the first operational amplifier connected to the connection node and the inverting input terminal. A tenth switch is connected between one electrode side of the sampling capacitor and a connection node between the first switch and the second switch, and the attenuation capacitor. The third switch is connected between the non-inverting input terminal of the first operational amplifier and the reference potential.

11. The solid-state imaging device according to claim 10, wherein In the first conversion gain signal reading mode, The first input switch and the third switch are kept in an on state. The reset switch and the tenth switch are kept in a non-conductive state. In the second conversion gain signal reading mode, The first input switch and the third switch are kept in a non-conductive state. The reset switch and the tenth switch are maintained in an on state.

12. The solid-state imaging device according to claim 11, wherein In the first operational amplifier, The inverting input terminal includes at least a second inverting input terminal in addition to the first inverting input terminal used for the inverting input terminal. The first reading unit further includes: a third input switch and a third sampling capacitor connected in series between the second inverting input terminal of the first operational amplifier and the input node; a second feedback capacitor connected between an output terminal of the first operational amplifier connected to the connection node and the second inverting input terminal; a second reset switch connected between an output terminal of the first operational amplifier connected to the connection node and the second inverting input terminal; The non-inverting input terminal of the first operational amplifier can be connected to at least a reference potential.

13. The solid-state imaging device according to claim 12, wherein The first input switch is kept in an on state in the first conversion gain signal reading mode. The second input switch is kept in an on state in the second conversion gain signal reading mode. The third input switch is maintained in an on state in a third conversion gain signal reading mode that is intermediate between the first conversion gain and the second conversion gain.

14. The solid-state imaging device according to claim 1, wherein The reading pixel, A first conversion gain signal and a second conversion gain signal corresponding to two conversion gains, whose signal directions are opposite to each other, can be read as pixel signals. The pixel signal processing unit, In the first conversion gain signal reading mode, the first reading section performs inversion reading of the first reading reset signal at the first conversion gain, and then, Performing inversion reading of the first read luminance signal with the first conversion gain, In the second conversion gain signal reading mode, the second reading section performs non-inversion reading of the second read luminance signal at the second conversion gain, and then, The non-inverted reading of the second read reset signal is performed with the second conversion gain.

15. The solid-state imaging device according to claim 12 or 13, characterized in that The reading pixel, At least a first conversion gain signal and a second conversion gain signal having signal directions in opposite directions corresponding to the conversion gains can be read as pixel signals. The pixel signal processing unit, In the first reading section, an inverted reading of a third reading reset signal is performed with a third conversion gain having an intermediate value between the first conversion gain and the second conversion gain, and then, In the first reading section, the first reading reset signal is inverted and read with a first conversion gain, and then, In the first reading section, the first read luminance signal is inverted and read with a first conversion gain, and then, In the first reading section, inversion reading of the third read luminance signal is performed with a third conversion gain, In the second reading section, non-inversion reading of the second read luminance signal is performed with a second conversion gain, and then, In the second reading section, non-inverted reading of the second reading reset signal is performed at a second conversion gain.

16. The solid-state imaging device according to claim 1, wherein The pixel signal processing unit comprises: an analog-to-digital (AD) converter that converts the pixel signal processed by the first reading unit and the second reading unit and output from the connection node from an analog signal into a digital signal; The first reading unit or the AD conversion unit includes: a sample-and-hold switch disposed on a connection line between the output terminal of the first operational amplifier and the connection node; The AD conversion unit includes: 2nd operational amplifier; An input capacitor is connected between the inverting input terminal of the second operational amplifier and the sample-and-hold switch. an eleventh switch connected to the inverting input terminal of the second operational amplifier and kept in an on state in the second conversion gain signal reading mode; The sampling and holding capacitor is connected between the 11th switch and the reference potential. a third reset switch connected between the inverting input terminal and the output terminal of the second operational amplifier and maintained in an on state in the second conversion gain signal reading mode; The non-inverting input terminal of the second operational amplifier can be connected to a reference potential or an output terminal of the second operational amplifier.

17. A method for driving a solid-state imaging device, characterized in that: The solid-state imaging device comprises: Reading the pixel, performing photoelectric conversion, and being capable of reading a first conversion gain signal and a second conversion gain signal corresponding to at least two conversion gains, the signal directions of which are opposite to each other, as pixel signals; and a pixel signal processing unit for processing the pixel signal read from the reading pixel; The pixel signal processing unit includes: An input node for inputting a pixel signal read from the read pixel; Connecting nodes, connected to the secondary circuit; a first reading section configured to invert a signal direction of the first conversion gain signal among pixel signals input to the input node and output the inverted first conversion gain signal to the connection node, the first reading section comprising a first operational amplifier having an inverting input terminal connected to the input node, a first input switch connected in series between the inverting input terminal of the first operational amplifier and the input node, and a first sampling capacitor; a feedback capacitor connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; a reset switch connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; The first input switch is kept in an on state in the first conversion gain signal reading mode; The non-inverting input terminal of the first operational amplifier is connectable to at least a reference potential; The second reading section maintains the signal direction of the second conversion gain signal among the pixel signals input to the input node and outputs the non-inverted second conversion gain signal to the connection node. The driving method comprises: In the first conversion gain signal reading mode, the first reading section performs inversion reading of the first reading reset signal at the first conversion gain, and then, Performing inversion reading of the first read luminance signal with the first conversion gain, In the second conversion gain signal reading mode, the second reading section performs non-inversion reading of the second read luminance signal at the second conversion gain, and then, The non-inverted reading of the second read reset signal is performed with the second conversion gain.

18. An electronic device, characterized in that include: solid-state imaging device; as well as an optical system for forming an image of a subject on the solid-state imaging device; The solid-state imaging device comprises: Reading the pixel, performing photoelectric conversion, and being capable of reading a first conversion gain signal and a second conversion gain signal corresponding to at least two conversion gains, the signal directions of which are opposite to each other, as pixel signals; and a pixel signal processing unit configured to process the pixel signal read from the read pixel; The pixel signal processing unit includes: An input node for inputting a pixel signal read from the read pixel; Connecting nodes, connected to the secondary circuit; a first reading section configured to invert a signal direction of the first conversion gain signal among pixel signals input to the input node and output the inverted first conversion gain signal to the connection node, the first reading section comprising a first operational amplifier having an inverting input terminal connected to the input node, a first input switch connected in series between the inverting input terminal of the first operational amplifier and the input node, and a first sampling capacitor; a feedback capacitor connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; a reset switch connected between an output terminal of the first operational amplifier connected to the connection node and the inverting input terminal; The first input switch is kept in an on state in the first conversion gain signal reading mode; The non-inverting input terminal of the first operational amplifier is connectable to at least a reference potential; The second reading section maintains the signal direction of the second conversion gain signal among the pixel signals input to the input node, and outputs the non-inverted second conversion gain signal to the connection node.

Images