Pixel circuit and display device including the same

Abstract

Disclosed are a pixel circuit and a display device including the same. The pixel circuit of the display device includes a first switching element including a first electrode to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to a second node; a second switching element including a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switching element including a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switching element including a first electrode connected to the third node, a gate electrode to which a first light emission control pulse is applied, and a second electrode connected to the fourth node.

Description

Technical Field

[0001] This disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Technology

[0002] Based on the material of the light-emitting layer, electroluminescent display devices can be divided into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have the advantages of fast response speed, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, organic light-emitting diodes (OLEDs) are formed in each pixel. Organic light-emitting display devices have fast response speed, excellent luminous efficiency, brightness, and viewing angle, and because black and grayscale can be represented as complete black, they also have excellent contrast and color reproduction.

[0003] The pixel circuit of a field emission display device includes an organic light-emitting diode (OLED) used as a light-emitting element and a driving element used to drive the OLED.

[0004] The anode electrode of an OLED can be connected to the source electrode of the driving element, and the cathode electrode can be connected to a low-potential voltage source. This low-potential voltage source can be connected to the pixel. In this configuration, fluctuations in the low-potential voltage source or the influence of the OLED can alter the gate-source voltage of the driving element, leading to image quality degradation. Because the current flowing through the OLED is determined by the gate-source voltage of the driving element, changes in this voltage cause variations in the OLED's brightness. Due to parasitic capacitance between the data lines where the data voltage is applied and the low-potential voltage source, significant variations in the data voltage can cause ripple in the low-potential voltage source. Consequently, crosstalk can occur between pixel rows where the data voltage changes, resulting in dark or bright lines on the screen. Summary of the Invention

[0005] The purpose of this disclosure is to address the aforementioned needs and / or problems. Specifically, this disclosure provides a pixel circuit and a display device including the pixel circuit, in which the gate-source voltage Vgs of the driving element is not affected by a low-potential voltage source and a light-emitting element.

[0006] The disadvantages addressed by this disclosure are not limited to those described above, and other disadvantages that this disclosure can address will become apparent to those skilled in the art from the following description.

[0007] A pixel circuit according to one embodiment of the present disclosure includes: a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a light-emitting element comprising an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied; a first switching element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the second node, and configured to provide an initialization voltage to the second node in response to the initialization pulse; and a second switching element comprising an electrode connected to either the third or fourth node. The system comprises: a first electrode, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied, and is configured to provide a reference voltage to a third node or a fourth node in response to a sensing pulse; a third switching element, comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to a second node, and is configured to provide a data voltage to a second node in response to a scan pulse; and a fourth switching element, comprising a first electrode connected to a third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to a fourth node, and is configured to connect the third node to the fourth node in response to the first emission control pulse.

[0008] A display device according to one embodiment of the present disclosure includes: a display panel having a plurality of data lines, a plurality of gating lines intersecting the data lines, a plurality of power lines having different constant voltages applied thereon, and a plurality of sub-pixels; a data driver configured to provide data voltages for pixel data to the data lines; and a gating driver configured to provide initialization pulses, sensing pulses, and light emission control pulses to the gating lines.

[0009] Each of the sub-pixels includes pixel circuitry.

[0010] By adding a switching element between the anode electrode of the light-emitting element and the source electrode of the driving element, this disclosure prevents the gate-source voltage Vgs of the driving element from changing due to the ripple of the low-potential voltage source and the voltage fluctuations of the light-emitting element. As a result, this disclosure achieves excellent image quality, wherein crosstalk caused by large variations in the data voltage in the display device is not visually perceptible, and low grayscale non-uniformity is also not visually perceptible.

[0011] Even if the cathode electrode and / or power line are implemented with metal (which may correspond to the work function of the light-emitting element, and where the cathode resistance of the light-emitting element increases when considering the microcavity), this disclosure is able to prevent brightness variations of the light-emitting element.

[0012] By blocking the influence of the anode voltage and low-potential voltage source of the light-emitting element on the gate-source voltage Vgs of the driving element during the initialization step, sensing step, and data writing step, and by separating the anode voltage and the reference voltage, this disclosure facilitates the control of the threshold voltage compensation range of the driving element.

[0013] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned above based on the appended claims. Attached Figure Description

[0014] The above and other objects, features, and advantages of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein:

[0015] Figure 1 This is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0016] Figure 2 It is shown Figure 1 The cross-sectional view of the display panel structure shown;

[0017] Figure 3 This is a circuit diagram illustrating an example of a pixel circuit according to a comparative example, wherein the gate-source voltage of the driving element is affected by the ripple of the low-potential supply voltage ELVSS.

[0018] Figure 4 This is a waveform diagram illustrating an example of how the gate-source voltage of a drive element changes when ripple occurs in a low-potential supply voltage.

[0019] Figure 5 This is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0020] Figure 6 It shows that it is applied to Figure 5 The waveform diagram of the gating signal of the pixel circuit shown;

[0021] Figure 7 It shows that it is applied to Figure 5 A diagram showing the constant voltage of the pixel circuit;

[0022] Figures 8A to 8D It is shown step by step. Figure 5 The circuit diagram showing the operation of the pixel circuit is shown.

[0023] Figure 9 This shows a comparison. Figure 3 The pixel circuit of the comparative example shown and Figure 5 A view showing experimental results of the brightness of the light-emitting element in the pixel circuit of this disclosure based on the cathode voltage;

[0024] Figure 10 This is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0025] Figure 11 It shows that it is applied to Figure 10 The waveform diagram of the gating signal of the pixel circuit shown;

[0026] Figures 12A to 12D It is shown step by step. Figure 11 The circuit diagram showing the operation of the pixel circuit is shown.

[0027] Figure 13 This is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure;

[0028] Figure 14 It shows that it is applied to Figure 13 The waveform diagram of the gating signal of the pixel circuit shown;

[0029] Figure 15 It shows that it is applied to Figure 13 A diagram showing the constant voltage of the pixel circuit;

[0030] Figures 16A to 16D It is shown step by step. Figure 13 The circuit diagram showing the operation of the pixel circuit is shown.

[0031] Figure 17 This is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure;

[0032] Figure 18 It shows that it is applied to Figure 17 The waveform diagram of the gating signal of the pixel circuit shown;

[0033] Figures 19A to 19D It is shown step by step. Figure 17 The circuit diagram shown illustrates the operation of the pixel circuit.

[0034] Figure 20 This is a circuit diagram illustrating a pixel circuit according to a fifth embodiment of the present disclosure;

[0035] Figure 21 and Figure 22 It shows that it is applied to Figure 20 The waveform diagram of the gating signal of the pixel circuit shown;

[0036] Figure 23 It is a diagram showing the on-state voltage and current of the OLED; and

[0037] Figure 24 It is shown Figure 23 The diagram shows the positive bias temperature stress (PBTS) margin for ΔV. Detailed Implementation

[0038] The advantages and features of this disclosure and its implementation methods will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope. This disclosure is limited only by the scope of the appended claims.

[0039] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0040] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0041] Even if not explicitly stated, the components will be interpreted as including the normal error range.

[0042] When using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0043] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding it.

[0044] The following implementations may be combined or integrated with each other in whole or in part, and may be linked and operated in technically different ways. These implementations may be implemented independently or in association with each other.

[0045] Each pixel may include multiple sub-pixels of different colors to reproduce the colors of an image on the screen of the display panel. Each sub-pixel includes a transistor that serves as a switching element or a driving element. This transistor can be implemented as a thin-film transistor (TFT).

[0046] The driving circuit of the display device writes pixel data of the input image to the pixels on the display panel. For this purpose, the driving circuit of the display device may include a data driving circuit configured to provide data signals to data lines, a gating driving circuit configured to provide gating signals to gating lines, etc.

[0047] In the display device of this disclosure, the pixel circuit and the gating drive circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc. In embodiments, an example of implementing the transistors based on the pixel circuit and the gating drive circuit as n-channel oxide TFTs is described, but this disclosure is not limited thereto.

[0048] Typically, a transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow out from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, because the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor, because the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited by the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0049] The gating signal oscillates between a gating on voltage and a gating off voltage. The gating on voltage is set to a voltage higher than the transistor's threshold voltage, and the gating off voltage is set to a voltage lower than the transistor's threshold voltage.

[0050] The transistor turns on in response to a gating on voltage and turns off in response to a gating off voltage. In the case of an n-channel transistor, the gating on voltage can be the high gating voltages VGH and VEH, and the gating off voltage can be the low gating voltages VGL and VEL.

[0051] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings. In these embodiments, the display device will be described primarily with respect to an organic light-emitting display device, but the present disclosure is not limited thereto. Furthermore, the scope of the present disclosure is not intended to be limited by the names of the components or signals in the following embodiments and claims.

[0052] Reference Figure 1 and Figure 2According to one embodiment of the present disclosure, a display device includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0053] Display panel 100 may be a rectangular display panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. Display panel 100 includes a pixel array for displaying an input image on the screen. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Display panel 100 may also include power lines commonly connected to the pixels. The power lines may include a power line applying a pixel drive voltage ELVDD, a power line applying an initialization voltage Vinit, a power line applying a reference voltage Vref, and a power line applying a low-potential power supply voltage ELVSS. These power lines are commonly connected to the pixels.

[0054] The pixel array comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction X in the pixel array of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction Y share the same data line 102. A horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0055] The display panel 100 can be implemented using either a non-transmissive or transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and actual objects in the background are visible.

[0056] The display panel can be made from a flexible display panel. A flexible display panel can be achieved using an OLED panel with a plastic substrate. The pixel array and light-emitting elements of the plastic OLED panel can be disposed on an organic thin film adhered to a backing plate.

[0057] Each pixel 101 can be divided into red, green, and blue sub-pixels to achieve color. Each pixel may also include a white sub-pixel. However, the embodiments disclosed herein are not limited to this. For example, each pixel 101 may also be divided into yellow, magenta, and cyan sub-pixels to achieve color. Other color combinations are also possible. Each sub-pixel includes pixel circuitry. In the following text, pixel may be interpreted as having the same meaning as sub-pixel. Each pixel circuit is connected to data lines, strobe lines, and power lines.

[0058] Pixels can be arranged as true-color pixels and pentile pixels. Pentile pixels can achieve higher resolution than true-color pixels by using a preset pixel rendering algorithm to drive two sub-pixels of different colors as a single pixel (101). The pixel rendering algorithm can compensate for the lack of color representation in each pixel by utilizing the colors of light emitted from neighboring pixels.

[0059] The touch sensor can be mounted on the screen of the display panel 100. The touch sensor can be mounted on the screen of the display panel in an on-cell or add-on manner, or it can be implemented by an in-cell touch sensor embedded in the pixel array AA.

[0060] like Figure 2 As shown, when viewed from a cross-sectional perspective, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0061] Circuit layer 12 may include pixel circuitry connected to wiring such as data lines, gating lines, and power lines; gating drivers (GIPs) connected to gating lines; a demultiplexer array 112; circuitry for automated probe inspection (omitted from the figure); etc. The wiring and circuitry of circuit layer 12 may include multiple insulating layers, two or more metal layers separated from each other and with the insulating layers located therebetween, and an active layer comprising semiconductor material. All transistors formed in circuit layer 12 may be implemented by an oxide TFT comprising an n-channel oxide semiconductor. However, embodiments of this disclosure are not limited thereto. For example, at least one transistor formed in circuit layer 12 may be implemented by an LTPS TFT comprising an n-channel LTPS semiconductor. Alternatively, at least one transistor formed in circuit layer 12 may be implemented by a TFT comprising a p-channel oxide semiconductor.

[0062] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL in the light-emitting element layer 14 may be covered by a multilayer protective layer consisting of stacked organic and inorganic films.

[0063] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating film structure with alternating layers of organic and inorganic films. The inorganic film prevents the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. If the organic and inorganic films are stacked in multiple layers, the path of moisture or oxygen becomes longer compared to a single layer, thus effectively preventing the penetration of moisture and oxygen that could affect light-emitting element layer 14.

[0064] A touch sensor layer can be formed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wiring pattern forming the capacitor of the touch sensor and an insulating film. The capacitor of the touch sensor can be formed between the metal wiring patterns. A polarizing plate can be disposed on the touch sensor layer. The polarizing plate can improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12. The polarizing plate can be implemented by a polarizing plate that combines a linear polarizing plate and a phase retardation film, or by a circular polarizing plate. A cover glass can be adhered to the polarizing plate.

[0065] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters, as well as a black matrix pattern. The color filter layer can absorb a portion of the wavelengths of light reflected from the circuit layer and the touch sensor layer, replacing the function of a polarizer and improving color purity. By applying a color filter layer 20, which has a higher transmittance than a polarizer, to the display panel, this implementation can improve the transmittance of the display panel and increase its thickness and flexibility. A cover glass sheet may be adhered to the color filter layer.

[0066] Power supply 140 generates the direct current (DC) power required to drive the pixel array and display panel driver of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, voltage regulator, buck converter, boost converter, etc. Power supply 140 can regulate the level of the DC input voltage applied from a host system (not shown), thereby generating constant voltages (or DC voltages), such as gamma reference voltage VGMA, gating on voltages VGH and VEH, gating off voltages VGL and VEL, pixel drive voltage ELVDD, low-level power supply voltage ELVSS, reference voltage Vref, initialization voltage Vinit, and anode voltage Vano. The gamma reference voltage VGMA is provided to data driver 110. The gating on voltages VGH and VEH, and the gating off voltages VGL and VEL are provided to gating driver 120. Constant voltages such as pixel drive voltage ELVDD, low-level power supply voltage ELVSS, reference voltage Vref, initialization voltage Vinit, and anode voltage Vano are collectively provided to each pixel.

[0067] The display panel driver, under the control of the timing controller TCON 130, writes the pixel data of the input image to the pixels of the display panel 100.

[0068] The display panel driver includes a data driver 110 and a strobe driver 120. The display panel driver may also include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0069] The demultiplexer array 112 sequentially supplies data voltages output from each channel of the data driver 110 to the data line 102 using multiple demultiplexers (DEMUX). The demultiplexers may include multiple switching elements disposed on the display panel 100. If the demultiplexers are disposed between the output terminals of the data driver 110 and the data line 102, the number of channels in the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0070] The display panel driver may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver and touch sensor driver can be integrated into a single driver integrated circuit (IC). The timing controller 130, power supply 140, data driver 110, touch sensor driver, etc., in a mobile device or wearable device can be integrated into a single driver IC.

[0071] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. When analyzing an input image and the input image does not change within a preset time, the low-speed drive mode can be set to reduce the power consumption of the display device. When a still image is input for a predetermined time or longer, the low-speed drive mode can reduce the power consumption of the display panel driver and the display panel 100 by reducing the pixel refresh rate. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device operates in standby mode, or when a user command or input image is not input to the display panel driver circuit for a predetermined time or longer, the display panel driver circuit can operate in low-speed drive mode.

[0072] The data driver 110 generates a data voltage by converting pixel data of the input image received in digital signal form from the timing controller 130 in each frame cycle into a gamma compensation voltage using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages for each grayscale by a voltage divider circuit and provided to the DAC. The data voltage is output through the output buffer in each channel of the data driver 110.

[0073] The gate driver 120 can be implemented by an in-panel gate (GIP) circuitry formed directly on the circuit layer 12 of the display panel 100 along with the wiring of the pixel array and the TFT array. The GIP circuitry can be disposed on the bezel area BZ, which is a non-display area of ​​the display panel 100, or it can be distributed in the pixel array that reproduces the input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate line 103. The gate driver 120 can shift the gate signals using a shift register, thereby sequentially providing the gate signals to the gate line 103. The gate signals may include scan pulses, light emission control pulses (hereinafter referred to as "EM pulses"), initialization pulses, and sensing pulses.

[0074] The shift register of the strobe driver 120 outputs a strobe signal pulse in response to the start pulse and shift clock from the timing controller 130, and shifts the pulse according to the shift clock timing.

[0075] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with it from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has two horizontal periods, each 1H.

[0076] The host system can be any of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system. The host system can scale the image signal from the video source to match the resolution of the display panel 100 and send it along with timing signals to the timing controller 13.

[0077] In normal drive mode, timing controller 130 can multiply the input frame rate by i and control the operating timing of the display panel driver at a frame rate of input frame rate × i (where i is a natural number) Hz. The input frame rate is 60 Hz in the US Television Standards Committee (NTSC) method and 50 Hz in the Phase Inverter (PAL) method. Timing controller 130 can reduce the drive frequency of the display panel driver by lowering the frame rate to a frequency between 1 Hz and 30 Hz, thereby reducing the pixel refresh rate in low-speed drive mode.

[0078] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gating timing control signal for controlling the operation timing of the gating driver 120. The timing controller 130 controls the operation timing of the display panel driver, thereby synchronizing the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gating driver 120.

[0079] The voltage level of the gating timing control signal output from the timing controller 130 can be converted into gating on-state voltages VGH and VEH and gating off-state voltages VGL and VEL by a level shifter (not shown), and provided to the gating driver 120. The level shifter converts the low-level voltage of the gating timing control signal into the gating off-state voltages VGL and VEL, and converts the high-level voltage of the gating timing control signal into the gating on-state voltages VGH and VEH. The gating timing signal includes a start pulse and a shift clock.

[0080] Due to variations in device characteristics and processes caused during the manufacturing process of the display panel 100, differences may exist in the electrical characteristics of the driving elements between pixels, and these differences may increase over time as the pixels are driven. To compensate for these variations in the electrical characteristics of the driving elements between pixels, internal or external compensation techniques can be applied to the organic light-emitting display device. Internal compensation techniques use an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element of each sub-pixel, thereby compensating for the gate-source voltage Vgs of the driving element using the threshold voltage. External compensation techniques use an external compensation circuit to sense in real time the current or voltage of the driving element that varies according to its electrical characteristics. External compensation techniques compensate for variations (or changes) in the electrical characteristics of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image using the amount of change (or alteration) in the electrical characteristics of the driving element sensed for each pixel. The display panel driver can drive pixels using external and / or internal compensation techniques. The pixel circuit of this disclosure can be implemented by a pixel circuit with an internal compensation circuit applied.

[0081] Figure 3 This is a circuit diagram showing an example of a pixel circuit according to a comparative example, wherein the gate-source voltage Vgs of the driving element DT is affected by the ripple of the low-potential supply voltage ELVSS. Figure 4 This is a waveform diagram illustrating an example of how the gate-source voltage Vgs of the drive element DT changes when ripple occurs in the low-potential supply voltage ELVSS.

[0082] Reference Figure 3 and Figure 4 The pixel circuit according to the comparative example includes a light-emitting element EL, a driving element DT, a switching element ST, and a capacitor Cst.

[0083] In the comparative pixel circuit, the light-emitting element EL may further include a capacitor Cel formed between the anode electrode and the cathode electrode. In each pixel, power lines or electrodes to which a low-potential power supply voltage ELVSS is applied are connected to a common ground. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first node n1 is connected to a first power line to which a pixel driving voltage ELVDD is applied. The light-emitting element EL includes an anode electrode connected to the third node and a cathode electrode connected to a second power line PL2 to which a low-potential power supply voltage ELVSS is applied. The driving element DT generates a current for driving the light-emitting element EL according to the gate-source voltage Vgs.

[0084] The switching element ST includes a first electrode to which a data voltage Vdata of pixel data is applied, a gate electrode to which a scan pulse SCAN is applied, and a second electrode connected to the second node n2. The switching element ST is turned on according to the gating voltage VGH of the scan pulse SCAN, and supplies the data voltage Vdata to the second node n2. The capacitor Cst stores the gate-source voltage Vgs of the driving element DT.

[0085] The anode electrode of the light-emitting element EL can be connected to the second electrode of the driving element DT, and a parasitic capacitance Cpar may exist between the data line DL and the second power line PL2. In this pixel circuit of the comparative example, when the data voltage Vdata changes significantly, ripple appears in the low-potential power supply voltage ELVSS applied to the second power line PL2 through the parasitic capacitance Cpar. The low-potential power supply voltage ELVSS is transmitted to the third node n3 through the capacitor Ce1 of the light-emitting element EL. In this case, the voltage of the third node n3 or the source voltage DTS is changed by the ripple of the low-potential power supply voltage ELVSS, resulting in a change in the brightness of the light-emitting element EL.

[0086] exist Figure 4In this context, "DTG" is the gate voltage of the driving element DT, and "DTS" is the source voltage of the driving element DT. "Vripple" is the source voltage DTS that changes under the influence of the low-level supply voltage ELVSS. "ΔVgs" is the gate-source voltage of the driving element DT that changes under the influence of the low-level supply voltage ELVSS. "Vsnormal" represents the ideal source voltage DTS, where there is no ripple from the low-level supply voltage ELVSS, or it is unaffected by the ripple from the low-level supply voltage ELVSS. "Vgs" is the gate-source voltage of the driving element DT when there is no ripple from the low-level supply voltage ELVSS.

[0087] like Figures 5 to 19D As shown, by adding a switching element between the light-emitting element EL and the third node n3, the pixel circuit of this disclosure blocks the influence of the low-potential power supply voltage ELVSS and the light-emitting element EL on the gate-source voltage Vgs of the driving element DT in each sub-pixel.

[0088] Figure 5 This is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure. Figure 6 It shows that it is applied to Figure 5 The waveform diagram of the gating signal of the pixel circuit is shown. Figure 7 It shows that it is applied to Figure 5 A diagram showing the constant voltage of the pixel circuit.

[0089] Reference Figure 5 and Figure 6 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M01 to M04, a first capacitor Cst, and a second capacitor C2. The driving element DT and the switching elements M01 to M04 can be implemented by an n-channel oxide TFT. However, the embodiments of this disclosure are not limited thereto. For example, at least one of the driving element DT and the switching elements M01 to M04 can be implemented by other types of n-channel TFTs or even by a p-channel TFT.

[0090] The pixel circuit is connected to the first power line PL1, which is subject to the pixel drive voltage ELVDD; the second power line PL2, which is subject to the low-potential power supply voltage ELVSS; the third power line PL3, which is subject to the initialization voltage Vinit; the fourth power line RL, which is subject to the reference voltage Vref; the data line DL, which is subject to the data voltage Vdata; and the gating lines GL1 to GL4, which are subject to the gating signals INIT, SENSE, SCAN and EM.

[0091] like Figure 6As shown, the pixel circuit can be driven in the initialization step Ti, sensing step Ts, data writing step Tw, and emission step Temp. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the second node n2. After the voltages of the second node n2 and the third node n3 rise in the boost step Tboost, the emission element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the emission step Temp.

[0092] In initialization step Ti, the voltages of the initialization pulse INIT, EM pulse, and sensing pulse SENSE are set to the gating voltages VGH and VEH, respectively, and the voltage of the scan pulse SCAN is set to the gating voltage VGL. In sensing step Ts, the voltages of the initialization pulse INIT and sensing pulse SENSE are set to the gating voltage VGH, and the voltages of the EM pulse EM and scan pulse SCAN are set to the gating voltages VGL and VEL, respectively. In data writing step Tw, the scan pulse SCAN, synchronized with the data voltage Vdata of the pixel data, is generated using the gating voltage VGH. In data writing step Tw, the voltage of the sensing pulse SENSE is set to the gating voltage VGH. In data writing step Tw, the voltages of the initialization pulse INIT and EM pulse EM are set to the gating voltages VGL and VEL, respectively. In emission step Tem, the voltage of the EM pulse EM is set to the gating voltage VEH, and the voltages of the other gating signals INIT, SENSE, and SCAN are set to the gating voltage VGL.

[0093] A hold period Th can be set between the sensing step Ts and the data writing step Tw. During the hold period Th, the voltages of the strobe signals INIT, EM, SENSE, and SCAN are the strobe cutoff voltages VGL and VEL, respectively. A boost step Tboost can be set between the data writing step Tw and the light emission step Tem. In the boost step Tboost, the voltage of the EM pulse EM is inverted to the strobe turn-on voltage VEH, and the voltages of the scan pulse SCAN and the sensing pulse SENSE are inverted to the strobe cutoff voltage VGL. In the boost step Tboost, the voltage of the initialization pulse INIT maintains the strobe cutoff voltage VGL. During the boost step Tboost, the voltages of the second node n2 and the third node n3 rise.

[0094] like Figure 7As shown, the constant voltages ELVDD, ELVSS, Vinit, and Vref applied to the pixel circuit can be set to ELVDD>Vinit>ELVSS>Vref or ELVDD>Vinit>Vref>ELVSS, including a voltage drop margin for operation in the saturation region of the driving element DT. Figure 7 In the middle, V OLED_peak This refers to the peak voltage between the two ends of the light-emitting element (EL). These constant voltages, ELVDD, ELVSS, Vinit, and Vref, can be set such that Vgs ≤ Vds under the worst-case condition. Figure 7 In this context, "Vds" represents the drain-source voltage of the driving element DT. The gate on-state voltages VGH and VEH can be set to voltages higher than the pixel driving voltage ELVDD, and the gate off-state voltages VGL and VEL can be set to voltages lower than the low-potential supply voltage ELVSS.

[0095] exist Figure 5 In the pixel circuit shown, the light-emitting element (EL) can be implemented using an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. This organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which a low-potential power supply voltage ELVSS is applied. When a voltage is applied to the anode and cathode electrodes of the EL, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the emissive layer (EML), forming excitons, and emitting visible light from the EML. The OLED used as the EL can have a tandem structure in which multiple emissive layers are stacked. Tandem structures in OLEDs can improve pixel brightness and lifetime.

[0096] The driving element DT generates current based on the gate-source voltage Vgs, thereby driving the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0097] The first capacitor Cst is connected between the second node n2 and the third node n3. The second capacitor C2 is connected between the first node n1 and the third node n3.

[0098] In the initialization step Ti, the first switching element M01 is turned on according to the gating voltage VGH of the initialization pulse INIT, and the initialization voltage Vinit is applied to the second node n2. The first switching element M01 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vinit is applied, a gate electrode connected to the first gating line GL1 to which the initialization pulse INIT is applied, and a second electrode connected to the second node n2.

[0099] The second switching element M02 is turned on according to the gating voltage VGH of the sensing pulse SENSE during the sensing step Ts and the data writing step Tw, and provides the reference voltage Vref to the fourth node n4. The second switching element M02 can maintain the on state during the hold period Th. The second switching element M02 includes a first electrode connected to the fourth node n4, a gate electrode connected to the second gating line GL2 to which the sensing pulse SENSE is applied, and a second electrode connected to the fourth power supply line RL.

[0100] The third switching element M03 is turned on in the data writing step Tw according to the gating voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and connects the data line DL to the second node n2. In the data writing step Tw, the data voltage Vdata is applied to the second node n2. The third switching element M03 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the third gating line GL3 to which the scan pulse SCAN is applied, and a second electrode connected to the second node n2.

[0101] In the initialization step Ti, the boost step Tboost, and the light emission step Tem, the fourth switching element M04 is turned on according to the gating voltage VEH of the EM pulse EM, and connects the third node n3 to the fourth node n4. The fourth switching element M04 includes a first electrode connected to the third node n3, a gate electrode connected to the fourth gating line GL4 to which the EM pulse EM is applied, and a second electrode connected to the fourth node n4.

[0102] like Figure 8A As shown, in initialization step Ti, the first switching element M01, the second switching element M02, and the fourth switching element M04 are turned on, while the third switching element M03 is turned off. At this time, the driving element DT is turned on, and the light-emitting element EL is not turned on.

[0103] In the sensing step Ts, such as Figure 8BAs shown, when the first switching element M01 and the second switching element M02 remain on, and the voltage of the third node n3 rises, causing the gate-source voltage Vgs of the driving element DT to reach the threshold voltage Vth, the driving element DT is turned off, and the threshold voltage Vth is stored in the first capacitor Cst. Since the fourth switching element M04 is turned off in the sensing step Ts, the third node n3 is not affected by the low-potential power supply voltage ELVSS and the light-emitting element EL. The ripple of the low-potential power supply voltage ELVSS is released through the second switching element M02 to the fourth power line RL, which is applied with a reference voltage Vref. During the holding period Th, the second node n2 and the third node n3 are floating, thereby maintaining their previous voltages, and the voltage of the fourth node n4 is the reference voltage Vref.

[0104] like Figure 8C As shown, in the data writing step Tw, the third switching element M03 is turned on, and the first switching element M01 is turned off. At this time, the pixel data voltage Vdata is applied to the second node n2, therefore, the voltage of the second node n2 changes to the data voltage Vdata.

[0105] During the boost step Tboost, the fourth switching element M04 is turned on, while the first switching element M01, the second switching element M02, and the third switching element M03 are turned off. At this time, the voltages at the second node n2 and the third node n3 rise.

[0106] like Figure 8D As shown, in the light-emitting step Tem, the fourth switching element M04 remains in the on state, while the first switching element M01, the second switching element M02, and the third switching element M03 remain in the off state. At this time, the current generated according to the gate-source voltage Vgs of the driving element DT (i.e., the voltage between the second node and the third node) is supplied to the light-emitting element EL, and the light-emitting element EL can emit light.

[0107] As described above, the pixel circuit of this disclosure cuts off the current path between the third node n3 and the low-potential power supply voltage ELVSS by turning off the fourth switching element M04 in the sensing step Ts and the data writing step Tw. As a result, since the gate-source voltage Vgs of the driving element DT is unaffected by the voltages of the low-potential power supply voltage ELVSS and the light-emitting element EL in the sensing step Ts and the data writing step Tw, the image quality of the display device does not deteriorate even when the anode voltages of the low-potential power supply voltage ELVSS and the light-emitting element EL change. The display device of this disclosure can achieve excellent image quality, wherein even in images where the data voltage Vdata changes significantly like a crosstalk pattern, pixel brightness fluctuations or crosstalk are not visually identifiable.

[0108] Figure 9This shows a comparison. Figure 3 The pixel circuit of the comparative example shown and Figure 5 The diagram shows experimental results of the brightness of the light-emitting element in the pixel circuit of this disclosure based on the cathode voltage.

[0109] Reference Figure 9 In the pixel circuit of the comparative example, since the light-emitting element EL is directly connected to the third node n3, the gate-source voltage Vgs of the driving element DT can change when the ripple of the low-potential power supply voltage ELVSS or the voltage of the light-emitting element EL changes. The low-potential power supply voltage ELVSS is applied to all pixels together through the second power line PL2 connected to all pixels. The second power line PL2 can correspond to the work function of the light-emitting element EL and can be a high-resistivity metal when considering the microcavity. If the resistance of the cathode electrode of the light-emitting element EL connected to the high-resistivity metal increases, the RC delay of the second power line PL2 increases and becomes more susceptible to ripple. Therefore, in the comparative example, as the cathode resistance of the light-emitting element EL increases, the brightness change ΔOLED of the light-emitting element EL becomes larger. On the other hand, in this disclosure, when the current path between the second electrode of the driving element DT and the light-emitting element EL is cut off in the sensing step Ts and the data writing step Tw, even if the cathode resistance, which is susceptible to the ripple of the low-potential power supply voltage ELVSS, increases, the brightness of the light-emitting element EL remains almost unchanged.

[0110] Figure 10 This is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure. Figure 11 It shows that it is applied to Figure 10 The waveform diagram of the gating signal of the pixel circuit is shown.

[0111] Reference Figure 10 and Figure 11 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M11 to M15, a first capacitor Cst, and a second capacitor C2. The driving element DT and the switching elements M11 to M15 can be implemented by an n-channel oxide TFT. However, the embodiments of this disclosure are not limited thereto. For example, at least one of the driving element DT and the switching elements M11 to M15 can be implemented by other types of n-channel TFTs or even by a p-channel TFT.

[0112] The pixel circuit is connected to the first power line PL1, which is subject to the pixel drive voltage ELVDD; the second power line PL2, which is subject to the low-potential power supply voltage ELVSS; the third power line PL3, which is subject to the initialization voltage Vinit; the fourth power line RL, which is subject to the reference voltage Vref; the data line DL, which is subject to the data voltage Vdata; and the gating lines GL1 to GL5, which are subject to the gating signals INIT, SENSE, SCAN, EM1 and EM2.

[0113] like Figure 10 As shown, the pixel circuit can be driven in the initialization step Ti, sensing step Ts, data writing step Tw, and emission step Temp. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the second node n2. After the voltages of the second node n2 and the third node n3 rise in the boost step Tboost, the emission element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the emission step Temp.

[0114] In initialization step Ti, the voltages of the initialization pulse INIT, the second EM pulse EM2, and the sensing pulse SENSE are the gate turn-on voltages VGH and VEH, and the voltages of the scan pulse SCAN and the first EM pulse EM1 are the gate cut-off voltages VGL and VEL. Figure 12A As shown, in initialization step Ti, the first switching element M11, the second switching element M12, the fifth switching element M15, and the driving element DT are turned on, while the third switching element M13 and the fourth switching element M14 are turned off. At this time, the initialization voltage Vinit is applied to the second node n2, and the reference voltage Vref is applied to the third node n3. Simultaneously, the pixel driving voltage ELVDD is applied to the first node n1.

[0115] The sensing pulse SENSE can rise to the gating on-state voltage VGH before entering the initialization step Ti, and fall to the gating off-state voltage VGL at the end of the initialization step Ti. During the pulse width of the sensing pulse SENSE (i.e., the portion of the gating on-state voltage VGH), the initialization pulse INIT reverses from the gating off-state voltage VGL to the gating on-state voltage VGH, and the first EM pulse EM1 reverses from the gating on-state voltage VEH to the gating off-state voltage VEL. The sensing pulse SENSE can be generated with a pulse width wider than that of the scan pulse SCAN. For example, the scan pulse SCAN has a pulse width of one horizontal period, while the sensing pulse SENSE can be generated within approximately two horizontal periods 2H.

[0116] In sensing step Ts, the initialization pulse INIT and the second EM pulse EM2 maintain the gated on-voltages VGH and VEH, while the scan pulse SCAN and the first EM pulse EM1 maintain the gated off-voltages VGL and VEL. In sensing step Ts, the sensing pulse SENSE is reversed to the gated off-voltage VGL. For example... Figure 12B As shown, in sensing step Ts, the first switching element M11 and the fifth switching element M15 remain in the on state, while the third switching element M13 and the fourth switching element M14 remain in the off state. In sensing step Ts, the second switching element M12 is off. When the voltage at the third node n3 rises, the driving element DT is off, and therefore the gate-source voltage Vgs reaches the threshold voltage Vth, which is stored in the first capacitor Cst.

[0117] In the data writing step Tw, a scan pulse SCAN is generated using the turn-on voltage VGH, synchronized with the data voltage Vdata of the pixel data. In the data writing step Tw, the second EM pulse EM2 can maintain the turn-on voltage VEH or reverse it to the turn-off voltage VEL. Therefore, in the data writing step Tw, the fifth switching element M15 can remain on or be off. When the second EM pulse EM2 maintains the turn-on voltage VEH in the data writing step Tw, the voltage of the third node n3 can change according to the mobility of the driving element DT, thereby compensating for changes or deviations in the mobility of the driving element DT.

[0118] In the data writing step Tw, the voltages of the initialization pulse INIT, the first EM pulse EM1, and the sensing pulse SENSE are set to the gating cutoff voltages VGL and VEL. For example... Figure 12C As shown, in the data writing step Tw, the third switching element M13 and the fifth switching element M15 are turned on, while the first switching element M11, the second switching element M12, and the fourth switching element M14 are turned off. When the voltage of the second node n2 rises to the data voltage Vdata and therefore the gate-source voltage Vgs becomes higher than the threshold voltage Vth, the driving element DT can be turned on.

[0119] In the light-emitting step Tem, the voltage of the first EM pulse EM1 and the second EM pulse EM2 is the gate turn-on voltage VEH, and the voltages of the other gate signals INIT, SENSE, and SCAN are the gate cut-off voltage VGL. For example... Figure 12DAs shown, in the light-emitting step Tem, the fourth switching element M14 and the fifth switching element M15 are turned on, while the first switching element M11, the second switching element M12, and the third switching element M13 are turned off. In the light-emitting step Tem, the pixel circuit operates as a source follower circuit, thus providing current to the light-emitting element EL according to the gate-source voltage Vgs of the driving element DT. At this time, the light-emitting element EL can emit light with a brightness corresponding to the grayscale of the pixel data.

[0120] The first EM pulse EM1 and the second EM pulse EM2 can swing between the gate on voltage VEH and the gate off voltage VEL to enhance the low grayscale performance in the light emission step Tem. In the light emission step Tem, the first EM pulse EM1 and the second EM pulse EM2 can swing with a duty cycle set to a preset pulse width modulation (PWM).

[0121] A floating period Tf can be set between the sensing step Ts and the data writing step Tw. During the floating period Tf, except for the second EM pulse EM2, the gating signals INIT, SENSE, SCAN, and EM1 are all at the gating cutoff voltages VGL and VEL. Therefore, during the floating period Tf, the first switching element M11 to the fourth switching element M14 are turned off, and the second node n2 to the fourth node n4 of the pixel circuit become floating, thereby maintaining their previous voltage.

[0122] A boost step Tboost can be set between the data writing step Tw and the light emission step Tem. In the boost step Tboost, the voltages of the first EM pulse EM1 and the second EM pulse EM2 are the turn-on voltage VEH, while the voltages of the other turn-on signals INIT, SENSE, and SCAN are the turn-off voltage VGL. Therefore, during the boost step Tboost, the fourth switching element M14 and the fifth switching element M15 are turned on, while the other switching elements M11, M12, and M13 are turned off. During the boost step Tboost, the voltages of the second node n2 and the third node n3 increase.

[0123] Apply to Figure 10 The constant voltages ELVDD, ELVSS, Vinit, and Vref of the pixel circuit shown can be set to ELVDD>Vinit>ELVSS>Vref or ELVDD>Vinit>Vref>ELVSS, as follows. Figure 7 As shown.

[0124] exist Figure 10In the pixel circuit shown, the light-emitting element EL can be implemented using an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. The anode electrode of the light-emitting element EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which a low-potential power supply voltage ELVSS is applied.

[0125] The driving element DT generates current based on the gate-source voltage Vgs, thereby driving the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0126] The first capacitor Cst is connected between the second node n2 and the third node n3. The second capacitor C2 is connected between the first node n1 and the third node n3.

[0127] In the initialization step Ti and the sensing step Ts, the first switching element M11 is turned on according to the gating voltage VGH of the initialization pulse INIT, and the initialization voltage Vinit is applied to the second node n2. The first switching element M11 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vinit is applied, a gate electrode connected to the first gating line GL1 to which the initialization pulse INIT is applied, and a second electrode connected to the second node n2.

[0128] In the initialization step Ti, the second switching element M12 is turned on according to the gating voltage VGH of the sensing pulse SENSE, and connects the third node n3 or the fourth node n4 to the fourth power supply line RL to which the reference voltage Vref is applied. The second switching element M12 includes a first electrode connected to the third node n3 or the fourth node n4, a gate electrode connected to the second gating line GL2 to which the sensing pulse SENSE is applied, and a second electrode connected to the fourth power supply line RL.

[0129] In the data writing step Tw, the third switching element M13 is turned on according to the gating voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and the data line DL is connected to the second node n2. In the data writing step Tw, the data voltage Vdata is applied to the second node n2. The third switching element M13 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the third gating line GL3 to which the scan pulse SCAN is applied, and a second electrode connected to the second node n2.

[0130] In the boost step Tboost and the light emission step Tem, the fourth switching element M14 is turned on according to the selection voltage VEH of the first EM pulse EM1, and connects the third node n3 to the fourth node n4. The fourth switching element M14 includes a first electrode connected to the third node n3, a gate electrode connected to the fourth selection line GL4 to which the first EM pulse EM1 is applied, and a second electrode connected to the fourth node n4.

[0131] In the initialization step Ti, sensing step Ts, floating period Tf, data writing step Tw, boosting step Tboost, and light emission step Tem, the fifth switching element M15 is turned on according to the gating voltage VEH of the second EM pulse EM2, and can provide the pixel driving voltage ELVDD to the first node n1. In another embodiment, in the data writing step Tw, the fifth switching element M15 can be reversed to the gating cutoff voltage VEL. The fifth switching element M15 includes a first electrode connected to the first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to the fifth gating line GL5 to which the second EM pulse EM2 is applied, and a second electrode connected to the first node n1.

[0132] exist Figure 10 In the pixel circuit shown, by separating the anode electrode of the light-emitting element EL and the third node n3, the fourth switching element M14 ensures that the ripple of the low-potential power supply voltage ELVSS and the voltage fluctuations of the light-emitting element EL do not affect the gate-source voltage Vgs of the driving element DT. By separating the anode voltage of the light-emitting element EL and the reference voltage Vref, the pixel circuit facilitates control of the threshold voltage compensation of the driving element DT and improves image quality. For example, by preventing the gate-source voltage Vgs of the driving element DT from changing according to the fluctuations of the anode voltage of the light-emitting element EL, crosstalk will not be visually detected in image patterns that cause crosstalk, and non-uniformity at low gray levels will not be visually detected.

[0133] Figure 13 This is a circuit diagram illustrating a pixel circuit according to a third embodiment of the present disclosure. Figure 14 It shows that it is applied to Figure 13 The waveform diagram of the gating signal of the pixel circuit is shown. Figure 15 It shows that it is applied to Figure 13 A diagram showing the constant voltage of the pixel circuit.

[0134] Reference Figure 13 and Figure 14The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M21 to M26, a first capacitor Cst, and a second capacitor C2. The driving element DT and the switching elements M21 to M26 can be implemented by an n-channel oxide TFT. However, embodiments of this disclosure are not limited thereto. For example, at least one of the driving element DT and the switching elements M21 to M26 can be implemented by other types of n-channel TFTs or even by a p-channel TFT.

[0135] The pixel circuit is connected to the first power line PL1, which is supplied with the pixel drive voltage ELVDD; the second power line PL2, which is supplied with the low-potential power supply voltage ELVSS; the third power line PL3, which is supplied with the initialization voltage Vinit; the fourth power line RL, which is supplied with the reference voltage Vref; the data line DL, which is supplied with the data voltage Vdata; and the gating lines GL1 to GL6, which are supplied with the gating signals INIT, INIT2, SENSE, SCAN, EM1, and EM2. The pixel circuit can also be connected to the fifth power line PL5, which is supplied with the preset anode voltage Vano.

[0136] like Figure 15 As shown, the constant voltages ELVDD, ELVSS, Vinit, Vref, and Vano applied to the pixel circuit can be set to ELVDD>Vano>Vinit>ELVSS>Vref or ELVDD>Vano>Vinit>Vref>ELVSS, including a voltage drop margin for operation in the saturation region of the driving element DT. Figure 15 In the middle, V OLED_peak It is the peak voltage between the two ends of the light-emitting element (EL). Figure 15 In this context, "Vds" represents the drain-source voltage of the driving element DT. The gate on-state voltages VGH and VEH can be set to voltages higher than the pixel driving voltage ELVDD, and the gate off-state voltages VGL and VEL can be set to voltages lower than the low-potential supply voltage ELVSS.

[0137] like Figure 14 As shown, the pixel circuit can be driven in the initialization step Ti, sensing step Ts, data writing step Tw, and emission step Temp. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the second node n2. After the voltages of the second node n2 and the third node n3 rise in the boost step Tboost, the emission element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the emission step Temp.

[0138] In initialization step Ti, the voltages of the initialization pulse INIT, the second initialization pulse INIT2, the second EM pulse EM2, and the sensing pulse SENSE are the gate turn-on voltages VGH and VEH, and the voltages of the scan pulse SCAN and the first EM pulse EM1 are the gate cut-off voltages VGL and VEL. Figure 16A As shown, in initialization step Ti, the first switching element M21, the second switching element M22, the fifth switching element M25, the sixth switching element M26, and the driving element DT are turned on, while the third switching element M23 and the fourth switching element M24 are turned off. At this time, the initialization voltage Vinit is applied to the second node n2, and the reference voltage Vref is applied to the third node n3. Simultaneously, the pixel driving voltage ELVDD is applied to the first node n1, and the initialization voltage Vinit or the anode voltage Vano is applied to the fourth node n4.

[0139] In sensing step Ts, the initialization pulse INIT, the second initialization pulse INIT2, and the second EM pulse EM2 maintain the gated on-voltages VGH and VEH, while the scan pulse SCAN and the first EM pulse EM1 maintain the gated off-voltages VGL and VEL. In sensing step Ts, the sensing pulse SENSE is reversed to the gated off-voltage VGL. For example... Figure 16B As shown, in sensing step Ts, the first switching element M21, the fifth switching element M25, and the sixth switching element M26 remain in the on state, while the third switching element M23 and the fourth switching element M24 remain in the off state. In sensing step Ts, the second switching element M22 is off. When the voltage at the third node n3 rises and therefore the gate-source voltage Vgs reaches the threshold voltage Vth, the driving element DT is off, and its threshold voltage Vth is stored in the first capacitor Cst.

[0140] In the data writing step Tw, a scan pulse SCAN is generated using the turn-on voltage VGH, synchronized with the data voltage Vdata of the pixel data. In the data writing step Tw, the second initialization pulse INIT2 maintains the turn-on voltage VGH. In the data writing step Tw, the second EM pulse EM2 can maintain the turn-on voltage VGH or reverse to the turn-off voltage VGL. Therefore, in the data writing step Tw, the fifth switching element M25 can remain on or be off.

[0141] In the data writing step Tw, the voltages of the initialization pulse INIT, the first EM pulse EM1, and the sensing pulse SENSE are set to the gating cutoff voltages VGL and VEL. For example... Figure 16CAs shown, in the data writing step Tw, the third switching element M23, the fifth switching element M25, and the sixth switching element M26 are turned on, while the first switching element M21, the second switching element M22, and the fourth switching element M24 are turned off. When the voltage of the second node n2 rises to the data voltage Vdata and therefore the gate-source voltage Vgs becomes higher than the threshold voltage Vth, the driving element DT can be turned on.

[0142] In the light-emitting step Tem, the voltage of the first EM pulse EM1 and the second EM pulse EM2 is the gate turn-on voltage VEH, and the voltages of the other gate signals INIT, INIT2, SENSE, and SCAN are the gate cut-off voltage VGL. For example... Figure 16D As shown, in the light-emitting step Tem, the fourth switching element M24 and the fifth switching element M25 are turned on, while the other switching elements M21, M22, M23, and M26 are turned off. In the light-emitting step Tem, the pixel circuit operates as a source follower circuit, thus supplying current to the light-emitting element EL according to the gate-source voltage Vgs of the driving element DT. At this time, the light-emitting element EL can emit light with a brightness corresponding to the grayscale of the pixel data.

[0143] The first EM pulse EM1 and the second EM pulse EM2 can swing between the gate on voltage VEH and the gate off voltage VEL to enhance the low grayscale performance in the light emission step Tem. In the light emission step Tem, the first EM pulse EM1 and the second EM pulse EM2 can swing with a duty cycle set to a preset pulse width modulation (PWM).

[0144] A hold period Th can be set between the sensing step Ts and the data writing step Tw. During the hold period Th, the voltages of the second initialization pulse INIT2 and the second EM pulse EM2 are the gating on voltages VGH and VEH, and the other gating signals INIT, SENSE, SCAN, and EM1 are at the gating off voltages VGL and VEL. During the hold period Th, the pixel drive voltage ELVDD is applied to the first node n1, and the initialization voltage Vinit or the anode voltage Vano is applied to the fourth node n4. During the hold period Th, the first switching element M21 to the fourth switching element M24 are turned off, therefore, the first node n1 to the third node n3 are in a floating state.

[0145] A boost step Tboost can be set between the data writing step Tw and the light emission step Tem. In the boost step Tboost, the voltages of the first EM pulse EM1 and the second EM pulse EM2 are the gate turn-on voltage VEH, and the voltages of the other gate signals INIT, INIT2, SENSE, and SCAN are the gate cut-off voltage VGL. Therefore, during the boost step Tboost, the fourth switching element M24 and the fifth switching element M25 are turned on, and the other switching elements M21, M22, M23, and M26 are turned off. During the boost step Tboost, the voltages of the second node n2 and the third node n3 increase.

[0146] On the other hand, the second initialization pulse INIT2 can maintain the gate on-state voltage VGH at the start of the boost step Tboost, and then reverse to the gate off-state voltage VGL. Therefore, the initialization voltage Vinit or the anode voltage Vano can be applied to the fourth node n4 at the start of the boost step Tboost.

[0147] exist Figure 13 In the pixel circuit shown, the light-emitting element EL can be implemented using an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. The anode electrode of the light-emitting element EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which a low-potential power supply voltage ELVSS is applied.

[0148] The driving element DT generates current based on the gate-source voltage Vgs, thereby driving the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0149] The first capacitor Cst is connected between the second node n2 and the third node n3. The second capacitor C2 is connected between the first node n1 and the third node n3.

[0150] In the initialization step Ti and the sensing step Ts, the first switching element M21 is turned on according to the gating voltage VGH of the initialization pulse INIT, and the initialization voltage Vinit is applied to the second node n2. The first switching element M21 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vinit is applied, a gate electrode connected to the first gating line GL1 to which the initialization pulse INIT is applied, and a second electrode connected to the second node n2.

[0151] In the initialization step Ti, the second switching element M22 is turned on according to the gating voltage VGH of the sensing pulse SENSE, and connects the third node n3 to the fourth power supply line RL to which the reference voltage Vref is applied. The second switching element M22 includes a first electrode connected to the third node n3, a gate electrode connected to the second gating line GL2 to which the sensing pulse SENSE is applied, and a second electrode connected to the fourth power supply line RL.

[0152] In the data writing step Tw, the third switching element M23 is turned on according to the gating voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and the data line DL is connected to the second node n2. In the data writing step Tw, the data voltage Vdata is applied to the second node n2. The third switching element M23 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the third gating line GL3 to which the scan pulse SCAN is applied, and a second electrode connected to the second node n2.

[0153] In the boost step Tboost and the light emission step Tem, the fourth switching element M24 is turned on according to the selection voltage VEH of the first EM pulse EM1, and connects the third node n3 to the fourth node n4. The fourth switching element M24 includes a first electrode connected to the third node n3, a gate electrode connected to the fourth selection line GL4 to which the first EM pulse EM1 is applied, and a second electrode connected to the fourth node n4.

[0154] In the initialization step Ti, sensing step Ts, hold period Th, data writing step Tw, boost step Tboost, and light emission step Temp, the fifth switching element M25 is turned on according to the gating voltage VEH of the second EM pulse EM2, and can provide the pixel driving voltage ELVDD to the first node n1. In another embodiment, in the data writing step Tw, the fifth switching element M25 can be reversed to the gating cutoff voltage VEL. The fifth switching element M25 includes a first electrode connected to a first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to a fifth gating line GL5 to which the second EM pulse EM2 is applied, and a second electrode connected to the first node n1.

[0155] In the initialization step Ti, sensing step Ts, hold period th, and data writing step Tw, the sixth switching element M26 is turned on according to the gating voltage VGH of the second initialization pulse INIT2, and applies the initialization voltage Vinit1 or the anode voltage Vano to the fourth node n4. The sixth switching element M26 includes a first electrode connected to the fourth node n4, a gate electrode connected to the sixth gating line GL6 to which the second initialization pulse INIT2 is applied, and a second electrode connected to the third power line PL3 to which the initialization voltage Vinit is applied or the fifth power line PL5 to which the anode voltage Vano is applied. If the initialization voltage Vinit is applied to the fourth node n4 through the sixth switching element M26, the bezel area BZ can be reduced as the number of power lines decreases because the fifth power line PL5 is not required, and design margins can also be ensured.

[0156] exist Figure 13 In the pixel circuit shown, by separating the anode electrode of the light-emitting element EL from the third node n3, the fourth switching element M24 ensures that the ripple of the low-potential power supply voltage ELVSS and the voltage fluctuation of the light-emitting element EL do not affect the gate-source voltage Vgs of the driving element DT. By separating the anode voltage of the light-emitting element EL from the reference voltage Vref, this pixel circuit facilitates control of the threshold voltage compensation of the driving element DT and improves image quality.

[0157] Figure 17 This is a circuit diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure. Figure 18 It shows that it is applied to Figure 17 The waveform of the gating signal for the pixel circuit shown is illustrated. This pixel circuit is the pixel circuit of the sub-pixel arranged in the nth (n is a natural number) pixel row.

[0158] Reference Figure 17 and Figure 18 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, multiple switching elements M31 to M36, a first capacitor Cst, and a second capacitor C2. The driving element DT and the switching elements M31 to M36 can be implemented by an n-channel oxide TFT.

[0159] The pixel circuit is connected to a first power line PL1 with an applied pixel drive voltage ELVDD, a second power line PL2 with an applied low-potential power supply voltage ELVSS, a third power line PL3 with an applied initialization voltage Vinit, a fourth power line RL with an applied reference voltage Vref, a data line DL with an applied data voltage Vdata, and gating lines GL1 to GL6 with applied gating signals [INIT, SENSE(n), SENSE(n+1), SCAN, EM1, and EM2]. The pixel circuit can be connected to a fifth power line PL5 with an applied preset anode voltage Vano. The (n+1)th sensing pulse [SENSE(n+1)] applied to the nth pixel row is applied as the nth sensing pulse [SENSE(n)] to the (n+1)th pixel row. The pulse width of the sensing pulses [SENSE(n), SENSE(n+1)] can be set to be wider than the pulse width of the scan pulse SCAN. For example, the sensing pulses [SENSE(n), SENSE(n+1)] can be set to a pulse width of two horizontal periods, while the scanning pulse SCAN can be set to a pulse width of one horizontal period. The (n+1)th sensing pulse [SENSE(n+1)] can be generated after the nth sensing pulse [SENSE(n)], and can overlap with the nth sensing pulse [SENSE(n)] by approximately one horizontal period.

[0160] The constant voltages ELVDD, ELVSS, Vinit, Vref, and Vano applied to the pixel circuit are... Figure 15 The same as shown.

[0161] like Figure 18 As shown, the pixel circuit can be driven in the initialization step Ti, sensing step Ts, data writing step Tw, and emission step Temp. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the second node n2. After the voltages of the second node n2 and the third node n3 rise in the boost step Tboost, the emission element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the emission step Temp.

[0162] In initialization step Ti, the voltages of the initialization pulse INIT, the second EM pulse EM2, and the nth sensing pulse [SENSE(n)] are the gate turn-on voltages VGH and VEH, and the voltages of the scan pulse SCAN, the (n+1)th sensing pulse [SENSE(n+1)], and the first EM pulse EM1 are the gate cut-off voltages VGL and VEL. Figure 19AAs shown, in initialization step Ti, the first switching element M31, the second switching element M32, the fifth switching element M35, and the driving element DT are turned on, while the third switching element M33, the fourth switching element M34, and the sixth switching element M36 are turned off. At this time, the initialization voltage Vinit is applied to the second node n2, and the reference voltage Vref is applied to the third node n3. Simultaneously, the pixel driving voltage ELVDD is applied to the first node n1.

[0163] In sensing step Ts, the initialization pulse INIT and the second EM pulse EM2 maintain the gating on voltages VGH and VEH, and the scan pulse SCAN and the first EM pulse EM1 maintain the gating off voltages VGL and VEL. The nth sensing pulse [SENSE(n)] and the (n+1)th sensing pulse [SENSE(n+1)] are generated at the start of sensing step Ts with the gating on voltage VGH, and then reversed to the gating off voltage VGL. Figure 19B As shown, in sensing step Ts, the first switching element M31, the second switching element M32, the fifth switching element M35, and the sixth switching element M36 are turned on, while the third switching element M33 and the fourth switching element M34 are turned off. When the voltage of the third node n3 rises and therefore the gate-source voltage Vgs reaches the threshold voltage Vth, the driving element DT is turned off, and its threshold voltage Vth is stored in the first capacitor Cst.

[0164] In the data writing step Tw, a scan pulse SCAN is generated using the turn-on voltage VGH, synchronized with the data voltage Vdata of the pixel data. In the data writing step Tw, the second EM pulse EM2 can maintain the turn-on voltage VGH or reverse to the turn-off voltage VGL. Therefore, in the data writing step Tw, the fifth switching element M35 can remain on or be off.

[0165] In the data writing step Tw, the voltages of the initialization pulse INIT, the first EM pulse EM1, the nth sensing pulse [SENSE(n)], and the (n+1)th sensing pulse [SENSE(n+1)] are set to the gating cutoff voltages VGL and VEL. For example... Figure 19C As shown, in the data writing step Tw, the third switching element M33 and the fifth switching element M35 are turned on, while the other switching elements M31, M32, M34, and M36 are turned off. When the voltage of the second node n2 rises through the data voltage Vdata and thus the gate-source voltage Vgs becomes higher than the threshold voltage Vth, the driving element DT can be turned on.

[0166] In the light-emitting step Tem, the voltages of the first EM pulse EM1 and the second EM pulse EM2 are the gate turn-on voltage VEH, and the voltages of the other gate signals [INIT, SENSE(n), SENSE(n+1), SCAN] are the gate cut-off voltage VGL. For example... Figure 19D As shown, in the light-emitting step Tem, the fourth switching element M34 and the fifth switching element M35 are turned on, while the other switching elements M31, M32, M33, and M36 are turned off. In the light-emitting step Tem, the pixel circuit operates as a source follower circuit, thus providing current to the light-emitting element EL according to the gate-source voltage Vgs of the driving element DT. At this time, the light-emitting element EL can emit light with a brightness corresponding to the grayscale of the pixel data.

[0167] In the light-emitting step Tem, the first EM pulse EM1 and the second EM pulse EM2 can swing between the gate on-voltage VEH and the gate off-voltage VEL to enhance low grayscale performance. In the light-emitting step Tem, the first EM pulse EM1 and the second EM pulse EM2 can swing with a duty cycle set to a preset pulse width modulation (PWM).

[0168] A floating period Tf can be set between the sensing step Ts and the data writing step Tw. During the floating period Tf, the voltage of the second EM pulse EM2 is the gating on-state voltage VEH, and the other gating signals [INIT, SENSE(n), SENSE(n+1), SCAN, EM1] are at the gating off-state voltages VGL and VEL. Therefore, during the floating period Tf, switching elements M31 to M34 and M36, except for the fifth switching element M35, are turned off, and the second to fourth nodes n2, n3 and n4 become floating, thereby maintaining their previous voltages.

[0169] A boost step Tboost can be set between the data writing step Tw and the light emission step Tem. In the boost step Tboost, the voltages of the EM pulses EM1 and EM2, and the sensing pulses [SENSE(n), SENSE(n+1)], are the gate turn-on voltages VEH and VGH, respectively, while the initialization pulse INIT and the scan pulse SCAN are at the gate cut-off voltage VGL. Therefore, during the boost step Tboost, the second switching element M32, the fourth switching element M34, the fifth switching element M35, and the sixth switching element M36 are turned on, while the first switching element M31 and the third switching element M33 are turned off. During the boost step Tboost, the voltages of the second node n2 and the third node n3 increase.

[0170] exist Figure 17In the pixel circuit shown, the light-emitting element EL can be implemented using an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. The anode electrode of the light-emitting element EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which a low-potential power supply voltage ELVSS is applied.

[0171] The driving element DT generates current based on the gate-source voltage Vgs, thereby driving the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0172] The first capacitor Cst is connected between the second node n2 and the third node n3. The second capacitor C2 is connected between the first node n1 and the third node n3.

[0173] In the initialization step Ti and the sensing step Ts, the first switching element M31 is turned on according to the gating voltage VGH of the initialization pulse INIT, and the initialization voltage Vinit is applied to the second node n2. The first switching element M31 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vinit is applied, a gate electrode connected to the first gating line GL1 to which the initialization pulse INIT is applied, and a second electrode connected to the second node n2.

[0174] In the sensing step Ts, the second switching element M32 is turned on according to the gating voltage VGH of the nth sensing pulse [SENSE(n)], and the third node n3 is connected to the fourth power supply line RL to which the reference voltage Vref is applied. The second switching element M32 includes a first electrode connected to the third node n3, a gate electrode connected to the second-first gating line GL2a to which the nth sensing pulse [SENSE(n)] is applied, and a second electrode connected to the fourth power supply line RL.

[0175] In the data writing step Tw, the third switching element M33 is turned on according to the gating voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and the data line DL is connected to the second node n2. In the data writing step Tw, the data voltage Vdata is applied to the second node n2. The third switching element M33 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the third gating line GL3 to which the scan pulse SCAN is applied, and a second electrode connected to the second node n2.

[0176] In the boost step Tboost and the light emission step Tem, the fourth switching element M34 is turned on according to the selection voltage VEH of the first EM pulse EM1, and connects the third node n3 to the fourth node n4. The fourth switching element M34 includes a first electrode connected to the third node n3, a gate electrode connected to the fourth selection line GL4 to which the first EM pulse EM1 is applied, and a second electrode connected to the fourth node n4.

[0177] In the initialization step Ti, sensing step Ts, floating period Tf, data writing step Tw, boost step Tboost, and light emission step Temp, the fifth switching element M35 is turned on according to the gating voltage VEH of the second EM pulse EM2, and can provide the pixel driving voltage ELVDD to the first node n1. In another embodiment, in the data writing step Tw, the fifth switching element M35 can be reversed to the gating cutoff voltage VEL. The fifth switching element M35 includes a first electrode connected to the first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to the fifth gating line GL5 to which the second EM pulse EM2 is applied, and a second electrode connected to the first node n1.

[0178] In the sensing step Ts and the boost write step Tboost, the sixth switching element M36 is turned on according to the gating voltage VGH of the (n+1)th sensing pulse [SENSE(n+1)], and applies an initialization voltage Vinit1 or an anode voltage Vano to the fourth node n4. The sixth switching element M36 includes a first electrode connected to the fourth node n4, a gate electrode connected to the second-second gating line GL2b to which the (n+1)th sensing pulse [SENSE(n+1)] is applied, and a second electrode connected to the third power line PL3 to which the initialization voltage Vinit is applied or the fifth power line PL5 to which the anode voltage Vano is applied. If the initialization voltage Vinit is applied to the fourth node n4 through the sixth switching element M36, the bezel area BZ can be reduced as the number of power lines decreases because the fifth power line PL5 is not required, and design margins can also be ensured.

[0179] Since the (n+1)th sensing pulse [SENSE(n+1)] is applied to the sixth switching element M36, it is related to... Figure 13 Compared to the pixel circuit shown, the number of gate lines can be reduced, and the border area can be reduced.

[0180] exist Figure 17In the pixel circuit shown, by separating the anode electrode of the light-emitting element EL and the third node n3, the fourth switching element M34 ensures that the ripple of the low-potential power supply voltage ELVSS and the voltage fluctuation of the light-emitting element EL do not affect the gate-source voltage Vgs of the driving element DT. By separating the anode voltage of the light-emitting element EL and the reference voltage Vref, this pixel circuit facilitates the control of the threshold voltage compensation of the driving element DT and improves image quality.

[0181] Figure 20 This is a circuit diagram illustrating a pixel circuit according to a fifth embodiment of the present disclosure; and Figure 21 and Figure 22 It shows that it is applied to Figure 20 The waveform of the gating signal for the pixel circuit is shown. Figure 21 and Figure 22 In this context, "DTG" is the voltage of the second node n2, and "DTS" is the voltage of the third node n3.

[0182] Reference Figures 20 to 22 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, multiple switching elements M51 to M55, a first capacitor Cst, and a second capacitor C2. The driving element DT and the switching elements M51 to M55 can be implemented as an n-channel oxide TFT.

[0183] The pixel circuit is connected to the first power line PL1, which is subject to the pixel drive voltage ELVDD; the second power line PL2, which is subject to the low-potential power supply voltage ELVSS; the third power line PL3, which is subject to the initialization voltage Vinit; the fourth power line RL, which is subject to the reference voltage Vref; the data line DL, which is subject to the data voltage Vdata; and the gating lines GL1 to GL5, which are subject to the gating signals INIT, SENSE, SCAN, EM1 and EM2.

[0184] like Figure 21 As shown, the pixel circuit can be driven in the initialization step Ti, sensing step Ts, data writing step Tw, and light emission step Tem. A boost step Tboost can be set between the data writing step Tw and the light emission step Tem, where the voltages of the second node n2 and the third node n3 increase. To prevent visually detectable flickering in low-speed drive mode, an anode reset step AR can be set between the data writing step Tw and the boost step Tboost.

[0185] In initialization step Ti, the voltages of the initialization pulse INIT, the first EM pulse EM1, the second EM pulse EM2, and the sensing pulse SENSE are the gate-on voltages VGH and VEH, respectively, and the voltage of the scanning pulse SCAN is the gate-off voltage VGL. Therefore, in initialization step Ti, the first switching element M51, the second switching element M52, the fourth switching element M54, the fifth switching element M55, and the driving element DT are turned on, while the third switching element M53 is turned off. In this case, the initialization voltage Vinit is applied to the second node n2, and the reference voltage Vref is applied to the third node n3. Simultaneously, the pixel driving voltage ELVDD is applied to the first node n1.

[0186] In sensing step Ts, the initialization pulse INIT, the sensing pulse SENSE, and the second EM pulse EM2 maintain the gate on voltages VGH and VEH, and the scan pulse SCAN maintains the gate off voltage VGL. In sensing step Ts, the first EM pulse EM1 reverses to the gate off voltage VEL. In sensing step Ts, the first switching element M51, the second switching element M52, and the fifth switching element M55 remain on, while the third switching element M53 and the fourth switching element M54 are off. In sensing step Ts, since the fourth switching element M54 is off and the second switching element M52 is on, the current path between the third node n3 and the fourth node n4 is cut off, and the reference voltage Vref is applied to the anode electrode of the light-emitting element EL. Therefore, residual charge in the light-emitting element EL can be removed, and the ripple of the low-potential power supply voltage ELVSS can be prevented from affecting the anode electrode of the light-emitting element EL and the third node n3.

[0187] like Figure 21 As shown, in the sensing step Ts, when the voltage DTS of the third node n3 rises so that the voltage between the second node n2 and the third node n3 (i.e., the gate-source voltage Vgs of the driving element DT) reaches the threshold voltage Vth, the driving element DT is turned off, and the threshold voltage is stored in the capacitor Cst.

[0188] In the data writing step Tw, a scan pulse SCAN, synchronized with the pixel data data voltage Vdata, is generated using the gate conduction voltage VGH, and a sensing pulse SENSE is also generated using the gate conduction voltage VGH. In the data writing step Tw, the data voltage Vdata is applied to the second node n2 to increase the voltages of the second node n2 and the third node n3. In the data writing step Tw, the second EM pulse EM2 can maintain the gate conduction voltage VEH or reverse to the gate cutoff voltage VEL. Therefore, in the data writing step Tw, the second switching element M52 and the third switching element M53 can be turned on, and the fifth switching element M55 can remain on or be turned off.

[0189] When the second EM pulse EM2 maintains the gate conduction voltage VEH during the data writing step Tw, the voltage of the third node n3 can be changed according to the mobility of the driving element DT, thereby compensating for changes or deviations in the mobility of the driving element DT. For example, as Figure 22 As shown, when the mobility μ of the driving element DT is high during the duration of the data writing step Tw, the voltage DTS of the third node n3 increases, thus reducing the gate-source voltage Vgs of the driving element DT. Conversely, when the mobility μ of the driving element DT is relatively lower, the voltage DTS of the third node n3 decreases, and the gate-source voltage Vgs of the driving element DT increases. Therefore, changes or deviations in the mobility of the driving element DT can be compensated for during the data writing step Tw.

[0190] In the data writing step Tw, the initialization pulse INIT and the first EM pulse EM1 are at the gate cutoff voltages VGL and VEL. In the data writing step Tw, the first switching element M51 and the fourth switching element M54 are turned off.

[0191] In the anode reset step AR, a first EM pulse EM1 and a sensing pulse SENSE are generated using the gate on-state voltages VGH and VEH, and a second EM pulse EM2, an initialization pulse INIT, and a scan pulse SCAN are generated using the gate off-state voltages VGL and VEL. Therefore, in the anode reset step AR, the second switching element M52 and the fourth switching element M54 are turned on to provide the reference voltage Vref to the third node n3 and the fourth node n4. In the anode reset step AR, the first switching element M51, the third switching element M53, and the fifth switching element M55 are turned off.

[0192] In the boost step Tboost, the first EM pulse EM1 and the second EM pulse EM2 are generated using the gate turn-on voltage VEH, and other gating signals INIT, SENSE, and SCAN are generated using the gate cut-off voltage VGL. In the boost step Tboost, the fourth switching element M54 and the fifth switching element M55 are turned on, while the first switching element M51, the second switching element M52, and the third switching element M53 are turned off. In the boost step Tboost, the voltages DTG and DTS of the second node n2 and the third node n3 rise to the turn-on voltage of the light-emitting element EL, and in this case, the capacitor of the light-emitting element EL (…) Figure 3 (Cel) charging.

[0193] In the light-emitting step Tem, the voltages of the first EM pulse EM1 and the second EM pulse EM2 maintain the gate on-state voltage VEH, and the voltages of other gate signals INIT, SENSE, and SCAN maintain the gate off-state voltage VGL. In the light-emitting step Tem, the fourth switching element M54 and the fifth switching element M55 are turned on, while the first switching element M51, the second switching element M52, and the third switching element M53 are turned off. In the light-emitting step Tem, the pixel circuit operates as a source follower circuit, thereby providing current to the light-emitting element EL according to the gate-source voltage Vgs of the driving element DT. At this time, the light-emitting element EL can emit light with a brightness corresponding to the grayscale of the pixel data.

[0194] The first EM pulse EM1 and the second EM pulse EM2 can swing between the gate on voltage VEH and the gate off voltage VEL to enhance the low grayscale performance in the light emission step Tem. In the light emission step Tem, the first EM pulse EM1 and the second EM pulse EM2 can swing with a duty cycle set to a preset pulse width modulation (PWM).

[0195] Apply to Figure 20 The constant voltages ELVDD, ELVSS, Vinit, and Vref of the pixel circuit shown can be set to ELVDD>Vinit>Vref>ELVSS, but are not limited to this. For example, the constant voltages can be set to ELVDD=12V, Vinit=1V, Vref=-4V, and ELVSS=-6V.

[0196] The light-emitting element (EL) can be implemented as an OLED. The OLED used as the light-emitting element (EL) can be a stacked structure in which multiple light-emitting layers are stacked. Preferably, the reference voltage Vref is set to a voltage less than the turn-on voltage of the OLED, that is, Vref < (ELVSS + voltage used to turn on the OLED), so that the black brightness does not increase. Figure 23 The on-state voltage and current IOLED of the OLED are shown.

[0197] exist Figure 23 In this context, "ΔV" represents the voltage difference between the initialization voltage Vinit and the reference voltage Vref. This can be considered... Figure 24The positive bias temperature stress (PBTS) margin is shown to set ΔV. Considering the maximum amount the threshold voltage of the drive element can shift towards positive polarity due to PBTS, a PBTS margin is ensured within the voltage compensation range. For example, when the threshold voltage Vth of the drive element DT shifts to 5V, it can be set to Vref = Vinit - 5V - PBTS margin (1V). The PBTS margin can be the minimum voltage deviation required to perform sensing operation on the threshold voltage of the drive element DT. Without ensuring this PBTS margin, the sensing error may further increase as the amount of threshold voltage shift by the drive element DT increases.

[0198] The driving element DT generates current based on the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0199] The first capacitor Cst is connected between the second node n2 and the third node n3. The second capacitor C2 is connected between the third node n3 and the fifth node n5. A constant voltage DC is applied to the fifth node n5. The constant voltage DC can be any one of ELVDD, Vinit, and Vref.

[0200] In the initialization step Ti and the sensing step Ts, the first switching element M51 is turned on according to the gating voltage VGH of the initialization pulse INIT, and the initialization voltage Vinit is applied to the second node n2. The first switching element M51 includes a first electrode connected to the third power supply line PL3 to which the initialization voltage Vinit is applied, a gate electrode connected to the first gating line GL1 to which the initialization pulse INIT is applied, and a second electrode connected to the second node n2.

[0201] The second switching element M52 is turned on according to the gating voltage VGH of the sensing pulse SENSE during the initialization step Ti and the sensing step Ts, and connects the fourth node n4 to the fourth power supply line RL to which a reference voltage Vref is applied. The second switching element M52 includes a first electrode connected to the fourth node n4, a gate electrode connected to the second gating line GL2 to which the sensing pulse SENSE is applied, and a second electrode connected to the fourth power supply line RL.

[0202] In the data writing step Tw, the third switching element M53 is turned on according to the gating voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and the data line DL is connected to the first node n2. In the data writing step Tw, the data voltage Vdata is applied to the second node n2. The third switching element M53 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the third gating line GL3 to which the scan pulse SCAN is applied, and a second electrode connected to the second node n2.

[0203] In the boost step Tboost and the light emission step Tem, the fourth switching element M54 is turned on according to the gating voltage VEH of the first EM pulse EM1, and the third node n3 is connected to the fourth node n4. In the anode reset step of the low-speed drive mode, the fourth switching element M54 can be turned on according to the gating voltage VEH of the first EM pulse EM1. The fourth switching element M54 includes a first electrode connected to the third node n3, a gate electrode connected to the fourth gating line GL4 to which the first EM pulse EM1 is applied, and a second electrode connected to the fourth node n4.

[0204] In the initialization step Ti, sensing step Ts, boost step Tboost, and light emission step Tem, the fifth switching element M55 is turned on according to the gating voltage VEH of the second EM pulse EM2, and provides the pixel driving voltage ELVDD to the first node n1. In the data writing step Tw, the fifth switching element M55 can be turned on according to the gating voltage VEH of the second EM pulse EM2. The fifth switching element M55 includes a first electrode connected to the first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to the fifth gating line GL5 to which the second EM pulse EM2 is applied, and a second electrode connected to the first node n1.

[0205] The objectives to be achieved, the means to achieve them, and the effects of this disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0206] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0207] Cross-references to related applications

[0208] This application claims priority and benefit to Korean Patent Application No. 10-2021-0089996, filed July 8, 2021; Korean Patent Application No. 10-2021-0170672, filed December 2, 2021; and Korean Patent Application No. 10-2022-0060579, filed May 18, 2022, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A pixel circuit, the pixel circuit comprising: A driving element, the driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; A light-emitting element, the light-emitting element comprising an anode electrode connected to a fourth node and a cathode electrode to which a low potential power supply voltage is applied; A first switching element includes a first electrode to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the second node, and the first switching element is configured to provide the initialization voltage to the second node in response to the initialization pulse; A second switching element includes a first electrode connected to the fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied, and the second switching element is configured to provide the reference voltage to the fourth node in response to the sensing pulse; A third switching element includes a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node, and the third switching element is configured to provide the data voltage to the second node in response to the scan pulse; as well as A fourth switching element includes a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node, and the fourth switching element is configured to connect the third node to the fourth node in response to the first emission control pulse. The pixel circuit is driven in the order of initialization, sensing, data writing, and light emission. In the sensing step, the voltages of the initialization pulse and the sensing pulse are gate turn-on voltages, and the voltages of the first light emission control pulse and the scanning pulse are gate cut-off voltages.

2. The pixel circuit according to claim 1, further comprising: A first capacitor is connected between the second node and the third node; as well as A second capacitor is connected between the third node and the node to which a constant voltage is applied. The constant voltage is one of the pixel driving voltage, the initialization voltage, and the reference voltage.

3. The pixel circuit according to claim 1, wherein, In the initialization step, the voltages of the initialization pulse, the first light emission control pulse, and the sensing pulse are the gate on-voltage, and the voltage of the scanning pulse is the gate off-voltage. In the data writing step, the voltages of the scanning pulse and the sensing pulse are the gate turn-on voltages, and the voltages of the initialization pulse and the first light emission control pulse are the gate cut-off voltages. In the light emission step, the voltage of the first light emission control pulse is the gate turn-on voltage, and the voltages of the initialization pulse, the sensing pulse, and the scanning pulse are the gate cut-off voltages. The first to the fourth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

4. The pixel circuit of claim 3, wherein, A hold period is set between the sensing step and the data writing step, and During the holding period, the voltages of the sensing pulse, the scanning pulse, and the first emission control pulse are maintained at the same voltages as those in the sensing step.

5. The pixel circuit according to claim 1, wherein, The initialization voltage is lower than the pixel driving voltage and higher than the low-potential power supply voltage, and The reference voltage is lower or higher than the low potential power supply voltage.

6. The pixel circuit according to claim 1, further comprising: A fifth switching element includes a first electrode connected to a power line to which the pixel driving voltage is applied, a gate electrode to which a second emission control pulse is applied, and a second electrode connected to the first node, and the fifth switching element is configured to connect the power line to the first node in response to the second emission control pulse.

7. The pixel circuit according to claim 6, wherein, The pixel circuit is driven in the order of the initialization step, the sensing step, the data writing step, the boost step, and the light emission step. In the initialization step, the voltages of the initialization pulse, the first light emission control pulse, the second light emission control pulse, and the sensing pulse are the gate on-state voltages, and the voltage of the scanning pulse is the gate off-state voltage. In the sensing step, the voltages of the initialization pulse, the sensing pulse, and the second emission control pulse are the gate on-voltages, and the voltages of the scanning pulse and the first emission control pulse are the gate off-voltages. In the data writing step, the voltages of the scanning pulse and the sensing pulse are the gate turn-on voltages, and the voltages of the initialization pulse and the first light emission control pulse are the gate cut-off voltages. In the data writing step, the voltage of the second light-emitting control pulse is either the gate on-voltage or the gate off-voltage. In the boost step and the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate on voltages, and the voltages of the initialization pulse, the sensing pulse, and the scanning pulse are the gate off voltages. In the boost step, the voltages of the second node and the third node increase, and The first to the fifth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

8. The pixel circuit according to claim 7, wherein, An anode reset step is provided between the data writing step and the boost step. In the anode reset step, the voltages of the first light emission control pulse and the sensing pulse are the gate turn-on voltages, and the voltages of the second light emission control pulse, the initialization pulse, and the scanning pulse are the gate cut-off voltages.

9. The pixel circuit according to claim 1, wherein, The driving element, the first switching element, the second switching element, the third switching element, and the fourth switching element are implemented by an n-channel oxide TFT.

10. The pixel circuit according to claim 9, wherein, The gate-on voltage is higher than the pixel driving voltage, and the gate-off voltage is lower than the low-potential power supply voltage.

11. A pixel circuit, the pixel circuit comprising: A driving element, the driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; A light-emitting element, the light-emitting element comprising an anode electrode connected to a fourth node and a cathode electrode to which a low potential power supply voltage is applied; A first switching element includes a first electrode to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the second node, and the first switching element is configured to provide the initialization voltage to the second node in response to the initialization pulse; A second switching element includes a first electrode connected to the third node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied, and the second switching element is configured to provide the reference voltage to the third node in response to the sensing pulse; A third switching element includes a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node, and the third switching element is configured to provide the data voltage to the second node in response to the scan pulse; A fourth switching element includes a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node, and the fourth switching element is configured to connect the third node to the fourth node in response to the first emission control pulse. In the initialization step of the pixel circuit, the voltages of the initialization pulse and the sensing pulse are gate-on voltages, and the voltages of the first emission control pulse and the scanning pulse are gate-off voltages.

12. The pixel circuit according to claim 11, wherein, The pixel circuit also includes: A fifth switching element includes a first electrode connected to a power line to which the pixel driving voltage is applied, a gate electrode to which a second emission control pulse is applied, and a second electrode connected to the first node, and the fifth switching element is configured to connect the power line to the first node in response to the second emission control pulse.

13. The pixel circuit according to claim 12, wherein, The pixel circuit is driven in the order of the initialization step, sensing step, data writing step, and light emission step. In the initialization step, the voltages of the initialization pulse, the second light emission control pulse, and the sensing pulse are the gate-on voltages, and the voltages of the scanning pulse and the first light emission control pulse are the gate-off voltages. In the sensing step, the voltages of the initialization pulse and the second emission control pulse are the gate turn-on voltages, and the voltages of the first emission control pulse, the sensing pulse, and the scanning pulse are the gate cut-off voltages. In the data writing step, the voltages of the scanning pulse and the second light emission control pulse are the gate on voltages, and the voltages of the initialization pulse, the first light emission control pulse, and the sensing pulse are the gate off voltages. In the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate on-voltages, and the voltages of the initialization pulse, the sensing pulse, and the scanning pulse are the gate off-voltages. The first to the fifth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

14. The pixel circuit according to claim 12, wherein, The pixel circuit is driven in the order of the initialization step, sensing step, data writing step, and light emission step. In the initialization step, the voltages of the initialization pulse, the second light emission control pulse, and the sensing pulse are the gate-on voltages, and the voltages of the scanning pulse and the first light emission control pulse are the gate-off voltages. In the sensing step, the voltages of the initialization pulse and the second emission control pulse are the gate turn-on voltages, and the voltages of the first emission control pulse, the sensing pulse, and the scanning pulse are the gate cut-off voltages. In the data writing step, the voltage of the scanning pulse is the gate turn-on voltage, and the voltages of the initialization pulse, the first light emission control pulse, the second light emission control pulse, and the sensing pulse are the gate cut-off voltages. In the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate on-voltages, and the voltages of the initialization pulse, the sensing pulse, and the scanning pulse are the gate off-voltages. The first to the fifth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

15. The pixel circuit according to claim 13 or 14, wherein, The sensing pulse is generated with a pulse width wider than that of the scanning pulse, and the sensing pulse rises to the gating on voltage before entering the initialization step and falls to the gating off voltage at the end of the initialization step.

16. The pixel circuit according to claim 13 or 14, wherein, The first light emission control pulse and the second light emission control pulse oscillate between the gate on voltage and the gate off voltage during the light emission step with a duty cycle set to a preset pulse width modulation.

17. The pixel circuit according to claim 12, further comprising: A sixth switching element includes a first electrode connected to the fourth node, a gate electrode to which a second initialization pulse is applied, and a second electrode to which the initialization voltage or the anode voltage is applied, and the sixth switching element is configured to apply the initialization voltage or the anode voltage to the fourth node in response to the second initialization pulse. in, The initialization voltage is lower than the pixel driving voltage and higher than the low-potential power supply voltage. The anode voltage is lower than the pixel driving voltage and higher than the initialization voltage. The reference voltage is lower or higher than the low potential power supply voltage.

18. The pixel circuit according to claim 17, wherein, The pixel circuit is driven in the order of the initialization step, sensing step, data writing step, and light emission step. In the initialization step, the voltages of the initialization pulse, the second initialization pulse, the second light emission control pulse, and the sensing pulse are the gate-on voltages, and the voltages of the scanning pulse and the first light emission control pulse are the gate-off voltages. In the sensing step, the voltages of the initialization pulse, the second initialization pulse, and the second emission control pulse are the gate on-voltages, and the voltages of the scanning pulse, the first emission control pulse, and the sensing pulse are the gate off-voltages. In the data writing step, the voltages of the scanning pulse, the second initialization pulse, and the second light emission control pulse are the gate on voltages, and the voltages of the initialization pulse, the first light emission control pulse, and the sensing pulse are the gate off voltages. In the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate turn-on voltages, and the voltages of the initialization pulse, the second initialization pulse, the sensing pulse, and the scanning pulse are the gate cut-off voltages. The first to the sixth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

19. The pixel circuit according to claim 17, wherein, The pixel circuit is driven in the order of the initialization step, sensing step, data writing step, and light emission step. In the initialization step, the voltages of the initialization pulse, the second initialization pulse, the second light emission control pulse, and the sensing pulse are the gate-on voltages, and the voltages of the scanning pulse and the first light emission control pulse are the gate-off voltages. In the sensing step, the voltages of the initialization pulse, the second initialization pulse, and the second emission control pulse are the gate on-voltages, and the voltages of the scanning pulse, the first emission control pulse, and the sensing pulse are the gate off-voltages. In the data writing step, the voltages of the scan pulse and the second initialization pulse are the gate turn-on voltages, and the voltages of the initialization pulse, the first light emission control pulse, the second light emission control pulse, and the sensing pulse are the gate cut-off voltages. In the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate turn-on voltages, and the voltages of the initialization pulse, the second initialization pulse, the sensing pulse, and the scanning pulse are the gate cut-off voltages. The first to the sixth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

20. The pixel circuit according to claim 12, further comprising: A sixth switching element includes a first electrode connected to the fourth node, a gate electrode to which a second sensing pulse generated after the sensing pulse is applied, and a second electrode to which the initialization voltage or a preset anode voltage is applied, and the sixth switching element is configured to apply the initialization voltage or the anode voltage to the fourth node in response to the second sensing pulse.

21. The pixel circuit according to claim 20, wherein, The pixel circuit is driven in the order of the initialization step, sensing step, data writing step, and light emission step. In the initialization step, the voltages of the initialization pulse, the second light emission control pulse, and the sensing pulse are the gate-on voltages, and the voltages of the scanning pulse, the second sensing pulse, and the first light emission control pulse are the gate-off voltages. In the sensing step, the voltages of the initialization pulse, the second light emission control pulse, the sensing pulse, and the second sensing pulse are the gate on-voltages, and the voltages of the scanning pulse and the first light emission control pulse are the gate off-voltages. In the data writing step, the voltages of the scanning pulse and the second light emission control pulse are the gate turn-on voltages, and the voltages of the initialization pulse, the first light emission control pulse, the sensing pulse, and the second sensing pulse are the gate cut-off voltages. In the light emission step, the voltages of the first light emission control pulse and the second light emission control pulse are the gate turn-on voltages, and the voltages of the initialization pulse, the sensing pulse, the second sensing pulse, and the scanning pulse are the gate cut-off voltages. The first to the sixth switching elements are turned on according to the gating on voltage and turned off according to the gating off voltage.

22. A display device, the display device comprising: The display panel has multiple data lines, multiple gate lines intersecting the data lines, multiple power lines with different constant voltages applied, and multiple sub-pixels. A data driver configured to provide a data voltage for pixel data to the data line; as well as A gating driver configured to provide initialization pulses, sensing pulses, and emission control pulses to the gating line. Each of the sub-pixels includes a pixel circuit according to any one of claims 1 to 21.

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