Compilation method, compilation circuit, mode register and memory

Abstract

An embodiment of the present application provides a compilation method, compilation circuit, mode register, and memory. The compilation method includes: receiving a signal to be compiled and an operating frequency signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register being unable to operate after receiving the reserved code. In addition, the compilation results of the reserved code vary depending on the operating frequency signal, allowing the mode register to better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms.

Description

Technical Field

[0001] The present application relates to the technical field of dynamic random access memory, and in particular to a compilation method, a compilation circuit, a mode register and a memory. Background Art

[0002] The mode register is a key component of dynamic random access memory (DRAM), primarily used to set DRAM parameters. Specifically, each mode register contains multiple input bits (also known as input codes or address codes). The levels of different input bits, after decoding, correspond to different parameter values.

[0003] However, the current mode register has poor compatibility with different application platforms, which brings inconvenience to the application of DRAM. Summary of the Invention

[0004] The present application provides a compilation method, a compilation circuit, a mode register, and a memory, which improve the compatibility of the mode register for different application platforms by pre-setting compilation rules for reserved codes.

[0005] The technical solution of this application is achieved as follows:

[0006] In a first aspect, an embodiment of the present application provides a compilation method, applied to a compilation circuit, the method comprising:

[0007] receiving a signal to be compiled and a working frequency signal;

[0008] Compile the signal to be compiled to obtain a compilation result signal;

[0009] In a case where the signal to be compiled is a reserved code, a compatibility selection process is performed on the compiled result signal based on the operating frequency signal to determine a first compiled value.

[0010] In a second aspect, an embodiment of the present application provides a compilation circuit, the compilation circuit including:

[0011] Signal input terminal, used for receiving the signal to be compiled and the operating frequency signal;

[0012] A compilation unit, used for compiling a signal to be compiled to obtain a compilation result signal;

[0013] The compatible selection unit is configured to perform compatible selection processing on the compiled result signal based on the operating frequency signal to determine a first compiled value when the signal to be compiled is a reserved code.

[0014] In a third aspect, an embodiment of the present application provides a mode register, which at least includes the compilation circuit as in the second aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a memory, which at least includes the mode register as described in the third aspect.

[0016] The present application provides a compilation method, a compilation circuit, a mode register, and a memory. The compilation method includes: receiving a signal to be compiled and an operating frequency signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value. The compilation circuit includes: a signal input terminal for receiving the signal to be compiled and the operating frequency signal; a compilation unit for compiling the signal to be compiled to obtain a compilation result signal; and a compatibility selection unit for performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value if the signal to be compiled is a reserved code. Thus, by presetting compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register being unable to operate after receiving the reserved code. In addition, the compilation results of the reserved code vary depending on the operating frequency signal, allowing the mode register to better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of a compilation method provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a compilation circuit provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of another compilation circuit provided in an embodiment of the present application;

[0020] Figure 4 A detailed structural diagram of a compilation circuit provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the structure of a mode register provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the applications. It should also be noted that for ease of description, only the parts relevant to the related applications are shown in the drawings.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0025] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0027] DRAM contains multiple mode registers, which are used to set different DRAM functions and operating modes. Specifically, each mode register contains multiple input bits (also called address codes, address bits, etc.). The level states of different input bits constitute the decoded signal, which is decoded to determine the corresponding parameter value.

[0028] In actual applications, users send a Mode Register Set Command (MRS Command) to the DRAM through the DRAM controller to set each mode register. Because the Basic Input Output System (BIOS) settings in different DRAM controllers vary, the mode registers offer different optional parameters to suit various application platforms.

[0029] The SPEC section of the 4th edition of the Double Data Rate SDRAM (DDR SDRAM, DDR4) technical specification defines the compilation rules between input bit combinations and parameter values ​​in the mode register. In addition to the specified input bit combinations, there are also some unused input bit combinations, known as reserved codes, for designers to use when they have special needs.

[0030] Generally speaking, in most cases where there's no special need, reserved codes aren't enabled. Consequently, DRAM doesn't have compiling circuitry for these reserved codes. However, because a DRAM controller may need to test and control multiple different DRAMs and isn't designed specifically for a single DRAM, it might issue control commands involving reserved codes. Consequently, if a DRAM without a compiling circuit for reserved codes receives a reserved code from the DRAM controller, the mode register won't function at all, reducing the mode register's compatibility across different application platforms.

[0031] Specifically, according to DDR4 regulations, there are six settings in the mode register related to the external operating frequency: (1) TWR & TRTP settings, see Table 1; (2) CAS Latency settings, see Table 2; (3) CS to CMD / ADDR Latency settings, see Table 3; (4) CRC+DM Write Command Latency settings, see Table 4; (5) C / A Parity Latency settings, see Table 5; (6) tCCDL / tDLLK settings, see Table 6. As can be seen from Tables 1 to 6, each specific setting item has a reserved code.

[0032] For example, the DRAM Controller in a company's test platform uses the reserved code in the tCCDL setting item to perform low-speed testing on the DRAM. However, since the mode register in the DRAM does not have a compilation circuit for the reserved code in tCCDL, the entire test will fail to start.

[0033] Table 1

[0034]

[0035]

[0036] Table 2

[0037]

[0038] Table 3

[0039]

[0040]

[0041] Table 4

[0042]

[0043] Table 5

[0044] A2 A1 A0 PL Speed ​​Bin 0 0 0 Disable 0 0 1 4 1600,1866,2133 0 1 0 5 2400,2666 0 1 1 6 2933,3200 1 0 0 8 RFU 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

[0045] Table 6

[0046]

[0047]

[0048] In particular, Tables 1 to 6 are all from the SPEC part of DRAM DDR4. A1, A2, ... A12 are bits in the corresponding mode register. The meanings of other related parameters can be found in the DDR4 file, and the meanings of the related parameters do not affect the understanding of the embodiments of this application, so they will not be described in detail here.

[0049] Based on this, an embodiment of the present application provides a compilation method, the basic concept of which is as follows: receiving a signal to be compiled and an operating frequency signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register being unable to operate after receiving the reserved code. In addition, the compilation results of the reserved code vary depending on the operating frequency signal, allowing the mode register to better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms.

[0050] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0051] In one embodiment of the present application, see Figure 1 , which shows a flow chart of a compilation method provided by an embodiment of the present application. Figure 1 As shown, the method may include:

[0052] S101: Receive a signal to be compiled and an operating frequency signal.

[0053] It should be noted that the compilation method provided in the embodiment of the present application is applied to the mode register of the DRAM.

[0054] In order to match the BIOS settings of the DRAM Controller, the DRAM mode register provides some adjustable parameters, so that the DRAM Controller can send MRS commands to the DRAM to set the mode register in the DRAM. The compilation method provided in the embodiment of the present application is specifically applied to the compilation circuit of the adjustable parameters in the mode register in the DRAM.

[0055] Generally speaking, different DRAM controllers may have different operating frequencies. Therefore, the mode register contains several settings to match the operating frequency, such as TWR & TPTP, CAS Latency, CS to CMD / ADDR Latency, CRC+DM Write Command Latency, C / A Parity Latency, and tCCDL / tDLLK. Generally speaking, each specific setting has multiple optional parameter values ​​to facilitate matching DRAM controllers with different operating frequencies.

[0056] For these settings, there are multiple input bits in the mode register. DDR4 specifies detailed encoding rules, such as specific input bit combinations and the corresponding compiled values. These clearly defined input bit combinations are generally called control codes (or non-reserved codes). In addition, DDR4 also has some unenabled input bit combinations, meaning that DDR4 does not specify the compiled values ​​for these input bit combinations. These input bit combinations are generally called reserved codes.

[0057] In related technologies, the hardware system for the mode register lacks a compilation circuit for reserved codes. Consequently, commands involving these codes may not work. To address this issue, embodiments of the present application provide a compilation method that pre-encodes and decodes the reserved codes in settings related to external operating frequencies, thereby achieving greater compatibility with different DRAM controllers.

[0058] The compilation method provided in the embodiment of the present application requires receiving a signal to be compiled and an operating frequency signal. Here, the signal to be compiled is determined according to the MRS command sent by the DRAM Controller, and the operating frequency signal is used to indicate whether the operating frequency of the DRAM Controller is high or low.

[0059] S102: Compile the signal to be compiled to obtain a compilation result signal.

[0060] It should be noted that the signal to be compiled is compiled to obtain a compilation result signal.

[0061] Here, due to the hardware improvement of the compilation circuit, that is, the compilation part for reserved codes is pre-designed in the compilation circuit, even if the signal to be compiled is a reserved code, the compilation result signal can be obtained without causing direct DRAM shutdown.

[0062] S103: When the signal to be compiled is a reserved code, perform compatibility selection processing on the compiled result signal based on the operating frequency signal to determine a first compiled value.

[0063] It should be noted that in the mode register, there are multiple setting items with different functions, and each setting item may have a reserved code. The reserved codes in the embodiments of the present application particularly relate to those setting items related to the operating frequency of the DRAM Controller, such as TWR&TPTP reserved code, CAS Latency reserved code, CS to CMD / ADDR Latency reserved code, CRC+DM Write Command Latency reserved code, C / A Parity Latency reserved code and tCCDL / tDLLK reserved code.

[0064] Because the specific parameter values ​​of these settings are related to the DRAM controller's operating frequency, when the signal to be programmed is a reserved code, the first programming value is determined based on the operating frequency signal to better match the DRAM controller's operating frequency. In other words, as long as the signal to be programmed is a reserved code, the final programming value is determined based on the operating frequency signal, rather than the reserved code itself.

[0065] Specifically, the coding value of the reserved code may be different depending on the operating frequency signal. Therefore, in some embodiments, performing compatibility selection processing on the coding result signal based on the operating frequency signal to determine the first coding value may include:

[0066] If the operating frequency signal is a first level signal, determining the first compiled value to be a first preset value;

[0067] If the operating frequency signal is a second level signal, the first compiled value is determined to be a second preset value.

[0068] It should be noted that if the operating frequency signal is a first level signal, the first compiled value is determined to be a first preset value; if the operating frequency signal is a second level signal, the first compiled value is determined to be a second preset value.

[0069] Here, the first-level signal and the second-level signal have different level states. For example, the first-level signal can be a high-level signal, also represented by "1," while the second-level signal can be a low-level signal, also represented by "0." Specifically, the level state of the operating frequency signal can indicate the high or low external operating frequency. For example, a low-level signal can indicate a high-frequency DRAM controller, while a high-level signal can indicate a low-frequency DRAM controller. Furthermore, the first preset value and the second preset value are different.

[0070] In this way, when the signal to be programmed is a reserved code, the first programming value can be determined to be the first preset value or the second preset value according to the operating frequency signal, thereby matching the operating frequencies of different DRAM controllers.

[0071] Furthermore, in some embodiments, when the signal to be compiled is a non-reserved code, the method may further include:

[0072] A second compiled value is determined according to the compiled result signal.

[0073] It should be noted that, for those non-reserved codes clearly defined by JEDEC DDR4 SPEC, the second compilation value may be directly determined according to the compilation result signal.

[0074] It should be understood that for non-reserved codes, the coding value needs to be determined according to the content of the non-reserved code itself; for reserved codes, the coding value needs to be determined according to the operating frequency signal.

[0075] The compilation method is further described below in conjunction with a specific compilation circuit structure.

[0076] In some embodiments, the compiling circuit may include a first compiling unit, a second compiling unit, and a compatible selection unit. The method may further include:

[0077] In a case where the signal to be coded is a reserved code, determining a first coding value by the first coding unit and the compatible selection unit;

[0078] In a case where the signal to be coded is a non-reserved code, a second coding value is determined by the second coding unit.

[0079] It should be noted that the compilation circuit can be divided into a first compilation unit, a second compilation unit, and a compatible selection unit. The first compilation unit is a unit that compiles for reserved codes. Since the compilation value of a reserved code needs to be determined based on the operating frequency signal, when the signal to be compiled is a reserved code, the first compilation value is determined by the first compilation unit and the compatible selection unit. The second compilation unit is a unit that compiles for non-reserved codes. When the signal to be compiled is a non-reserved code, the second compilation unit directly determines the second compilation value.

[0080] It should also be noted that DDR4 explicitly defines a programming value for each non-reserved code. However, a reserved code is essentially an unactivated input bit combination, for which DDR4 does not define a programming value. To save circuit area, some programming values ​​of non-reserved codes can be reused as programming values ​​of reserved codes. Therefore, in some embodiments, the second programming value includes n programming values, where n is a positive integer. The method may further include:

[0081] Selecting a maximum value from the n compiled values, and determining the maximum value as a first preset value;

[0082] A minimum value is selected from the n compiled values, and the minimum value is determined as the second preset value.

[0083] It should be noted that for a specific setting item, the setting item may have several non-reserved codes, each corresponding to a different programming value, to indicate several different operating modes to match DRAM crossovers with different operating frequencies. In this case, the maximum value of these programming values ​​can be determined as the first preset value, and the minimum value of these programming values ​​can be determined as the second preset value.

[0084] In particular, the first compilation value and the second compilation value both belong to the compilation circuit of the same setting item. In other words, when designing the specific value of the first compilation value, it can be selected from the second compilation value corresponding to the non-reserved code corresponding to the same setting item as the reserved code.

[0085] Taking the aforementioned six settings related to the operating frequency as an example, one of the specific compilation schemes provided in the embodiment of the present application is given: (1) TWR&TPTP setting item, see Table 7; (2) CAS Latency setting item, see Table 8; (3) CSto CMD / ADDR Latency setting item, see Table 9; (4) CRC+DM Write Command Latency setting item, see Table 10; (5) C / A Parity Latency setting item, see Table 11; (6) tCCDL / tDLLK setting item, see Table 12. In particular, in Tables 6 to 12, the bold parts show the compilation value of the reserved code. For each reserved code, there are two specific values ​​(equivalent to the first preset value and the second preset value mentioned above). In actual applications, the specific compilation value of the reserved code needs to be determined according to the operating frequency signal.

[0086] Table 7

[0087] A13 A11 A10 A9 WR RTP 0 0 0 0 10 5 0 0 0 1 12 6 0 0 1 0 14 7 0 0 1 1 16 8 0 1 0 0 18 9 0 1 0 1 20 10 0 1 1 0 24 12 0 1 1 1 22 11 1 0 0 0 26 13 1 0 0 1 26 / 10 13 / 5 1 0 1 0 26 / 10 13 / 5 1 0 1 1 26 / 10 13 / 5 1 1 0 0 26 / 10 13 / 5 1 1 0 1 26 / 10 13 / 5 1 1 1 0 26 / 10 13 / 5 1 1 1 1 26 / 10 13 / 5

[0088] Table 8

[0089]

[0090]

[0091] Table 9

[0092] A8 A7 A6 CAL 0 0 0 Disable 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 8 1 1 0 8 / 3 1 1 1 8 / 3

[0093] Table 10

[0094]

[0095] Table 11

[0096]

[0097]

[0098] Table 12

[0099]

[0100] As shown in Table 8, for the CAS Latency setting item, the coding value of the non-reserved code includes multiple values ​​from 9 to 32. In this case, for the reserved code of the CAS Latency setting item, the first coding value can be determined to be 9 or 32. In particular, for the TWR&TPTP setting item, as shown in Table 7, the coding value of each non-reserved code actually includes two parameters, namely the WR parameter and the RTP parameter. The coding value of the non-reserved code includes multiple combinations of values ​​between (WR: 10, RTP: 5) and (WR: 26, RTP: 13). Similarly, the first coding value can still select the extreme values ​​of the second coding value, namely (WR: 10, RTP: 5) and (WR: 26, RTP: 13).

[0101] The benefits of doing so include: (1) the maximum and minimum values ​​can correspond to relatively extreme external operating frequencies, ensuring that the DRAM can operate normally in a high-operating-frequency DRAM Crontroller or a low-operating-frequency DRAM Crontroller; (2) the compilation value of the reserved code reuses the compilation value of the non-reserved code, and part of the circuit and output end can be reused during the circuit design process, saving the layout area of ​​the integrated circuit.

[0102] It should be understood that the above is only one method for determining the first compiled value and does not constitute a limitation to the embodiments of the present application.

[0103] Furthermore, in some embodiments, the method may further include:

[0104] Determining a first category of non-reserved codes and a second category of non-reserved codes; wherein the first category of non-reserved codes includes non-reserved codes corresponding to the maximum value and the minimum value, respectively, and the second category of non-reserved codes includes remaining non-reserved codes in the non-reserved codes except the first category of non-reserved codes;

[0105] Accordingly, the compilation circuit includes a first compilation unit, a second compilation unit, and a compatibility selection unit, and the second compilation unit includes a second-first compilation unit and a second-second compilation unit. The method may further include:

[0106] When the signal to be coded is a reserved code or a first type of non-reserved code, determining a first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit;

[0107] When the signal to be coded is a second type non-reserved code, a third coding value is determined by the second second coding unit; wherein the third coding value is the remaining coding value in the second coding value except the first coding value.

[0108] It should be noted that, in order to achieve circuit reuse, non-reserved codes are divided into a first category of non-reserved codes and a second category of non-reserved codes. The first category of non-reserved codes includes the reserved codes corresponding to the aforementioned maximum value and the aforementioned minimum value, respectively, and the second category of non-reserved codes includes all non-reserved codes except the first category of non-reserved codes.

[0109] Correspondingly, the second compiled value can also be classified into a first compiled value and a third compiled value, the first compiled value includes the aforementioned maximum value and the aforementioned minimum value, and the third compiled value refers to the part of the second compiled value excluding the first compiled value.

[0110] On this basis, the second compilation unit is divided into a second-first compilation unit and a second-second compilation unit; wherein the second-first compilation unit is used to compile the first type of non-reserved code, and the second-second compilation unit is used to compile the second type of non-reserved code. In this case, the compilation process may specifically include:

[0111] For the reserved code or the first type of non-reserved code, the first coding value is determined by the first coding unit, the second-first coding unit, and the compatible selection unit; for the second type of non-reserved code, the third coding value is directly determined by the second-second coding unit.

[0112] In this way, the compilation circuit of the reserved code reuses part of the compilation circuit and output end of the first type of non-reserved code, which can save circuit area.

[0113] Furthermore, in some embodiments, determining the first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit may include:

[0114] Compiling the signal to be compiled by the first compilation unit to obtain a first compiled signal;

[0115] performing compilation processing on the signal to be compiled by the second-first compilation unit to obtain a second-first compiled signal;

[0116] The compatible selection unit performs logic calculation on the first compiling processing signal, the second compiling processing signal and the operating frequency signal, and determines a first compiling value according to the logic calculation result.

[0117] It should be noted that an example of a circuit processing process for determining the first compiled value is as follows:

[0118] (1) The first coding unit compiles the signal to be compiled to obtain a first coding signal. Here, the first coding signal can indicate whether the signal to be compiled is a reserved code (because the coding value of the reserved code is determined only according to the operating frequency signal).

[0119] (2) The second-first coding unit compiles the signal to be compiled to obtain a second-first coding signal. Here, the second-first coding signal can not only indicate whether the signal to be compiled is a first-class non-reserved code, but also needs to indicate which first-class non-reserved code it is (because the coding value of the non-reserved code needs to be determined based on the non-reserved code itself).

[0120] (3) Performing a logical calculation on the first compilation signal, the second compilation signal, and the operating frequency signal, and determining a specific value based on the logical calculation result. Here, the logical calculation algorithm needs to be designed accordingly according to different application scenarios.

[0121] In this way, through the compilation method provided in the embodiment of the present application, both reserved codes and non-reserved codes can be decoded. Even if instructions related to reserved codes are received, the DRAM can still operate normally and will not crash. In addition, for the reserved codes, the final compilation value needs to be determined based on the operating frequency signal so that the DRAM can match DRAM controllers with different operating frequencies, thereby ultimately improving the compatibility of the DRAM.

[0122] In summary, the embodiments of the present application belong to the field of synchronous dynamic random access memory (SDRAM) DDR4 design, and are specifically applied to mode registers in DRAM. In the latest version of JEDEC DDR4 SPEC, there are still definitions of mode setting reserved codes involving operating frequencies for some mode registers, and these reserved codes are also available setting codes for different DRAM Controller designers. Therefore, different DRAM Controller design schemes may apply the reserved codes to different encoding and speed environments, resulting in some DRAMs being incompatible with the DRAM Controller. In order to improve the compatibility of DDR4 circuits and to adapt to more DRAM Controller design schemes, these reserved codes can be encoded and decoded in advance in the design of DRAM.

[0123] In other words, the purpose of the embodiments of this application is to improve the system compatibility of DDR4 with DRAM controllers. Specifically, to better adapt to the use of DRAM reserved codes in different DRAM controller designs, the settings of six speed-related (i.e., operating frequency) mode reserved codes are pre-compiled in the DDR4 design, thereby further improving compatibility with different system platforms.

[0124] Specifically, the six mode setting items include: TWR&TPTP reserved code, CAS Latency reserved code, CS toCMD / ADDR Latency reserved code, CRC+DM Write Command Latency reserved code, C / A Parity Latency reserved code and tCCDL / tDLLK reserved code. For the above six speed-related mode setting reserved codes, their compiled values ​​can correspond to high-frequency settings or low-frequency settings at the same time. As for how to finally decide whether to correspond to high-frequency settings or low-frequency settings, it can be selected through a compatible selection circuit (or Design For Test circuit) based on different Controller user usage environments, thereby further improving compatibility with different system platforms. As shown in Tables 7 to 12, the embodiments of the present application provide a possible encoding setting for the reserved code, where the larger value is the encoding adapted to the high-frequency environment, and the smaller value is the encoding adapted to the low-frequency environment.

[0125] In this way, by presetting the reserved codes related to the frequency speed defined in different mode registers in the DDR4 JEDEC SPEC, better compatibility with the BIOS settings of different DRAM controllers can be achieved.

[0126] An embodiment of the present application provides a compilation method, comprising receiving a signal to be compiled and an operating frequency signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, a mode register can compile the reserved code sent by the application platform, thereby avoiding the problem of the mode register being unable to operate after receiving the reserved code. Furthermore, the compilation results of the reserved code vary depending on the operating frequency signal, thereby enabling the mode register to better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms.

[0127] In another embodiment of the present application, see Figure 2 , which shows a schematic diagram of the structure of a compiling circuit 20 provided in an embodiment of the present application. Figure 2 As shown, the compiling circuit 20 includes:

[0128] The signal input terminal 201 is used to receive the signal to be compiled and the operating frequency signal;

[0129] A compiling unit 202 is configured to compile a signal to be compiled to obtain a compilation result signal;

[0130] The compatible selection unit 203 is configured to perform compatible selection processing on the coding result signal based on the operating frequency signal to determine a first coding value when the signal to be coded is a reserved code.

[0131] It should be noted that if Figure 2 As shown, the compiling circuit 20 includes a signal input terminal 201, a compiling unit, and a compatibility selection unit 203. The signal input terminal 201 is used to receive a signal to be compiled and an operating frequency signal. The compiling unit 202 is used to compile the signal to be compiled and output a compilation result signal. The compatibility selection unit 203 is connected to both the compiling unit 202 and the signal input terminal 201. When the signal to be compiled is a reserved code, compatibility selection is performed on the compilation result signal based on the operating frequency signal to obtain a first compilation value.

[0132] Here, the reserved code includes at least one of the following: TWR&TPTP reserved code, CAS Latency reserved code, CS to CMD / ADDR Latency reserved code, CRC+DM Write Command Latency reserved code, C / A Parity Latency reserved code, and tCCDL / tDLLK reserved code.

[0133] Further, in some embodiments, the compatible selection unit 203 is specifically configured to determine that the first compilation value is a first preset value when the signal to be compiled is a reserved code and the operating frequency signal is a first-level signal; and to determine that the first compilation value is a second preset value when the signal to be compiled is a reserved code and the operating frequency signal is a second-level signal; wherein the first-level signal and the second-level signal are different, and the first preset value is different from the second preset value.

[0134] It should be noted that for the reserved code, if the operating frequency signal is a first level signal, the compatibility selection unit 203 determines the first compilation value to be a first preset value; if the operating frequency signal is a second level signal, the compatibility selection unit 203 determines the first compilation value to be a second preset value. The first level signal can be designed to be a low level signal, and the second level signal can be designed to be a high level signal.

[0135] Furthermore, in some embodiments, the compiling circuit 20 is further configured to determine a second coding value according to the coding result signal when the signal to be compiled is a non-reserved code.

[0136] It should be noted that, for non-reserved codes, the compiling circuit 20 directly determines the second compiling value according to the compiling result signal. Here, the second compiling value includes n compiling values, where n is a positive integer.

[0137] On this basis, the first preset value may be the maximum value among the n compiled values, and the second preset value may be the minimum value among the n compiled values.

[0138] Furthermore, in some embodiments, Figure 3 As shown, the compilation unit 202 includes a first compilation unit 2021 and a second compilation unit 2022; wherein,

[0139] A first compiling unit 2021 is configured to compile a signal to be compiled to obtain a first compilation result signal;

[0140] The second compiling unit 2022 is configured to compile the signal to be compiled to obtain a second compilation result signal.

[0141] It should be noted that the compilation unit 202 can be divided into a first compilation unit 2021 and a second compilation unit 2022. The first compilation unit 2021 is used to compile the reserved code to obtain a first compilation result signal; the second compilation unit 2022 is used to compile the non-reserved code to obtain a second compilation result signal.

[0142] Here, since the compilation value of the reserved code is essentially determined based on the operating frequency signal, the first compilation result signal only needs to indicate whether the signal to be compiled is a reserved code. However, since the compilation value of the non-reserved code needs to be determined based on the specific content of the non-reserved code, the second compilation result signal needs to indicate which non-reserved code the signal to be compiled is.

[0143] Furthermore, in some embodiments, Figure 3 As shown, the non-reserved code includes the first type of non-reserved code, and the second compilation unit 2022 includes the second first compilation unit 20221;

[0144] A second-first compiling unit 20221 is configured to compile the signal to be compiled to obtain a second-first compiling result signal;

[0145] The compatible selection unit 203 is specifically configured to perform a logical operation on the first compilation result signal, the second-first compilation result signal, and the operating frequency signal when the signal to be compiled is a first type non-reserved code or a reserved code, and determine a first compilation value according to the logical operation result.

[0146] as well as,

[0147] In some embodiments, as Figure 3 As shown, the non-reserved code further includes a second type of non-reserved code, and the second compilation unit 2022 further includes a second second compilation unit 20222;

[0148] The second second coding unit 20222 is configured to perform coding processing on the signal to be coded to obtain a second second coding result signal; and when the signal to be coded is a second type non-reserved code, directly determine a third coding value according to the second second coding result signal.

[0149] It should be noted that, to save circuit area, non-reserved codes can be divided into two categories: Category 1 non-reserved codes and Category 2 non-reserved codes. Category 1 non-reserved codes include the non-reserved codes corresponding to the aforementioned maximum value and minimum value, respectively; Category 2 non-reserved codes correspond to the remaining non-reserved codes except the Category 1 non-reserved codes.

[0150] Accordingly, the second compiled value can be divided into a first compiled value and a third compiled value, the first compiled value includes the aforementioned maximum value and the aforementioned minimum value, and the third compiled value includes the portion of the second compiled value excluding the first compiled value.

[0151] At this time, the compilation process of the reserved code can be combined with part of the first type of non-reserved code, thereby saving circuit area. Therefore, the second compilation unit 2022 can be divided into a second first compilation unit 20221 and a second second compilation unit 20222.

[0152] For the first type of non-reserved code or reserved code, the first compilation unit 201 and the second-first compilation unit 20221 perform compilation processing to obtain a first compilation result signal and a second-first compilation result signal. Then, the compatible selection unit 203 performs a logical calculation on the first compilation result signal and the second-first compilation result signal to determine a first compilation value.

[0153] The second coding unit 20222 performs coding processing on the second type of non-reserved codes to obtain a second coding result signal, and directly determines the third coding value according to the second coding result signal.

[0154] Furthermore, in some embodiments, the compatible selection unit 203 includes a first selection subunit 2031 and a second selection subunit 2032; wherein,

[0155] The first selection subunit 2031 is configured to determine that the first coding value is a first preset value when the signal to be coded is a reserved code and the operating frequency signal is a low-level signal, or when the signal to be coded is a non-reserved code corresponding to a maximum value;

[0156] The second selection subunit 2032 is configured to determine that the first coding value is a second preset value when the signal to be coded is a reserved code and the operating frequency signal is a high-level signal, or when the signal to be coded is a non-reserved code corresponding to the minimum value.

[0157] It should be noted that the first compiled value may include the aforementioned maximum value and the aforementioned minimum value. Accordingly, the compatible selection unit 203 includes a first selection subunit 2031 and a second selection subunit 2032 .

[0158] The first selection subunit 2031 is connected to the output terminal of the maximum value, and is configured to output the maximum value when the signal to be compiled is a reserved code and the operating frequency signal is a low-level signal, or when the signal to be compiled is a non-reserved code corresponding to the maximum value;

[0159] The second selection subunit 2032 is connected to the output terminal of the minimum value, and is configured to output the minimum value when the signal to be compiled is a reserved code and the operating frequency signal is a high-level signal, or when the signal to be compiled is a non-reserved code corresponding to the minimum value.

[0160] In summary, to better adapt to the use of DRAM reserved codes in different DRAM controller designs, the settings of the reserved codes for six speed-related modes are pre-compiled in the DDR4 design, thereby further improving DRAM compatibility with different system platforms.

[0161] The technical solution provided by the embodiment of the present application includes: on the one hand, the reserved codes set for the six speed-related modes defined in DDR4 SPEC are pre-encoded in the design; on the other hand, the compilation circuit includes three parts, (1) a compilation circuit for the coding clearly specified by SPEC (equivalent to the aforementioned second encoding unit); (2) a compilation circuit for the reserved codes (equivalent to the aforementioned first encoding unit); (3) a DFT selection circuit for improving compatibility (equivalent to the aforementioned compatibility selection unit 203); on the other hand, the above three parts of the circuit are all used to achieve the improved SPEC compilation truth table (Table 7 to Table 12) as the goal, so the specific details of the circuit can be reflected in a variety of specific circuit structures and circuit logic; on the other hand, through the compatibility selection circuit, different high and low speed application environments of the Controller platform can be targeted when targeting different system platforms.

[0162] An embodiment of the present application provides a compilation circuit, comprising a signal input terminal for receiving a signal to be compiled and an operating frequency signal; a compilation unit for compiling the signal to be compiled to obtain a compilation result signal; and a compatibility selection unit for, when the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the operating frequency signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, the compatibility of the mode register for different application platforms is improved. Furthermore, depending on the operating frequency signal, the compilation results of the reserved code vary, enabling the mode register to better match different coding and speed environments.

[0163] In another embodiment of the present application, a specific example of a compilation circuit is provided, using the tCCDL setting item as an example. See Table 13, which shows the original SPEC definition of the tCCDL setting item in the related art, and Table 14, which shows the improved SPEC definition of the tCCDL setting item in the embodiment of the present application.

[0164] Table 13

[0165]

[0166] Table 14

[0167]

[0168] As can be seen from Table 14, when the signal to be compiled is a reserved code, the compilation value needs to be determined based on the operating frequency signal (also called the TM_LF signal). If the TM_LF signal is 0, it means that the DRAM controller is operating at a high frequency, and the compilation value of the reserved code is the maximum value "8". Conversely, if the TM_LF signal is 1, it means that the DRAM controller is operating at a low frequency, and the compilation value of the reserved code is the minimum value "4".

[0169] According to DDR4 specifications, the tCCDL setting is encoded by the three input bits A12, A11, and A10 of mode register MR6. A12_T represents the signal value of A12, and A12_B represents the signal value of A12 after the negation operation. The following three-digit value describes the tCCDL input bit combination. For example, 101 represents A12 as a logic 1, A11 as a logic 0, and A10 as a logic 1.

[0170] To implement Table 14, see Figure 4 , which shows a detailed structural diagram of a compiling circuit 20 provided in an embodiment of the present application. Figure 4 , the compiling circuit 20 includes an arithmetic unit 301, an arithmetic unit 302, an arithmetic unit 303, an arithmetic unit 304, an arithmetic unit 305, an arithmetic unit 306, an arithmetic unit 307, an arithmetic unit 308, an arithmetic unit 309, an arithmetic unit 310, a data selector 311, and a data selector 312. Among them, the arithmetic units 301 to 305 are all three-input AND gates, the arithmetic units 306 to 308 are all two-input NAND gates, and the arithmetic units 309 and 310 are both OR gates. For the detailed connection of the above components, please refer to Figure 4 , I will not go into details here.

[0171] like Figure 4As shown, from a functional perspective, the compilation circuit 20 can be divided into three parts: (1) the compilation circuit for the encoding clearly defined by SPEC (SPEC Defined Decode Block); (2) the compilation circuit for the reserved code (SPEC Reserved Decode Block); (3) the DFT selection circuit for improving compatibility (DFT Block For Better Compatibility).

[0172] (1) The SPEC Defined Decode Block includes an operator 301, an operator 302, an operator 303, an operator 304, and an operator 305. Operators 301, 302, and 303 are circuits for compiling the second type of non-reserved codes, and operators 304 and 305 are circuits for compiling the first type of non-reserved codes.

[0173] (2) The compilation circuit for the reserved code (SPEC Reserved Decode Block) includes an operator 306, an operator 307, and an operator 308.

[0174] (3) DFT selection circuit for improving compatibility (DFT Block For Better Compatibility): operator 309, operator 310, data selector 311 and data selector 312.

[0175] based on Figure 4 The compilation circuit in , the specific compilation principle is as follows:

[0176] If the signal to be compiled is a second type non-reserved code, such as 001, the operator 301 outputs logic 1, the output terminal TCCDL_5 is high, and the other output terminals are low, and the final compiled value is 5.

[0177] If the signal to be compiled is the first type of reserved code, such as 000, the operator 304 outputs logic 1, the operator 308 outputs logic 0, and the operator 309 outputs logic 1. At this time, both input ports of the data selector 311 are logic 1. Therefore, regardless of whether the operating frequency signal is logic 1 or logic 0, the result of the two-to-one data selector 311 is logic 1, that is, the output terminal TCCDL_4 is high, and the other output terminals are low, and the final compiled value is 4.

[0178] If the signal to be compiled is a reserved code, such as 101, operator 304 outputs logic 0, operator 305 outputs logic 0, operator 308 outputs logic 1, operator 309 outputs logic 1, and operator 310 outputs logic 1. At this time, the two input ports of data selector 311 and data selector 312 each include a logic 0 and a logic 1. At this time, if the operating frequency signal is logic 0, data selector 311 selects to output logic 0, data selector 312 selects to output logic 1, output terminal TCCDL_8 is high, and other output terminals are low, and the final compiled value is 8; conversely, if the operating frequency signal is logic 1, data selector 311 outputs logic 1, data selector 312 outputs logic 0, output terminal TCCDL_4 is high, and other output terminals are low, and the final compiled value is 4.

[0179] In particular, for compiled circuits, Figure 4 This is only one circuit implementation method of Table 14. Due to the diversity of logic devices, even for the same compiled truth table, it can be implemented through a variety of circuit structures, and the embodiments of this application are not exhaustive. Therefore, as long as it conforms to the concept of the embodiments of this application, that is, the reserved code is pre-encoded and decoded based on the operating frequency signal, then the corresponding circuit structure is within the scope of protection of the embodiments of this application.

[0180] It should be noted that the application scenarios of the embodiments of this application generally occur during pre-delivery testing. During user use, the reserved code is generally not used for control. Therefore, before delivery, the operating frequency signal can be preset to a low-level signal or a high-level signal. Since users generally do not send commands related to the reserved code, this will not affect the user experience. Of course, if the user sends a control command involving the reserved code, it can also ensure that the DRAM can perform the relevant decoding and operate normally.

[0181] In summary, the embodiments of the present application preset the reserved codes related to the frequency speed defined in different mode registers in the DDR4 JEDEC SPEC, thereby achieving better compatibility with the BIOS settings of different DRAM controllers.

[0182] An embodiment of the present application provides a compilation circuit, and this embodiment describes in detail the specific implementation method of the aforementioned embodiment. It can be seen that by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem that the mode register cannot work after receiving the reserved code; in addition, the compilation results of the reserved code are different depending on the operating frequency signal, so that the mode register can better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms.

[0183] In yet another embodiment of the present application, see Figure 5 , which shows a schematic diagram of the structure of a mode register 40 provided in an embodiment of the present application. Figure 5 As shown, the mode register 40 at least includes the aforementioned compilation circuit 20 .

[0184] Since the mode register 40 includes the aforementioned compilation circuit 20, and the compilation rules of the reserved code are pre-set, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem that the mode register cannot work after receiving the reserved code; in addition, the compilation results of the reserved code are different depending on the operating frequency signal, so that the mode register can better match application platforms with different operating frequencies, ultimately improving the compatibility of the mode register with different application platforms.

[0185] In yet another embodiment of the present application, see Figure 6 , which shows a schematic diagram of the structure of a memory 50 provided in an embodiment of the present application. Figure 6 As shown, the memory 50 at least includes the aforementioned mode register 40 .

[0186] Since the memory 50 includes the aforementioned mode register 40, and the compilation rules of the reserved code are pre-set, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem that the memory cannot work after receiving the reserved code; in addition, the compilation results of the reserved code are different depending on the operating frequency signal, so that the memory can better match application platforms with different operating frequencies, ultimately improving the compatibility of the memory with different application platforms.

[0187] Furthermore, the memory 50 at least includes a dynamic random access memory DRAM and complies with DDR4 memory specifications.

[0188] The above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application.

[0189] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0190] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0191] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0192] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0193] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0194] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A compilation method, characterized in that: Applied to a compiling circuit, the method includes: receiving a signal to be compiled and a working frequency signal; Compiling the signal to be compiled to obtain a compilation result signal; When the signal to be compiled is a reserved code, performing compatibility selection processing on the compiled result signal based on the operating frequency signal to determine a first compiled value; In a case where the signal to be compiled is a non-reserved code, the method further includes: determining a second compiled value according to the compiled result signal; The compiling circuit includes a first compiling unit, a second compiling unit, and a compatibility selection unit, and the method further includes: When the signal to be coded is a reserved code, determining the first coding value by the first coding unit and the compatible selection unit; When the signal to be coded is a non-reserved code, determining the second coding value by the second coding unit; The second compiled value includes n compiled values, where n is a positive integer, and the method further includes: Selecting a maximum value from the n compiled values, and determining the maximum value as a first preset value; A minimum value is selected from the n compiled values, and the minimum value is determined as the second preset value.

2. The compiling method according to claim 1, wherein: When the signal to be compiled is a reserved code, performing compatibility selection processing on the compiled result signal based on the operating frequency signal to determine a first compiled value includes: If the operating frequency signal is a first level signal, determining the first compiled value to be a first preset value; If the operating frequency signal is a second level signal, determining the first compiled value to be a second preset value; The first level signal and the second level signal are different, and the first preset value and the second preset value are different.

3. The compiling method according to claim 2, wherein: The first level signal is a low level signal, and the second level signal is a high level signal.

4. The compiling method according to claim 1, wherein: The method further comprises: Determining a first category of non-reserved codes and a second category of non-reserved codes; wherein the first category of non-reserved codes includes the non-reserved codes corresponding to the maximum value and the minimum value, respectively, and the second category of non-reserved codes includes the remaining non-reserved codes in the non-reserved codes except the first category of non-reserved codes; Accordingly, the second compilation unit includes a second-first compilation unit and a second-second compilation unit, and the method further includes: When the signal to be coded is a reserved code or a first type of non-reserved code, determining the first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit; When the signal to be coded is a second-type non-reserved code, a third coding value is determined by the second second coding unit; wherein the third coding value is the remaining coding value of the second coding value except the first coding value.

5. The compiling method according to claim 4, wherein: The determining the first coding value by using the first coding unit, the second-first coding unit, and the compatible selection unit includes: Compiling the signal to be compiled by the first compiling unit to obtain a first compiled signal; performing compilation processing on the signal to be compiled by the second-first compilation unit to obtain a second-first compiled signal; The compatible selection unit performs a logic calculation on the first compiling processing signal, the second compiling processing signal, and the operating frequency signal, and determines the first compiling value according to the logic calculation result.

6. The compiling method according to any one of claims 1 to 5, characterized in that: The reserved code includes at least one of the following: TWR&TRTP reserved code, CAS Latency reserved code, CS to CMD / ADDR Latency reserved code, CRC+DM Write Command Latency reserved code, C / A Parity Latency reserved code and tCCDL / tDLLK reserved code.

7. A compiling circuit, characterized in that: The compiling circuit comprises: Signal input terminal, used for receiving the signal to be compiled and the operating frequency signal; A compiling unit, configured to compile the signal to be compiled to obtain a compilation result signal; a compatible selection unit, configured to, when the signal to be compiled is a reserved code, perform compatible selection processing on the compiled result signal based on the operating frequency signal to determine a first compiled value; The compatible selection unit is specifically configured to determine, when the signal to be compiled is a reserved code and the operating frequency signal is a first level signal, the first compilation value to be a first preset value; and when the signal to be compiled is a reserved code and the operating frequency signal is a second level signal, the first compilation value to be a second preset value; Wherein, the first level signal and the second level signal are different, and the first preset value and the second preset value are different; The compiling circuit is further configured to determine a second compiling value according to the compiling result signal when the signal to be compiled is a non-reserved code; wherein the second compiling value includes n compiling values, where n is a positive integer; The first preset value is the maximum value among the n coding values, and the second preset value is the minimum value among the n coding values.

8. The compiling circuit according to claim 7, wherein: The first level signal is a low level signal, and the second level signal is a high level signal.

9. The compiling circuit according to claim 7, wherein: The compilation unit includes a first compilation unit and a second compilation unit; wherein, The first compiling unit is configured to compile the signal to be compiled to obtain a first compilation result signal; The second compiling unit is configured to compile the signal to be compiled to obtain a second compilation result signal.

10. The compiling circuit according to claim 9, wherein: The non-reserved code includes a first type of non-reserved code, and the second coding unit includes a second-first coding unit; The second-first compiling unit is configured to compile the signal to be compiled to obtain a second-first compiling result signal; The compatible selection unit is specifically configured to, when the signal to be compiled is a first type non-reserved code or the signal to be compiled is a reserved code, perform a logical calculation on the first compilation result signal, the second-first compilation result signal, and the operating frequency signal, and determine the first compilation value according to the logical operation result; The first type of non-reserved codes includes non-reserved codes corresponding to the maximum value and the minimum value of the n coding values.

11. The compiling circuit according to claim 10, wherein: The non-reserved code further includes a second type of non-reserved code, and the second coding unit further includes a second second coding unit; The second-second coding unit is configured to perform coding processing on the signal to be coded to obtain a second-second coding result signal; and when the signal to be coded is a second-type non-reserved code, directly determine a third coding value according to the second-second coding result signal; The second type of non-reserved codes includes the remaining non-reserved codes in the non-reserved codes except the first type of non-reserved codes, and the third coding value is the remaining coding values ​​in the second coding value except the first coding value.

12. The compiling circuit according to claim 10, wherein: The compatible selection unit includes a first selection subunit and a second selection subunit; wherein, The first selection subunit is configured to determine that the first coding value is the first preset value when the signal to be compiled is a reserved code and the operating frequency signal is a low-level signal, or when the signal to be compiled is a non-reserved code corresponding to the maximum value; The second selection subunit is configured to determine that the first coding value is the second preset value when the signal to be compiled is a reserved code and the operating frequency signal is a high-level signal, or when the signal to be compiled is a non-reserved code corresponding to the minimum value.

13. The compiling circuit according to any one of claims 7 to 12, characterized in that: The reserved code includes at least one of the following: TWR&TRTP reserved code, CAS Latency reserved code, CS to CMD / ADDR Latency reserved code, CRC+DM Write Command Latency reserved code, C / A Parity Latency reserved code and tCCDL / tDLLK reserved code.

14. A mode register, characterized in that: The mode register at least includes the compilation circuit according to any one of claims 7 to 13.

15. A memory, characterized in that: The memory includes at least the mode register as claimed in claim 14.

16. The memory according to claim 15, wherein: The memory at least includes dynamic random access memory DRAM and complies with DDR4 memory specifications.

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