Multilayer capacitor

Abstract

The present disclosure provides a multilayer capacitor including a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a plurality of first internal electrodes and a plurality of second internal electrodes alternately stacked, and a dielectric layer is interposed between the plurality of first internal electrodes and the plurality of second internal electrodes. The first external electrode and the second external electrode are electrically connected to the plurality of first internal electrodes and the plurality of second internal electrodes, respectively. A first Schottky layer is Schottky-joined to an interface between the dielectric layer and the first internal electrode in the capacitor body. A second Schottky layer is Schottky-joined to an interface between the dielectric layer and the second internal electrode in the capacitor body. A work function value of the first Schottky layer and the second Schottky layer is higher than a work function value of the first internal electrode and the second internal electrode.

Description

[0001] This application is a divisional application of the invention patent application filed on December 12, 2018, with application number 201811516709.1 and invention title "Multilayer Capacitor". Technical Field

[0002] This disclosure relates to a multilayer capacitor. Background Technology

[0003] Multilayer capacitors are conventional passive components and consist of a dielectric layer, an inner electrode, and an outer electrode.

[0004] Recently, multilayer capacitors have needed to increase capacitance while maintaining the same size as existing multilayer capacitors, and require thinner dielectric layers and internal electrodes, atomized dielectric particles, etc.

[0005] For example, in recent high-end products, in order to increase the capacitance of multilayer capacitors, dielectric layers and internal electrodes are laminated in hundreds of layers, and high capacitance is achieved by using high integration of dielectric layers with a thickness of 1 μm or less.

[0006] However, the thinning and fogging of the dielectric layer increases the insulation resistance.

[0007] Thin and fogged dielectric layers increase the risk of short circuits when two adjacent internal electrodes come into contact. This can reduce the reliability of multilayer capacitors. Summary of the Invention

[0008] One aspect of this disclosure provides a multilayer capacitor that reduces the risk of electrical short circuits when two adjacent inner electrodes are in contact, and simultaneously reduces the thickness of the dielectric layer and the thickness of the inner electrodes, thereby improving the capacitance and reliability of the product.

[0009] According to one aspect of this disclosure, a multilayer capacitor includes a capacitor body and a first external electrode and a second external electrode. The capacitor body includes a plurality of alternately stacked first internal electrodes and a plurality of second internal electrodes, and a dielectric layer is interposed between the plurality of first internal electrodes and the plurality of second internal electrodes. The first external electrode and the second external electrode are electrically connected to the plurality of first internal electrodes and the plurality of second internal electrodes, respectively. A first Schottky layer is located at a corresponding interface between the dielectric layer and the first internal electrode. A second Schottky layer is located at a corresponding interface between the dielectric layer and the second internal electrode. The work function values ​​of the first Schottky layer and the second Schottky layer are higher than the work function values ​​of the first internal electrode and the second internal electrode.

[0010] In an exemplary embodiment of this disclosure, the first Schottky layer may be formed only on one surface of the first inner electrode, and the second Schottky layer may also be formed only on one surface of the second inner electrode.

[0011] In an exemplary embodiment of this disclosure, the capacitor body can be formed by repeating a stacked structure in which a dielectric layer, a first inner electrode, a first Schottky base layer, another dielectric layer, a second inner electrode, and a second Schottky base layer are laminated.

[0012] In an exemplary embodiment of this disclosure, the capacitor body can be formed by repeating a stacked structure in which a dielectric layer, a first Schottky layer, a first inner electrode, another dielectric layer, a second Schottky layer, and a second inner electrode are laminated.

[0013] In an exemplary embodiment of this disclosure, the first Schottky layer may cover the entire surface of the first inner electrode, and the second Schottky layer may cover the entire surface of the second inner electrode.

[0014] In an exemplary embodiment of this disclosure, the first Schottky layer may be formed on both the upper and lower surfaces of the first inner electrode, and the second Schottky layer may be formed on both the upper and lower surfaces of the second inner electrode.

[0015] In an exemplary embodiment of this disclosure, the first Schottky layer may cover the entire upper surface and the entire lower surface of the first inner electrode, respectively, and the second Schottky layer may cover the entire upper surface and the entire lower surface of the second inner electrode, respectively.

[0016] In an exemplary embodiment of this disclosure, the capacitor body may be formed by repeating a stacked structure in which a dielectric layer, a first Schottky layer, a first inner electrode, another first Schottky layer, another dielectric layer, a second Schottky layer, a second inner electrode, and another second Schottky layer are laminated.

[0017] In an exemplary embodiment of this disclosure, the first Schottky layer and the second Schottky layer may be insulating semiconductor layers.

[0018] In exemplary embodiments of this disclosure, the insulating semiconductor layer may include molybdenum disulfide (MoS2) or molybdenum oxide (MoO2). x At least one of tungsten diselenide (WSe2), cadmium telluride (CdTe), and cadmium sulfide (CdS).

[0019] In exemplary embodiments of this disclosure, the dielectric layer may include barium titanate (BaTiO3).

[0020] In exemplary embodiments of this disclosure, the first internal electrode and the second internal electrode may include one or more of platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloy, nickel (Ni), and copper (Cu).

[0021] In an exemplary embodiment of this disclosure, the dimensions of the surfaces of the first Schottky substrate and the second Schottky substrate may be equal to or greater than the dimensions of the upper or lower surfaces of the first inner electrode and the second inner electrode.

[0022] In an exemplary embodiment of this disclosure, the capacitor body includes: a first surface and a second surface opposite to each other in the stacking direction; a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the length direction; and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposite to each other in the width direction. The length direction corresponds to the larger of the two directions of the capacitor body other than the stacking direction. The first inner electrode and the second inner electrode may be exposed on the third surface and the fourth surface, respectively.

[0023] In an exemplary embodiment of this disclosure, the first Schottky substrate and the second Schottky substrate may also be exposed on the third surface and the fourth surface of the capacitor body, respectively.

[0024] According to one aspect of this disclosure, a multilayer capacitor may include: an effective region comprising a plurality of first inner electrodes and a plurality of second inner electrodes, a plurality of dielectric layers, and a plurality of Schottky layers, the plurality of Schottky layers being respectively disposed between the plurality of dielectric layers and the inner electrodes, the inner electrodes comprising the plurality of first inner electrodes and the plurality of second inner electrodes; an upper cover comprising one or more dielectric layers located above an upper surface of the effective region in a stacking direction; a lower cover comprising one or more dielectric layers located below a lower surface of the effective region in the stacking direction; a first outer electrode connection portion located on a first side surface of the effective region, the upper cover, and the lower cover that is substantially parallel to the stacking direction and electrically connected to the first inner electrodes; and a second outer electrode connection portion located on a second side surface of the effective region, the upper cover, and the lower cover that is substantially parallel to the stacking direction and opposite to the first side surface and electrically connected to the second inner electrodes, wherein the Schottky layers have a first work function value, the plurality of first inner electrodes and the plurality of second inner electrodes have a second work function value, and the first work function value is greater than the second work function value.

[0025] According to one aspect of this disclosure, a multilayer capacitor may include: a plurality of stacked structures, each stacked structure sequentially including a dielectric layer having a first work function value, a first insulating layer having a second work function value, and an inner electrode having a third work function value; and an outer electrode electrically connected to a corresponding inner electrode of a repeating stacked structure, wherein the third work function value is greater than the first work function value, and the second work function value is greater than the third work function value. Attached Figure Description

[0026] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a schematic perspective view illustrating a multilayer capacitor according to an exemplary embodiment of the present disclosure;

[0028] Figures 2A to 2B It is a plan view showing the Schottky substrate bonded to the upper and lower surfaces of the first inner electrode and the Schottky substrate bonded to the upper and lower surfaces of the second inner electrode, respectively.

[0029] Figure 3 It is shown Figure 1 A perspective cross-sectional view of the portion;

[0030] Figure 4 It is shown Figure 3 An enlarged cross-sectional view of part 'A';

[0031] Figure 5 This is the energy band diagram between the dielectric layer and the internal electrode in a traditional multilayer capacitor.

[0032] Figure 6 This is an energy band diagram between the dielectric layer, Schottky layer and internal electrodes in a multilayer capacitor according to exemplary embodiments of the present disclosure;

[0033] Figure 7 This is a perspective cross-sectional view showing a portion of a multilayer capacitor according to another exemplary embodiment of the present disclosure; and

[0034] Figure 8 It is shown Figure 7 Enlarged cross-sectional view of part 'B'. Detailed Implementation

[0035] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] However, this disclosure may be illustrated in many different forms and should not be construed as being limited to the specific embodiments set forth herein.

[0037] More precisely, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0038] In the accompanying drawings, the shape and size of the elements may be exaggerated for clarity.

[0039] Furthermore, in the accompanying drawings, elements having the same function within the same scope of the inventive concept will be represented by the same reference numerals.

[0040] In the following, when the orientation of the capacitor body 110 is defined to clearly explain the exemplary embodiments in this disclosure, X, Y, and Z shown in the drawings represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Furthermore, in this exemplary embodiment, the Z direction may conceptually be the same as the stacking direction in which the dielectric layers are laminated.

[0041] Figure 1 This is a schematic perspective view illustrating a multilayer capacitor according to an exemplary embodiment of the present disclosure. Figures 2A to 2B This is a plan view showing the Schottky layers bonded to the upper and lower surfaces of the first inner electrode and the Schottky layers bonded to the upper and lower surfaces of the second inner electrode, respectively. Figure 3 It is shown Figure 1 A perspective view of a portion of the image. Figure 4 It is shown Figure 3 Enlarged cross-sectional view of part 'A'.

[0042] Reference Figures 1 to 4 According to this exemplary embodiment, the multilayer capacitor 100 includes a capacitor body 110, a first external electrode 131, and a second external electrode 132. The capacitor body 110 includes a first Schottky layer 141 and a second Schottky layer 142. The work function values ​​of the first Schottky layer and the second Schottky layer are higher than the work function values ​​of the inner electrodes. The length of the capacitor body 110 in the longitudinal direction X is greater than the width of the capacitor body 110 in the width direction Y.

[0043] The capacitor body 110 is formed by laminating multiple dielectric layers 111 in the Z direction and then firing the multiple dielectric layers 111. The boundaries between adjacent dielectric layers 111 of the capacitor body 110 can be integrated, making them difficult to identify without the use of a scanning electron microscope (SEM).

[0044] The capacitor body 110 may typically have a hexahedral shape, but this disclosure is not limited thereto. The shape and size of the capacitor body 110 and the number of laminated dielectric layers 111 are not limited to the shape, size, and number shown in the drawings of this exemplary embodiment.

[0045] In this exemplary embodiment, for ease of explanation, the surfaces of the capacitor body 110 that are opposite to each other in the Z direction are defined as first surface 1 and second surface 2; the surfaces connected to first surface 1 and second surface 2 and opposite to each other in the X direction are defined as third surface 3 and fourth surface 4; and the surfaces connected to first surface 1 and second surface 2 and connected to third surface 3 and fourth surface 4 and opposite to each other in the Y direction are defined as fifth surface 5 and sixth surface 6. In this exemplary embodiment, the mounting surface of the multilayer capacitor 100 may be the first surface 1 of the capacitor body 110.

[0046] The dielectric layer 111 may include ceramic materials with high dielectric constants, such as barium titanate (BaTiO3)-based ceramic powder or strontium titanate (SrTiO3)-based ceramic powder. However, this disclosure is not limited thereto, as long as sufficient capacitance can be obtained.

[0047] Ceramic additives, organic solvents, plasticizers, binders, dispersants, etc., can also be added to the dielectric layer 111 together with the ceramic powder.

[0048] Ceramic additives can be, for example, transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), aluminum (Al), etc.

[0049] The capacitor body 110 may include an effective area that facilitates capacitance formation, and an upper cover 112 and a lower cover 113 formed in the upper and lower parts of the effective area in the Z direction, respectively, as an upper edge and a lower edge.

[0050] Except for the absence of an inner electrode, the upper cover 112 and the lower cover 113 may have the same material and construction as the dielectric layer 111.

[0051] The upper cover 112 and the lower cover 113 can be formed by laminating a single dielectric layer or two or more dielectric layers on each of the upper and lower surfaces in the Z direction of the effective region. The upper cover 112 and the lower cover 113 can prevent damage to the first inner electrode 121 and the second inner electrode 122 due to physical or chemical stress.

[0052] The first inner electrode 121 and the second inner electrode 122 are stacked alternately in the Z direction, and one or more dielectric layers 111 are interposed therebetween. The first inner electrode 121 and the second inner electrode 122 may be applied with different polarities and have ends that are exposed to the third surface 3 and the fourth surface 4 of the capacitor body 110, respectively.

[0053] The first inner electrode 121 and the second inner electrode 122 are electrically insulated from each other through the dielectric layer 111 between them.

[0054] The ends of the first inner electrode 121 and the second inner electrode 122, which are alternately exposed on the third and fourth surfaces of the capacitor body 110, can be connected to the first outer electrode 131 and the second outer electrode 132, respectively. The first outer electrode 131 and the second outer electrode 132 can be on the third and fourth surfaces of the capacitor body 110, respectively.

[0055] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge accumulates between the first internal electrode 121 and the second internal electrode 122.

[0056] The capacitance of the multilayer capacitor 100 is proportional to the stacked area of ​​the first inner electrode 121 and the second inner electrode 122 when viewed in the Z direction.

[0057] The materials used to form the first internal electrode 121 and the second internal electrode 122 are not specifically limited. The first internal electrode 121 and the second internal electrode 122 can be formed by using, for example, noble metal materials (such as platinum (Pt), palladium (Pd) and palladium-silver (Pd-Ag) alloys) and conductive pastes made using at least one or more of nickel (Ni) and copper (Cu).

[0058] Conductive paste can be printed using methods such as screen printing and gravure printing, but this disclosure is not limited to these methods.

[0059] The first Schottky base layer 141 is Schottky bonded to the interface between the dielectric layer 111 in the capacitor body 110 and the first internal electrode 121.

[0060] In this exemplary embodiment, there may be two first Schottky layers 141 that cover the upper and lower surfaces of the first inner electrode 121 that are opposite to each other in the Z direction.

[0061] The surface dimensions of the first Schottky substrate 141 may be substantially equal to the dimensions of the upper or lower surface of the first inner electrode 121, so as to cover the entire upper or lower surface of the first inner electrode 121. Optionally, the surface dimensions of the first Schottky substrate 141 may be larger than the dimensions of the upper or lower surface of the first inner electrode 121.

[0062] The end of the first Schottky base layer 141 may be exposed to the third surface 3 of the capacitor body 110 and may contact the first connection portion 131a of the first external electrode 131.

[0063] The second Schottky base layer 142 is Schottky bonded to the interface between the dielectric layer 111 in the capacitor body 110 and the second internal electrode 122.

[0064] In this exemplary embodiment, there may be two second Schottky layers 142 that cover the upper and lower surfaces of the second inner electrode 122 that are opposite to each other in the Z direction.

[0065] The surface dimensions of the second Schottky substrate 142 may be substantially equal to the dimensions of the upper or lower surface of the second inner electrode 122, so as to cover the entire upper or lower surface of the second inner electrode 122. Optionally, the surface dimensions of the second Schottky substrate 142 may be larger than the dimensions of the upper or lower surface of the second inner electrode 122.

[0066] The end of the second Schottky base layer 142 may be exposed on the fourth surface 4 of the capacitor body 110 and may contact the second connection portion 132a of the second external electrode 132.

[0067] The first Schottky layer 141 and the second Schottky layer 142 may have insulating properties and may be formed using a material having a work function value higher than that of the metals included in the first inner electrode 121 and the second inner electrode 122. For example, the first Schottky layer 141 and the second Schottky layer 142 may be formed using an insulating semiconductor layer.

[0068] Insulating semiconductor layers can be achieved by using molybdenum disulfide (MoS2) or molybdenum oxide (MoO2). x It may be formed from at least one of tungsten diselenide (WSe2), cadmium telluride (CdTe), and cadmium sulfide (CdS), and this disclosure is not limited thereto.

[0069] MoS2, MoO x The work function values ​​of WSe2, CdTe, and CdS are 5.38 eV, 6.8 eV or less, 5.27 eV or less, 5.65 eV or less, and 5.87 eV or less, respectively, which are higher than the work function values ​​of the metals included in the inner electrode.

[0070] By using plasma sputtering, electron beam evaporation, thermal evaporation, laser molecular beam epitaxy (L-MBE), pulsed laser deposition (PLD), etc., the first Schott layer 141 and the second Schott layer 142 can be inserted between the dielectric layer 111 and the first inner electrode 121 and between the dielectric layer 111 and the second inner electrode 122, respectively.

[0071] According to this structure, the capacitor body 110 of this exemplary embodiment can be formed by repeating a laminated structure in which a dielectric layer 111, a first Schottky layer 141, a first internal electrode 121, another first Schottky layer 141, another dielectric layer 111, a second Schottky layer 142, a second internal electrode 122 and another second Schottky layer 142 are laminated.

[0072] The first external electrode 131 and the second external electrode 132 are subjected to voltages of different polarities. The first external electrode 131 and the second external electrode 132 are respectively disposed on the third surface 3 and the fourth surface 4 of the capacitor body 110, and can be connected to the exposed portion of the first internal electrode 121 and the exposed portion of the second internal electrode 122, respectively.

[0073] The first external electrode 131 and the second external electrode 132 may include conductive layers formed on the third and fourth surfaces of the capacitor body 110, respectively, and plating layers formed on the respective conductive layers.

[0074] The coating may include a nickel (Ni) coating and a tin (Sn) coating formed on the nickel (Ni) coating.

[0075] The first external electrode 131 may include a first connecting portion 131a and a first strip portion 131b.

[0076] A first connecting portion 131a is formed on the third surface 3 of the capacitor body 110 and is connected to the first internal electrode 121. A first strip portion 131b extends from the first connecting portion 131a on a portion of the first surface 1 of the capacitor body 110.

[0077] To improve the fixing strength, the first strip 131b may also extend on portions of the fifth surface 5 and the sixth surface 6, as well as portions of the second surface 2.

[0078] The second external electrode 132 may include a second connecting portion 132a and a second strip portion 132b.

[0079] A second connecting portion 132a is formed on the fourth surface 4 of the capacitor body 110 to connect to the second internal electrode 122. A second strip portion 132b extends from the second connecting portion 132a on a portion of the first surface 1 of the capacitor body 110.

[0080] To improve the fixing strength, the second strip 132b may also extend on portions of the fifth surface 5 and the sixth surface 6, as well as portions of the second surface 2.

[0081] In traditional multilayer capacitors, the metal component of the internal electrode has a higher work function value than that of the dielectric layer.

[0082] For example, the work function of a dielectric layer with BaTiO3 is 4.80 eV. The work function values ​​of internal electrodes with Ni, Cu, Pd, or Pt are 5.20 eV, 4.82 eV, 5.41 eV, and 5.53 eV, respectively.

[0083] Figure 5 The band structure diagram is an example in which the internal electrode includes nickel (Ni).

[0084] In detail, EVAC It is a vacuum energy level, E F It is the Fermi level, E C It is the conductor band, E V It is the price band, E G It is a band gap.

[0085] Reference Figure 5 When an inner electrode with a relatively high work function value is bonded to the dielectric layer, band bending occurs at the interface of the dielectric layer to maintain E F The balance between them. Band bending is represented as a Schottky junction.

[0086] The energy space where charge can accumulate exists at the Schottky barrier of the interface.

[0087] When a multilayer capacitor is operated, charge accumulates in the Schottky barrier through polarization caused by the electric field generated in the dielectric.

[0088] By improving the charge accumulation rate of a multilayer capacitor, the capacitance of a certain multilayer capacitor can be improved.

[0089] However, in traditional multilayer capacitors, the thinning and fogging of the dielectric layer leads to a decrease in the internal resistance of the dielectric layer, which may cause problems in ensuring insulation properties.

[0090] The insulation properties of a multilayer capacitor according to an exemplary embodiment of the present disclosure can be improved by controlling the interface between the dielectric layer and the internal electrode.

[0091] Therefore, in the capacitor body, a Schottky base layer comprising a semiconductor material having a high work function value is provided at the junction of the dielectric layer and the internal electrode.

[0092] Figure 6 The band structure diagram is an exemplary embodiment of this disclosure in which the Schottky base layer includes MoS2.

[0093] Reference Figure 6 MoS2 has a higher work function value (Φ) than nickel (Ni) in the internal electrode. Ni The work function value (Φ) is high at 5.2 eV. MS (5.38eV), thereby increasing the band bending at the interface of the dielectric layer, which significantly improves the performance of the Schottky junction.

[0094] Compared to multilayer capacitors that use only conventional internal electrodes, such a significantly enhanced Schottky barrier can improve the capacitance of multilayer capacitors by accumulating a relatively large amount of charge.

[0095] Because materials such as MoS2 used in the Schottky base layer have excellent insulating properties, the insulation between adjacent internal electrodes in the capacitor body after firing can be improved.

[0096] Therefore, even when the thickness of the dielectric layer and the inner electrode is reduced compared to that of a conventional multilayer capacitor, the risk of electrical short circuits caused by contact between adjacent inner electrodes can be reduced.

[0097] This structure can be applied not only to small-sized multilayer capacitors commonly used in consumer electronics, but also to large-sized multilayer capacitors commonly used in industrial and electrical fields.

[0098] Schottky layers can suppress electric field concentration and degradation of the portion of the capacitor body adjacent to the internal electrodes. Therefore, it is expected that the dielectric loss of multilayer capacitors can be reduced, long-term reliability improved, and temperature stability enhanced. Temperature stability refers to the phenomenon of the dielectric constant changing with temperature.

[0099] Figure 7 This is a perspective view showing a portion of a multilayer capacitor according to another exemplary embodiment of the present disclosure. Figure 8 yes Figure 7 Enlarged cross-sectional view of part 'B'.

[0100] Reference Figure 7 and Figure 8 According to another exemplary embodiment of the present disclosure, a multilayer capacitor may have a Schottky base layer located only on one of the surfaces of the first inner electrode 121 and the second inner electrode 122 that are opposite to each other in the Z direction.

[0101] Reference Figure 8 The capacitor body 110' can be formed by repeating the lamination structure in which dielectric layer 111, first inner electrode 121, first Schottky layer 141, another dielectric layer 111, second inner electrode 122 and second Schottky layer 142 are laminated in the Z direction.

[0102] However, this disclosure is not limited thereto, and, for example, the capacitor body can be formed by repeating a laminated structure in which a dielectric layer, a first Schottky base layer, a first inner electrode, another dielectric layer, a second Schottky base layer, and a second inner electrode are laminated. That is, according to this exemplary embodiment, the Schottky base layer may be located on the upper surface of the inner electrode, or alternatively, the Schottky base layer may be located on the lower surface of the inner electrode.

[0103] The first Schottky base layer 141 may be formed to cover the entire surface of the first inner electrode 121, and the second Schottky base layer 142 may be formed to cover the entire surface of the second inner electrode 122.

[0104] against Figure 3 and Figure 4 The capacitor body shown in the figure, because the Schottky base layer is bonded to the two surfaces of the internal electrodes, although the insulation between the internal electrodes is improved, the manufacturing process of the capacitor body becomes more complex and the efficiency of the manufacturing process may be reduced.

[0105] On the contrary, targeting Figure 7 and Figure 8 The capacitor body shown in the figure has a relatively simple lamination process because the Schottky base layer is only bonded to one surface of the internal electrode, and the insulation between the internal electrodes is still partially maintained, thus improving manufacturing efficiency.

[0106] As described above, according to exemplary embodiments of this disclosure, a Schottky layer having a work function value higher than that of the inner electrode is located on the inner electrode, such that the dielectric layer and the inner electrode can have reduced thickness and reduced risk of electrical short circuit, thereby improving the capacitance and reliability of the multilayer capacitor.

[0107] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A multilayer capacitor, the multilayer capacitor comprising: The capacitor body includes a plurality of alternately stacked first internal electrodes and a plurality of second internal electrodes, and a dielectric layer is disposed between the plurality of first internal electrodes and the plurality of second internal electrodes; The first external electrode and the second external electrode are electrically connected to the plurality of first internal electrodes and the plurality of second internal electrodes, respectively. The first Schottky layer is located at the interface between the first inner electrode and the dielectric layer; as well as The second Schottky layer is located at the interface between the second inner electrode and the dielectric layer. Wherein, the first work function value of the first Schottky layer and the second work function value of the second Schottky layer are both higher than the third work function values ​​of the first inner electrode and the second inner electrode, and the third work function values ​​of the first inner electrode and the second inner electrode are higher than the fourth work function value of the dielectric layer, and The capacitor body includes a repeating stacked structure, which includes, in sequence, one of the dielectric layers, one of the plurality of first internal electrodes, one of the plurality of first Schottky layers, another of the dielectric layers, one of the plurality of second internal electrodes, and one of the plurality of second Schottky layers.

2. The multilayer capacitor according to claim 1, wherein, The first Schottky layer is located on only one of the upper and lower surfaces of the first inner electrode in the stacking direction of the dielectric layer, and the second Schottky layer is located on only one of the upper and lower surfaces of the second inner electrode in the stacking direction.

3. The multilayer capacitor according to claim 2, wherein, The first Schottky layer covers the entire surface of the first inner electrode, and the second Schottky layer covers the entire surface of the second inner electrode.

4. The multilayer capacitor according to claim 1, wherein, The first Schottky layer is located on the lower surface of the first inner electrode in the stacking direction of the dielectric layer, and the second Schottky layer is located on the lower surface of the second inner electrode in the stacking direction.

5. The multilayer capacitor according to claim 4, wherein, The first Schottky layer covers the entire lower surface of the first inner electrode, and the second Schottky layer covers the entire lower surface of the second inner electrode.

6. The multilayer capacitor according to claim 1, wherein, The first Schottky layer and the second Schottky layer are insulating semiconductor layers.

7. The multilayer capacitor according to claim 6, wherein, The insulating semiconductor layer includes at least one of molybdenum disulfide, molybdenum oxide, tungsten diselenide, cadmium telluride, and cadmium sulfide.

8. The multilayer capacitor according to claim 1, wherein, The dielectric layer includes barium titanate.

9. The multilayer capacitor according to claim 1, wherein, The first internal electrode and the second internal electrode comprise one or more of platinum, palladium, palladium-silver alloy, nickel, and copper.

10. The multilayer capacitor according to claim 1, wherein, The first dimension of the upper or lower surface of the first Schottky substrate and the second dimension of the upper or lower surface of the second Schottky substrate are both equal to or greater than the third dimension of the upper or lower surface of the first or second inner electrode.

11. The multilayer capacitor according to claim 1, wherein, The capacitor body includes: a first surface and a second surface opposite to each other in a stacking direction; a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in a length direction generally perpendicular to the stacking direction; and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface, and opposite to each other in a width direction generally perpendicular to the stacking direction and the length direction. Wherein, the length of the capacitor body in the length direction is greater than the width of the capacitor body in the width direction, and The first inner electrode and the second inner electrode are exposed on the third surface and the fourth surface, respectively.

12. The multilayer capacitor according to claim 11, wherein, The first Schottky base layer and the second Schottky base layer are respectively exposed on the third surface and the fourth surface of the capacitor body.

13. A multilayer capacitor, the multilayer capacitor comprising: The effective region includes multiple first internal electrodes and multiple second internal electrodes, multiple dielectric layers and multiple Schottky layers, wherein the multiple Schottky layers are respectively located between the multiple dielectric layers and the internal electrodes, and the internal electrodes include the multiple first internal electrodes and the multiple second internal electrodes; The upper cover includes one or more dielectric layers located above the upper surface of the effective region in the stacking direction; The lower cover includes one or more dielectric layers located below the lower surface of the effective region in the stacking direction; The first external electrode connection portion is located on the first side surface of the effective area, the upper cover and the lower cover that is substantially parallel to the stacking direction, and is electrically connected to the first internal electrode; The second external electrode connection portion is located on the second side surface of the effective area, the upper cover, and the lower cover, which is substantially parallel to the stacking direction and opposite to the first side surface, and is electrically connected to the second internal electrode. Wherein, the Schottky base layer has a first work function value, the plurality of first inner electrodes and the plurality of second inner electrodes have second work function values, and the plurality of dielectric layers have a third work function value, wherein the first work function value is greater than the second work function value, and the second work function value is greater than the third work function value. The effective region includes a repeating stacked structure, which includes, in sequence, one of the dielectric layers, one of the plurality of first inner electrodes, one of the plurality of Schottky layers, another of the dielectric layers, one of the plurality of second inner electrodes, and another of the plurality of Schottky layers.

14. The multilayer capacitor according to claim 13, wherein, The plurality of Schottky base layers include at least one of molybdenum disulfide, molybdenum oxide, tungsten diselenide, cadmium telluride, and cadmium sulfide.

15. The multilayer capacitor according to claim 13, wherein, The plurality of Schottky base layers have a corresponding first region perpendicular to the stacking direction, the corresponding first region being equal to or greater than the corresponding second regions of the plurality of first inner electrodes and the plurality of second inner electrodes perpendicular to the stacking direction.

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