Gate resistance reduction method for fsoi transistors for radio frequencies
By fabricating the gate contact holes in the active region of the FDSOI transistor and adjusting the contact hole distribution and etching process, the problem of excessive gate resistance was solved, and the RF performance was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOI MICRO CO LTD
- Filing Date
- 2022-10-26
- Publication Date
- 2026-06-05
AI Technical Summary
The gate resistance of FDSOI transistors is relatively high, especially after the adoption of post-gate technology, which affects RF performance, including fmax and thermal noise.
In FDSOI transistors, gate contact holes are fabricated within the active region. By adjusting the distribution and spacing of the contact holes, the gate resistance is reduced. This involves etching and cleaning processes to ensure the fabrication of the contact holes, and metal filling is used.
It effectively reduces gate resistance, improves RF performance, avoids the increase in resistance caused by post-gate processing, and is suitable for RF applications.
Smart Images
Figure CN115602534B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of contact hole fabrication technology, and more specifically to a method for reducing the gate resistance of FDSOI transistors used in radio frequency. Background Technology
[0002] As device channel lengths shrink, the short-channel effect has pushed bulk CMOS to its limits. FDSOI structures have become the solution beyond 20nm, ensuring continued miniaturization of CMOS processes. Furthermore, to further shorten channel lengths, FinFET has become the mainstream process technology and will evolve further into GAA structures in the future. Compared to three-dimensional FinFETs, planar FDSOI offers advantages such as simpler process design and lower manufacturing costs. In terms of control, FDSOI's unique substrate bias voltage control gives it a significant advantage in low-power and low-efficiency applications. Structurally, FDSOI's buried oxide layer reduces parasitic capacitance and enhances isolation, making it promising for RF applications, especially given the declining RF performance of FinFET-based RF chips due to further miniaturization of FinFETs.
[0003] There are two methods for fabricating the gate of a MOSFET: front gate and back gate. The front gate process has advantages such as simple process and low gate resistance, but disadvantages such as high threshold voltage and difficulty in further miniaturization of Tinv. The back gate process has advantages such as low power consumption, low leakage current and stable high-frequency operation, but disadvantages such as high gate resistance. However, the back gate process will become the future development trend of FDSOI gate manufacturing.
[0004] Currently, the gate contact holes of FDSOI are located outside the active region and on the STI, which has defects such as relatively large gate resistance. Large gate resistance will degrade the RF performance of the device, including fmax and thermal noise. In particular, FDSOI will need to adopt post-gate process in the future, and the gate resistance of post-gate process is relatively larger, which will further increase the impact of gate resistance on RF performance. In addition, when fabricating the source and drain contacts of FDSOI, rows of source and drain contacts are fabricated, with equal spacing between them. The distance between two adjacent source contacts is between c1 and c2, where c1 is less than c2. The distance between two adjacent drain contacts is between c3 and c4, where c3 is less than c4. The distance between the source contacts and the gate is between a1 and a2, where a1 is less than a2. The distance between the drain contacts and the gate is between a3 and a4, where a3 is less than a4. a1, a2, a3, a4, c1, c2, c3, and c4 are all positive real numbers, and their values should all be within the range required by the design rules. The smaller the process node, the smaller a1, a3, c1, and c3 are. Summary of the Invention
[0005] In view of the deficiencies of the background technology, the present invention provides a method for reducing the gate resistance of an FDSOI transistor for radio frequency, which can reduce the gate resistance of an FDSOI transistor fabricated using the back-gate process without affecting its radio frequency performance.
[0006] To solve the above technical problems, the present invention provides the following technical solutions: A method for reducing the gate resistance of an FDSOI transistor for radio frequency, comprising:
[0007] S1: Provide a semiconductor device, which includes a substrate and a buried oxide layer arranged from bottom to top. An isolation trench and an active region are provided on the buried oxide layer. An active electrode, a drain electrode, and a gate electrode are fabricated in the active region, and the gate electrode is fabricated using the back-gate process;
[0008] S2: Fabricate a material layer on the top of the semiconductor device, fabricate a mask layer on the top of the material layer, and fabricate a photoresist layer on the top of the mask layer;
[0009] S3: Define the positions of the gate contact holes, the source contact holes, and the drain contact holes in the region corresponding to the active region on the photoresist layer through an exposure process and a development process;
[0010] S4: Etch the mask layer and the material layer in sequence at the defined positions of the gate contact holes, the source contact holes, and the drain contact holes through an etching process until the gate electrode, the drain electrode, and the source electrode are exposed.
[0011] As a further technical solution, in step S3, at least one column of source contact holes and at least one column of drain contact holes are defined in the region corresponding to the active region on the photoresist layer; the source contact holes in each column of source contact holes are equally spaced, and the distance between adjacent two source contact holes is between d1 and d2, where d1 < d2 and d1 > c2. The drain contact holes in each column of drain contact holes are equally spaced, and the distance between adjacent two drain contact holes is between d3 and d4, where d3 is greater than c4.
[0012] As a further technical solution, in step S3, the distance between the source contact hole and the gate electrode is between b1 and b2, where b1 < b2 and b1 > a2. The distance between the drain contact hole and the gate electrode is between b3 and b4, where b3 < b4 and b3 is greater than a4.
[0013] As a further technical solution, in step S3, the defined position of the gate contact hole is in the middle of the gate electrode.
[0014] As a further technical solution, the material layer includes an etch stop layer and an oxide layer.
[0015] As a further technical solution, in step S3, the positions of the second gate contact holes are defined on the photoresist layer and in the regions at both ends of the gate, respectively, and the second gate contact holes are outside the active region.
[0016] As a further technical solution, the following steps are also included:
[0017] S5: The byproducts generated during step S4 are removed by a cleaning process, and metal is filled into the etched gate metal holes, source contact holes and drain contact holes respectively.
[0018] The gate resistance of FDSOI has two components: parallel and vertical. The vertical resistance is mainly determined by the interface resistance of various gate materials and is not significantly affected by the front and rear metal gate processes. It is primarily reduced by increasing the device width in the circuit design. The parallel resistance is closely related to the metal material and the channel length, representing a key area for improvement in the manufacturing process. This invention, by fabricating the gate contact hole within the active region, shortens the signal propagation path of the RF signal, thereby reducing resistance and preventing excessive gate resistance in FDSOIs manufactured using a rear-gate process. Attached Figure Description
[0019] Figure 1 This is a flowchart of the present invention as illustrated in the embodiments;
[0020] Figure 2 This is a schematic diagram showing the distribution of existing source and drain contact holes;
[0021] Figure 3 This is a schematic diagram showing the distribution of the source and drain contact holes of the present invention;
[0022] Figure 4 This is a schematic diagram showing another distribution of the source and drain contact holes of the present invention;
[0023] Figure 5 This is a schematic diagram showing the radio frequency signal propagation path of the gate contact hole outside and inside the active region.
[0024] In the diagram: 1. Gate, 2. Gate contact hole, 3. Source / drain contact hole. Detailed Implementation
[0025] The illustrative embodiments of this application include, but are not limited to, methods for reducing the gate resistance of FDSOI transistors for radio frequency.
[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0027] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.
[0028] like Figure 1 As shown, a method for reducing the gate resistance of an FDSOI transistor used in radio frequency includes:
[0029] S1: Provides a semiconductor device, which includes a substrate and a buried oxide layer arranged from bottom to top. The buried oxide layer has isolation trenches and an active region. The active region has a channel, a source, a drain, and a gate. The gate is fabricated using a post-gate process.
[0030] S2: A material layer is formed on top of the semiconductor device, a mask layer is formed on top of the material layer, and a photoresist layer is formed on top of the mask layer;
[0031] S3: The positions of the gate contact hole, the source contact hole, and the drain contact hole are defined on the photoresist layer in the region corresponding to the active region by the exposure and development processes.
[0032] S4: Using an etching process, the mask layer and material layer are sequentially etched at the defined positions of the gate contact hole, the source contact hole, and the drain contact hole until the gate, drain, and source are exposed.
[0033] S5: The byproducts generated during step S4 are removed by a cleaning process, and metal is filled into the etched gate metal holes, source contact holes and drain contact holes respectively.
[0034] Specifically, in step S1, the substrate can be [substrate type]; the gate includes a high-k dielectric layer and a gate metal, and the high-k dielectric layer and the gate metal are disposed on the channel from bottom to top. The material of the high-k dielectric layer can be HfO2. After the channel, source, drain, and gate are fabricated on the active region in step S1, the gate resistance is relatively large because the gate is manufactured using a post-gate process, i.e., HKMG process. Since the gate resistance of FDSOI has two components, parallel and vertical, the vertical resistance is mainly determined by the interface resistance of various gate materials and is not significantly related to the front and rear metal gate processes. It is mainly reduced by increasing the device width in the circuit design. The parallel resistance is closely related to the metal material and the channel length, and is the main area for improvement in the process. Therefore, in steps S2-S4 of this invention, the overall gate resistance is reduced by fabricating the gate contact hole within the active region.
[0035] Specifically, in step S2, the material layer includes an etch stop layer and an oxide layer. The etch stop layer serves as the etch endpoint when etching the gate contact hole, source contact hole, and drain contact hole. Additionally, for contact holes with large height differences, to avoid over-etching, the material layer includes a first etch stop layer, a first insulating layer, a second etch stop layer, and an oxide layer arranged from bottom to top. By setting two etch stop layers, different degrees of over-etching of the gate, source, and drain can be prevented.
[0036] Specifically, the photoresist used in step S2 to fabricate the photoresist layer can be either a positive or negative photoresist. Depending on the exposure light source and radiation source, it can be ultraviolet photoresist, deep ultraviolet photoresist, X-ray photoresist, electron beam photoresist, or ion beam photoresist. During the fabrication of the photoresist layer, the photoresist is placed on a mask layer, and then the semiconductor device is rotated to evenly distribute the photoresist on the mask layer. After the photoresist layer is fabricated, the semiconductor device can be dried. In step S31, ultraviolet light, electron beam, ion beam, or X-rays can be used for irradiation or radiation to achieve exposure.
[0037] Specifically, in step S3, depending on the type of photoresist, ultraviolet light, electron beam, ion beam, or X-rays can be used to irradiate or radiate the photomask to achieve exposure. The photomask has a pre-defined pattern of gate contact holes, source contact holes, and drain contact holes. The light source illuminates the photoresist layer with the positions of the gate contact holes, source contact holes, and drain contact holes through the photomask. After the positions of the gate contact holes, source contact holes, and drain contact holes are determined on the photoresist layer, the photoresist corresponding to the gate contact holes, source contact holes, and drain contact holes is removed using a development process. It should be noted that compared to FDSOI devices used in CPUs and memory, FDSOI devices used in RF chips have less stringent area requirements, allowing for some sacrifice in device area to improve the performance of the RF chip. Since this application requires the fabrication of gate contact holes in the active region, increasing the number of contact holes fabricated in the same area without increasing the active region area would lead to increased etching difficulty. Therefore, in this embodiment, when at least one column of source contact holes and at least one column of drain contact holes are defined on the photoresist layer corresponding to the active region in step S3; the source contact holes in each column of source contact holes are evenly spaced and the spacing between two adjacent source contact holes is between d1 and d2, where d1<d2,d1> c2 represents the drain contacts in each row of drain contacts being evenly spaced, with the spacing between two adjacent drain contacts between d3 and d4, where d3 is greater than c4. d1, d2, d3, and d4 are all positive real numbers. The explanations of c2 and c4 are provided in the background section. Since the spacing requirements differ for different process nodes, taking 28nm as an example, c1 can be 70nm, c3 can be 70nm, and c2 and c4 should both be greater than 70nm, and must be within the design rule requirements. Furthermore, the smaller the process node, the smaller the values of c1 and c3. (Illustratively, refer to...) Figure 2 and Figure 3 When the active region area remains constant, this application increases the distance between two adjacent source contacts and two adjacent drain contacts by reducing the number of source and drain contacts in the same column. In practical applications, although reducing the number of source and drain contacts increases the source-drain voltage and reduces the source-drain current, this method can reduce the gate resistance, ensuring that the manufactured FDSOI device can be better applied in the radio frequency field.
[0038] Alternatively, when increasing the area of the active region, the distance between the source contact hole and the gate and the distance between the drain contact hole and the gate can be increased to ensure that the gate contact hole, the source contact hole, and the drain contact hole can be etched out normally. Among them, the distance between the source contact hole and the gate is between b1 and b2, b1 < b2, b1 > a2, the distance between the drain contact hole and the gate is between b3 and b4, b3 < b4, b3 is greater than a4, and b1, b2, b3, and b4 are all positive real numbers. For the explanations of a2 and a4, see the background art section. Since the pitch requirements for different process nodes are different, taking 28nm as an example, a1 can be 70nm, a3 can be 70nm, both a2 and a4 should be greater than 70nm and within the requirements of the design rules. In addition, the smaller the process node, the smaller the values of a1 and a3. Schematically, referring to Figure 2 and Figure 4 , when the number of source contact holes and drain contact holes in the same column remains unchanged, the present application ensures that the gate contact hole, the source contact hole, and the drain contact hole can be etched out normally by increasing the distance between the source contact hole and the gate and increasing the distance between the drain contact hole and the gate. In actual use, although this method will increase the area of the FDSOI device, it can reduce the gate resistance through this method and ensure that the manufactured FDSOI device can be better applied in the radio frequency field.
[0039] After the positions of the gate contact hole, the source contact hole, and the drain contact hole are defined, the gate contact hole, the source contact hole, and the drain contact hole can be etched through an etching process. In actual use, the contact holes can be etched by dry etching or wet etching. In actual use, two etching processes can be used to etch the contact holes. For example, first, the mask layer is etched through one etching process, and then the oxide layer is etched through a second etching process. The etching gases used in the first etching process and the second etching process can be selected according to actual needs. As a reference, the etching gas can be based on the etching rate ratio of the mask layer and the oxide layer under the condition of ensuring cost. The larger the etching rate ratio of the etching gas to the mask layer and the oxide layer, the better, so as to ensure that the over-etching amount of the contact hole is smaller.
[0040] After the gate contact hole, the source contact hole, and the drain contact hole are etched, some by-products will be generated during the etching process, so cleaning with a cleaning solution is required. In actual use, the semiconductor device can be cleaned with CR solution, DHF solution, SC1 solution, and SC2 solution, or the semiconductor device can be cleaned with CR solution, DHF solution, SC1 solution, and SC2 solution in different cleaning sequences.
[0041] The CR solution, which consists of H2SO4 and H2O2, is used for cleaning after photoresist removal and is typically in a 4:1 ratio. It should be noted that this ratio is for illustrative purposes only; the ratio of H2SO4 to H2O2 can be adjusted according to cleaning requirements in actual use.
[0042] The DHF solution comprises HF and H₂O, with the HF concentration ranging from 0.49% to 2%. It should be noted that this ratio is for illustrative purposes only; the HF concentration can be adjusted according to the cleaning requirements in actual use.
[0043] The SC1 solution comprises NH4OH, H2O2, and H2O in a ratio typically ranging from 0.05 to 1:1:5. It should be noted that this ratio is for illustrative purposes only; the actual ratio of NH4OH, H2O2, and H2O can be adjusted according to cleaning requirements.
[0044] The SC2 solution comprises HCl, H2O2, and H2O in a typical ratio of 1:1:6. It should be noted that this ratio is for illustrative purposes only; the ratio of HCl, H2O2, and H2O can be adjusted according to cleaning requirements in actual use.
[0045] like Figure 5 As shown, by fabricating the gate contact hole within the active region, the present invention can shorten the signal propagation path of the radio frequency signal, thereby reducing the resistance and avoiding excessive gate resistance during FDSOI fabrication using a post-gate process.
[0046] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. Method for reducing gate resistance of FDSOI transistor for radio frequency, comprising: S1: Provide a semiconductor device, which includes a substrate and a buried oxide layer arranged from bottom to top. An isolation trench and an active region are provided on the buried oxide layer, and an active electrode, a drain electrode and a gate electrode are fabricated in the active region. It is characterized in that the gate electrode is fabricated by a back-gate process; and the following steps are further included: S2: Fabricate a material layer on the top of the semiconductor device, fabricate a mask layer on the top of the material layer, and fabricate a photoresist layer on the top of the mask layer; S3: Define the positions of gate contact holes, source contact holes and drain contact holes in the area corresponding to the active region on the photoresist layer through exposure process and development process; S4: Etch the mask layer and the material layer in sequence at the positions of the defined gate contact holes, source contact holes and drain contact holes through etching process until the gate electrode, drain electrode and source electrode are exposed; In step S3, at least one column of source contact holes and at least one column of drain contact holes are defined in the area corresponding to the active region on the photoresist layer; the source contact holes in each column of source contact holes are equally spaced and the spacing between two adjacent source contact holes is between d1 and d2, d1 < d2, d1 > c2, the drain contact holes in each column of drain contact holes are equally spaced and the spacing between two adjacent drain contact holes is between d3 and d4, d3 is greater than c4; both c2 and c4 are greater than 70nm; In step S3, the distance between the source contact hole and the gate electrode is between b1 and b2, b1 < b2, b1 > a2, the distance between the drain contact hole and the gate electrode is between b3 and b4, b3 < b4, b3 is greater than a4; both a2 and a4 are greater than 70nm; The material layer includes a first etch stop layer, a first insulating layer, a second etch stop layer and an oxide layer arranged from bottom to top.
2. The method for reducing the gate resistance of an FDSOI transistor for radio frequency according to claim 1, characterized in that, In step S3, the position of the defined gate contact hole is in the middle of the gate electrode.
3. The method for reducing the gate resistance of an FDSOI transistor for radio frequency according to claim 1, characterized in that, In step S3, the positions of second gate contact holes are further defined in the areas corresponding to both ends of the gate electrode on the photoresist layer, and the second gate contact holes are outside the active region.
4. The method for reducing the gate resistance of an FDSOI transistor for radio frequency according to claim 1, characterized in that, The following steps are further included: S5: Wash away the by-products generated during the execution of step S4 through a cleaning process, and fill metals in the etched gate metal holes, source contact holes and drain contact holes respectively.