Semiconductor structure and method of forming the same

Abstract

The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: forming a base, wherein the base comprises a substrate, a dielectric layer on the substrate, and a via structure penetrating through the dielectric layer and the substrate; etching the dielectric layer to form a groove exposing the sidewall of the via structure, wherein the inner diameter of the groove gradually increases along the direction of the substrate pointing to the dielectric layer; and filling a heat-conducting material in the groove to form a heat-dissipation layer. In one aspect, the present application is beneficial to upwardly transmitting the heat generated by the via structure and improving the heat-dissipation efficiency of the via structure. In another aspect, the present application can effectively reduce the occupation of the active area inside the substrate, reduce the stress influence and temperature influence of the via structure on the surrounding components, and thus improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Through-Silicon Via (TSV) technology is used in three-dimensional integrated circuits to interconnect stacked chips. However, stacking multiple layers of chips together via TSVs leads to a sharp increase in the overall power consumption of the semiconductor structure. High heat generation and poor heat dissipation cause the chip's operating temperature to rise. Furthermore, since only the bottom-most chip is adjacent to the heat sink, overall heat dissipation of the semiconductor structure is extremely difficult, and the excessively high heat density severely compromises the reliability and stability of TSVs.

[0003] Furthermore, because the metal filling the through-silicon vias (TSVs) is prone to expansion and contraction due to thermal stress, it can easily cause stress deformation in the silicon substrate and the dielectric layer surrounding the TSVs. This can affect the device characteristics in the active region within the substrate and even cause structural damage to the active region. Currently, the integrity of the substrate and dielectric layer is relatively high, therefore, there is no effective method to eliminate stress.

[0004] Therefore, how to effectively dissipate the heat in through-silicon vias (TSVs), improve the reliability and stability of TSVs, reduce the stress impact on surrounding devices, and improve the performance of semiconductor structures are urgent technical problems to be solved. Summary of the Invention

[0005] This invention provides a semiconductor structure and its formation method to solve the problem of heat dissipation difficulties in through-silicon vias (TSVs) in the prior art, thereby improving the reliability and stability of TSVs, reducing the stress impact on devices around the TSVs, and improving the performance of the semiconductor structure.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0007] A substrate is formed, the substrate including a substrate, a dielectric layer located on the substrate, and a via structure penetrating the dielectric layer and the substrate;

[0008] The dielectric layer is etched to form a groove that exposes the sidewall of the via structure, and the inner diameter of the groove gradually increases along the direction from the substrate to the dielectric layer;

[0009] A heat-conducting material is filled into the groove to form a heat dissipation layer.

[0010] Optionally, the specific steps for forming the substrate include:

[0011] A substrate is provided, the surface of which is covered with a dielectric layer;

[0012] Etch the dielectric layer and the substrate to form a through-hole penetrating the dielectric layer and the substrate;

[0013] A first diffusion barrier layer is formed covering the inner wall of the through hole;

[0014] A conductive pillar is formed to fill the through-hole and cover the surface of the first diffusion barrier layer, thereby forming a through-hole structure including the through-hole, the first diffusion barrier layer and the conductive pillar.

[0015] Optionally, the specific steps for forming the grooves exposing the sidewalls of the through-hole structure include:

[0016] The dielectric layer around the periphery of the via structure is etched to form a groove surrounding the periphery of the via structure and exposing the first diffusion barrier layer.

[0017] Optionally, the groove includes a plurality of sub-grooves stacked and interconnected along a direction perpendicular to the surface of the substrate, wherein the inner diameter of the sub-grooves closer to the substrate in two adjacent sub-grooves is smaller than the inner diameter of the sub-grooves farther from the substrate.

[0018] Optionally, the specific steps of etching the dielectric layer to form a groove exposing the sidewalls of the via structure include:

[0019] The dielectric layer around the periphery of the via structure is etched to form an initial sub-groove surrounding the via structure;

[0020] Perform the following loop steps at least once:

[0021] The dielectric layer is etched downward along the initial sub-groove to form a next sub-groove surrounding the periphery of the via structure and exposing the first diffusion barrier layer. The inner diameter of the next sub-groove is smaller than the inner diameter of the initial sub-groove. The initial sub-groove and the formed next sub-groove are used together as the initial sub-groove for the next cycle step.

[0022] Optionally, the specific steps of etching the dielectric layer downwards along the initial sub-groove include:

[0023] An initial protective layer is formed covering the sidewalls and bottom of the initial sub-groove;

[0024] The initial protective layer within the initial sub-groove and the dielectric layer below the initial sub-groove are etched downwards in a direction perpendicular to the substrate to form a next sub-groove surrounding the periphery of the via structure and exposing the first diffusion barrier layer. The inner diameter of the next sub-groove is smaller than the inner diameter of the initial sub-groove.

[0025] Optionally, the through-hole structure further includes an isolation layer located between the inner wall of the through-hole and the first diffusion barrier layer; the specific steps for forming the initial sub-groove surrounding the through-hole structure include:

[0026] The dielectric layer and the isolation layer around the periphery of the via structure are etched to form an initial sub-groove surrounding the periphery of the via structure and exposing the first diffusion barrier layer.

[0027] Optionally, the specific steps of etching the dielectric layer downwards along the initial sub-groove include:

[0028] The dielectric layer and the isolation layer at the bottom of the initial sub-groove portion are etched.

[0029] Optionally, before filling the groove with thermally conductive material, the following steps are also included:

[0030] A portion of the isolation layer between the substrate and the first diffusion barrier layer is removed, forming an air gap between the substrate and the first diffusion barrier layer.

[0031] Optionally, before filling the groove with thermally conductive material, the method further includes:

[0032] A second diffusion barrier layer is formed covering the inner wall of the groove.

[0033] Optionally, the specific steps of filling the groove with thermally conductive material include:

[0034] Spin-coating heat-dissipating metal particles into the groove.

[0035] To address the above problems, the present invention also provides a semiconductor structure, comprising:

[0036] Substrate;

[0037] A dielectric layer is located on the substrate;

[0038] A through-hole structure extends through the dielectric layer and the substrate;

[0039] A groove is located within the dielectric layer, the groove exposes the sidewall of the via structure, and the inner diameter of the groove gradually increases along the direction from the substrate to the dielectric layer;

[0040] A heat dissipation layer is located within the dielectric layer. The heat dissipation layer is in direct contact with the sidewall of the through-hole structure, and the diameter of the heat dissipation layer gradually increases along the direction from the substrate to the dielectric layer.

[0041] Optionally, the through-hole structure includes:

[0042] A conductive pillar penetrates the dielectric layer and the substrate;

[0043] A first diffusion barrier layer covers the surface of the sidewall of the conductive pillar.

[0044] Optionally, the heat dissipation layer surrounds the outer periphery of the through-hole structure and is in direct contact with the first diffusion barrier layer.

[0045] Optionally, the edge of the heat dissipation layer away from the via structure includes multiple steps stacked in a direction perpendicular to the surface of the substrate, and the step closer to the substrate in two adjacent steps protrudes and extends toward the side closer to the via structure.

[0046] Optional, also includes:

[0047] The second diffusion barrier layer is located between the heat dissipation layer and the dielectric layer.

[0048] Optional, also includes:

[0049] An isolation layer is located between the substrate and the first diffusion barrier layer.

[0050] Optional, also includes:

[0051] An air gap is located between the substrate and the first diffusion barrier layer, and the air gap is located between the second diffusion barrier layer and the isolation layer.

[0052] Optionally, the material of the heat dissipation layer is metal particles.

[0053] Optionally, the metal particles include one or more of Ag particles, Au particles, Pt particles, Al particles, W particles, Cu particles, and Ru particles.

[0054] The semiconductor structure and its formation method provided by this invention form a groove exposing the sidewalls of the via structure by etching a dielectric layer. The inner diameter of the groove gradually increases along the direction from the substrate to the dielectric layer, so that the subsequently formed heat dissipation layer is in direct contact with the via structure. The heat dissipation layer has an inverted conical structure. On the one hand, this facilitates the upward transfer of heat generated by the via structure, improving the heat dissipation efficiency of the via structure. On the other hand, since the heat dissipation layer exists only in the dielectric layer, it can effectively reduce the area occupied by the active region inside the substrate and reduce the stress and temperature effects of the via structure on surrounding components, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0055] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of the present invention;

[0056] Appendix Figure 2A-2PThis is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure in a specific embodiment of the present invention;

[0057] Appendix Figure 3 This is a schematic diagram of the semiconductor structure in a specific embodiment of the present invention. Detailed Implementation

[0058] The specific embodiments of the semiconductor structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0059] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. Figure 2A-2P This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure in a specific embodiment of the present invention. For example... Figure 1 , Figures 2A-2P As shown, the method for forming the semiconductor structure includes the following steps:

[0060] Step S11, forming a substrate, the substrate including a substrate 20, a dielectric layer 22 located on the substrate 20, and a via structure 23 penetrating the dielectric layer 22 and the substrate 20, such as Figure 2A As shown.

[0061] Optionally, the specific steps for forming the substrate include:

[0062] A substrate 20 is provided, the surface of which is covered with a dielectric layer 22;

[0063] Etch the dielectric layer 22 and the substrate 20 to form a through-hole 231 penetrating the dielectric layer 22 and the substrate 20;

[0064] A first diffusion barrier layer 233 is formed covering the inner wall of the through hole 231;

[0065] Conductive pillars 234 are formed to fill the through-hole 231 and cover the surface of the first diffusion barrier layer 233, thereby forming a through-hole structure 23 including the through-hole 231, the first diffusion barrier layer 233 and the conductive pillars 234.

[0066] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 has a plurality of active regions arranged in an array, and shallow trench isolation structures 21 located between adjacent active regions. The via 231 penetrates the dielectric layer 22 and the substrate 20 in a direction perpendicular to the surface of the substrate 20. The first diffusion barrier layer 233 covers the sidewalls and bottom wall surfaces of the via 231, and is used to prevent conductive particles in the conductive pillar 234 from diffusing into the substrate 20 and / or the dielectric layer 22. The material of the first diffusion barrier layer 233 may be, but is not limited to, TiN material. The material of the conductive pillar 234 may be a conductive metal material, such as tungsten.

[0067] Step S12: Etch the dielectric layer 22 to form a groove 24 exposing the sidewalls of the via structure 23. The inner diameter of the groove 24 gradually increases along the direction from the substrate 20 to the dielectric layer 22, such as... Figure 2M As shown.

[0068] The groove 24 may expose only a portion of the sidewall of the through-hole structure 23, or it may expose the entire sidewall of the through-hole structure 23. Optionally, the specific steps for forming the groove 24 that exposes the sidewall of the through-hole structure 23 include:

[0069] The dielectric layer 22 around the periphery of the via structure 23 is etched to form a groove 24 surrounding the periphery of the via structure 23 and exposing the first diffusion barrier layer 233.

[0070] In this specific embodiment, the groove 24 is arranged around the outer periphery of the through hole structure 23, thereby maximizing the exposure of the sidewall of the through hole structure 23, so that the heat in the through hole structure 23 can be dissipated more fully.

[0071] Optionally, the groove 24 includes a plurality of sub-grooves stacked and interconnected along a direction perpendicular to the surface of the substrate 20, and the inner diameter of the sub-grooves closer to the substrate 20 in two adjacent sub-grooves is smaller than the inner diameter of the sub-grooves farther from the substrate 20.

[0072] Specifically, the groove 24 includes a plurality of sub-grooves stacked and interconnected along a direction perpendicular to the surface of the substrate 20, and the inner diameter of the plurality of sub-grooves gradually decreases along the direction from the dielectric layer 22 to the substrate 20, thereby making the sidewall of the groove 24 step-shaped, and in two adjacent steps, the step closer to the substrate 20 protrudes and extends towards the side closer to the through-hole structure 23.

[0073] This specific embodiment is illustrated using the stepped sidewall of the groove 24 as an example. In other embodiments, those skilled in the art can also make the groove 24 have a flat sidewall with an inverted conical shape to simplify the manufacturing process.

[0074] Optionally, the specific steps of etching the dielectric layer 22 to form a groove 24 exposing the sidewall of the via structure 23 include:

[0075] The dielectric layer 22 on the outer periphery of the through-hole structure 23 is etched to form an initial sub-groove 241 surrounding the through-hole structure 23;

[0076] Perform the following loop steps at least once:

[0077] The dielectric layer 22 is etched downward along the initial sub-groove 241 to form a next sub-groove 242 that surrounds the outer periphery of the via structure 23 and exposes the first diffusion barrier layer 233. The inner diameter of the next sub-groove 242 is smaller than the inner diameter of the initial sub-groove 241. The initial sub-groove 241 and the formed next sub-groove 242 are used together as the initial sub-groove for the next cycle step.

[0078] Optionally, the specific steps of etching the dielectric layer 22 downward along the initial sub-groove 241 include:

[0079] An initial protective layer 251 is formed covering the sidewalls and bottom of the initial sub-groove 241;

[0080] The initial protective layer 251 within the initial sub-groove 241 and the dielectric layer 22 below the initial sub-groove 241 are etched downwards in a direction perpendicular to the substrate to form a next sub-groove 242 surrounding the outer periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233. The inner diameter of the next sub-groove 242 is smaller than the inner diameter of the initial sub-groove 241.

[0081] Optionally, the through-hole structure 23 further includes an isolation layer 232 located between the inner wall of the through-hole 231 and the first diffusion barrier layer 233; the specific steps for forming the initial sub-groove 241 surrounding the through-hole structure 23 include:

[0082] The dielectric layer 22 and the isolation layer 232 on the outer periphery of the via structure 23 are etched to form an initial sub-groove 241 surrounding the outer periphery of the via structure 23 and exposing the first diffusion barrier layer 233.

[0083] Optionally, the specific steps of etching the dielectric layer 22 downward along the initial sub-groove 241 include:

[0084] The dielectric layer 22 and the isolation layer 232 at the bottom of the initial sub-groove 241 portion are etched.

[0085] Specifically, the isolation layer 232 is used to electrically isolate the substrate 20 from the conductive pillar 234. The material of the isolation layer 232 is an insulating material, such as silicon dioxide. Therefore, the thermal conductivity of the isolation layer 232 is poor. In this specific embodiment, the isolation layer 232 is etched away while the dielectric layer 22 is being etched, which helps to dissipate the heat in the conductive pillar 234.

[0086] For example, firstly, the dielectric layer 22 is etched around the outer periphery of the via structure 23 to form the initial sub-groove 241 that exposes the first diffusion barrier layer 233 of the via structure 23, such as... Figure 2B As shown. Next, the first cycle step is performed: the initial protective layer 251 is deposited in the initial sub-groove 241, as shown. Figure 2C As shown; then, the position of the next sub-groove is defined in the initial protective layer 251. After exposing and developing the patterned initial protective layer 251, the initial protective layer 251 and the dielectric layer 22 and the isolation layer 232 below the initial sub-groove 241 are etched downward along the direction perpendicular to the substrate, forming a second sub-groove 242 surrounding the periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233, as shown. Figure 2D As shown; the second sub-groove 242 is connected to the initial sub-groove 241. The material of the initial protective layer 251 can be a photoresist material.

[0087] Next, the second cycle step is performed: a second protective layer 252 is deposited in the second sub-groove 242, as follows. Figure 2E As shown; then, the position of the next sub-groove is defined in the second protective layer 252. After exposing and developing the patterned second protective layer 251, the second protective layer 251 and the dielectric layer 22 and the isolation layer 232 below the second sub-groove 242 are etched downwards in a direction perpendicular to the substrate, forming a third sub-groove 243 surrounding the periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233, as shown. Figure 2F As shown; the third sub-groove 243 is connected to both the initial sub-groove 241 and the second sub-groove 242. The material of the second protective layer 252 can also be a photoresist material.

[0088] Next, the third cycle step is performed: a third protective layer 253 is deposited in the third sub-groove 243, as follows. Figure 2GAs shown; then, the position of the next sub-groove is defined in the third protective layer 253. After exposing and developing the patterned third protective layer 253, the third protective layer 253 and the dielectric layer 22 and the isolation layer 232 below the third sub-groove 243 are etched downwards in a direction perpendicular to the substrate, forming a fourth sub-groove 244 surrounding the periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233, as shown. Figure 2H As shown, the fourth sub-groove 244 is connected to the initial sub-groove 241, the second sub-groove 242, and the third sub-groove 243. The material of the third protective layer 253 can also be a photoresist material.

[0089] Next, the fourth cycle step is performed: a fourth protective layer 254 is deposited in the fourth sub-groove 244, as follows. Figure 2I As shown; then, the position of the next sub-groove is defined in the fourth protective layer 254. After exposing and developing the patterned fourth protective layer 254, the fourth protective layer 254 and the dielectric layer 22 and the isolation layer 232 below the fourth sub-groove 244 are etched downwards in a direction perpendicular to the substrate, forming a fifth sub-groove 245 surrounding the outer periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233, as shown. Figure 2J As shown, the fifth sub-groove 245 is connected to the initial sub-groove 241, the second sub-groove 242, the third sub-groove 243, and the fourth sub-groove 244. The material of the fourth protective layer 254 can also be a photoresist material.

[0090] Next, the fifth cycle step is performed: a fifth protective layer 255 is deposited in the fifth sub-groove 245, as follows. Figure 2K As shown; then, the position of the next sub-groove is defined in the fifth protective layer 255. After exposing and developing the patterned fifth protective layer 255, the fifth protective layer 255 and the dielectric layer 22 and the isolation layer 232 below the fifth sub-groove 245 are etched downwards in a direction perpendicular to the substrate, forming a sixth sub-groove 246 surrounding the outer periphery of the through-hole structure 23 and exposing the first diffusion barrier layer 233, as shown. Figure 2L As shown, the sixth sub-groove 246 is connected to the initial sub-groove 241, the second sub-groove 242, the third sub-groove 243, the fourth sub-groove 244, and the fifth sub-groove 245. The material of the fifth protective layer 255 can also be a photoresist material.

[0091] During the execution of the cyclic steps, it is determined whether the formed sub-groove exposes the substrate 20. If so, the cyclic step is terminated to avoid damage to the substrate 20. For example, after the formation of the sixth sub-groove 246, if the bottom of the sixth groove 246 exposes the substrate 20, the cyclic step is terminated. After the cyclic step is terminated, all remaining protective layers are removed, such as the remaining first protective layer 251, the remaining second protective layer 252, the remaining third protective layer 253, the remaining fourth protective layer 254, and the remaining fifth protective layer 255, to obtain the following: Figure 2N The structure shown.

[0092] Step S13: Fill the groove 24 with thermally conductive material to form a heat dissipation layer 28, such as... Figure 2P As shown.

[0093] Optionally, before filling the thermally conductive material into the groove 24, the following steps are also included:

[0094] A portion of the isolation layer 232 between the substrate 20 and the first diffusion barrier layer 233 is removed, forming an air gap 26 between the substrate 20 and the first diffusion barrier layer 233, as shown below. Figure 2M As shown.

[0095] Specifically, the formation of the air gap 26 effectively prevents the formation of a metal-oxide-semiconductor (MOS transistor) structure from the substrate 20, the isolation layer 232, and the conductive pillars 234. This prevents electrical signals in the conductive pillars 234 from coupling to the substrate 20 or devices surrounding the conductive pillars 234, reducing or even eliminating signal distortion and leakage current within the semiconductor structure, and reducing the static power consumption of the semiconductor structure. The air gap 26 also reduces the impact of thermal stress from the via structure on the active region.

[0096] Optionally, after forming the air gap 26 before filling the thermally conductive material into the groove 24, the method further includes:

[0097] A second diffusion barrier layer 27 is formed covering the inner wall of the groove 24. An air gap 26 is located between the substrate 20 and the first diffusion barrier layer 233, and the air gap 26 is located above the isolation layer 232 and below the second diffusion barrier layer 27. Figure 2O As shown.

[0098] Specifically, a physical vapor deposition process can be used to deposit materials such as TiN on the inner wall of the groove 24 to form the second diffusion barrier layer 27. The second diffusion barrier layer 27 is used to prevent particles in the subsequently formed heat dissipation layer 28 from diffusing into the substrate 20 and / or the via structure 23.

[0099] Optionally, the specific steps of filling the groove 24 with thermally conductive material include:

[0100] Spin-coating heat dissipation metal particles into the groove 24, specifically into the second diffusion barrier layer 27 on the inner wall of the groove 24.

[0101] Specifically, the metal particles include one or more of Ag particles, Au particles, Pt particles, Al particles, W particles, Cu particles, and Ru particles. The heat dissipation layer 28 fills the groove 24. Since the inner diameter of the groove 24 gradually increases along the direction from the substrate 20 to the dielectric layer 22, the diameter R of the formed heat dissipation layer 28 also gradually increases along the direction from the substrate 20 to the dielectric layer 22, that is, the heat dissipation layer 28 is generally inverted conical. The inverted conical heat dissipation layer 28 can dissipate the heat generated in the through-hole structure 23 upwards, avoiding the impact on the components around and at the bottom of the through-hole structure 23, and reducing the area occupied by the active region of the substrate 20, thereby improving the heat dissipation efficiency. In this specific embodiment, the diameter R of the heat dissipation layer 28 refers to the width of the heat dissipation layer 28 in the radial direction parallel to the through-hole structure 23.

[0102] Furthermore, this specific embodiment also provides a semiconductor structure, with attached... Figure 3 This is a schematic diagram of a semiconductor structure according to a specific embodiment of the present invention. The semiconductor structure provided in this specific embodiment can adopt, for example... Figure 1 , Figures 2A-2P The semiconductor structure shown is formed using the method described. Figure 3 As shown, the semiconductor structure includes:

[0103] Substrate 20;

[0104] Dielectric layer 22 is located on the substrate 20;

[0105] The through-hole structure 23 penetrates the dielectric layer 22 and the substrate 20;

[0106] A groove 24 is located within the dielectric layer 22. The groove 24 exposes the sidewall of the via structure 23, and the inner diameter of the groove 24 gradually increases along the direction from the substrate 20 to the dielectric layer 22.

[0107] The heat dissipation layer 28 is located inside the dielectric layer 22. The heat dissipation layer 28 is in direct contact with the sidewall of the through-hole structure 23, and the diameter R of the heat dissipation layer 28 gradually increases along the direction from the substrate 20 to the dielectric layer 22.

[0108] Optionally, the through-hole structure 23 includes:

[0109] The conductive pillar 234 penetrates the dielectric layer 22 and the substrate 20;

[0110] A first diffusion barrier layer 233 covers the sidewall surface of the conductive pillar 24.

[0111] Optionally, the heat dissipation layer 28 surrounds the outer periphery of the through-hole structure 23 and is in direct contact with the first diffusion barrier layer 233.

[0112] Optionally, the edge of the heat dissipation layer 28 away from the via structure 23 includes multiple steps stacked in a direction perpendicular to the surface of the substrate 20, and the step closer to the substrate 20 in two adjacent steps protrudes and extends toward the side closer to the via structure 23.

[0113] Optionally, the semiconductor structure further includes:

[0114] The second diffusion barrier layer 27 is located between the heat dissipation layer 28 and the dielectric layer 22.

[0115] Optionally, the semiconductor structure further includes:

[0116] An isolation layer 232 is located between the substrate 20 and the first diffusion barrier layer 233.

[0117] Optionally, the semiconductor structure further includes:

[0118] An air gap 26 is located between the substrate 20 and the first diffusion barrier layer 233, and the air gap 26 is located between the second diffusion barrier layer 27 and the isolation layer 232.

[0119] Optionally, the heat dissipation layer 28 is made of metal particles.

[0120] Optionally, the metal particles include one or more of Ag particles, Au particles, Pt particles, Al particles, W particles, Cu particles, and Ru particles.

[0121] The semiconductor structure and its formation method provided in this specific embodiment form a groove exposing the sidewalls of the via structure by etching the dielectric layer. The inner diameter of the groove gradually increases along the direction from the substrate to the dielectric layer, so that the subsequently formed heat dissipation layer is in direct contact with the via structure. The heat dissipation layer has an inverted conical structure. On the one hand, this facilitates the upward transfer of heat generated by the via structure, improving the heat dissipation efficiency of the via structure. On the other hand, since the heat dissipation layer exists only in the dielectric layer, it can effectively reduce the area occupied by the active region inside the substrate and reduce the stress and temperature effects of the via structure on surrounding components, thereby improving the performance of the semiconductor structure.

[0122] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate being covered with a dielectric layer on its surface; etching the dielectric layer and the substrate to form a via through the dielectric layer and the substrate; forming a first diffusion barrier layer covering the inner wall of the via; forming a conductive pillar filling the via and covering the surface of the first diffusion barrier layer to form a via structure comprising the via, the first diffusion barrier layer and the conductive pillar; etching the dielectric layer around the periphery of the via structure to form an initial sub-recess around the periphery of the via structure and exposing the sidewall of the via structure; performing at least one cycle of the following steps to form a recess exposing the sidewall of the via structure and gradually increasing in inner diameter along the substrate in the direction of the dielectric layer: etching the dielectric layer along the initial sub-recess to form a next sub-recess around the periphery of the via structure and exposing the sidewall of the via structure, the inner diameter of the next sub-recess being smaller than that of the initial sub-recess, and taking the initial sub-recess and the formed next sub-recess as the initial sub-recess of the next cycle of steps until the recess is formed, the recess comprising a plurality of sub-recesses stacked in the direction perpendicular to the surface of the substrate and connected to each other, and the inner diameter of the sub-recess closer to the substrate among two adjacent sub-recesses being smaller than that of the sub-recess farther from the substrate; filling the recess with a thermally conductive material to form a heat dissipation layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The specific step of etching the dielectric layer along the initial sub-recess comprises: forming an initial protective layer covering the sidewall and bottom of the initial sub-recess; etching the initial protective layer in the initial sub-recess and the dielectric layer below the initial sub-recess in the direction perpendicular to the substrate to form a next sub-recess around the periphery of the via structure and exposing the first diffusion barrier layer, the inner diameter of the next sub-recess being smaller than that of the initial sub-recess.

3. The method according to claim 1, wherein the via structure further comprises an isolation layer between the inner wall of the via and the first diffusion barrier layer, and the specific step of forming an initial sub-recess around the via structure comprises: etching the dielectric layer and the isolation layer around the periphery of the via structure to form an initial sub-recess around the periphery of the via structure and exposing the first diffusion barrier layer.

4. The method of forming a semiconductor structure of claim 3, wherein, The specific step of etching the dielectric layer along the initial sub-recess comprises: etching the dielectric layer and the isolation layer in part of the bottom of the initial sub-recess.

5. The method of forming a semiconductor structure of claim 3, wherein, Before filling the recess with a thermally conductive material, the method further comprises the following step: removing part of the isolation layer between the substrate and the first diffusion barrier layer to form an air gap between the substrate and the first diffusion barrier layer.

6. The method of forming a semiconductor structure of claim 1, wherein, Before filling the recess with a thermally conductive material, the method further comprises: forming a second diffusion barrier layer covering the inner wall of the recess.

7. The method of forming a semiconductor structure of claim 1, wherein, The specific step of filling the recess with a thermally conductive material comprises: spinning a thermally conductive metal particle in the recess.

8. A semiconductor structure, characterized by It comprises: a substrate; a dielectric layer on the substrate; a via structure penetrating through the dielectric layer and the substrate, the via structure comprising: a conductive pillar penetrating through the dielectric layer and the substrate, and a first diffusion barrier layer covering a sidewall surface of the conductive pillar; a recess located in the dielectric layer, the recess exposing a sidewall of the via structure, and an inner diameter of the recess gradually increasing in a direction from the substrate to the dielectric layer; a heat dissipation layer located in the dielectric layer, the heat dissipation layer directly contacting the sidewall of the via structure, and a diameter of the heat dissipation layer gradually increasing in a direction from the substrate to the dielectric layer, an edge of the heat dissipation layer away from the via structure comprising a plurality of levels of steps stacked in a direction perpendicular to a surface of the substrate, and a level of the steps closer to the substrate of two adjacent levels of the steps protruding and extending to a side closer to the via structure.

9. The semiconductor structure of claim 8, wherein: the heat dissipation layer surrounds an outer periphery of the via structure and directly contacts the first diffusion barrier layer.

10. The semiconductor structure of claim 8, wherein, Further comprising: a second diffusion barrier layer located between the heat dissipation layer and the dielectric layer.

11. The semiconductor structure of claim 10, wherein, Further comprising: an isolation layer located between the substrate and the first diffusion barrier layer.

12. The semiconductor structure of claim 11, wherein, Further comprising: an air gap located between the substrate and the first diffusion barrier layer, and the air gap being located between the second diffusion barrier layer and the isolation layer.

13. The semiconductor structure of claim 8, wherein: a material of the heat dissipation layer is a metal particle.

14. The semiconductor structure of claim 13, wherein: the metal particle comprises one of Ag particle, Au particle, Pt particle, Al particle, W particle, Cu particle, Ru particle, or a combination of two or more thereof.

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