Trench-type silicon carbide device and method of manufacturing the same

Abstract

Disclosed is a trench type silicon carbide device and a method for manufacturing the same. The method for manufacturing the trench type silicon carbide device includes forming a trench on a silicon carbide substrate, depositing a first oxide layer including silicon dioxide, and performing a densification process by introducing oxygen gas to react with the silicon carbide substrate to form silicon dioxide. The trench is filled to make the first oxide layer and the silicon carbide substrate more tightly combined and less likely to be separated from each other.

Description

Technical Field

[0001] This invention relates to silicon carbide devices, and more specifically, to trench-type silicon carbide devices. Background Technology

[0002] With the development of semiconductor materials, silicon carbide (SiC) materials have become increasingly popular due to their large bandgap, high thermal conductivity, and high saturated electron drift velocity. Because of these characteristics, SiC devices have performance limits that are far superior to those of silicon devices, and can meet the application requirements under harsh conditions such as high temperature, high frequency, and high power. In particular, trench SiC devices have further improved the high power performance of SiC devices.

[0003] However, unlike silicon substrates, the presence of carbon—specifically, silicon dangling bonds, carbon dangling bonds, or carbon-carbon bonds—results in a high density of interface states at the silicon dioxide / silicon carbide interface formed through thermal oxidation in trench silicon carbide devices. This density is more than two orders of magnitude higher than that of the silicon dioxide / silicon interface. This high density of silicon dioxide / silicon carbide interface states makes trench silicon carbide devices prone to delamination over long-term use, leading to failure of silicon carbide power semiconductor devices.

[0004] Therefore, there is a need for a trench-type silicon carbide device that has higher reliability. Summary of the Invention

[0005] One embodiment of the present invention provides a device structure including a trench, a first oxide layer, a conductive layer, a second oxide layer, a dielectric layer, and an insulating layer. The trench is formed in a silicon carbide substrate and has a lower surface and a side surface perpendicular to the lower surface. The first oxide layer, comprising silicon dioxide, covers the side surface of the trench and has a lower surface and an upper surface, wherein the lower surface contacts the silicon carbide substrate on the side surface of the trench. The conductive layer covers the silicon carbide substrate on the lower surface of the trench and the substrate support, and has a lower surface and an upper surface, wherein the lower surface contacts the silicon carbide substrate. The second oxide layer, comprising silicon dioxide, covers the upper surface of the first oxide layer and the upper surface of the conductive layer. The dielectric layer, comprising silicon nitride, covers the second oxide layer. The insulating layer, comprising borosilicate glass, covers the dielectric layer.

[0006] One embodiment of the present invention provides a method for filling trenches, the method comprising: forming trenches on a silicon carbide substrate; depositing a first oxide layer comprising silicon dioxide; and a densification process by introducing oxygen.

[0007] The junction field-effect transistor provided by the present invention, since oxygen is introduced after the formation of the first oxide layer, the oxygen reacts with the first oxide layer and the silicon carbide substrate to generate silicon dioxide, making the contact between the first oxide layer and the silicon carbide substrate tighter and less prone to separation, thus having higher reliability. Attached Figure Description

[0008] To better understand the present invention, embodiments thereof will be described with reference to the following accompanying drawings, which are for illustrative purposes only. The drawings typically show only some features of the embodiments and are not necessarily drawn to scale.

[0009] Figure 1 A schematic diagram of an existing silicon carbide device with trenches is given.

[0010] Figure 2 A schematic diagram of the structure of a trench-type silicon carbide device 200 according to an embodiment of the present invention is provided.

[0011] Figure 3 A schematic diagram of a trench field-effect transistor 300 according to an embodiment of the present invention is provided.

[0012] Figure 4 A schematic diagram of a trench field-effect transistor 400 according to another embodiment of the present invention is provided.

[0013] Figure 5 A flowchart of some steps of a method 500 for filling a trench according to an embodiment of the present invention is provided.

[0014] Figures 6A-6F The manufacturing process according to an embodiment of the present invention is shown as follows: Figure 2 A longitudinal cross-sectional schematic diagram of some steps in the trench-type device 200 shown.

[0015] Figure 7 The manufacturing process according to an embodiment of the present invention is shown as follows: Figure 4 The flowchart shows some steps of the method for making a trench field-effect transistor 400.

[0016] Figures 8A-8E A longitudinal cross-sectional schematic diagram of some steps in manufacturing a trench field-effect transistor 400 according to an embodiment of the present invention is provided.

[0017] The same reference numerals in different schematic diagrams indicate the same or similar parts or features. Detailed Implementation

[0018] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other embodiments, well-known circuits, materials, or methods have not been specifically described in order to avoid obscuring the invention.

[0019] In this specification and claims, the use of terms such as "left," "right," "inner," "outer," "upper," "lower," "above," and "below" is merely for descriptive convenience and does not indicate a necessary or permanent relative position of components / structures. Those skilled in the art should understand that such terms are interchangeable where appropriate, for example, so that embodiments of this disclosure can still operate in orientations different from those depicted in this specification. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, the term "coupled" means a connection, directly or indirectly, electrically or non-electrically. "A / this / that" is not used specifically to refer to the singular but may encompass the plural form. The phrases "an embodiment," "embodiment," "an example," and "example" appearing throughout the specification do not necessarily refer to the same embodiment or example. Those skilled in the art should understand that the various useful terms "and / or" disclosed in one or more embodiments of this disclosure include any and all combinations of one or more of the associated listed items.

[0020] Figure 1 A schematic diagram of an existing trench-equipped silicon carbide device is given. For example... Figure 1 As shown, trenches TH are typically formed on a silicon carbide substrate 10 using an etching process. The trenches TH have a lower surface S1 located in a recess and a side surface S2 perpendicular to the lower surface. In this application, the silicon carbide substrate 10 between the trenches is referred to as the keel MESA.

[0021] Figure 2 A schematic diagram of a trench-type silicon carbide device 200 according to an embodiment of the present invention is provided. Figure 2 As shown, the trench-type silicon carbide device 200 includes a silicon carbide substrate 10, and trench TH ( Figure 2 The trench TH is filled with multiple layers, making it impossible to clearly identify the specific structure of the trench TH. Please refer to [reference needed]. Figure 1 The trench shown (TH) includes a first oxide layer 101, a conductive layer 102, and a second oxide layer 103. Figure 2In this embodiment, a trench TH is formed in a silicon carbide substrate 10, and the trench TH has a lower surface S1 located in a recess and a side surface S2 perpendicular to the lower surface S1. In one embodiment, the trench TH is rectangular, having a lower surface S1 located in a rectangular recess and a side surface S2 perpendicular to the lower surface S1. A first oxide layer 101 covers the side surface S2 of the trench TH and is in close contact with the silicon carbide substrate 10 located on the side surface S2 of the trench TH. The first oxide layer 101 has a lower surface and an upper surface S3, the lower surface being in close contact with the silicon carbide substrate 10. In one embodiment, the first oxide layer 101 comprises silicon dioxide, and the thickness of the first oxide layer 101 is... Between. In another embodiment, the thickness of the first oxide layer 101 is... The conductive layer 102 is located on the silicon carbide substrate 10 on the lower surface S1 of the trench TH and on the keel MESA, wherein the silicon carbide substrate 10 between the trenches TH is referred to as the keel MESA. The conductive layer 102 has a lower surface and an upper surface S4, wherein the lower surface and the silicon carbide substrate 10 at the lower surface S1 of the trench TH are in close contact. In one embodiment, the conductive layer 102 is formed by depositing metal. In another embodiment, the conductive layer 102 is formed by depositing nickel. In one embodiment, the thickness of the conductive layer 102 is... Between. In another embodiment, the thickness of the conductive layer 102 is between. The second oxide layer 103 covers the upper surface S4 of the conductive layer 102 and the upper surface S3 of the first oxide layer 101. It should be noted that in some embodiments, vias exist in the second oxide layer 103 to connect the potential of the conductive layer 102 to the outside. In one embodiment, the second oxide layer 103 comprises silicon dioxide. In another embodiment, the thickness of the second oxide layer 103 is approximately... Within this range, the thickness of the second oxide layer 103 can effectively buffer the stress difference between the conductive layer 102 and the dielectric layer 104 (formed subsequently) caused by temperature changes. It should be noted that as the thickness of the second oxide layer 103 decreases, its effectiveness in buffering the stress difference between the conductive layer 102 and the dielectric layer 104 due to temperature changes diminishes, and the contact interfaces between the conductive layer 102 and the second oxide layer 103, as well as between the second oxide layer 103 and the dielectric layer 104, are prone to separation. In one embodiment, the first oxide layer 101 is formed before the conductive layer 102, and the second oxide layer 103 is formed after the conductive layer 102. Figure 2 As shown, the trench-type silicon carbide device 100 further includes a dielectric layer 104 and an insulating layer 105. The dielectric layer 104 covers the second oxide layer 103. In one embodiment, the dielectric layer 104 comprises silicon nitride. In one embodiment, the thickness of the dielectric layer 104 is... The thickness of the dielectric layer 104 is within this range. The stress difference between the dielectric layer 104 and the second oxide layer 103 caused by temperature changes is small, effectively preventing interlayer separation due to different stresses caused by temperature changes. This results in higher reliability for the trench silicon carbide device 100. It should be noted that as the thickness of the dielectric layer 104 increases, the stress difference between the dielectric layer 104 and the second oxide layer 103 caused by temperature changes increases, making separation at the contact interface between the second oxide layer 103 and the dielectric layer 104 more likely. The insulating layer 105 comprises borosilicate glass and covers the dielectric layer 104. Figure 2 In the illustrated embodiment, the dielectric layer 104 forms a recessed region T1, and the insulating layer 105 fills the recessed region T1. The upper surface of the dielectric layer 104 above the keel MESA is defined as the keel surface S5, meaning that the upper surface S6 of the insulating layer 105 and the keel surface S5 are on the same horizontal plane. It should be noted that, for ease of illustration, the recessed region T1 is... Figure 2 The recessed area T1 on the right side is not filled with insulating layer 105. In one embodiment, the thickness of insulating layer 105 is... Between. In another embodiment, the thickness of the insulating layer 105 is between. about.

[0022] Figure 3 A schematic diagram of a trench field-effect transistor 300 according to an embodiment of the present invention is provided. Figure 2 Compared to the trench-type silicon carbide device 200 shown, the trench-type field-effect transistor 300 further includes a source region 106, a gate region 107, a drain region 108, and a channel region 109. The source region 106 is located at the upper end of the keel MESA and is formed by ion implantation. Figure 3 In the illustrated embodiment, the source region 106 has a first conductivity type. The gate region 107 is located in the silicon carbide substrate 10 below the trench TH and in the silicon carbide substrate 10 on the trench TH side surface S2. Figure 3 In the illustrated embodiment, gate region 107 has a second conductivity type. Drain region 108, located in silicon carbide substrate 10, is... Figure 3 In the illustrated embodiment, the drain region 108 has the same first conductivity type as the source region 106. A channel region 109 is located in the silicon carbide substrate 10 between the source region 106 and the drain region 108. Figure 3 In the illustrated embodiment, the channel region 109 has a first conductivity type. When the gate region 107 receives a certain voltage, the channel region 109 provides a conduction path for the source region 106 and the drain region 108. In one embodiment, the trench field-effect transistor 300 further includes a drift region 110 located in the silicon carbide substrate 10 between the channel region 109 and the drain region 108. Figure 3In the illustrated embodiment, the drift region 110 has a first conductivity type, and the doping concentration of the drift region 110 is less than the doping concentration of the drain region 108.

[0023] Figure 4 A schematic diagram of a trench field-effect transistor 400 according to another embodiment of the present invention is provided. Figure 3 Compared to the trench field-effect transistor 300 shown, the trench field-effect transistor 400 has a different gate structure. Figure 4 In the illustrated embodiment, the gate region of the trench field-effect transistor 400 includes a first gate region 107a, a second gate region 107b, a third gate region 107c, and a gate extension region 111. The first gate region 107a is located on a first side of the keel MESA, the second gate region 107b is located on a second side of the keel MESA, and the third gate region 107c is located in the silicon carbide substrate 10 below the trench TH. In one embodiment, the first gate region 107a and the second gate region 107b are formed simultaneously using angular ion implantation, and the third gate region 107c is formed using vertical ion implantation. The gate extension region 111 is located between the second gate region 107b and the channel region 109, extending from the second gate region 107b through the keel MESA to the channel region 109. Both the gate extension region 111 and the second gate region 107b have a second conductivity type, and the doping concentration of the gate extension region 111 is less than that of the second gate region 107b. The trench field-effect transistor 400 includes a source region 106, a drain region 108, and a channel region 109. The source region 106 is located at the upper end of the MESA (Mesh Anode), the drain region 108 is located at the bottom of the silicon carbide substrate 10, and the channel region 109 is located in the silicon carbide substrate 10 between the source region 106 and the drain region 108. When the gate region receives a certain voltage, the channel region 109 provides a conduction path for the source region 106 and the drain region 108. Figure 4 In the illustrated embodiment, the trench field-effect transistor 400 further includes a drift region 110, which is located between the channel region 109 and the drain region 108. It should be noted that, as... Figure 8E As shown, the first gate region 107a and the third gate region 107c, the second gate region 107b and the third gate region 107c have a certain physical overlap. The dashed lines in the figure are used to indicate the division.

[0024] Figure 5 A partial flowchart of a method 500 for filling a trench according to an embodiment of the present invention is provided. Method 500 includes steps ST1-ST3.

[0025] Step ST1: Form trenches on a silicon carbide substrate;

[0026] Step ST2: Forming the first oxide layer; and

[0027] Step ST3: The densification process by introducing oxygen.

[0028] In one embodiment, method 500 further includes subsequent steps ST4-ST7 for forming a silicon carbide device.

[0029] Step ST4: Form a conductive layer;

[0030] Step ST5: Formation of the second oxide layer;

[0031] Step ST6: Forming a dielectric layer; and

[0032] Step ST7: Form an insulating layer.

[0033] Figures 6A-6F The manufacturing process according to an embodiment of the present invention is shown as follows: Figure 2 A longitudinal cross-sectional schematic diagram of some steps in the trench-type device 200 shown.

[0034] refer to Figure 6A This section describes step ST1 of method 500, which involves forming a trench TH on a silicon carbide substrate 10. In one embodiment, the trench TH is etched into the silicon carbide substrate 10 using an etching method. In the illustrated embodiment, the trench TH is etched using a dry etching process. The trench TH has a lower surface S1 located at a recess in the trench TH and a side surface S2 perpendicular to the lower surface S1. In one embodiment, the trench TH is rectangular, having a lower surface S1 located at a recess and a side surface S2 perpendicular to the lower surface S1 (i.e., the sidewalls of the trench TH). The silicon carbide substrate 10 typically has a first conductivity type or a second conductivity type. In this application, the silicon carbide substrate 10 between the trench THs is referred to as the keel MESA.

[0035] refer to Figure 6B The following describes step ST2 of method 600, which involves forming a first oxide layer 101. In one embodiment, the first oxide layer 101 is formed by chemical vapor deposition, and the first oxide layer 101 comprises silicon dioxide. In one embodiment, the thickness of the first oxide layer 101 is... Between. In another embodiment, the thickness of the first oxide layer 101 is between. Left and right. It should be noted that step ST2, forming the first oxide layer 101, specifically includes multiple process steps, such as photolithography. In one embodiment, step ST2 includes forming an oxide layer by depositing it on the surface of the silicon carbide substrate 10, and then performing photolithography on the oxide layer to form the desired first oxide layer 101. Figure 6B In the embodiment shown, after the photolithography process, a first oxide layer 101 covers the side surface S2 of the trench TH.

[0036] Continue to refer to Figure 6BThe densification process of introducing oxygen in step ST3 of method 600 is described below. In one embodiment, in step ST3, the introduced oxygen can pass through the first oxide layer 101 to reach the surface of the silicon carbide substrate 10 and react chemically with the silicon carbide substrate 10 to form silicon dioxide (i.e., a dense layer). The presence of the silicon dioxide dense layer improves the surface adhesion between the first oxide layer 101 and the silicon carbide substrate 10, making separation at the interface less likely. In one embodiment, the oxygen densification process is carried out at a temperature of 1100-1200 degrees Celsius, resulting in a fast oxidation rate and short time. The first oxide layer 101 has a lower surface and an upper surface S3, the lower surface of which contacts the silicon carbide substrate 10 on the trench TH side surface S2.

[0037] refer to Figure 6C The following describes step ST4 of method 500, which involves forming a conductive layer 102. In one embodiment, the conductive layer 102 is formed by deposition. In another embodiment, the conductive layer 102 is formed by depositing metallic nickel. In one embodiment, forming the conductive layer 102 includes... Figure 6B A layer of metal is deposited on the structure shown, and the metal reacts with the silicon carbide substrate 10 to form a metal silicide. For example... Figure 6C In the illustrated embodiment, a conductive layer 102 is formed on the silicon carbide substrate 10 at the bottom of the trench TH and on the keel MESA. The conductive layer 102 has a lower surface and an upper surface S4, wherein the lower surface is in contact with the silicon carbide substrate 10.

[0038] refer to Figure 6D The following describes step ST5 of method 500, which involves forming the second oxide layer 103. In one embodiment, the second oxide layer 103 is formed by deposition on the conductive layer 102 and the upper surface S3 of the first oxide layer 101. In one embodiment, the thickness of the second oxide layer 103 is... Within this range, the thickness of the second oxide layer 103 can effectively buffer the stress difference between the conductive layer 102 and the dielectric layer 104 (formed subsequently) caused by temperature changes. It should be noted that when the thickness of the second oxide layer 103 decreases, it cannot effectively buffer the stress difference between the conductive layer 102 and the dielectric layer 104 caused by temperature changes, and the contact interfaces between the second oxide layer 103 and the conductive layer 102, and between the second oxide layer 103 and the dielectric layer 104, are prone to separation.

[0039] refer to Figure 6E The following describes step ST6 of method 500, which involves forming the dielectric layer 104. In one embodiment, the dielectric layer 104 is formed by deposition on the second oxide layer 103. In one embodiment, the thickness of the dielectric layer 104 is... Within this range, the thickness of the dielectric layer 104 exhibits minimal stress variation with temperature, effectively preventing interlayer separation between the dielectric layer 104 and the second oxide layer 103 due to stress differences during temperature changes. This results in higher reliability for the trench-type silicon carbide device 200. It is important to note that as the thickness of the dielectric layer 104 increases, the stress variation with temperature also increases, making the interface between the dielectric layer 104 and the second oxide layer 103 more prone to separation. The dielectric layer 104 forms a recessed structure T1, and the upper surface of the dielectric layer 104 above the MESA is defined as the MESA surface S5.

[0040] refer to Figure 6F The following describes step ST7 of method 500, which involves forming an insulating layer 105. In one embodiment, the insulating layer 105 comprises borosilicate glass. In one embodiment, by... Figure 6E An insulating layer 105 is deposited on the structure shown, the insulating layer 105 having an upper surface S6. The insulating layer 105 is used to fill the recessed structure T1, that is, the upper surface S6 of the insulating layer 105 and the keel surface S5 are located on the same horizontal plane. In one embodiment, the thickness of the insulating layer 105 is... Between. In another embodiment, the thickness of the insulating layer 105 is between. about.

[0041] It should be noted that steps ST1-ST7 only list some key steps to illustrate the process of filling the trench TH in the trench device 200. When forming a trench field-effect transistor, different field-effect transistors may require different steps due to their different structures. Some steps are interspersed between steps ST1-ST7.

[0042] Figure 7 The manufacturing process according to an embodiment of the present invention is shown as follows: Figure 4 The flowchart shows the method for manufacturing a trench field-effect transistor 400. Figure 5 Compared to the method shown, Figure 7 The method shown also includes the step STA-STD.

[0043] Step STA: Forming the gate extension region;

[0044] Step STB: Formation of the source region;

[0045] Step STC: Forming the channel region; and

[0046] Step STD: Form the gate region.

[0047] Figures 8A-8D A longitudinal cross-sectional schematic diagram of some steps in manufacturing a trench field-effect transistor 400 according to an embodiment of the present invention is provided.

[0048] refer to Figure 8A The step STA, forming the gate extension region 111, will be described below. Figure 8A As shown, a gate extension region 111 is formed on a silicon carbide substrate 10, which includes an initial substrate 108 and a drift region 110. The initial substrate 108 has a first conductivity type (N-type, used to form the drain region of a trench field-effect transistor 400), the drift region 110 has a first conductivity type, and the doping concentration of the drift region 110 is less than that of the initial substrate 108. In one embodiment, the drift region 110 is formed by a long epitaxial layer on the initial substrate 108. In one embodiment, the gate extension region 111 is formed on the upper surface of the drift region 110 by ion implantation. In the illustrated embodiment, the gate extension region 111 is of a second conductivity type (P-type) and is located above the drift region 110.

[0049] refer to Figure 8B The step STB, forming source region 106, is described below. In one embodiment, source region 106 is formed over gate extension region 111 by ion implantation, and source region 106 has a first conductivity type. In the illustrated embodiment, source 108 has a first conductivity type (N-type).

[0050] refer to Figure 8C The following describes step ST1, forming the trench TH. In one embodiment, the trench TH is etched into the drift region 110 using an etching method. In the illustrated embodiment, the trench TH is etched using a dry etching process.

[0051] refer to Figure 8D The step STC, which involves forming a channel region 109 using ion implantation, is described below. In the illustrated embodiment, an N-type channel region 109 is formed using ion implantation.

[0052] refer to Figure 8E The step STD, which involves forming a gate region using ion implantation, is described below. In the illustrated embodiment, the gate region includes a first gate region 107a, a second gate region 107b, and a third gate region 107c. The first gate region 107a is located on the first side of the keel MESA, the second gate region 107b is located on the second side of the keel MESA, and the third gate region 107c is located in the silicon carbide substrate 10 below the trench TH. In one embodiment, the first gate region 107a and the second gate region 107b are formed simultaneously using ion implantation at a certain angle. The third gate region 107c is formed using vertical ion implantation. It should be noted that, as... Figure 8E As shown, the first gate region 107a and the third gate region 107c, the second gate region 107b and the third gate region 107c have a certain physical overlap. The dashed lines in the figure are only for illustration.

[0053] It should be noted that, Figure 7 Only some key steps are listed to illustrate the formation process of the trench field-effect transistor 400. The fabrication process of silicon carbide devices is extremely complex, for example... Figure 7 The annealing process and the subsequent metal interconnect process required to connect the source region 106, drain region 108, and gate region 107 of the trench field-effect transistor 400 to the outside are not illustrated, but some standard process flows that should be known to those skilled in the art can be included in this invention. For example, the rapid annealing process is not shown in the figure, but the actual process includes multiple rapid annealing steps. In one embodiment, rapid annealing includes a first rapid annealing and a second rapid annealing. In one embodiment, rapid annealing includes a first rapid annealing and a second rapid annealing, wherein the first rapid annealing is performed at a temperature of 600°C-700°C for about 1 minute. The second rapid annealing is performed at a temperature of 1050°C for about 3 minutes.

[0054] The trench-type silicon carbide device of the present invention, on the one hand, achieves a tighter bond between the silicon carbide surface and the oxide layer by oxidizing the oxygen layer through the oxygen flow, thus preventing separation between the oxide layer and the silicon carbide surface. On the other hand, by controlling the thickness of the first oxide layer and the passivation layer, the stress difference caused by temperature changes is mitigated, preventing interlayer separation. Therefore, the trench-type device of the present invention is less prone to interlayer separation and has higher reliability.

[0055] The specific embodiments described above are merely exemplary illustrations of the high-voltage devices and manufacturing methods of the present invention. These embodiments are not exhaustive and are not intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit of the invention and the scope of protection defined by the claims.

Claims

1. A device structure, comprising: A trench is formed in a silicon carbide substrate, the trench having a lower surface and a side surface perpendicular to the lower surface; A first oxide layer, including silicon dioxide, covers the side surface of the trench. The first oxide layer has a lower surface and an upper surface, wherein the lower surface is in contact with the silicon carbide substrate on the side of the trench. A conductive layer is applied to the silicon carbide substrate on the lower surface of the trench and to the keel. The conductive layer has a lower surface and an upper surface, wherein the lower surface is in contact with the silicon carbide substrate. The second oxide layer, including silicon dioxide, covers the upper surface of the first oxide layer and the upper surface of the conductive layer; A dielectric layer, comprising silicon nitride, is overlaid on a second oxide layer; as well as An insulating layer, including borosilicate glass, covers the dielectric layer.

2. The device structure as claimed in claim 1, wherein the thickness of the second oxide layer is between 600 Å and 1300 Å.

3. The device structure as described in claim 1, wherein the thickness of the dielectric layer is between 1700 Å and 2900 Å.

4. The device structure of claim 1, wherein the conductive layer comprises a metal silicide.

5. The device structure as described in claim 1, further comprising: The source area is located at the upper end of the keel area; The gate region is located in the silicon carbide substrate below the trench and in the silicon carbide substrate in contact with the trench side surface; The drain region is located at the bottom of the silicon carbide substrate; as well as The channel region, located below the source region, provides a conduction path for the drain and source regions when the gate region receives a certain voltage.

6. The device structure of claim 5 further includes a drift region located between the channel region and the drain region.

7. The device structure as described in claim 1, further comprising: The source area is located at the upper end of the keel area; The gate region includes a first gate region, a second gate region, a third gate region, and a gate extension region, wherein the first gate region is located in a first side of the keel, the second gate region is located in a second side of the keel, the third gate region is located in a silicon carbide substrate below the trench, and the gate extension region extends from the second gate region through the keel to the trench region. The drain region is located at the bottom of the silicon carbide substrate; as well as The channel region, located below the source region, provides a conduction path for the drain and source regions when the gate region receives a certain voltage.

8. The device structure of claim 7 further includes a drift region located between the channel region and the drain region.

9. A method for filling a trench, the method comprising: Trenches are formed on a silicon carbide substrate; A first oxide layer is deposited to form silicon dioxide; During the densification process, oxygen is introduced. Metal is deposited to form a conductive layer; A second oxide layer is deposited to form silicon dioxide; A dielectric layer is deposited to form a dielectric layer comprising silicon nitride; and An insulating layer is deposited, the insulating layer comprising borosilicate glass.

10. The method for filling trenches as claimed in claim 9, wherein oxygen undergoes an oxidation reaction through the first oxide layer and the silicon carbide substrate.

11. The method for filling trenches as described in claim 9, wherein the thickness of the second oxide layer is 600 Å to 1300 Å.

12. The method for filling trenches as described in claim 9, wherein the thickness of the dielectric layer is between 1700 Å and 2900 Å.

13. The method for filling a trench as described in claim 9, further comprising: A gate extension region is formed on a silicon carbide substrate; Formation of source region; Formation of a channel area; as well as A gate region is formed, comprising a first gate region, a second gate region, and a third gate region, wherein the first gate region is located in the first side of the keel, the second gate region is located in the second side of the keel, and the third gate region is located in the silicon carbide substrate below the trench.

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