Short-circuit protection circuit of the chip

Abstract

The present disclosure relates to the field of circuit technologies, and particularly to a short-circuit protection circuit for a chip, including: a charge pump module, a voltage comparison module, a programmable clock generation module, and a short-circuit protection control module; the charge pump module is configured to output a positive charge pump voltage signal through a first output terminal of the charge pump module, and output a negative charge pump voltage signal through a second output terminal of the charge pump module; the short-circuit protection control module is configured to output a first control signal through an output terminal of the short-circuit protection control module in response to that the logical value of at least one of a first digital detection signal and a second digital detection signal is 1 for a time greater than or equal to a preset duration, and the first control signal is used to control the programmable clock generation module to set the signal frequency of a clock signal to a first target frequency. When a short circuit occurs at an output terminal of the chip, a lower operating frequency is provided for the charge pump, so that the output current of the charge pump is reduced, thereby reducing the thermal effect during chip short circuit and improving the reliability of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technologies, and particularly to a short - circuit protection circuit for a chip. Background Art

[0002] A charge pump, also known as a switched - capacitor voltage converter, is a converter that stores energy using "flying" or "pumping" capacitors (instead of inductors or transformers), and is widely used in micro - energy harvesting chips, such as RS232 chips with charge pumps.

[0003] Generally, for an RS232 chip with a charge pump, the output terminal of the RS232 chip is connected to an external interface. When the RS232 chip is under operations such as hot - plugging, it often causes a short - circuit at the output terminal of the RS232 chip. Since the RS232 chip has a built - in charge pump circuit, when a short - circuit occurs at the output terminal of the RS232 chip, the charge pump operates in a high - frequency scenario, causing the output current of the charge pump to increase. As a result, the components of the chip will get hot or even damaged due to long - term output of excessive current, and then the chip fails. Summary of the Invention

[0004] To solve the problems in the related technologies, an embodiment of the present disclosure provides a short - circuit protection circuit for a chip.

[0005] In a first aspect, an embodiment of the present disclosure provides a short - circuit protection circuit for a chip.

[0006] Specifically, the short - circuit protection circuit includes: a charge pump module, a voltage comparison module, a programmable clock generation module, and a short - circuit protection control module;

[0007] A first output terminal of the charge pump module is connected to a first input terminal of the voltage comparison module, and a second output terminal of the charge pump module is connected to a second input terminal of the voltage comparison module. The charge pump module is configured to output a positive charge pump voltage signal through the first output terminal of the charge pump module and output a negative charge pump voltage signal through the second output terminal of the charge pump module;

[0008] A first output terminal of the voltage comparison module is connected to a first input terminal of the programmable clock generation module, and a second output terminal of the voltage comparison module is connected to a second input terminal of the programmable clock generation module. The voltage comparison module is configured to output a first digital detection signal through the first output terminal of the voltage comparison module in response to the positive charge pump voltage signal being greater than or equal to a first signal threshold, and output a second digital detection signal through the second output terminal of the voltage comparison module in response to the negative charge pump voltage signal being less than or equal to a second signal threshold;

[0009] The output terminal of the programmable clock generation module is connected to the input terminal of the charge pump module, and the third input terminal of the programmable clock generation module is connected to the output terminal of the short - circuit protection control module. The programmable clock generation module is used to output a clock signal through the output terminal of the programmable clock generation module, and the clock signal is used to control the operating frequency of the charge pump module;

[0010] The first input terminal of the short - circuit protection control module is connected to the first output terminal of the voltage comparison module, and the second input terminal of the short - circuit protection control module is connected to the second output terminal of the voltage comparison module. The short - circuit protection control module is used to respond that the time when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 is greater than or equal to a preset duration, and output a first control signal through the output terminal of the short - circuit protection control module. The first control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency.

[0011] In an implementation manner of the embodiment of the present disclosure, the short - circuit protection control module is used to respond that the time when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 is less than the preset duration, and output a second control signal through the output terminal of the short - circuit protection control module. The second control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a second target frequency, and the second target frequency is greater than the first target frequency.

[0012] In an implementation manner of the embodiment of the present disclosure, the short - circuit protection control module is used to respond that the logical values of the first digital detection signal and the second digital detection signal are both 0, and output the third control signal through the output terminal of the short - circuit protection control module. The third control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a third target frequency, and the third target frequency is greater than the first target frequency.

[0013] In an implementation manner of the embodiment of the present disclosure, the short - circuit protection control module includes: a first circuit unit, a second circuit unit, and a third circuit unit;

[0014] The input terminal of the first circuit unit is connected to the first output terminal of the voltage comparison module, the first output terminal of the first circuit unit is connected to the first input terminal of the third circuit unit, and the second output terminal of the first circuit unit is connected to the second input terminal of the third circuit unit;

[0015] The input end of the second circuit unit is connected to the second output end of the voltage comparison module. The first output end of the second circuit unit is connected to the third input end of the third circuit unit, and the second output end of the second circuit unit is connected to the fourth input end of the third circuit unit;

[0016] The output end of the third circuit unit is connected to the third input end of the programmable clock generation module.

[0017] In an implementation manner of the embodiment of the present disclosure, the first circuit unit is composed of N first flip - flops;

[0018] Among the N first flip - flops, one data latch output end of the i - th first flip - flop is connected to the data input end of the (i + 1) - th first flip - flop. The data input end of the first first flip - flop and the set ends of the N first flip - flops are both connected to the first output end of the voltage comparison module, where i≥1;

[0019] Among the N first flip - flops, the data input end of the last first flip - flop is connected to the first input end of the third circuit unit, and one data latch output end of the last first flip - flop is connected to the second input end of the third circuit unit.

[0020] In an implementation manner of the embodiment of the present disclosure, the second circuit unit is composed of N second flip - flops;

[0021] Among the N second flip - flops, one data latch output end of the j - th second flip - flop is connected to the data input end of the (j + 1) - th second flip - flop. The data input end of the first second flip - flop and the set ends of the N second flip - flops are both connected to the second output end of the voltage comparison module, where j≥1;

[0022] Among the N second flip - flops, the data input end of the last second flip - flop is connected to the third input end of the third circuit unit, and one data latch output end of the last second flip - flop is connected to the fourth input end of the third circuit unit.

[0023] In an implementation manner of the embodiment of the present disclosure, the third circuit unit includes a first AND gate, a second AND gate, and a NAND gate;

[0024] The first AND gate is respectively connected to the data input end of the last first flip - flop and one data latch output end of the last first flip - flop;

[0025] The second AND gate is respectively connected to the data input end of the last second flip - flop and one data latch output end of the last second flip - flop;

[0026] The NAND gate is respectively connected to the output end of the first AND gate and the output end of the second AND gate, and the output end of the NAND gate is connected to the third input end of the programmable clock generation module.

[0027] In an implementation manner of the embodiment of the present disclosure, the short-circuit protection control module further includes: a fourth circuit unit;

[0028] The first input end of the fourth circuit unit is connected to the output end of the programmable clock generation module, the second input end of the fourth circuit unit inputs a chip startup signal, and the fourth circuit unit is configured to divide the clock signal output through the output end of the programmable clock generation module in response to the logic value of the chip startup signal being 1 to obtain a divided clock signal, and output the divided clock signal through the output end of the fourth circuit unit.

[0029] In an implementation manner of the embodiment of the present disclosure, the clock input end of each of the N first flip-flops is connected to the output end of the fourth circuit unit, and the preset duration is determined according to the number of the N first flip-flops and the period of the divided clock signal.

[0030] In an implementation manner of the embodiment of the present disclosure, the clock input end of each of the N second flip-flops is connected to the output end of the fourth circuit unit, and the preset duration is determined according to the number of the N second flip-flops and the period of the divided clock signal.

[0031] In a second aspect, an embodiment of the present disclosure provides an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the method as described in the first aspect and any implementation manner of the first aspect.

[0032] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the method as described in the first aspect and any implementation manner of the first aspect is implemented.

[0033] According to the short - circuit protection circuit of a chip provided by an embodiment of the present disclosure, it includes a charge pump module, a voltage comparison module, a programmable clock generation module, and a short - circuit protection control module; the first output terminal of the charge pump module is connected to the first input terminal of the voltage comparison module, and the second output terminal of the charge pump module is connected to the second input terminal of the voltage comparison module. The charge pump module is used to output a positive charge pump voltage signal through the first output terminal of the charge pump module and output a negative charge pump voltage signal through the second output terminal of the charge pump module; the first output terminal of the voltage comparison module is connected to the first input terminal of the programmable clock generation module, and the second output terminal of the voltage comparison module is connected to the second input terminal of the programmable clock generation module. The voltage comparison module is used to output a first digital detection signal through the first output terminal of the voltage comparison module in response to the positive charge pump voltage signal being greater than or equal to a first signal threshold, and output a second digital detection signal through the second output terminal of the voltage comparison module in response to the negative charge pump voltage signal being less than or equal to a second signal threshold; the output terminal of the programmable clock generation module is connected to the input terminal of the charge pump module, and the third input terminal of the programmable clock generation module is connected to the output terminal of the short - circuit protection control module. The programmable clock generation module is used to output a clock signal through the output terminal of the programmable clock generation module, and the clock signal is used to control the operating frequency of the charge pump module; the first input terminal of the short - circuit protection control module is connected to the first output terminal of the voltage comparison module, and the second input terminal of the short - circuit protection control module is connected to the second output terminal of the voltage comparison module. The short - circuit protection control module is used to output a first control signal through the output terminal of the short - circuit protection control module in response to the time when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 being greater than or equal to a preset duration. The first control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency. Through this short - circuit protection circuit, when a short - circuit occurs at the output terminal of the chip, that is, if the time when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 is greater than or equal to a preset duration, a first control signal is output through the output terminal of the short - circuit protection control module to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency. Since the first target frequency is much lower than the operating frequency of the charge pump when a short - circuit occurs at the output terminal of the chip, the programmable clock generation module can provide a lower operating frequency for the charge pump, so that the output current of the charge pump decreases, thus reducing the system thermal effect when the chip is short - circuited and improving the reliability of the chip.

[0034] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0035] In conjunction with the accompanying drawings, through the following detailed description of non-limiting embodiments, other features, objectives, and advantages of the present disclosure will become more apparent. In the drawings...

[0036] Figure 1 Fig. 1 shows one of the schematic structural diagrams of the short-circuit protection circuit of a chip according to an embodiment of the present disclosure.

[0037] Figure 2 Fig. 2 shows another schematic structural diagram of the short-circuit protection circuit of a chip according to an embodiment of the present disclosure.

[0038] Figure 3 Fig. 3 shows yet another schematic structural diagram of the short-circuit protection circuit of a chip according to an embodiment of the present disclosure.

[0039] Figure 4 Fig. 4 shows a schematic diagram of signal timing changes according to an embodiment of the present disclosure. Detailed Embodiments

[0040] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for clarity, parts unrelated to the description of the exemplary embodiments are omitted in the drawings.

[0041] In the present disclosure, it should be understood that terms such as "including" or "having" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0042] In addition, it should be noted that, without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other. The present disclosure will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0043] In the present disclosure, if it involves operations of obtaining user information or user data or operations of presenting user information or user data to others, such operations are all operations authorized, confirmed, or actively selected by the user.

[0044] As mentioned above, a charge pump, also known as a switched-capacitor voltage converter, is a converter that stores energy using "flying" or "pumping" capacitors (instead of inductors or transformers) and is widely used in micro energy harvesting chips, such as RS232 chips with charge pumps.

[0045] Generally, for an RS232 chip with a charge pump, the output terminal of the RS232 chip is connected to an external interface. When the RS232 chip is under operations such as hot plugging, it often causes a short circuit at the output terminal of the RS232 chip. Since the RS232 chip has a built-in charge pump circuit, when a short circuit occurs at the output terminal of the RS232 chip, the charge pump operates in a high-frequency scenario, causing the output current of the charge pump to increase. As a result, due to the long-term output of excessive current, the components of the chip will become hot or even damaged, leading to chip failure.

[0046] Based on the above technical deficiencies, the short-circuit protection circuit of the chip provided by the embodiments of the present disclosure includes a charge pump module, a voltage comparison module, a programmable clock generation module, and a short-circuit protection control module; a first output end of the charge pump module is connected to a first input end of the voltage comparison module, and a second output end of the charge pump module is connected to a second input end of the voltage comparison module. The charge pump module is configured to output a positive charge pump voltage signal through the first output end of the charge pump module and output a negative charge pump voltage signal through the second output end of the charge pump module; a first output end of the voltage comparison module is connected to a first input end of the programmable clock generation module, and a second output end of the voltage comparison module is connected to a second input end of the programmable clock generation module. The voltage comparison module is configured to output a first digital detection signal through the first output end of the voltage comparison module in response to the positive charge pump voltage signal being greater than or equal to a first signal threshold, and output a second digital detection signal through the second output end of the voltage comparison module in response to the negative charge pump voltage signal being less than or equal to a second signal threshold; an output end of the programmable clock generation module is connected to an input end of the charge pump module, and a third input end of the programmable clock generation module is connected to an output end of the short-circuit protection control module. The programmable clock generation module is configured to output a clock signal through the output end of the programmable clock generation module, and the clock signal is used to control the operating frequency of the charge pump module; a first input end of the short-circuit protection control module is connected to the first output end of the voltage comparison module, and a second input end of the short-circuit protection control module is connected to the second output end of the voltage comparison module. The short-circuit protection control module is configured to output a first control signal through the output end of the short-circuit protection control module in response to the logical value of at least one of the first digital detection signal and the second digital detection signal being 1 for a time greater than or equal to a preset duration, and the first control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency. Through this short-circuit protection circuit, when a short circuit occurs at the output end of the chip, that is, if the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 for a time greater than or equal to a preset duration, a first control signal is output through the output end of the short-circuit protection control module to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency. Since the first target frequency is much lower than the operating frequency of the charge pump when a short circuit occurs at the output end of the chip, the programmable clock generation module can provide a lower operating frequency for the charge pump, so that the output current of the charge pump is reduced, thereby reducing the system thermal effect during chip short circuit and improving the reliability of the chip.

[0047] Figure 1 FIG. shows a schematic structural diagram of a short-circuit protection circuit of a chip according to an embodiment of the present disclosure. AsFigure 1 As shown, the short - circuit protection circuit includes: a charge pump module 101, a voltage comparison module 102, a programmable clock generation module 103, and a short - circuit protection control module 104.

[0048] Among them, the first output terminal of the charge pump module 101 is connected to the first input terminal of the voltage comparison module 102, and the second output terminal of the charge pump module 101 is connected to the second input terminal of the voltage comparison module 102. The charge pump module 101 is used to output a positive charge pump voltage signal through the first output terminal of the charge pump module 101, and output a negative charge pump voltage signal through the second output terminal of the charge pump module 101.

[0049] Among them, the first output terminal of the voltage comparison module 102 is connected to the first input terminal of the programmable clock generation module 103, and the second output terminal of the voltage comparison module 102 is connected to the second input terminal of the programmable clock generation module 103. The voltage comparison module 102 is used to respond to the positive charge pump voltage signal being greater than or equal to a first signal threshold, and output a first digital detection signal through the first output terminal of the voltage comparison module 102, and respond to the negative charge pump voltage signal being less than or equal to a second signal threshold, and output a second digital detection signal through the second output terminal of the voltage comparison module 102.

[0050] Among them, the output terminal of the programmable clock generation module 103 is connected to the input terminal of the charge pump module 101, and the third input terminal of the programmable clock generation module 103 is connected to the output terminal of the short - circuit protection control module 104. The programmable clock generation module 103 is used to output a clock signal through the output terminal of the programmable clock generation module 103, and the clock signal is used to control the operating frequency of the charge pump module 101.

[0051] Among them, the first input terminal of the short - circuit protection control module 104 is connected to the first output terminal of the voltage comparison module 102, and the second input terminal of the short - circuit protection control module 104 is connected to the second output terminal of the voltage comparison module 102. The short - circuit protection control module 104 is used to respond to the time when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 being greater than or equal to a preset duration, and output a first control signal through the output terminal of the short - circuit protection control module 104. The first control signal is used to control the programmable clock generation module 103 to set the signal frequency of the clock signal to a first target frequency.

[0052] In an embodiment of the present disclosure, the charge pump module 101 can be understood as a charge pump circuit, and the type of this charge pump circuit is not limited in the embodiments of the present disclosure.

[0053] In an embodiment of the present disclosure, the voltage comparison module 102 can be understood as a voltage comparator. For details, reference can be made to the related art, and the embodiments of the present disclosure do not limit this.

[0054] In an embodiment of the present disclosure, the positive charge pump voltage signal and the negative charge pump voltage signal can be understood as analog signals. Through the voltage comparison module 102, the charge pump voltage signal can be compared with the reference voltage signal to obtain a first digital detection signal and a second digital detection signal, that is, the first digital detection signal and the second digital detection signal are 0 or 1. That is, the first signal threshold and the second signal threshold, as the reference voltage signal, can be preset.

[0055] In an embodiment of the present disclosure, the short - circuit protection circuit may further include a resistor. After the positive charge pump voltage signal and the negative charge pump voltage signal are divided by the resistor, they are respectively input to the first input terminal and the second input terminal of the voltage comparison module 102.

[0056] In an embodiment of the present disclosure, the preset duration is a preset duration. For example, the preset duration is 120 ms.

[0057] Exemplarily, taking the preset duration as 120 ms and the first target frequency as 125 kHz as an example. Combining the above Figure 1 , the programmable clock generation module 103 includes three input control signals: the first digital detection signal VP_det, the second digital detection signal VN_det, and the first control signal Short_Enb1. For VP_det, VN_det, Short_Enb1, and the first target frequency, there are the following 3 possible situations, as shown in Table 1 below:

[0058] Table 1

[0059]

[0060] In this way, when a short - circuit occurs in the chip including the charge pump module 101, the output current of the charge pump module 101 increases. Therefore, the charge pump module 101 continuously operates at a high frequency. That is, as long as the time when at least one of the logic values of VP_DET and VN_DET is 1 is greater than or equal to 120 ms, the first control signal Short_Enb1 output by the output terminal of the short - circuit protection control module is 0. It should be noted that when the first control signal is output by the output terminal of the short - circuit protection control module, it indicates that the short - circuit protection function of the short - circuit protection control module is enabled, thereby triggering the signal frequency of the clock signal CLK generated by the programmable clock generation module to be 125 Khz (i.e., the first target frequency).

[0061] It should be noted that the first target frequency is less than the operating frequency of the charge pump module when the short - circuit protection function of the short - circuit protection control module is not enabled when a short - circuit occurs at the output end of the chip (for example, 400 KHz). Thus, when the chip is short - circuited, the charge pump operates at a frequency of 125 KHz. In this way, compared with the charge pump operating at 400 KHz when the chip is short - circuited, the output current of the charge pump operating at 125 KHz is reduced, that is, by enabling the short - circuit protection control module, the current consumed when the chip is short - circuited is smaller.

[0062] The embodiment of the present disclosure provides a short - circuit protection circuit for a chip. When a short - circuit occurs at the output end of the chip, that is, if the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 for a time greater than or equal to a preset duration, a first control signal is output through the output end of the short - circuit protection control module to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency. Since the first target frequency is much less than the operating frequency of the charge pump when a short - circuit occurs at the output end of the chip, the programmable clock generation module can provide a lower operating frequency for the charge pump, so that the output current of the charge pump is reduced. In this way, the system thermal effect when the chip is short - circuited is reduced, and the reliability of the chip is improved.

[0063] In an implementation manner of the embodiment of the present disclosure, the short - circuit protection control module is configured to output a second control signal through the output end of the short - circuit protection control module in response to the logical value of at least one of the first digital detection signal and the second digital detection signal being 1 for a time less than the preset duration. The second control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a second target frequency, and the second target frequency is greater than the first target frequency.

[0064] In an implementation manner of the present disclosure, the logical value of at least one of the first digital detection signal and the second digital detection signal being 1 indicates that the chip has a short - circuit. Since the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 for a time less than the preset duration, that is, it indicates that the chip starts to enter a short - circuit and the short - circuit protection of the short - circuit protection control module has not been enabled, a second control signal is output through the output end of the short - circuit protection control module.

[0065] Exemplarily, taking the preset duration as 120 ms and the second target frequency as 400 kHz as an example. Combining the above Figure 1, the programmable clock generation module 103 includes three input control signals: the first digital detection signal VP_det, the second digital detection signal VN_det, and the second control signal Short_Enb2. There are three possible cases for VP_det, VN_det, Short_Enb2, and the second target frequency, as shown in Table 2 below:

[0066] Table 2

[0067]

[0068] In this way, when a short circuit starts to occur in the chip including the charge pump module 101, that is, when the logical value of at least one of VP_DET and VN_DET is 1 for less than 120 ms, the second control signal Short_Enb1 is output as 1 through the output terminal of the short-circuit protection control module. It should be noted that when the second control signal is output from the output terminal of the short-circuit protection control module, it indicates that the short-circuit protection function of the short-circuit protection control module has not been enabled, so that the programmable clock generation module can be triggered to set the signal frequency of the clock signal CLK to 400 Khz (i.e., the second target frequency).

[0069] It should be noted that the second target frequency is greater than the operating frequency of the charge pump when no short circuit occurs at the output terminal of the chip (e.g., 250 Khz).

[0070] In this embodiment, the short-circuit protection control module is configured to output a second control signal through the output terminal of the short-circuit protection control module in response to the logical value of at least one of the first digital detection signal and the second digital detection signal being 1 for less than the preset duration. The second control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to the second target frequency. Thus, when a short circuit just starts to occur in the chip, the programmable clock generation module can be controlled to set the signal frequency of the clock signal to the second target frequency. When it is determined that the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 for greater than or equal to the preset duration, a first control signal is output through the output terminal of the short-circuit protection control module to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency smaller than the second target frequency. In this way, it is possible to prevent the charge pump from continuously operating in a high-frequency scenario.

[0071] In an implementation manner of an embodiment of the present disclosure, the short - circuit protection control module is configured to output the third control signal through an output end of the short - circuit protection control module in response to both logical values of the first digital detection signal and the second digital detection signal being 0. The third control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a third target frequency, and the third target frequency is greater than the first target frequency.

[0072] In an implementation manner of the present disclosure, when both logical values of the first digital detection signal and the second digital detection signal are 0, it means that both the signal upper limit value and the signal lower limit value of the charge pump voltage signal output through the output end of the charge pump module reach typical values. Therefore, the output voltage of the charge pump module is stable, and no short - circuit problem occurs in the chip. Thus, there is no need to enable the short - circuit protection function of the short - circuit protection control module, and the third control signal is output through the output end of the short - circuit protection control module.

[0073] In an implementation manner of the present disclosure, since the operating frequency of the charge pump module when the chip has a short - circuit is greater than the operating frequency of the charge pump module when the chip has no short - circuit, the third target frequency is less than the second target frequency.

[0074] Exemplarily, taking the third target frequency as 400 kHz as an example. Combining the above Figure 1 , the programmable clock generation module 103 includes three input control signals, namely the first digital detection signal VP_det, the second digital detection signal VN_det, and the second control signal Short_Enb2. When VP_det is 0 and VN_det is 0, the third control signal Short_Enb2 output through the output end of the short - circuit protection control module is 1, that is, the short - circuit protection function of the short - circuit protection control module is not enabled. In this way, Short_Enb2 can be used to control the programmable clock generation module to set the signal frequency of the clock signal to the third target frequency (i.e., 400 kHz).

[0075] It should be noted that when the short - circuit of the chip is removed, initially the charge pump still operates at 125 KHz. At this frequency, after a period of time, the charge pump slowly resumes normal typical value output. Once it resumes the normal typical value, the logical values of both VP_DET / VN_DET are 0, and the logical value of the short - circuit protection circuit output Short_ENb is pulled to 1, that is, the short - circuit exits. In this way, the operating frequency of the charge pump resumes to the normal 400 KHz and 250 KHz.

[0076] In this embodiment, since the short-circuit protection control module can be configured to output the third control signal through the output terminal of the short-circuit protection control module in response to both the logical values of the first digital detection signal and the second digital detection signal being 0, and the third control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a third target frequency, if the short circuit of the chip is removed, then when the logical values of the first digital detection signal and the second digital detection signal are both 0, the logical value of the third control signal output through the output terminal of the short-circuit protection control module is 1, that is, the short-circuit protection function of the short-circuit protection control module is turned off, so that the operating frequency of the charge pump returns to normal.

[0077] In an embodiment of the present disclosure, the short-circuit protection control module includes: a first circuit unit, a second circuit unit, and a third circuit unit.

[0078] Wherein, the input terminal of the first circuit unit is connected to the first output terminal of the voltage comparison module, the first output terminal of the first circuit unit is connected to the first input terminal of the third circuit unit, and the second output terminal of the first circuit unit is connected to the second input terminal of the third circuit unit.

[0079] Wherein, the input terminal of the second circuit unit is connected to the second output terminal of the voltage comparison module, the first output terminal of the second circuit unit is connected to the third input terminal of the third circuit unit, and the second output terminal of the second circuit unit is connected to the fourth input terminal of the third circuit unit.

[0080] Wherein, the output terminal of the third circuit unit is connected to the third input terminal of the programmable clock generation module.

[0081] In an embodiment of the present disclosure, the first digital detection signal is input to the input terminal of the first circuit unit, and the second digital detection signal is input to the input terminal of the second circuit unit. Therefore, it is possible to determine whether the chip has a short circuit by judging the logical values of the first digital detection signal and the second digital detection signal. Further, when it is determined that the chip has a short circuit and meets a preset duration, a first control signal is output through the output terminal of the third circuit unit to turn on the short-circuit protection function.

[0082] In an embodiment of the present disclosure, the first circuit unit is composed of N first flip-flops.

[0083] Wherein, among the N first flip-flops, one data latch output terminal of the i-th first flip-flop is connected to the data input terminal of the (i + 1)-th first flip-flop, the data input terminal of the first first flip-flop and the set terminals of the N first flip-flops are both connected to the first output terminal of the voltage comparison module, and i ≥ 1.

[0084] Among the N first flip - flops, the data input terminal of the last first flip - flop is connected to the first input terminal of the third circuit unit, and one data latch output terminal of the last first flip - flop is connected to the second input terminal of the third circuit unit.

[0085] In this embodiment, by setting N first flip - flops, it is determined whether the time when the logical value of the first digital detection signal is 1 is greater than or equal to a preset duration, thereby avoiding misjudging that the positive charge pump voltage signal fails to reach the typical value under normal conditions (such as voltage drop) as a short - circuit occurrence, thus improving the accuracy of the short - circuit protection of the chip.

[0086] In an embodiment of the present disclosure, the second circuit unit is composed of N second flip - flops.

[0087] Among the N second flip - flops, one data latch output terminal of the j - th second flip - flop is connected to the data input terminal of the (j + 1) - th second flip - flop, and the data input terminal of the first second flip - flop and the set terminals of the N second flip - flops are both connected to the second output terminal of the voltage comparison module, where j≥1;

[0088] Among the N second flip - flops, the data input terminal of the last second flip - flop is connected to the third input terminal of the third circuit unit, and one data latch output terminal of the last second flip - flop is connected to the fourth input terminal of the third circuit unit.

[0089] In this embodiment, by setting N second flip - flops, it is determined whether the time when the logical value of the second digital detection signal is 1 is greater than or equal to a preset duration, thereby avoiding misjudging that the negative charge pump voltage signal fails to reach the typical value under normal conditions (such as voltage drop) as a short - circuit occurrence, thus improving the accuracy of the short - circuit protection of the chip.

[0090] In an embodiment of the present disclosure, the third circuit unit includes a first AND gate, a second AND gate, and a NAND gate.

[0091] The first AND gate is respectively connected to the data input terminal of the last first flip - flop and one data latch output terminal of the last first flip - flop.

[0092] The second AND gate is respectively connected to the data input terminal of the last second flip - flop and one data latch output terminal of the last second flip - flop.

[0093] Wherein, the NAND gate is respectively connected to the output end of the first AND gate and the output end of the second AND gate, and the output end of the NAND gate is connected to the third input end of the programmable clock generation module.

[0094] Exemplarily, taking the preset time as 120 ms, the first circuit unit consists of 3 first flip-flops, and the second circuit unit consists of 3 second flip-flops as an example. As Figure 2 shown in the structural schematic diagram of the short-circuit protection circuit of the chip, the 3 first flip-flop groups are 201, 202, and 203 respectively, the 3 second flip-flops are 301, 302, and 303 respectively, and the third circuit unit includes a first AND gate 401, a second AND gate 402, and a NAND gate 403. Wherein, a data latch output end of 201 is connected to the data input end of 202, a data latch output end of 202 is connected to the data input end of 203, the data input end and the set end of 201, the set ends of 202 and 203 are all connected to the first output end of the voltage comparison module 102; a data latch output end of 301 is connected to the data input end of 302, a data latch output end of 302 is connected to the data input end of 303, the data input end and the set end of 301, the set ends of 302 and 303 are all connected to the second output end of the voltage comparison module 102; 401 is respectively connected to the data input end and a data latch output end of 203, 402 is respectively connected to the data input end and a data latch output end of 303, 403 is respectively connected to the output end of 401 and the output end of 402, and the output end of 403 is connected to the third input end of the programmable clock generation module.

[0095] In this embodiment, since the first AND gate is respectively connected to the data input end of the last first flip-flop and a data latch output end of the last first flip-flop, the second AND gate is respectively connected to the data input end of the last second flip-flop and a data latch output end of the last second flip-flop, the NAND gate is respectively connected to the output end of the first AND gate and the output end of the second AND gate, and the output end of the NAND gate is connected to the third input end of the programmable clock generation module, when the logical value of at least one of the first digital detection signal and the second digital detection signal is 1 for a time greater than or equal to the preset duration, through the logical operations of the first AND gate, the second AND gate, and the NAND gate, a first control signal can be obtained, and the first control signal is output through the output end of the NAND gate. Thus, the first control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to the first target frequency. In this way, when the chip has a short circuit, the operating frequency of the charge pump can be reduced.

[0096] In an implementation manner of the embodiment of the present disclosure, the short - circuit protection control module further includes: a fourth circuit unit.

[0097] Wherein, a first input end of the fourth circuit unit is connected to an output end of the programmable clock generation module, a second input end of the fourth circuit unit inputs a chip startup signal, and the fourth circuit unit is configured to divide the clock signal output through the output end of the programmable clock generation module in response to the logic value of the chip startup signal being 1 to obtain a divided - frequency clock signal, and output the divided - frequency clock signal through an output end of the fourth circuit unit.

[0098] In an implementation manner of the embodiment of the present disclosure, a clock input end of each of the N first flip - flops is connected to an output end of the fourth circuit unit, and the preset duration is determined according to the number of the N first flip - flops and the period of the divided - frequency clock signal.

[0099] In this implementation manner, since a clock input end of each of the N first flip - flops is connected to an output end of the fourth circuit unit, and the preset duration is determined according to the number of the N first flip - flops and the period of the divided - frequency clock signal, it is possible to determine whether the time when the logic value of the first digital detection signal is 1 is greater than or equal to the preset duration according to the divided - frequency clock signal input to the clock input ends of the N first flip - flops.

[0100] In an implementation manner of the embodiment of the present disclosure, a clock input end of each of the N second flip - flops is connected to an output end of the fourth circuit unit, and the preset duration is determined according to the number of the N second flip - flops and the period of the divided - frequency clock signal.

[0101] In this implementation manner, since a clock input end of each of the N second flip - flops is connected to an output end of the fourth circuit unit, and the preset duration is determined according to the number of the N second flip - flops and the period of the divided - frequency clock signal, it is possible to determine whether the time when the logic value of the second digital detection signal is 1 is greater than or equal to the preset duration according to the divided - frequency clock signal input to the clock input ends of the N second flip - flops.

[0102] Exemplarily, taking the preset time as 120 ms as an example, when the chip starts to short - circuit, taking the signal frequency of the clock signal output from the output end of the programmable clock generation module as 400 KHz as an example. Combining the above - mentioned embodiments Figure 2 , such as Figure 3Schematic structural diagram of the short-circuit protection circuit of the shown chip. The short-circuit protection control module may further include a fourth circuit unit 501. When the chip startup signal is at a high level, 501 divides the signal frequency of the clock signal by 14 times, so that a divided clock signal is output through the output terminal of 501, and one period of the divided clock signal is 40 ms. Thus, it is necessary to set 3 first flip-flops to determine whether the time when the logical value of the first digital detection signal is 1 meets 120 ms, and set 3 second flip-flops to determine whether the time when the logical value of the second digital detection signal is 1 meets 120 ms.

[0103] Specifically, for different logical values of the first digital detection signal VP_det and the second digital detection signal VN_det, as Figure 4 shown, a set of Q0 and Q1, and a set of Q0n and Q1n are respectively output. When it is determined that the duration when VP_det is 1 reaches 120 ms, Q0 is 1 and Q1 is 0; when it is determined that the duration when VN_det is 1 reaches 120 ms, Q0n is 1 and Q1 is 0.

[0104] In this embodiment, the fourth circuit unit is used to respond to the logical value of the chip startup signal being 1, divide the clock signal output through the output terminal of the programmable clock generation module, so as to obtain a divided clock signal. Thus, the divided clock signal can be used as the signal input to the clock input terminals of the first flip-flops and the second flip-flops, that is, the clock input terminal of each of the N first flip-flops is connected to the output terminal of the fourth circuit unit, and the clock input terminal of each of the N second flip-flops is connected to the output terminal of the fourth circuit unit. Thus, the preset duration can be determined according to the number of the N first flip-flops or the N second flip-flops, and the period of the divided clock signal, and then it can be determined whether the time when at least one of the logical values of the first digital detection signal and the second digital detection signal is 1 is greater than or equal to the preset duration.

[0105] The above description is only the preferred embodiments of the present disclosure and the description of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present disclosure.

Claims

1. A short - circuit protection circuit for a chip, characterized in that, The short - circuit protection circuit includes: a charge pump module, a voltage comparison module, a programmable clock generation module, and a short - circuit protection control module; The first output terminal of the charge pump module is connected to the first input terminal of the voltage comparison module, and the second output terminal of the charge pump module is connected to the second input terminal of the voltage comparison module. The charge pump module is configured to output a positive charge pump voltage signal through the first output terminal of the charge pump module and output a negative charge pump voltage signal through the second output terminal of the charge pump module; The first output terminal of the voltage comparison module is connected to the first input terminal of the programmable clock generation module, and the second output terminal of the voltage comparison module is connected to the second input terminal of the programmable clock generation module. The voltage comparison module is configured to output a first digital detection signal through the first output terminal of the voltage comparison module in response to the positive charge pump voltage signal being greater than or equal to a first signal threshold, and output a second digital detection signal through the second output terminal of the voltage comparison module in response to the negative charge pump voltage signal being less than or equal to a second signal threshold; The output terminal of the programmable clock generation module is connected to the input terminal of the charge pump module, and the third input terminal of the programmable clock generation module is connected to the output terminal of the short - circuit protection control module. The programmable clock generation module is configured to output a clock signal through the output terminal of the programmable clock generation module, and the clock signal is used to control the operating frequency of the charge pump module; The first input terminal of the short - circuit protection control module is connected to the first output terminal of the voltage comparison module, and the second input terminal of the short - circuit protection control module is connected to the second output terminal of the voltage comparison module. The short - circuit protection control module is configured to output a first control signal through the output terminal of the short - circuit protection control module in response to the time when at least one of the logical values of the first digital detection signal and the second digital detection signal is 1 being greater than or equal to a preset duration. The first control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a first target frequency; the first target frequency is less than the operating frequency of the charge pump module when the short - circuit protection function of the short - circuit protection control module is not enabled when a short - circuit occurs at the output terminal of the chip.

2. The short - circuit protection circuit according to claim 1, characterized in that, The short - circuit protection control module is configured to output a second control signal through the output terminal of the short - circuit protection control module in response to the time when at least one of the logical values of the first digital detection signal and the second digital detection signal is 1 being less than the preset duration. The second control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a second target frequency, and the second target frequency is greater than the first target frequency.

3. The short - circuit protection circuit according to claim 1, characterized in that, The short - circuit protection control module is configured to respond to the logical values of the first digital detection signal and the second digital detection signal both being 0, and output a third control signal through the output terminal of the short - circuit protection control module. The third control signal is used to control the programmable clock generation module to set the signal frequency of the clock signal to a third target frequency, and the third target frequency is greater than the first target frequency.

4. The short - circuit protection circuit according to claim 1, characterized in that, The short - circuit protection control module includes: a first circuit unit, a second circuit unit, and a third circuit unit; The input terminal of the first circuit unit is connected to the first output terminal of the voltage comparison module. The first output terminal of the first circuit unit is connected to the first input terminal of the third circuit unit, and the second output terminal of the first circuit unit is connected to the second input terminal of the third circuit unit; The input terminal of the second circuit unit is connected to the second output terminal of the voltage comparison module. The first output terminal of the second circuit unit is connected to the third input terminal of the third circuit unit, and the second output terminal of the second circuit unit is connected to the fourth input terminal of the third circuit unit; The output terminal of the third circuit unit is connected to the third input terminal of the programmable clock generation module.

5. The short - circuit protection circuit according to claim 4, characterized in that, The first circuit unit is composed of N first flip - flops; Among the N first flip - flops, one data latch output terminal of the i - th first flip - flop is connected to the data input terminal of the (i + 1) - th first flip - flop. The data input terminal of the first first flip - flop and the set terminals of the N first flip - flops are both connected to the first output terminal of the voltage comparison module, where i≥1; Among the N first flip - flops, the data input terminal of the last first flip - flop is connected to the first input terminal of the third circuit unit, and one data latch output terminal of the last first flip - flop is connected to the second input terminal of the third circuit unit.

6. The short - circuit protection circuit according to claim 5, characterized in that, The second circuit unit is composed of N second flip - flops; Among the N second flip - flops, one data latch output terminal of the j - th second flip - flop is connected to the data input terminal of the (j + 1) - th second flip - flop. The data input terminal of the first second flip - flop and the set terminals of the N second flip - flops are both connected to the second output terminal of the voltage comparison module, where j≥1; Among the N second flip - flops, the data input terminal of the last second flip - flop is connected to the third input terminal of the third circuit unit, and one data latch output terminal of the last second flip - flop is connected to the fourth input terminal of the third circuit unit.

7. The short - circuit protection circuit according to claim 6, characterized in that, The third circuit unit includes a first AND gate, a second AND gate, and a NAND gate; The first AND gate is respectively connected to the data input terminal of the last first flip - flop and one data latch output terminal of the last first flip - flop; The second AND gate is respectively connected to the data input terminal of the last second flip - flop and one data latch output terminal of the last second flip - flop; The NAND gate is respectively connected to the output terminals of the first AND gate and the second AND gate, and the output terminal of the NAND gate is connected to the third input terminal of the programmable clock generation module.

8. The short - circuit protection circuit according to claim 7, characterized in that, The short - circuit protection control module further includes: a fourth circuit unit; The first input terminal of the fourth circuit unit is connected to the output terminal of the programmable clock generation module. A chip startup signal is input to the second input terminal of the fourth circuit unit. The fourth circuit unit is configured to divide the clock signal output from the output terminal of the programmable clock generation module in response to the logic value of the chip startup signal being 1 to obtain a divided clock signal, and output the divided clock signal through the output terminal of the fourth circuit unit.

9. The short - circuit protection circuit according to claim 8, characterized in that, The clock input terminal of each of the N first flip-flops is connected to the output terminal of the fourth circuit unit. The preset duration is determined according to the number of the N first flip-flops and the period of the divided clock signal.

10. The short - circuit protection circuit according to claim 8, characterized in that, The clock input terminal of each of the N second flip-flops is connected to the output terminal of the fourth circuit unit. The preset duration is determined according to the number of the N second flip-flops and the period of the divided clock signal.

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