A low-distortion pulse filtering circuit

Abstract

The application discloses a low-distortion pulse filtering circuit, which comprises an XOR gate, a single-side filtering circuit, a gating circuit and an RS flip-flop, one input end of the XOR gate is connected with an input pulse signal IN, the output of the XOR gate is connected with the input end of the single-side filtering circuit, the output of the single-side filtering circuit is connected with the data input port of the gating circuit, the selection input port of the gating circuit is connected with the connection end of the XOR gate and the IN, the set signal output of the gating circuit is connected with the set input end S of the RS flip-flop, one reset signal output of the gating circuit is connected with the reset input end R1 of the RS flip-flop, the other reset input end R2 of the RS flip-flop is connected with the reset input signal end RST of the low-distortion pulse filtering circuit, and the output end Q of the RS flip-flop is connected with the other input end of the XOR gate as the output signal OUT of the low-distortion pulse filtering circuit.

Description

Technical Field

[0001] This application relates to pulse filtering circuits, and more particularly to a low-distortion pulse filtering circuit, belonging to the field of integrated circuit technology. Background Technology

[0002] In some applications, such as motor control and DC-DC power supplies, the digital signal input ports of chips generate pulse noise signals. These pulse noise signals may affect the normal operating noise of the system and may even cause damage to the system. To suppress this pulse noise, pulse filtering circuits are usually added to the digital signal input ports.

[0003] Traditional pulse filter circuits, such as Figure 1 As shown, this circuit, composed of an inverter, resistor, and capacitor, has a simple structure but a serious problem: the output signal will be distorted, especially when the input pulse width is narrow. Figure 2 As shown, when the input pulse width is wide, the output pulse width is approximately equal to the input pulse width. However, when the input pulse width is narrow, especially close to the input pulse filter width, the output pulse will be severely distorted, producing a waveform signal narrower than the input pulse width. In this case, the filter circuit has lost its function.

[0004] To address the problems of traditional pulse filter circuits, many different solutions have been proposed. For example... Figure 3 As shown, US Patent US6940326B2 provides a pulse filter circuit structure. The circuit includes two filter circuits (fist pulse generator) and a flip-flop. The filtering or delay time of the two filter circuits is the same. When the input pulse width is less than or equal to the filtering time, the input pulse is filtered out as noise. When the input pulse width is greater than the filtering width, one filter circuit performs the filtering function, while the delay function of the other filter circuit restores the input pulse width. Through the logic operation of the flip-flop, the output pulse width is finally made approximately equal to the input pulse width.

[0005] US Patent US8154324B2 proposes another circuit structure, which includes an inverter, resistor, capacitor, diode and Schmitt trigger. The two ends of the capacitor are connected to the input and output ports of the Schmitt trigger, respectively. This structure takes advantage of the characteristic that the voltage across the capacitor does not change abruptly. When the output voltage of the Schmitt trigger changes, the voltage at the input port of the Schmitt trigger is quickly increased or decreased. Compared with traditional filter circuits, it can significantly reduce the distortion of the output signal.

[0006] US Patent US8598911B2 proposes another different circuit structure, which uses several switching devices to control different resistors and capacitors to achieve filtering and delay, ultimately enabling the circuit to filter out pulse noise while achieving low-distortion signal transmission.

[0007] The above-mentioned US patent structures can effectively suppress impulse noise signals and achieve low-distortion transmission of input signals; however, each of these patent structures has its own drawbacks. For example, the US6940326B2 circuit structure includes two filter circuits. Typically, the resistors and capacitors in the delay filter circuit are large, resulting in a large layout area. Furthermore, mismatch between the two filter circuits can increase signal distortion. While the US8154324B2 circuit structure is relatively simple, the rise and fall times of the input signal cannot be kept consistent under various conditions (different voltages, temperatures, process angles), resulting in high signal distortion. The US8598911B2 circuit structure uses different resistors and capacitors to define the filtering time for different edges, which also increases signal distortion. Additionally, the use of more switching devices in the circuit leads to an increase in layout area. Summary of the Invention

[0008] To overcome the shortcomings of existing technologies, this invention provides a low-distortion pulse filter circuit to solve the problem of signal distortion in existing pulse filter circuits.

[0009] To achieve the above-mentioned objectives, the present invention employs the following technical solution: a low-distortion pulse filter circuit, characterized in that it comprises an XOR gate, a single-sided filter circuit, a gating circuit, and an RS flip-flop; one input terminal of the XOR gate is connected to the input pulse signal IN, the output of the XOR gate is connected to the input terminal of the single-sided filter circuit, the output of the single-sided filter circuit is connected to the data input port of the gating circuit, the selection input port of the gating circuit is connected to the connection terminal of the XOR gate and the input pulse signal IN, the set signal output of the gating circuit is connected to the set input terminal S of the RS flip-flop, one reset signal output of the gating circuit is connected to the reset input terminal R1 of the RS flip-flop, the other reset input terminal R2 of the RS flip-flop is connected to the reset input signal terminal RST of the low-distortion pulse filter circuit, and the output terminal Q of the RS flip-flop serves as the output terminal of the low-distortion pulse filter circuit, outputting the signal OUT and feeding back to the other input terminal of the XOR gate;

[0010] The RS flip-flop includes a two-input NOR gate NOR1 and a three-input NOR gate NOR2. One input of the two-input NOR gate NOR1 is used as the set input S of the RS flip-flop and connected to the set signal output by the gating circuit. The output of the two-input NOR gate NOR1 is connected to one input of the three-input NOR gate NOR2. The other two inputs of the three-input NOR gate NOR2 are used as the reset input R1 and the reset input R2 of the RS flip-flop, respectively. The output of the three-input NOR gate NOR2 is used as the output Q of the RS flip-flop and connected to the other input of the two-input NOR gate NOR1.

[0011] The gating circuit includes an inverter INV1, a transmission gate TG1, a transmission gate TG2, and NMOS transistors N1 and N2. The output of the single-sided filter circuit is connected to the input terminals of transmission gate TG1 and TG2, which serve as the data input ports of the gating circuit. The gate of the NMOS transistor in transmission gate TG1 is connected to the input terminal of inverter INV1, the gate of the PMOS transistor in transmission gate TG2 (which serves as the selection input port of the gating circuit and is connected to the input pulse signal IN), and the gate of NMOS transistor N2. The output of inverter INV1 is connected to the gate of the PMOS transistor in transmission gate TG1, the gate of the NMOS transistor in transmission gate TG2, and the gate of NMOS transistor N1. The output terminal of transmission gate TG1 is connected to the drain of NMOS transistor N1 and serves as the set signal output terminal of the gating circuit. The source of NMOS transistor N1 is grounded. The output terminal of transmission gate TG2 is connected to the drain of NMOS transistor N2 and serves as a reset signal output terminal of the gating circuit, connected to the reset input terminal R1 of the RS flip-flop. The source of NMOS transistor N2 is grounded.

[0012] Furthermore, in the above-mentioned gating circuit, two AND gates AND1 and AND2 can be used to replace transmission gates TG1 and TG2, as well as NMOS transistors N1 and NMOS transistor N2. The output of the single-sided filter circuit is connected to one input of AND gate AND1, which serves as the data input port of the gating circuit, and one input of AND gate AND2. The other input of AND gate AND1 is connected to the input of inverter INV1 and serves as the selection input port of the gating circuit, connected to the input pulse signal IN. The output of inverter INV1 is connected to the other input of AND gate AND2. The output of AND gate AND1 serves as the set signal output of the gating circuit, and the output of AND gate AND2 serves as a reset signal output of the gating circuit, connected to the reset input R1 of the RS flip-flop.

[0013] Alternatively, a D flip-flop can be used to replace the gating circuit and the RS flip-flop. In this case, the input of the single-sided filter circuit is connected to the output of the XOR gate, the output of the single-sided filter circuit is connected to the clock input of the D flip-flop, the clock signal of the D flip-flop is the rising edge clock signal, the data input D of the D flip-flop is connected to the connection point of the XOR gate and the input pulse signal IN, the reset input port Reset of the D flip-flop is connected to the reset input signal RST of the low distortion pulse filter circuit, and the output Q of the D flip-flop serves as the output of the low distortion pulse filter circuit, outputting the signal OUT and feeding back to the other input port of the XOR gate.

[0014] In the low-distortion pulse filter circuit, the single-sided filter circuit includes an inverter INV2, a PMOS transistor P1, an NMOS transistor N3, a resistor RES1, a capacitor C1, and a buffer BUF1. The input terminal of the inverter INV2 serves as the input terminal of the single-sided filter circuit and is connected to the output of the XOR gate. The output of the inverter INV2 is connected to the gates of the PMOS transistor P1 and the NMOS transistor N3. The source of the PMOS transistor P1 is connected to VDD. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N3, one end of the capacitor C1, and the input terminal of the buffer BUF1 through the resistor RES1. The other end of the capacitor C1 is connected to the source of the NMOS transistor N3 and grounded. The output terminal of the buffer BUF1 is the output terminal of the single-sided filter circuit.

[0015] In the above single-sided filter circuit, resistor RES1 can also be removed, and the drain of PMOS transistor P1, the drain of NMOS transistor N3, one end of capacitor C1, and the input of buffer BUF1 can be directly connected. At the same time, a current source I1 can be added between the source of PMOS transistor P1 and VDD. The input of current source I1 is connected to VDD, and the output of current source I1 is connected to the source of PMOS transistor P1.

[0016] In the above single-sided filter circuit, an AND gate AND3 can also be added to the output of the buffer BUF1. The output of the buffer BUF1 is connected to one input of the AND gate AND3, and the other input of the AND gate AND3 is connected to the input of the inverter INV2. The output of the AND gate AND3 serves as the output of the single-sided filter circuit.

[0017] The input pulse signal IN is either a positive pulse or a negative pulse.

[0018] Advantages and significant effects of the present invention:

[0019] 1. This invention can filter out input pulse noise signals and restore the pulse width of the input signal, achieving low-distortion transmission. The circuit structure of this invention contains only one single-sided filter circuit, one flip-flop, and one XOR gate, making the circuit structure relatively simple.

[0020] 2. This invention employs the same single-sided filter circuit multiplexing at both the rising and falling edges, ensuring low-distortion transmission of the input signal under different temperature, voltage, and process conditions, while also reducing the circuit layout area. Since the rising and falling edge delays are generated by the same filter circuit, the input and output pulse widths remain essentially equal under different temperature, voltage, and process conditions, resulting in minimal input and output signal distortion.

[0021] 3. Compared with most existing technologies, the circuit structure is simple, resulting in a smaller layout area, which helps to reduce chip costs. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a traditional pulse filter circuit.

[0023] Figure 2 This is a schematic diagram of the working waveform of a traditional pulse filter circuit;

[0024] Figure 3 This is a schematic diagram of the circuit structure of patent US6940326B2;

[0025] Figure 4a This is a schematic diagram of a circuit structure proposed in this invention;

[0026] Figure 4b This is a schematic diagram of another circuit structure proposed in this invention;

[0027] Figure 5a This is a schematic diagram of one implementation structure of a gating circuit;

[0028] Figure 5b This is a schematic diagram of another implementation structure of the gating circuit;

[0029] Figure 6a This is a schematic diagram of one implementation structure of a single-sided filter circuit;

[0030] Figure 6b This is a schematic diagram of the second implementation structure of a single-sided filter circuit;

[0031] Figure 6c This is a schematic diagram of the third implementation structure of a single-sided filter circuit;

[0032] Figure 7 This is a schematic diagram of one implementation structure of an RS flip-flop;

[0033] Figure 8 This is the first embodiment of the invented structure;

[0034] Figure 9 This is a waveform diagram of the first embodiment of the invented structure;

[0035] Figure 10 This is the second embodiment of the invented structure;

[0036] Figure 11 This is a waveform diagram of the second embodiment of the invented structure.

[0037] Figure 12 This is a diagram illustrating the implementation effect of the invented structure. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] Figure 4a This is an embodiment of the low-distortion pulse filter circuit of the present invention, including an XOR gate, a single-sided filter circuit, a gating circuit, and an RS flip-flop. When the selection input of the gating circuit is high, the output voltage of the set output is equal to the voltage of the data input, while the output voltage of the reset output is low; when the selection input is low, the output voltage of the reset output is equal to the voltage of the data input, while the output voltage of the set output is low. When the set input of the RS flip-flop is high and both reset inputs are low, the output port of the RS flip-flop is high; when one reset input is high or both reset inputs are high and the set input is low, the output of the RS flip-flop is low; when the set input and both reset inputs are low, the output port voltage of the RS flip-flop remains in the previous state.

[0040] Figure 5a , Figure 5b They are Figure 4a Two implementation circuits for the selection circuit. Figure 5a This includes inverter INV1, transmission gate TG1, transmission gate TG2, and NMOS transistors N1 and NMOS transistor N2. Figure 5b The middle part uses two AND gates, AND1 and AND2, to replace Figure 5a The transmission gates TG1 and TG2, as well as NMOS transistors N1 and NMOS transistor N2.

[0041] Figure 7 yes Figure 4aThe implementation structure of the RS flip-flop includes a two-input NOR gate NOR1 and a three-input NOR gate NOR2. One input of the two-input NOR gate NOR1 serves as the set input S of the RS flip-flop, connected to the set signal output by the gating circuit. The output of the two-input NOR gate NOR1 is connected to one input of the three-input NOR gate NOR2. The other two inputs of the three-input NOR gate NOR2 serve as the reset inputs R1 and R2 of the RS flip-flop, respectively. The output of the three-input NOR gate NOR2 serves as the output Q of the RS flip-flop and is connected to the other input of the two-input NOR gate NOR1.

[0042] Figure 4b This is another implementation of the low-distortion pulse filter circuit of the present invention, which uses a D flip-flop to replace... Figure 4a In the scheme using the selection circuit and RS flip-flop, the input of the single-sided filter circuit is connected to the output of the XOR gate, the output of the single-sided filter circuit is connected to the clock input of the D flip-flop, the clock signal of the D flip-flop is the rising edge clock signal, the data input D of the D flip-flop is connected to the connection point of the XOR gate and the input pulse signal IN, the reset input port Reset of the D flip-flop is connected to the reset input signal RST of the low distortion pulse filter circuit, and the output Q of the D flip-flop serves as the output port OUT of the low distortion pulse filter circuit and is fed back to the other input port of the XOR gate.

[0043] Figure 4a and Figure 4b The single-sided filter circuit in the image can be implemented using three different circuits, such as... Figure 6a , Figure 6b and Figure 6c The single-sided filter circuit only delays the rising edge of its input signal. If the pulse width of the input signal is less than or equal to the filtering time Tfilter, the output voltage remains low, indicating that the input pulse signal has been filtered out. If the pulse width of the input signal is greater than the filtering time, the output voltage becomes high. And if the input signal becomes low, the output also immediately becomes low. Figure 6a It includes inverter INV2, PMOS transistor P1, NMOS transistor N3, resistor RES1, capacitor C1, and buffer BUF1. Figure 6b In the middle, deleted Figure 6a The resistor RES1, the drain of PMOS transistor P1 and the drain of NMOS transistor N3, one end of capacitor C1 and the input of buffer BUF1 are changed to be directly connected. At the same time, a current source I1 is added between the source of PMOS transistor P1 and VDD. The input of current source I1 is connected to VDD and the output of current source I1 is connected to the source of PMOS transistor P1. Figure 6c In Figure 6aAn AND gate AND3 is added to the output of buffer BUF1. The output of buffer BUF1 is connected to one input of AND gate AND3, and the other input of AND gate AND3 is connected to the input of inverter INV2. The output of AND gate AND3 serves as the output of a single-sided filter circuit.

[0044] Figure 8 This invention relates to a low-distortion pulse filter circuit. Figure 4a The single-sided filter circuit in the middle adopts Figure 6a The circuit, the gating circuit adopts Figure 5b The circuit implementation circuit. Figure 9 yes Figure 8 The circuit's waveform diagram illustrates the operation. The delay time of the single-sided filter circuit is t_flt. When the input IN goes high or low, the output OUT and IN undergo an XOR operation, causing A to change from low to high. At this point, the single-sided filter circuit begins timing. When the input IN pulse width is less than or equal to t_flt (i.e., before the output B of the single-sided filter circuit undergoes a level flip), the input IN changes. Due to the XOR effect, A changes from high to low, and OUT remains unchanged. When the input IN pulse width is greater than t_flt, the output B of the single-sided filter circuit flips, changing from low to high. The RS flip-flop's set input S (or reset input R) also becomes high, and the RS flip-flop's output OUT changes from low to high (or from high to low). Simultaneously, due to the XOR effect, A immediately changes from high to low, and B also becomes low, representing a pulse signal. The input IN undergoes two timing operations and several logic operations on both the rising and falling edges, ultimately resulting in an output OUT with the same pulse width as the input IN. The circuit's effect is as follows: Figure 12 As shown, the input IN pulse width is Pw_in, and the output OUT pulse width is Pw_out. When Pw_in is less than or equal to t_flt, Pw_out equals 0. When Pw_in is greater than t_flt, Pw_out equals Pw_in.

[0045] Figure 10 The low-distortion pulse filter circuit of this invention adopts Figure 4b The implementation structure, in which the single-sided filter circuit adopts Figure 6c The circuit connects the output of AND gate AND3 to the clock input clk of the D flip-flop. Figure 11 yes Figure 10 The operating waveform diagram of the implemented circuit can also be obtained. Figure 12Effect. The delay time of the single-sided filter circuit is t_flt. When the input IN goes high or low, the output OUT and IN undergo an XOR operation, causing A to change from low to high. At this time, the single-sided filter circuit starts timing. When the input IN pulse width is less than or equal to t_flt, that is, before the output B of the single-sided filter circuit has a level flip, the input IN changes. Due to the XOR effect, A changes from high to low, and OUT remains unchanged. When the input IN pulse width is greater than t_flt, the output B of the single-sided filter circuit flips, changing from low to high. This generates a rising edge on B, which is input to the clock input Clk of the D flip-flop. The output OUT of the D flip-flop changes to the same level as D(IN). After OUT becomes the same as IN, it undergoes an XOR operation, causing A to go low and B to go low as well. In this way, after the input signal IN is processed at both the beginning and end edges, the final output signal OUT will have the same pulse width as IN.

[0046] The single-sided filter circuit only delays the rising edge of its input signal A. If the pulse width of the input signal A is less than or equal to the filtering time Tfilter, the output voltage remains low, indicating that the input pulse signal A has been filtered out. If the pulse width of the input signal A is greater than the filtering time, the output voltage B becomes high. And if the input signal A becomes low, the output B also immediately becomes low.

[0047] If the pulse width of the input signal IN at the pulse input terminal of the low-distortion pulse filter circuit is less than or equal to the filtering time Tfilter of the single-sided filter circuit, the output remains unchanged; if the pulse width of the input signal IN is greater than the filtering time Tfilter of the single-sided filter circuit, the output pulse width OUT is equal to the pulse width of the input signal IN.

[0048] Those skilled in the art will understand that all or part of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0049] The above embodiments are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-distortion pulse filtering circuit, characterized by, The low-distortion pulse filter circuit comprises an exclusive OR gate XOR, a one-side filter circuit, a gating circuit and an RS flip-flop; one input end of the exclusive OR gate XOR is connected with an input pulse signal IN, an output of the exclusive OR gate XOR is connected with an input end of the one-side filter circuit, an output of the one-side filter circuit is connected with a data input port of the gating circuit, a selection input port of the gating circuit is connected with a connection end of the exclusive OR gate XOR and the input pulse signal IN, a set signal output of the gating circuit is connected with a set input end S of the RS flip-flop, one reset signal output of the gating circuit is connected with a reset input end R1 of the RS flip-flop, and another reset input end R2 of the RS flip-flop is connected with a reset input signal end RST of the low-distortion pulse filter circuit; and an output end Q of the RS flip-flop outputs a signal OUT as an output end of the low-distortion pulse filter circuit and is connected with another input end of the exclusive OR gate XOR in feedback mode. The gating circuit comprises an inverter INV1, a transmission gate TG1, a transmission gate TG2, an NMOS tube N1 and an NMOS tube N2; an output of the one-side filter circuit is connected with an input end of the transmission gate TG1 and an input end of the transmission gate TG2 which are data input ports of the gating circuit; a gate of the NMOS tube in the transmission gate TG1 is connected with an input end of the inverter INV1 and a gate of a PMOS tube and a gate of the NMOS tube N2 in the transmission gate TG2 which are selection input ports of the gating circuit and are connected with the input pulse signal IN; an output of the inverter INV1 is connected with a gate of a PMOS tube in the transmission gate TG1, a gate of an NMOS tube in the transmission gate TG2 and a gate of the NMOS tube N1; an output end of the transmission gate TG1 is connected with a drain of the NMOS tube N1 and is a set signal output end of the gating circuit; a source of the NMOS tube N1 is grounded; an output end of the transmission gate TG2 is connected with a drain of the NMOS tube N2 and is connected with the reset input end R1 of the RS flip-flop which is one reset signal output of the gating circuit; and a source of the NMOS tube N2 is grounded. The one-side filter circuit comprises an inverter INV2, a PMOS tube P1, an NMOS tube N3, a resistor RES1, a capacitor C1 and a buffer BUF1; an input end of the inverter INV2 which is an input end of the one-side filter circuit is connected with an output of the exclusive OR gate XOR; an output of the inverter INV2 is connected with a gate of the PMOS tube P1 and a gate of the NMOS tube N3; a source of the PMOS tube P1 is connected with VDD; a drain of the PMOS tube P1 is connected with a drain of the NMOS tube N3, one end of the capacitor C1 and an input end of the buffer BUF1 through the resistor RES1; another end of the capacitor C1 is connected with a source of the NMOS tube N3 and is grounded; and an output end of the buffer BUF1 is an output end of the one-side filter circuit. The RS flip-flop comprises a two-input NOR gate NOR1 and a three-input NOR gate NOR2, one input terminal of the two-input NOR gate NOR1 is connected to a set signal output by the gating circuit as a set input terminal S of the RS flip-flop, the output of the two-input NOR gate NOR1 is connected to one input terminal of the three-input NOR gate NOR2, the other two input terminals of the three-input NOR gate NOR2 are respectively a reset input terminal R1 and a reset input terminal R2 of the RS flip-flop, and the output of the three-input NOR gate NOR2 is connected to the other input terminal of the two-input NOR gate NOR1 as an output terminal Q of the RS flip-flop.

2. The low distortion pulse filtering circuit of claim 1, wherein, In the gating circuit, the transmission gates TG1 and TG2 and the NMOS tubes N1 and N2 are replaced by two AND gates AND1 and AND2, the output of the single-side filter circuit is connected to one input terminal of the AND gate AND1 and one input terminal of the AND gate AND2 as a data input terminal of the gating circuit, the other input terminal of the AND gate AND1 is connected to the input terminal of an inverter INV1 and is connected to an input pulse signal IN as a selection input terminal of the gating circuit, the output of the inverter INV1 is connected to the other input terminal of the AND gate AND2, the output of the AND gate AND1 is connected to the reset input terminal R1 of the RS flip-flop as a reset signal output of the gating circuit.

3. The low distortion pulse filtering circuit of claim 1, wherein, The gating circuit and the RS flip-flop are replaced by a D flip-flop, the input terminal of the single-side filter circuit is connected to the output terminal of an XOR gate, the output of the single-side filter circuit is connected to the clock input terminal of the D flip-flop, the data input terminal D of the D flip-flop is connected to the connection terminal of the XOR gate and the input pulse signal IN, the reset input terminal port Reset of the D flip-flop is connected to the reset input signal terminal RST of the low-distortion pulse filter circuit, and the output terminal Q of the D flip-flop is connected to the other input terminal of the XOR gate as the output terminal of the low-distortion pulse filter circuit and outputs a signal OUT.

4. The low distortion pulse filtering circuit of claim 3, wherein, The clock signal of the D flip-flop is a rising edge clock signal.

5. The low distortion pulse filtering circuit of claim 1 or 3, wherein, In the single-side filter circuit, the resistor RES1 is deleted, the drain of the PMOS tube P1 is directly connected to the drain of the NMOS tube N3, one end of the capacitor C1 and the input terminal of the buffer BUF1, and a current source I1 is additionally arranged between the source of the PMOS tube P1 and VDD, the input terminal of the current source I1 is connected to VDD, and the output terminal of the current source I1 is connected to the source of the PMOS tube P1.

6. The low distortion pulse filtering circuit of claim 5, wherein, In the single-side filter circuit, an AND gate AND3 is additionally arranged at the output terminal of the buffer BUF1, one input terminal of the AND gate AND3 is connected to the output of the buffer BUF1, the other input terminal of the AND gate AND3 is connected to the input terminal of an inverter INV2, and the output of the AND gate AND3 is connected to the output terminal of the single-side filter circuit.

7. The low distortion pulse filtering circuit of claim 1 or 3, wherein, The input pulse signal IN is a positive pulse or a negative pulse.

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