Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises the following steps: providing a substrate; forming a plurality of semiconductor pillars extending along a first direction on the substrate, the semiconductor pillars are arranged at intervals along a second direction and a third direction, the semiconductor pillars comprise a first doped region, a channel region and a second doped region, the first doped region and the second doped region are located on opposite sides of the channel region, wherein the channel region comprises a plurality of channel layers parallel to the plane of the third direction and the first direction; forming a plurality of word lines extending along the third direction, each word line along the third direction is connected to the channel regions of a plurality of semiconductor pillars, and the word line covers at least part of the surface of the channel layer; the third direction is perpendicular to the surface of the substrate, the first direction and the second direction intersect and are both parallel to the surface of the substrate, at least the gate control capability of the transistor is improved and the power consumption is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the continuous scaling of semiconductor devices, in order to meet the requirements of the on-state voltage and the saturation current, three-dimensional device structures (for example, fin field effect transistor (FinFET) and nanowire) are becoming the development direction of the industry. In the three-dimensional device structure, the gate structure can surround the channel region of the transistor, so as to maximize the control of the transistor on the current therein.

[0003] In the research of 3D DRAM, it is also necessary to further explore the method of improving the gate control ability and reducing the power consumption. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least facilitate to improve the gate control ability of the transistor and reduce the power consumption.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure, comprising: providing a substrate; forming a plurality of semiconductor pillars extending along a first direction on the substrate, the semiconductor pillars are arranged at intervals along a second direction and a third direction, the semiconductor pillars comprise a first doped region, a channel region and a second doped region, the first doped region and the second doped region are located on opposite sides of the channel region, wherein the channel region comprises a plurality of channel layers parallel to the plane of the third direction and the first direction; forming a plurality of word lines extending along the third direction, each word line along the third direction connects the channel regions of a plurality of semiconductor pillars, and the word line covers at least part of the surface of the channel layer; the third direction is perpendicular to the surface of the substrate, and the first direction and the second direction intersect and are both parallel to the surface of the substrate.

[0006] In some embodiments, after forming the word lines, further comprising: forming a plurality of bit lines extending along the second direction, each bit line along the second direction connects the first doped regions of a plurality of semiconductor pillars; and / or forming a storage unit, the storage unit extends along the first direction and is connected with the second doped regions of the semiconductor pillars.

[0007] In some embodiments, forming a plurality of semiconductor pillars extending along a first direction on a substrate includes: forming a stack structure on the substrate, the stack structure including alternatingly stacked sacrificial layers and semiconductor layers along a third direction; etching the stack structure to form a plurality of first recesses spaced along a second direction, the first recesses being located within the sacrificial layers and the semiconductor layers and extending along the first direction; filling insulating layers in the first recesses; etching the semiconductor layers between the first recesses along the third direction to form a plurality of second recesses spaced along the second direction, the remaining semiconductor layers serving as the semiconductor pillars, the second recesses being located at least between adjacent first recesses, and the adjacent first recesses having a plurality of the second recesses therebetween, the semiconductor pillars between the second recesses serving as channel layers, and the channel layers between the adjacent first recesses constituting channel regions.

[0008] In some embodiments, forming a plurality of word lines extending along a third direction includes: forming a gate dielectric layer covering a channel layer surface of the semiconductor pillars; filling a conductive layer in the second recesses, the conductive layer covering a surface of the gate dielectric layer; patterning the conductive layer to form the word lines and a plurality of third recesses extending along the first direction, the third recesses being located between adjacent word lines; and filling insulating material in the third recesses.

[0009] In some embodiments, after forming the second recesses, the method further includes: removing the sacrificial layers between the first recesses to form gaps between adjacent semiconductor pillars along the third direction; and filling the conductive layer in the second recesses further includes filling the conductive layer in the gaps.

[0010] In some embodiments, after forming the first recesses, the method further includes: removing the sacrificial layers between the first recesses; and filling the insulating layers in the first recesses further includes filling the insulating layers in the gaps between the first recesses; and after forming the second recesses, the method further includes: removing the insulating layers between the first recesses to form gaps between adjacent semiconductor pillars along the third direction; and filling the conductive layer in the second recesses further includes filling the conductive layer in the gaps.

[0011] In some embodiments, the process of forming the first recesses includes a dry etching process, and the process of forming the second recesses includes a dry etching process.

[0012] In some embodiments, forming a plurality of semiconductor pillars extending along a first direction and a plurality of word lines extending along a third direction on a substrate comprises: forming a stack structure on the substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked along the third direction; etching the stack structure to form a plurality of channel trench groups spaced apart along a second direction, each of the channel trench groups being located within the stack structure, each of the channel trench groups comprising a plurality of channel trenches, and semiconductor layers between adjacent channel trenches serving as channel layers, and channel layers corresponding to a same channel trench group serving as a channel region; forming the word lines in the channel trenches; etching the stack structure to form a plurality of isolation trenches extending along the first direction, the isolation trenches being located between the channel trench groups, and remaining semiconductor layers serving as the semiconductor pillars; and filling the isolation trenches with an isolation layer.

[0013] In some embodiments, after forming the channel trench groups, the method further comprises: removing the sacrificial layers between the channel trenches of the channel trench groups to form gaps; and forming the word lines in the channel trenches, the method further comprising: filling the gaps with the word lines.

[0014] In some embodiments, forming the word lines comprises: forming a gate dielectric layer covering surfaces of the channel layers of the semiconductor pillars; forming a conductive layer covering surfaces of the gate dielectric layer and filling the channel trenches, an upper surface of the conductive layer being higher than an upper surface of the stack structure; and patterning the conductive layer to form the word lines, the word lines corresponding one-to-one to the channel trench groups and being spaced apart along the second direction.

[0015] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a semiconductor structure, comprising: a substrate, and a plurality of semiconductor pillars extending along a first direction on the substrate, the semiconductor pillars being spaced apart along a second direction and a third direction, the semiconductor pillars comprising a first doped region, a channel region, and a second doped region, the first doped region and the second doped region being located on opposite sides of the channel region, wherein the channel region comprises a plurality of channel layers parallel to a plane in which the third direction and the first direction lie; and a plurality of word lines extending along the third direction, each of the word lines connecting channel regions of a plurality of the semiconductor pillars along the third direction, the word lines covering at least part of surfaces of the channel layers; the third direction being perpendicular to a surface of the substrate, and the first direction and the second direction both being parallel to the surface of the substrate.

[0016] In some embodiments, the semiconductor structure further comprises: a plurality of bit lines extending along the second direction, each of the bit lines connecting the first doped regions of a plurality of the semiconductor pillars along the second direction; and / or a memory cell extending along the first direction and connected to the second doped regions of the semiconductor pillars.

[0017] In some embodiments, the semiconductor pillars, the word lines, the bit lines, and the memory cell constitute a memory array structure, the memory array structure being arranged along the first direction on the substrate, and in the first direction, two adjacent memory array structures being symmetrically arranged along the bit lines, and semiconductor pillars located at a same layer in the two adjacent memory array structures being connected to a same bit line.

[0018] In some embodiments, the word line surrounds the channel layer of the semiconductor pillar, or the word line is located on both sides of the channel layer along the second direction.

[0019] In some embodiments, the channel layer is an insulating layer or a sacrificial layer along both sides in the third direction.

[0020] In some embodiments, in the second direction, the ratio of the width of the channel layer to the width of the channel region ranges from 0.2 to 0.6.

[0021] The technical solution provided by the semiconductor structure of the embodiment of the present disclosure has at least the following advantages: by forming a plurality of semiconductor pillars extending along the first direction, and arranging the semiconductor pillars along the second direction and the third direction, the arrangement density of the transistor structure formed by the semiconductor pillars can be improved, and the integration density of the semiconductor structure can be improved; the channel region of the semiconductor pillar includes a plurality of channel layers parallel to the plane where the third direction and the first direction are located, which can increase the surface area of the channel region, thereby increasing the contact area between the word line and the channel region of the semiconductor pillar, improving the gate control capability of the transistor structure and reducing power consumption; the word line extends along the third direction, and each word line is connected to a plurality of channel regions of the semiconductor pillars along the third direction, which can increase the control capability of the word line. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting, except as otherwise explicitly provided, the drawings in the accompanying drawings do not constitute proportion limits; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments will be briefly introduced below, and obviously, the drawings in the following description can also be obtained by those skilled in the art without creating labor, and other drawings can also be obtained according to these drawings.

[0023] Figures 1 to 16 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by an embodiment of the present disclosure is provided.

[0024] Figure 17 The semiconductor structure schematic diagram provided by another embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0025] As known from the background, in the research process of 3D DRAM, methods for improving gate control capability and reducing power consumption also need to be further explored.

[0026] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which is at least advantageous in improving the gate control capability of the transistor and reducing power consumption.

[0027] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are presented in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0028] Figures 1 to 16 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figures 6 to 9 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figure 5 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figure 11 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figure 12 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figure 10 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figures 13 to 16 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, Figure 4 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to the drawings, and specifically as follows:

[0029] The manufacturing method of the semiconductor structure comprises:

[0030] Referring to Figure 1 , a substrate 100 is provided.

[0031] For the substrate 100, the material forming the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.

[0032] Referring to Figure 2 and Figure 3 , a plurality of semiconductor pillars 101 extending along a first direction X are formed on a substrate (not shown in the figure), the semiconductor pillars 101 are arranged at intervals along a second direction Y and a third direction Z, the semiconductor pillars 101 comprise a first doped region I, a channel region II and a second doped region III, the first doped region I and the second doped region III are located on opposite sides of the channel region II, wherein the channel region II comprises a plurality of channel layers 102 parallel to the plane of the third direction Z and the first direction X; a plurality of word lines 103 extending along the third direction Z are formed, each word line 103 along the third direction Z connects a plurality of channel regions II of the semiconductor pillars 101, and the word line 103 covers at least part of the surface of the channel layer 102; the third direction Z is perpendicular to the surface of the substrate, and the first direction X and the second direction Y intersect and are both parallel to the surface of the substrate.

[0033] It should be noted that in the present embodiment, the included angle between the first direction X and the second direction Y is 90°; in other embodiments, the included angle between the first direction and the second direction can be 30°, 45° or 60°, and the present embodiment does not constitute a limitation on the included angle between the first direction and the second direction.

[0034] For the semiconductor pillar 101, in some embodiments, the material forming the semiconductor pillar 101 includes an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material can be germanium, silicon, selenium, boron, tellurium or antimony; the compound semiconductor material can be gallium arsenide, indium phosphide, indium antimony, silicon carbide, cadmium sulfide or gallium arsenide silicon, etc. In other embodiments, the material forming the semiconductor pillar 101 can also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide).

[0035] For the first doped region I and the second doped region III, the first doped region I and the second doped region III are located on opposite sides of the channel region II, and in some embodiments, the first doped region I and the second doped region III can each have P-type doping ions; in other embodiments, the first doped region I and the second doped region III can each have N-type doping ions. Specifically, the N-type ions can be phosphorus ions, arsenic ions or antimony ions; the P-type ions can be boron ions, indium ions or boron fluoride ions.

[0036] For the word line 103, the material forming the word line 103 includes at least one of polysilicon, titanium nitride, titanium aluminum, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, molybdenum, titanium or tungsten.

[0037] Further, in some embodiments, the method for manufacturing the semiconductor structure further comprises: forming a plurality of bit lines 104 extending along the second direction Y, each of the plurality of bit lines 104 connecting the first doped regions I of a plurality of semiconductor pillars 101 along the second direction Y; and forming a plurality of memory cells 105 extending along the first direction X and connected to the second doped regions III of the semiconductor pillars 101. By forming the plurality of bit lines 104 extending along the second direction Y and each of the plurality of bit lines 104 connecting the first doped regions I of a plurality of semiconductor pillars 101 along the second direction Y, the control ability of the bit lines 104 can be improved. By forming the plurality of memory cells 105 (e.g. cylindrical capacitors, cup-shaped capacitors) extending along the first direction X and connected to the second doped regions III of the semiconductor pillars 101, the memory cells 105 can extend along a direction parallel to the surface of the substrate 100, thereby facilitating an increase in the length of the memory cells 105 along the first direction X to improve the charge storage ability of the memory cells 105, and avoiding the memory cells from tilting due to an excessively high height.

[0038] Reference Figures 4 to 8 In some embodiments, the plurality of semiconductor pillars 101 extending along the first direction X on the substrate 100 are formed by:

[0039] Reference Figure 4 The stack structure 113 is formed on the substrate 100, and the stack structure 113 comprises sacrificial layers 111 and semiconductor layers 112 alternately stacked along a third direction Z. The stack structure 113 is etched to form a plurality of first grooves 124 spaced along the second direction Y, the first grooves 124 being located in the sacrificial layers 111 and the semiconductor layers 112 and extending along the first direction X. The insulating layers 114 are filled in the first grooves 124. Figure 5

[0040] In the drawings provided in the present embodiment, the stack structure 113 comprises 6 layers of sacrificial layers 111 and semiconductor layers 112 alternately stacked, i.e. the number of layers of the sacrificial layers 111 is 3 and the number of layers of the semiconductor layers 112 is 3. In other embodiments, the stack structure can comprise 4 layers, 8 layers, 10 layers or 12 layers of sacrificial layers and semiconductor layers alternately stacked, i.e. the number of layers of the sacrificial layers and the number of layers of the semiconductor layers are 2, 4, 5 or 6, etc. The present embodiment does not limit the number of layers of the sacrificial layers and the semiconductor layers in the stack structure.

[0041] The material forming the sacrificial layers 111 comprises silicon, germanium, silicon germanium, silicon carbide and gallium arsenide, etc.

[0042] ​For the semiconductor layer 112, the material forming the semiconductor layer 112 includes an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material can be germanium, silicon, selenium, boron, tellurium or antimony; the compound semiconductor material can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide or gallium arsenide silicon, etc. In other embodiments, the material forming the semiconductor layer 112 can also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide).

[0043] In some embodiments, the material forming the semiconductor layer 112 is the same as the material forming the substrate 100; in other embodiments, the material forming the semiconductor layer is different from the material forming the substrate.

[0044] In some embodiments, the process of forming the sacrificial layer 111 and the semiconductor layer 112 can be a deposition process, which can use a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc. In other embodiments, the process of forming the sacrificial layer 111 and the semiconductor layer 112 can be an epitaxial growth process, which can be a molecular beam epitaxial growth process, an atmospheric and reduced pressure epitaxial growth process or an ultrahigh vacuum chemical vapor deposition process, etc.

[0045] For the first recess 124, the process of forming the first recess 124 includes a dry etching process. Since the dry etching is anisotropic, the first recess 124 can be formed by etching the stack structure 113 along the third direction Z through the dry etching process, and the first recess 124 penetrates the stack structure 113 along the third direction Z, so that the formed semiconductor pillars 101 extend along the first direction X and are arranged along the third direction Z.

[0046] For the insulating layer 114, the material forming the insulating layer 114 includes silicon oxide, silicon nitride or silicon oxynitride, etc.

[0047] Reference Figure 6 The semiconductor layer 112 between the first recesses 124 is etched along the third direction Z to form a plurality of second recesses 123 spaced along the second direction Y, the second recesses 123 are located at least between adjacent first recesses 124, and there are a plurality of second recesses 123 between adjacent first recesses 124, the remaining semiconductor layer 112 serves as the semiconductor pillars 101, the semiconductor pillars 101 between the second recesses 123 serve as the channel layer 102, and the channel layer 102 between adjacent first recesses 124 constitutes the channel region II.

[0048] For the second recess 123, the process of forming the second recess 123 includes a dry etching process, and the second recess 123 penetrates the stack structure 113 along the third direction Z. By dry etching, the second recess 123 can have the same etching direction as the first recess 124, so that the channel layer 102 formed thereby can be parallel to the plane in which the first direction X and the third direction Z lie, which is conducive to the subsequent formation of the word line 103 extending along the third direction Z, and the channel regions II of the plurality of semiconductor pillars 101 along the third direction Z can be connected to the same word line 103.

[0049] Referring to Figure 7 In some embodiments, the second recess 123 can also be partially located in the first recess 124. By forming the second recess 123 partially in the first recess 124, the second recess 123 can expose the opposite two surfaces of the channel layer 102 along the second direction Y, which can increase the contact area between the word line and the channel layer 102 when the word line is formed, and improve the gate control capability of the transistor.

[0050] Further, in some embodiments, after the second recess is formed, a conductive layer can be filled in the second recess to form the word line, i.e., along the third direction, the two sides of the channel layer are the sacrificial layer, thereby improving the manufacturing efficiency of the semiconductor structure.

[0051] Referring to Figure 8 In some embodiments, after the second recess 123 is formed, the method further includes: removing the sacrificial layer 111 between the first recess 124 to form a gap 115 between the adjacent semiconductor pillars 101 along the third direction Z; referring to Figure 9 filling the conductive layer in the second recess further includes: filling the conductive layer in the gap. By removing the sacrificial layer 111 between the first recess 124, the opposite two surfaces of the channel layer 102 along the third direction Z can be exposed, so that the word line can surround the surface of the channel layer 102 when the word line is formed, the contact area between the word line and the channel layer 102 is further increased, the contact area between the channel region and the word line of the transistor structure is improved, and the gate control capability of the transistor is improved.

[0052] It can be understood that, along the first direction X, the width of the second recess is equal to the width of the channel region, so that the word line formed after the conductive material is filled in the second recess can pass through the channel layer between the channel region and cover the surface of the channel layer; therefore, along the first direction X, the sacrificial layer and the semiconductor layer at both ends of the second recess are reserved, and when the sacrificial layer between the first recesses is removed after the second recess is formed, the remaining channel layer is supported by the semiconductor layer to avoid collapse of the channel layer.

[0053] Referring to Figure 9In some embodiments, forming multiple word lines 103 extending in a third direction Z includes: forming a gate dielectric layer 116 covering the surface of the channel layer 102 of the semiconductor pillar 101; filling a conductive layer 117 in a second recess 123, the conductive layer 117 covering the surface of the gate dielectric layer 116, and the upper surface of the conductive layer 117 being higher than the upper surface of the channel layer 102; patterning the conductive layer 117 to form word lines 103 and multiple third recesses 125 extending in a first direction X, the third recesses 125 being located between adjacent word lines 103; and filling the third recesses 125 with an insulating material. A gate dielectric layer 116 is formed to cover the surface of the semiconductor layer 112, and a conductive layer 117 is formed to cover the surface of the gate dielectric layer 116 to form the gate structure of the transistor. The conductive layer 117 is formed to fill the second groove 123 and then patterned, which can separate adjacent word lines 103, thereby avoiding short circuits caused by interconnection between adjacent word lines 103 along the second direction Y. The word lines 103 extend along the third direction Z, and the same word line 103 can control transistors formed by multiple semiconductor pillars 101 along the third direction Z, thereby improving the control capability of the word lines 103.

[0054] For the gate dielectric layer 116, the material forming the gate dielectric layer 116 includes silicon oxide, metal oxide, high-K material, etc. For example, the gate dielectric layer is at least one of SiO2, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON.

[0055] For the conductive layer 117, the material forming the conductive layer 117 includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, molybdenum, titanium, or tungsten.

[0056] The insulating material can be silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the insulating material is the same as the material of the insulating layer and is characterized by the same features. In other embodiments, the insulating material may be different from the material of the insulating layer.

[0057] refer to Figures 10 to 12 In other embodiments, after forming the first groove 124, the method further includes: referencing Figure 10 The process of removing the sacrificial layer 111 between the first grooves 124 and filling the gaps between the first grooves 124 with an insulating layer 114 further includes filling the gaps between the first grooves 124 with an insulating layer 114. Removing the sacrificial layer 111 between the first grooves 124 and filling the gaps between the first grooves 124 with an insulating layer 114 can separate the subsequently formed semiconductor pillars 101 by the insulating layer 114, thereby avoiding mutual interference between adjacent semiconductor pillars 101 and improving the stability of the semiconductor structure.

[0058] It can be understood that the provided schematic diagram is only a part of the semiconductor structure, and other structures or material layers can be further provided around the stack structure 113. When the sacrificial layer 111 between the first grooves 124 is removed, the other structures or material layers can serve as support layers for the remaining semiconductor layer 112, so as to avoid collapse of the semiconductor layer 112 after the sacrificial layer 111 is removed.

[0059] Referring to Figure 11 , the semiconductor layer 112 between the first grooves 124 is etched along the third direction Z to form a plurality of second grooves 123 spaced along the second direction Y, the second grooves 123 being located at least between adjacent first grooves 124, and there being a plurality of second grooves 123 between adjacent first grooves 124, the semiconductor layer 112 between the second grooves 123 serving as a channel layer 102, the channel layer 102 between adjacent first grooves 124 constituting a channel region II, and the remaining semiconductor layer 112 serving as a semiconductor pillar 101.

[0060] Referring to Figure 12 , a plurality of word lines 103 extending along the third direction Z are formed, including: forming a gate dielectric layer 116 covering the surface of the channel layer 102 of the semiconductor pillar 101; filling a conductive layer 117 in the second groove 123, the conductive layer 117 covering the surface of the gate dielectric layer 116, and the upper surface of the conductive layer 117 being higher than the upper surface of the stack structure 113; patterning the conductive layer 117 to form the word lines 103 and a plurality of third grooves 125 extending along the first direction X, the third grooves 125 being located between adjacent word lines 103; and filling an insulating material in the third grooves 125.

[0061] By the method for forming the semiconductor pillar and the word line shown in Figures 10 to 12 , in the third direction, both sides of the channel layer are insulating layers, and the formed word line only covers the opposite two surfaces of the channel layer in the second direction, so as to reduce the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure while meeting the requirement of increasing the contact area of the word line and the channel region.

[0062] In some embodiments, after the second grooves 123 are formed, the method further includes: removing the insulating layer 114 between the first grooves 124 to form a gap 115 between adjacent semiconductor pillars 101 in the third direction Z; and filling the conductive layer in the second grooves 123, further including: filling the conductive layer in the gap 115. Thus, the word line structure shown in Figure 9 is formed, so that the conductive layer 117 forms the word line 103 surrounding the channel layer 102 of the semiconductor pillar 101, thereby increasing the contact area of the channel region II of the semiconductor pillar 101 and the word line 103 and improving the gate control capability of the transistor.

[0063] The method for forming the semiconductor pillars and the word lines provided in the above embodiments can first form the semiconductor pillars extending along the first direction and along the second direction and the third direction, then form the channel layers in the channel regions of the semiconductor pillars and fill the conductive material to form the word lines. In other embodiments, the channel layers and the word lines extending along the third direction and covering the surfaces of the channel layers can be first formed, then the isolation grooves along the first direction are formed to separate the word lines and the semiconductor layer to form the plurality of semiconductor pillars.

[0064] Specifically, referring to Figure 4 and Figures 13 to 16 , the method for forming the plurality of semiconductor pillars 101 extending along the first direction X and the plurality of word lines 103 extending along the third direction Z on the substrate 100 comprises: Figure 4 forming a stack structure 113 on the substrate 100, the stack structure 113 comprising the sacrificial layers 111 and the semiconductor layers 112 alternately stacked along the third direction Z; referring to Figure 13 etching the stack structure 113 to form a plurality of channel groove groups 129 spaced apart along the second direction Y, the channel groove groups 129 being located in the stack structure 113, the channel groove groups 129 comprising a plurality of channel grooves 119, and the semiconductor layers 112 between adjacent channel grooves 119 in the channel groove groups 129 serving as the channel layers 102, and the channel layers 102 corresponding to the same channel groove group 129 serving as the channel regions II.

[0065] In some embodiments, the process of forming the channel grooves 119 comprises a dry etching process. The spacing between adjacent channel grooves 119 in the channel groove groups 129 is smaller than the spacing between adjacent channel groove groups 129. It can be understood that the dry etching is anisotropic, and by forming the channel grooves 119 through the dry etching process, all the channel grooves 119 in the channel groove groups 129 can be formed along the third direction Z, so that the remaining semiconductor layers 112 between the channel grooves 119 can all be parallel to the plane of the first direction X and the third direction Z.

[0066] Referring to Figure 14 In some embodiments, after forming the channel groove groups 129, the method further comprises: removing the sacrificial layers 111 between the channel grooves 119 in the channel groove groups 129 to form gaps; and forming the word lines in the channel grooves, further comprising: filling the word lines in the gaps. By removing the sacrificial layers 111 between the channel grooves 119 in the channel groove groups 129 to form the gaps, the opposite two surfaces of the channel layers 102 along the third direction Z can be exposed, and when the word lines are formed by filling the conductive layers in the gaps, the word lines can surround the surfaces of the channel layers 102, thereby increasing the contact area of the channel regions II and the word lines of the transistor structure, and further improving the gate control capability of the transistor.

[0067] Referring to Figure 15The word line 103 is formed in the channel trench 119. Specifically, forming the word line 103 includes: forming the gate dielectric layer 116 covering the surface of the channel layer 102 of the semiconductor pillar 101; forming the conductive layer 117 covering the surface of the gate dielectric layer 116; patterning the conductive layer 117 to form the word line 103 corresponding to the channel trench group 129 and arranged in the second direction Y. Covering the surface of the gate dielectric layer 116 with the conductive layer 117 and patterning the conductive layer 117 can make the word line 103 correspond to the channel trench group 129, extend in the third direction Z, and be arranged in the second direction Y. The same word line 103 can control multiple transistors formed by the semiconductor pillars 101 in the third direction Z, thereby improving the control ability of the word line 103.

[0068] Reference Figure 16 The stack structure 113 is etched to form multiple isolation trenches 135 extending in the first direction X and located between the channel trench groups 129. The isolation layer is filled in the isolation trenches 135, and the remaining semiconductor layer 112 is the semiconductor pillar 101.

[0069] In some embodiments, the process of forming the isolation trench 135 includes a dry etching process. It can be understood that the dry etching is anisotropic. Forming the isolation trench 135 by the dry etching can make the isolation trench 135 have the same etching direction as the channel trench 119, thereby separating the adjacent channel trench groups 129 and etching the stack structure 113 to form the semiconductor pillar 101.

[0070] For the isolation layer, the material for forming the isolation layer includes silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0071] It should be noted that in the embodiments of the present disclosure, the number of channel layers in the channel region of the same semiconductor pillar is 4, and the number of channel layers in the channel region of different semiconductor pillars is the same. In other embodiments, the number of channel layers in the channel region of the same semiconductor pillar can also be 2, 3, 5, or 8, and the number of channel layers in the channel region of different semiconductor pillars can be different. The present embodiment does not limit the number of channel layers in the channel region of the same semiconductor pillar, nor does it limit the number relationship of the channel layers in the channel region of different semiconductor pillars.

[0072] The method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure can improve the arrangement density of the transistor structure formed by the semiconductor pillars and the integration density of the semiconductor structure by forming a plurality of semiconductor pillars extending along a first direction and arranged along a second direction and a third direction; the channel region of the semiconductor pillar includes a plurality of channel layers parallel to the plane where the third direction and the first direction are located, which can increase the surface area of the channel region, thereby increasing the contact area between the word line and the channel region of the semiconductor pillar, improving the gate control capability of the transistor structure and reducing power consumption; the word line extends along the third direction, and each word line along the third direction is connected to the channel region of a plurality of semiconductor pillars, which can increase the control capability of the word line.

[0073] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a semiconductor structure, which is at least beneficial to improve the gate control capability of the transistor structure. It should be noted that the same or corresponding parts as the above-mentioned embodiments can refer to the corresponding description of the foregoing embodiments, which will not be described in detail below.

[0074] Figure 2 、 Figure 3 、 Figure 9 、 Figure 12 and Figure 17 The present disclosure provides a variety of semiconductor structure schematic diagrams, which will be described in detail below in combination with the accompanying drawings, as follows:

[0075] Continuing to refer to Figure 2 and Figure 3 , the semiconductor structure includes a substrate (not shown in the figure) and a semiconductor pillar 101 extending along a first direction X on the substrate, the semiconductor pillar 101 is arranged along a second direction Y and a third direction Z, the semiconductor pillar 101 includes a first doped region I, a channel region II and a second doped region III, the first doped region I and the second doped region III are located on the opposite sides of the channel region II, wherein the channel region II includes a plurality of channel layers 102 parallel to the plane where the third direction Z and the first direction X are located; a plurality of word lines 103 extending along the third direction Z, each word line 103 along the third direction Z is connected to the channel region II of a plurality of semiconductor pillars 101, and the word line 103 covers at least part of the surface of the channel layer 102; the third direction Z is perpendicular to the surface of the substrate, and the first direction X and the second direction Y intersect and are both parallel to the surface of the substrate.

[0076] In some embodiments, the semiconductor structure further comprises: a plurality of bit lines 104 extending along the second direction Y, each bit line 104 connecting the first doped regions I of a plurality of semiconductor pillars 101 along the second direction Y; and a plurality of memory cells 105 extending along the first direction X and connected to the second doped regions III of the semiconductor pillars 101. The bit lines 104 extend along the second direction Y and connect the first doped regions I of a plurality of semiconductor pillars 101 along the second direction Y, which can improve the control ability of the bit lines 104. The memory cells 105 extend along the first direction X and are connected to the second doped regions III of the semiconductor pillars 101, which can make the memory cells 105 extend along a direction parallel to the surface of the substrate, thereby facilitating the increase of the length of the memory cells 105 along the first direction X to improve the charge storage ability of the memory cells 105, and avoiding the collapse of the memory cells due to the excessive height of the memory cells perpendicular to the surface of the substrate.

[0077] Referring to Figure 17 In some embodiments, the semiconductor pillars 101, the word lines 103, the bit lines 104 and the memory cells 105 form a memory array structure (as shown in Figure 2 ), which is arranged along the first direction X on a substrate (not shown in the figure). Along the first direction X, two adjacent memory array structures are symmetrically arranged along the bit lines 104, and the semiconductor pillars 101 at the same layer in the two adjacent memory array structures are connected to the same bit line 104. By arranging the memory array structures along the first direction and symmetrically arranging two adjacent memory array structures along the bit lines, the semiconductor pillars 101 at the same layer in the two adjacent memory array structures can be connected to the same bit line, which further improves the control ability of the bit lines, and the control ends of the bit lines can be reduced, thereby improving the space utilization of the semiconductor structure and facilitating the improvement of the integration density of the semiconductor structure.

[0078] In some embodiments, referring to Figure 9 , the word line surrounds the channel layer of the semiconductor pillar. The word line surrounding the channel layer of the semiconductor pillar can further increase the contact area between the word line and the channel region, thereby improving the gate control ability of the transistor structure.

[0079] In some embodiments, referring to Figure 9 , the gate dielectric layer 116 surrounds the outer surface of the channel layer of the semiconductor pillar.

[0080] In some embodiments, referring to Figure 12 , the word line 103 comprises a first part in contact with at least two surfaces of the channel layer 102 of the semiconductor pillar 112, and a second part connected to a plurality of first parts connected to a plurality of channel layers 102 of the same semiconductor pillar 112, the second part being located above the stack structure, and the second parts of the adjacent word lines 103 are separated by a third recess 125 filled with an insulating material.

[0081] In some embodiments, referring to Figure 12 The word line 103 covers two opposite side surfaces of the channel layer 102 of the semiconductor pillar 112 along the second direction Y, and covers two opposite side surfaces of the filling insulating layer 114 between the channel layers 102 along the third direction Z along the second direction Y.

[0082] In some embodiments, two sides of the channel layer along the third direction are insulating layers or sacrificial layers, which can serve as supports between the channel layers along the third direction to improve the stability of the semiconductor structure.

[0083] In some embodiments, the ratio of the width of the channel layer to the width of the channel region along the second direction is in the range of 0.2-0.6. It can be understood that the plurality of channel layers of the same semiconductor pillar constitute the channel region, and the thinner the thickness of the channel layer along the second direction, the more the number of corresponding channel layers, and the larger the surface area of the channel region constituted by the channel layer. However, too thin channel layer can result in that the first doped region and the second doped region along the first direction cannot be electrically connected through the channel region; when the thickness of the channel layer is too thick, it can be difficult to form multiple channel layers in the same channel region. Therefore, the ratio of the width of the channel layer to the width of the channel region along the second direction needs to be adjusted within a certain range to increase the contact area of the channel region and the word line while avoiding affecting the performance of the semiconductor structure.

[0084] The semiconductor structure provided by the embodiments of the present disclosure has a plurality of semiconductor pillars extending along the first direction, and the semiconductor pillars are arranged along the second direction and the third direction, which can improve the arrangement density of the transistor structure formed by the semiconductor pillars and improve the integration density of the semiconductor structure; the channel region of the semiconductor pillar includes a plurality of channel layers parallel to the plane where the third direction and the first direction are located, which can increase the surface area of the channel region, thereby increasing the contact area of the word line and the channel region of the semiconductor pillar, improving the gate control ability of the transistor structure and reducing power consumption; the word line extends along the third direction, and each word line along the third direction is connected to the channel region of a plurality of semiconductor pillars, which can increase the control ability of the word line.

[0085] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising sacrificial layers and semiconductor layers alternately stacked along a third direction; etching the stack structure to form a plurality of first recesses spaced along a second direction, the first recesses being located in the sacrificial layers and the semiconductor layers and extending along a first direction; filling insulating layers in the first recesses; etching the semiconductor layers between the first recesses along the third direction to form a plurality of second recesses spaced along the second direction, the remaining semiconductor layers serving as semiconductor pillars, the second recesses being located at least between adjacent first recesses, and there being a plurality of the second recesses between adjacent first recesses, the semiconductor pillars between the second recesses serving as channel layers, the channel layers between adjacent first recesses constituting channel regions; the semiconductor pillars extending along the first direction and being spaced along the second and third directions, the semiconductor pillars comprising first doped regions, channel regions, and second doped regions, the first doped regions and the second doped regions being located on opposite sides of the channel regions, wherein the channel regions comprise a plurality of channel layers parallel to a plane in which the third direction and the first direction lie; forming a plurality of word lines extending along the third direction, each of the word lines along the third direction connecting the channel regions of a plurality of the semiconductor pillars, the word lines covering at least part of the surfaces of the channel layers; the third direction being perpendicular to the surface of the substrate, the first direction and the second direction both being parallel to the surface of the substrate.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein After forming the word lines, further comprising: forming a plurality of bit lines extending along the second direction, each of the bit lines along the second direction connecting the first doped regions of a plurality of the semiconductor pillars; and / or forming memory cells extending along the first direction and connected to the second doped regions of the semiconductor pillars.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein forming the plurality of word lines extending along the third direction, comprising: forming a gate dielectric layer covering the surfaces of the channel layers of the semiconductor pillars; filling a conductive layer in the second recesses, the conductive layer covering the surfaces of the gate dielectric layer; patterning the conductive layer to form the word lines and a plurality of third recesses extending along the first direction, the third recesses being located between adjacent word lines; filling insulating material in the third recesses.

4. The method of manufacturing a semiconductor structure according to claim 3, wherein After forming the second recesses, further comprising: removing the sacrificial layers between the first recesses to form gaps between adjacent semiconductor pillars along the third direction; filling the conductive layer in the second recesses further comprises filling the conductive layer in the gaps.

5. The method of manufacturing a semiconductor structure according to claim 3, wherein After forming the first recesses, further comprising: removing the sacrificial layers between the first recesses; filling the insulating layers in the first recesses further comprises filling the insulating layers in gaps between the first recesses; After forming the second recesses, further comprising: removing the insulating layers between the first recesses to form gaps between adjacent semiconductor pillars along the third direction; filling the conductive layer in the second recesses further comprises filling the conductive layer in the gaps.

6. The method of manufacturing a semiconductor structure according to claim 3, wherein The process of forming the first groove comprises a dry etching process, and the process of forming the second groove comprises a dry etching process.

7. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a stack structure on the substrate, the stack structure comprising sacrificial layers and semiconductor layers alternately stacked along a third direction; etching the stack structure to form a plurality of channel trench groups spaced apart in a second direction, the channel trench groups being located in the stack structure, the channel trench groups comprising a plurality of channel trenches, the semiconductor layers between adjacent channel trenches serving as channel layers, the channel layers corresponding to the same channel trench group serving as channel regions, and the remaining semiconductor layers serving as semiconductor pillars; the semiconductor pillars extending along a first direction and being spaced apart along the second direction and the third direction, the semiconductor pillars comprising first doped regions, channel regions, and second doped regions, the first doped regions and the second doped regions being located on opposite sides of the channel regions, wherein the channel regions comprise a plurality of channel layers parallel to a plane in which the third direction and the first direction lie; forming word lines extending along the third direction in the channel trenches, each of the word lines along the third direction connecting the channel regions of a plurality of the semiconductor pillars, the word lines covering at least part of the surfaces of the channel layers; etching the stack structure to form a plurality of isolation trenches extending along the first direction, the isolation trenches being located between the channel trench groups, and the remaining semiconductor layers serving as the semiconductor pillars; filling the isolation trenches with an isolation layer; the third direction being perpendicular to a surface of the substrate, and the first direction and the second direction intersecting and being parallel to the surface of the substrate.

8. The method of manufacturing a semiconductor structure according to claim 7, wherein After forming the channel trench groups, the method further comprises: removing the sacrificial layers between the channel trenches in the channel trench groups to form gaps; and forming the word lines extending along the third direction in the channel trenches, and further comprises: filling the gaps with the word lines.

9. The method of manufacturing a semiconductor structure according to claim 7, wherein The method of forming the word lines comprises: forming a gate dielectric layer covering the surfaces of the channel layers of the semiconductor pillars; forming a conductive layer covering the surfaces of the gate dielectric layer and filling the channel trenches, an upper surface of the conductive layer being higher than an upper surface of the stack structure; patterning the conductive layer to form the word lines, the word lines corresponding one-to-one to the channel trench groups and being spaced apart along the second direction.

10. A semiconductor structure, characterized by The method comprises: a substrate, and semiconductor pillars extending along a first direction on the substrate, the semiconductor pillars being spaced apart along a second direction and a third direction, the semiconductor pillars comprising first doped regions, channel regions, and second doped regions, the first doped regions and the second doped regions being located on opposite sides of the channel regions, wherein the channel regions comprise a plurality of channel layers parallel to a plane in which the third direction and the first direction lie; a first doped region, a plurality of channel layers, and a second doped region included in each of the semiconductor pillars being an integrally formed structure, wherein a first doped region connects one side of the corresponding plurality of channel layers, and a second doped region connects the other side of the corresponding plurality of channel layers; a plurality of word lines extending along the third direction, each of the word lines connecting the channel regions of a plurality of the semiconductor pillars along the third direction, the word lines covering at least part of the surfaces of the channel layers; the third direction is perpendicular to the substrate surface, and the first direction and the second direction are both parallel to the substrate surface.

11. The semiconductor structure of claim 10, wherein, The semiconductor structure further comprises: a plurality of bit lines extending along the second direction, each of the bit lines connecting the first doped regions of a plurality of the semiconductor pillars along the second direction; and / or a storage unit extending along the first direction and connected to the second doped regions of the semiconductor pillars.

12. The semiconductor structure of claim 11, wherein, The semiconductor pillars, the word lines, the bit lines and the storage unit constitute a storage array structure, the storage array structure being arranged along the first direction on the substrate, in the first direction, two adjacent storage array structures are symmetrically arranged along the bit lines, and the semiconductor pillars at the same layer in the two adjacent storage array structures are connected to the same bit line.

13. The semiconductor structure of claim 10, wherein, The word lines surround the channel layers of the semiconductor pillars, or the word lines are located on both sides of the channel layers along the second direction.

14. The semiconductor structure of claim 10, wherein, The channel layers are surrounded by insulating layers or sacrificial layers along the third direction.

15. The semiconductor structure of claim 10, wherein, In the second direction, the ratio of the width of the channel layer to the width of the channel region ranges from 0.2 to 0.6.

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