Display substrate and display panel

Abstract

A display substrate and a panel. The display substrate comprises: a plurality of sub-pixels, a first voltage line, a scan signal line, a first light-emitting control signal line and a second light-emitting control signal line, each sub-pixel comprising a pixel circuit and a light-emitting element, the pixel circuit comprising: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit and a data writing sub-circuit, the first light-emitting control sub-circuit being electrically connected to a first end of the driving sub-circuit, a first electrode of the light-emitting element and the first light-emitting control signal line; the second light-emitting control sub-circuit being electrically connected to a second end of the driving sub-circuit, the first voltage line and the second light-emitting control signal line; the data writing sub-circuit being electrically connected to the second end of the driving sub-circuit and the scan signal line; the first light-emitting control signal line, the scan signal line and the second light-emitting control signal line extend along a first direction and are arranged along a second direction, in the second direction, the scan signal line is located between the first light-emitting control signal line and the second light-emitting control signal line.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display panel. Background Technology

[0002] With the rapid development of organic light-emitting diodes (OLEDs) in the display field, people have increasingly higher requirements for display quality. Due to their advantages such as high display quality, high-resolution display devices are being used more and more widely. In the display field, a crucial technology is the layout design of pixel circuits. Summary of the Invention

[0003] This disclosure provides a display substrate in several embodiments. The display substrate includes a substrate and a plurality of sub-pixels, a first voltage line, a data line, a scan signal line, a first light-emitting control signal line, and a second light-emitting control signal line disposed on the substrate. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and a data writing sub-circuit. The first light-emitting control sub-circuit is electrically connected to a first terminal of the driving sub-circuit, a first electrode of the light-emitting element, and the first light-emitting control signal line, and is configured to control the connection between the first terminal of the driving sub-circuit and the first electrode of the light-emitting element to be turned on or off under the control of a first light-emitting control signal on the first light-emitting control signal line. The second light-emitting control sub-circuit is electrically connected to the driving sub-circuit. The second terminal of the driving sub-circuit, the first voltage line, and the second light-emitting control signal line are configured to control the connection between the second terminal of the driving sub-circuit and the first voltage line to be turned on or off under the control of the second light-emitting control signal on the second light-emitting control signal line; the data writing sub-circuit is electrically connected to the second terminal of the driving sub-circuit, the data line, and the scan signal line, and is configured to transmit the data voltage on the data line to the second terminal of the driving sub-circuit under the control of the scan signal on the scan signal line; the first light-emitting control signal line, the scan signal line, and the second light-emitting control signal line extend along a first direction and are arranged along a second direction that is not parallel to the first direction, in which the scan signal line is located between the first light-emitting control signal line and the second light-emitting control signal line in the second direction.

[0004] For example, in some embodiments of the display substrate provided in this disclosure, the pixel circuit further includes a storage capacitor, the first electrode plate of the storage capacitor is electrically connected to the control terminal of the driving sub-circuit, the second electrode plate of the storage capacitor is electrically connected to the first voltage line, and in the second direction, the orthographic projection of the first light emission control signal line on the substrate and the orthographic projection of the second light emission control signal line on the substrate are located on both sides of the orthographic projection of the second electrode plate of the storage capacitor on the substrate.

[0005] For example, in some embodiments of the display substrate provided in this disclosure, in the second direction, the orthographic projection of the scanning signal line on the substrate and the orthographic projection of the second light emission control signal line on the substrate are located on both sides of the orthographic projection of the second electrode plate of the storage capacitor on the substrate.

[0006] For example, some embodiments of this disclosure provide a display substrate that further includes a reset signal line and an initial signal line disposed on the substrate. The pixel circuit further includes a reset sub-circuit and a threshold compensation sub-circuit. The reset sub-circuit is electrically connected to the control terminal of the driving sub-circuit, the initial signal line, the first light emission control signal line, and the reset signal line, and is configured to transmit an initial voltage on the initial signal line to the control terminal of the driving sub-circuit under the control of the first light emission control signal and the reset control signal on the reset signal line. The threshold compensation sub-circuit is electrically connected to the control terminal and the first terminal of the driving sub-circuit and the reset signal line, and is configured to control the connection between the first terminal of the driving sub-circuit and the control terminal of the driving sub-circuit to be turned on or off under the control of the reset control signal. The reset signal line extends along the first direction, and in the second direction, the reset signal line is located on the side of the first light emission control signal line away from the scan signal line.

[0007] For example, in some embodiments of the display substrate provided in this disclosure, the reset sub-circuit includes a first reset transistor, the first reset transistor includes a reset active layer, the reset active layer includes a first reset active layer portion, the threshold compensation sub-circuit includes a threshold compensation transistor, the threshold compensation transistor includes a compensation active layer, the compensation active layer includes a first compensation active layer portion, the orthographic projection of the first reset active layer portion on the substrate and the orthographic projection of the initial signal line on the substrate at least partially overlap, and the orthographic projection of the first compensation active layer portion on the substrate and the orthographic projection of the initial signal line on the substrate at least partially overlap.

[0008] For example, in some embodiments of the present disclosure, the initial signal line includes a first sub-initial signal line that extends along the first direction. The orthographic projection of the first reset active layer portion on the substrate and the orthographic projection of the first compensation active layer portion on the substrate are both located within the orthographic projection of the first sub-initial signal line on the substrate.

[0009] For example, in some embodiments of the present disclosure, the first reset active layer portion and the first compensation active layer portion are arranged sequentially in the first direction.

[0010] For example, in some embodiments of the present disclosure, the initial signal line further includes a second sub-initial signal line, which extends along the second direction, and the first sub-initial signal line and the second sub-initial signal line are electrically connected.

[0011] For example, in some embodiments of the present disclosure, the display substrate includes an active semiconductor layer, a first conductive layer, a second conductive layer, and a source / drain metal layer. In a direction perpendicular to the substrate, the active semiconductor layer is located between the substrate and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, the second conductive layer is located between the first conductive layer and the source / drain metal layer, the first sub-initial signal line is located in the second conductive layer, and the second sub-initial signal line is located in the source / drain metal layer.

[0012] For example, in some embodiments of the display substrate provided in this disclosure, the reset active layer further includes a second reset active layer portion, the compensation active layer includes a second compensation active layer portion, the orthographic projection of the second reset active layer portion on the substrate and the orthographic projection of the reset signal line on the substrate at least partially overlap, the orthographic projection of the second compensation active layer portion on the substrate and the orthographic projection of the reset signal line on the substrate at least partially overlap, and the second reset active layer portion and the second compensation active layer portion are arranged sequentially in the first direction.

[0013] For example, in some embodiments of the display substrate provided in this disclosure, both the first reset transistor and the threshold compensation transistor are dual-gate transistors.

[0014] For example, in some embodiments of the present disclosure, the display substrate includes an active semiconductor layer and a first conductive layer. In a direction perpendicular to the substrate, the active semiconductor layer is located between the substrate and the first conductive layer. The reset signal line, the scan signal line, the first light emission control signal line, and the second light emission control signal line are all located in the first conductive layer.

[0015] For example, in some embodiments of the display substrate provided in this disclosure, under the control of the first light emission control signal and the reset control signal, the initial voltage is transmitted to the first electrode of the light emission element via the reset sub-circuit, the threshold compensation sub-circuit, and the first light emission control sub-circuit.

[0016] For example, in some embodiments of the display substrate provided in this disclosure, the driving sub-circuit includes a driving transistor, the control terminal of the driving sub-circuit includes the gate of the driving transistor, the first terminal of the driving circuit includes the first electrode of the driving transistor, and the second terminal of the driving circuit includes the second electrode of the driving transistor; the first light-emitting control sub-circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage line; the second light-emitting control sub-circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected to the first voltage line. The data writing sub-circuit includes a data writing transistor, the gate of which is electrically connected to the scan signal line, the first terminal of which is electrically connected to the data line, and the second terminal of which is electrically connected to the second terminal of the driving transistor. The reset sub-circuit includes a first reset transistor and a second reset transistor, the gate of which is electrically connected to the reset signal line, the first terminal of which is electrically connected to the initial signal line, and the second terminal of which is electrically connected to the first terminal of the second reset transistor. The gate of the second reset transistor is electrically connected to the first light emission control signal line, and the second terminal of which is electrically connected to the gate of the driving transistor. The threshold compensation sub-circuit includes a threshold compensation transistor, the gate of which is electrically connected to the reset signal line, the first terminal of which is electrically connected to the first terminal of the driving transistor, and the second terminal of which is electrically connected to the gate of the driving transistor.

[0017] For example, in some embodiments of the present disclosure, the display substrate includes an active semiconductor layer, a first conductive layer, a second conductive layer, a source / drain metal layer, and a planarization layer. In a direction perpendicular to the substrate, the active semiconductor layer is located between the substrate and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, the second conductive layer is located between the first conductive layer and the source / drain metal layer, and the planarization layer is located on the side of the source / drain metal layer away from the substrate. The second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a first via penetrating the planarization layer. In the second direction, the orthographic projection of the first via on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate.

[0018] For example, in some embodiments of the present disclosure, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located between the active semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, and the third insulating layer is located between the second conductive layer and the source-drain metal layer. The portion of the active semiconductor layer corresponding to the second electrode of the first light-emitting control transistor is electrically connected to a first connection electrode in the source-drain metal layer through a second via penetrating the first insulating layer, the second insulating layer, and the third insulating layer. The first connection electrode is electrically connected to the second electrode of the first light-emitting control transistor and is electrically connected to the first electrode of the light-emitting element through the first via.

[0019] For example, in some embodiments of the present disclosure, in the second direction, the orthogonal projection of the first via on the substrate is located between the orthogonal projection of the scan signal line on the substrate and the orthogonal projection of the first light emission control signal line on the substrate.

[0020] For example, in some embodiments of the present disclosure, the first voltage line includes a first sub-voltage line and a second sub-voltage line, the first sub-voltage line and the second sub-voltage line are electrically connected, the first sub-voltage line extends along the second direction, and the second sub-voltage line extends along the first direction.

[0021] For example, in some embodiments of the present disclosure, the pixel circuits of the plurality of sub-pixels are arranged in an array along the first direction and the second direction.

[0022] For example, in some embodiments of the display substrate provided in this disclosure, the initial signal line includes a first sub-initial signal line and a second sub-initial signal line. The first sub-initial signal line extends along a first direction, and the second sub-initial signal line extends along a second direction. The first sub-initial signal line and the second sub-initial signal line are electrically connected. The data line extends along the second direction. The first sub-voltage line, the data line, and the second sub-initial signal line are located on the same layer. The data line, the first sub-voltage line, and the second sub-initial signal line are arranged along the first direction, and in the first direction, the first sub-voltage line is located between the data line and the second sub-initial signal line.

[0023] For example, in some embodiments of the present disclosure, the plurality of sub-pixels include a plurality of sub-pixel pairs, the plurality of sub-pixel pairs are arranged in an array along the first direction and the second direction, each sub-pixel pair includes two adjacent sub-pixels in the first direction, and the pixel circuits of the two sub-pixels are mirror-symmetrical along an axis of symmetry parallel to the second direction.

[0024] For example, in some embodiments of the display substrate provided in this disclosure, the initial signal line includes a first sub-initial signal line and a second sub-initial signal line. The first sub-initial signal line extends along a first direction, and the second sub-initial signal line extends along a second direction. The first sub-initial signal line and the second sub-initial signal line are electrically connected. The data line extends along the second direction. The first sub-voltage line, the data line, and the second sub-initial signal line are located on the same layer. The data line, the first sub-voltage line, and the second sub-initial signal line are arranged along the first direction, and in the first direction, the data line is located between the first sub-voltage line and the second sub-initial signal line.

[0025] For example, in some embodiments of the present disclosure, for two sub-pixel pairs that are adjacent in the first direction among the plurality of sub-pixel pairs, the pixel circuits of the two sub-pixels that are adjacent to each other in the first direction are electrically connected to the same first sub-voltage line.

[0026] For example, in some embodiments of the display substrate provided in this disclosure, the shape of the first light-emitting control signal line is a curved shape or a straight shape.

[0027] For example, in some embodiments of the display substrate provided in this disclosure, the first direction and the second direction are perpendicular to each other.

[0028] Some embodiments of this disclosure also provide a display panel, including the display substrate according to any of the above embodiments. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0030] Figure 1 A schematic block diagram of a display substrate provided for some embodiments of this disclosure;

[0031] Figure 2A This is a schematic diagram of the structure of a pixel circuit provided in some embodiments of this disclosure;

[0032] Figure 2B A circuit timing diagram of a pixel circuit provided for some embodiments of this disclosure;

[0033] Figure 3 This is a schematic diagram of the layout of a pixel circuit provided for some embodiments of this disclosure;

[0034] Figure 4A-4M This is a schematic diagram showing the layout of the various structural layers of a pixel circuit provided in some embodiments of this disclosure;

[0035] Figure 4N A schematic diagram of the structure of a source / drain metal layer provided in some other embodiments of this disclosure;

[0036] Figure 4O A schematic diagram of the structure of a planarization layer provided for other embodiments of this disclosure;

[0037] Figure 4P This is a schematic diagram showing the stacking position relationship of the active semiconductor layer, the first conductive layer, the second conductive layer, the third insulating layer, the source / drain metal layer, and the planarization layer provided for other embodiments of this disclosure;

[0038] Figure 5A for Figure 4M A schematic diagram of the cross-sectional structure at point A on the central line;

[0039] Figure 5B for Figure 4M A schematic diagram of the cross-sectional structure at point B on the middle line;

[0040] Figure 6A-6M A schematic diagram showing the layout of the various structural layers of a pixel circuit provided for other embodiments of this disclosure;

[0041] Figure 7A for Figure 6M A schematic diagram of the cross-sectional structure at point A' in the middle line;

[0042] Figure 7B for Figure 6M A schematic diagram of the cross-sectional structure at point B' in the middle line;

[0043] Figure 8 A schematic diagram of the structure of a first conductive layer provided for other embodiments of this disclosure;

[0044] Figure 9 This is a schematic diagram of a display panel provided for at least one embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0048] This disclosure provides at least some embodiments of a display substrate and a display panel. The display substrate includes: a substrate and a plurality of sub-pixels, a first voltage line, a data line, a scan signal line, a first light-emitting control signal line, and a second light-emitting control signal line disposed on the substrate. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit includes: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and a data writing sub-circuit. The first light-emitting control sub-circuit is electrically connected to a first terminal of the driving sub-circuit, a first electrode of the light-emitting element, and the first light-emitting control signal line, and is configured to control the connection between the first terminal of the driving sub-circuit and the first electrode of the light-emitting element to be turned on or off under the control of a first light-emitting control signal on the first light-emitting control signal line. The second light-emitting control sub-circuit... The control sub-circuit is electrically connected to the second terminal of the drive sub-circuit, the first voltage line, and the second light-emitting control signal line, and is configured to control the connection between the second terminal of the drive sub-circuit and the first voltage line to be turned on or off under the control of the second light-emitting control signal on the second light-emitting control signal line; the data writing sub-circuit is electrically connected to the second terminal of the drive sub-circuit, the data line, and the scan signal line, and is configured to transmit the data voltage on the data line to the second terminal of the drive sub-circuit under the control of the scan signal on the scan signal line; the first light-emitting control signal line, the scan signal line, and the second light-emitting control signal line extend along a first direction and are arranged along a second direction that is not parallel to the first direction, wherein the scan signal line is located between the first light-emitting control signal line and the second light-emitting control signal line in the second direction.

[0049] In this display substrate, by extending the first light-emitting control signal line, the scanning signal line, and the second light-emitting control signal line along the first direction and arranging them sequentially along the second direction, the number of traces can be reduced, the light-transmitting space can be increased, and the photosensitive element below the pixel circuit can better perform light sensing. In addition, this display substrate has a simple structure, is easy to design and manufacture, and has a low cost.

[0050] The following describes some embodiments of the present disclosure in detail with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0051] Figure 1 This is a schematic block diagram of a display substrate provided in some embodiments of the present disclosure. Figure 2A This is a schematic diagram of the structure of a pixel circuit provided in some embodiments of this disclosure. Figure 2B This is a circuit timing diagram of a pixel circuit provided for some embodiments of this disclosure.

[0052] For example, such as Figure 1 As shown, the display substrate 100 provided in the embodiments of this disclosure includes a substrate 10 and a plurality of sub-pixels 12, a first voltage line, a data line, a scan signal line, a first light emission control signal line, and a second light emission control signal line disposed on the substrate 10. It should be noted that... Figure 1 The first voltage line, data line, scan signal line, first light emission control signal line, and second light emission control signal line are not shown.

[0053] For example, the display substrate 100 can be applied to a display panel, such as an active matrix organic light-emitting diode (AMOLED) display panel. The display substrate 100 can be an array substrate.

[0054] For example, the substrate 10 can be a flexible substrate or a rigid substrate. For example, the substrate 10 can be made of glass, plastic, quartz or other suitable materials, and the embodiments disclosed herein are not limited thereto.

[0055] For example, each sub-pixel 12 includes a light-emitting element 121 and a pixel circuit 120, with the light-emitting element 121 located on the side of the pixel circuit 120 away from the substrate 10. The pixel circuit 120 is configured to drive the light-emitting element 121 to emit light. (The following is in conjunction with...) Figure 2A and Figure 2B The pixel electrode and its working principle are explained.

[0056] For example, such as Figure 2A As shown, the pixel circuit 120 includes a driving sub-circuit 200, a first light emission control sub-circuit 210, a second light emission control sub-circuit 220, and a data writing sub-circuit 230.

[0057] For example, such as Figure 2A As shown, the first light-emitting control sub-circuit 210 is electrically connected to the first end of the driving sub-circuit 200, the first electrode of the light-emitting element 121, and the first light-emitting control signal line EM1, and is configured to control the connection between the first end of the driving sub-circuit 200 and the first end of the light-emitting element 121 to be turned on or off under the control of the first light-emitting control signal on the first light-emitting control signal line EM1.

[0058] For example, such as Figure 2A As shown, the second light-emitting control sub-circuit 220 is electrically connected to the second terminal of the driving sub-circuit 200, the first voltage line VDD, and the second light-emitting control signal line EM2, and is configured to control the connection between the second terminal of the driving sub-circuit 200 and the first voltage line VDD to be turned on or off under the control of the second light-emitting control signal on the second light-emitting control signal line EM2.

[0059] For example, such as Figure 2A As shown, the data writing sub-circuit 230 is electrically connected to the second terminal of the driving sub-circuit 200, the data line Vda and the scan signal line Ga, and is configured to transmit the data voltage on the data line Vda to the second terminal of the driving sub-circuit 200 under the control of the scan signal on the scan signal line Ga.

[0060] For example, such as Figure 2A As shown, the second electrode of the light-emitting element 121 is electrically connected to the second voltage line VSS.

[0061] For example, the light-emitting element 121 can be a light-emitting diode (LED). The LED can be a micro LED, an organic light-emitting diode (OLED), or a quantum dot LED (QLED). The light-emitting element 121 is configured to receive a light-emitting signal (e.g., a drive current) and emit light of an intensity corresponding to the light-emitting signal during operation. The light-emitting element 121 may include a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes. The first electrode of the light-emitting element 121 can be an anode, and the second electrode of the LED can be a cathode. It should be noted that, in embodiments of this disclosure, the light-emitting layer of the light-emitting element may include an electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. Generally, the light-emitting element 121 has a light-emitting threshold voltage, and emits light when the voltage between the first and second electrodes of the light-emitting element 121 is greater than or equal to the light-emitting threshold voltage. In practical applications, the specific structure of the light-emitting element 121 can be designed and determined according to the actual application environment, and no limitation is made here.

[0062] For example, such as Figure 2A As shown, the pixel circuit 120 also includes a storage capacitor Cst. The first electrode plate CC1 of the storage capacitor Cst is electrically connected to the control terminal of the driving sub-circuit 200, and the second electrode plate CC2 of the storage capacitor Cst is electrically connected to the first voltage line VDD.

[0063] For example, such as Figure 2A As shown, the display substrate 100 also includes a reset signal line Rt and an initial signal line Vinit disposed on the substrate 10. The pixel circuit 120 also includes a reset sub-circuit 240 and a threshold compensation sub-circuit 250.

[0064] For example, the reset sub-circuit 240 is electrically connected to the control terminal, initial signal line Vinit, first light emission control signal line EM1, and reset signal line Rt of the driver sub-circuit 200, and is configured to transmit the initial voltage on the initial signal line Vinit to the control terminal of the driver sub-circuit 200 under the control of the first light emission control signal and the reset control signal on the reset signal line Rt.

[0065] For example, the threshold compensation sub-circuit 250 is electrically connected to the control terminal and the first terminal of the drive sub-circuit 200 and the reset signal line Rt, and is configured to control the connection between the first terminal of the drive sub-circuit 200 and the control terminal of the drive sub-circuit 200 to be turned on or off under the control of the reset control signal on the reset signal line Rt.

[0066] For example, when the reset subcircuit 240 transmits the initial voltage output from the initial signal line Vinit to the control terminal of the drive subcircuit 200 to initialize the control terminal of the drive subcircuit 200, the threshold compensation subcircuit 250 is configured to be turned on under the control of the reset control signal. Simultaneously, the first light-emitting control subcircuit 210 is turned on under the control of the first light-emitting control signal. Thus, the initial voltage can be transmitted to the first electrode of the light-emitting element 121 via the threshold compensation subcircuit 250 and the first light-emitting control subcircuit 210 to initialize the first electrode of the light-emitting element 121. In other words, under the control of the first light-emitting control signal and the reset control signal, the initial voltage is transmitted to the control terminal of the drive subcircuit 200 via the reset subcircuit 240, and to the first electrode of the light-emitting element 121 via the reset subcircuit 240, the threshold compensation subcircuit 250, and the first light-emitting control subcircuit 210, thereby simultaneously initializing both the control terminal of the drive subcircuit 200 and the first electrode of the light-emitting element 121.

[0067] For example, such as Figure 2A As shown, the driving sub-circuit 200 includes a driving transistor T3. The control terminal of the driving sub-circuit 200 includes the gate of the driving transistor T3. The first terminal of the driving sub-circuit 200 includes the first electrode of the driving transistor T3, and the second terminal of the driving sub-circuit 200 includes the second electrode of the driving transistor T3. The gate of the driving transistor T3 is electrically connected to the first node N1, the second electrode of the driving transistor T3 is electrically connected to the second node N2, and the first electrode of the driving transistor T3 is electrically connected to the third node N3.

[0068] The first light-emitting control sub-circuit 210 includes a first light-emitting control transistor T6. The gate of the first light-emitting control transistor T6 is electrically connected to the first light-emitting control signal line EM1. The first electrode of the first light-emitting control transistor T6 is electrically connected to the third node N3, that is, electrically connected to the first electrode of the driving transistor T3. The second electrode of the first light-emitting control transistor T6 is electrically connected to the fourth node N4. The first electrode of the light-emitting element 121 is electrically connected to the fourth node N4. In other words, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 121.

[0069] The second light-emitting control sub-circuit 220 includes a second light-emitting control transistor T5. The gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2. The first electrode of the second light-emitting control transistor T5 is electrically connected to the second node N2, that is, electrically connected to the second electrode of the driving transistor T3. The second electrode of the second light-emitting control transistor T5 is electrically connected to the first voltage line VDD.

[0070] The data writing sub-circuit 230 includes a data writing transistor T4. The gate of the data writing transistor T4 is electrically connected to the scan signal line Ga. The first terminal of the data writing transistor T4 is electrically connected to the data line Vda. The second terminal of the data writing transistor T4 is electrically connected to the second node N2, that is, electrically connected to the second terminal of the driving transistor T3.

[0071] The reset sub-circuit 240 includes a first reset transistor T1 and a second reset transistor T7. The gate of the first reset transistor T1 is electrically connected to the reset signal line Rt, the first terminal of the first reset transistor T1 is electrically connected to the initial signal line Vinit, and the second terminal of the first reset transistor T1 is electrically connected to the first terminal of the second reset transistor T7. The gate of the second reset transistor T7 is electrically connected to the first light-emitting control signal line EM1, and the second terminal of the second reset transistor T7 is electrically connected to the first node N1, that is, electrically connected to the gate of the driving transistor T3.

[0072] The threshold compensation sub-circuit 250 includes a threshold compensation transistor T2, the gate of which is electrically connected to the reset signal line Rt, the first terminal of which is electrically connected to the third node N3, i.e., electrically connected to the first terminal of the driving transistor T3, and the second terminal of which is electrically connected to the first node N1, i.e., electrically connected to the gate of the driving transistor T3.

[0073] For example, in some embodiments, the first reset transistor T1 and the threshold compensation transistor T2 are both dual-gate transistors, which can reduce the leakage current of the first reset transistor T1 and the threshold compensation transistor T2, which are electrically connected to the gate of the driving transistor T3, and ensure the voltage of the gate of the driving transistor T3 is stable.

[0074] For example, the voltage output from the first voltage line VDD and the voltage output from the second voltage line VSS may be either high or low. Figure 2A In the illustrated embodiment, the voltage output by the first voltage line VDD is a constant first voltage, which is a positive voltage; while the voltage output by the second voltage line VSS is a constant second voltage, which is a negative voltage, and so on. For example, in some examples, the second voltage line VSS may be grounded.

[0075] For example, according to the characteristics of transistors, transistors can be classified into N-type transistors and P-type transistors. For the sake of clarity, in the embodiments of the present disclosure, the transistors are taken as P-type transistors (e.g., P-type MOS transistors) to elaborate the technical solutions of the present disclosure in detail. That is to say, in the description of the present disclosure, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T6, the second light emission control transistor T5, the first reset transistor T1, the second reset transistor T7, etc. can all be P-type transistors, thereby reducing the manufacturing process. However, the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to the actual application environment, which is not limited herein.

[0076] It should be noted that the transistors adopted in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors can include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, polycrystalline silicon thin film transistors, etc. The source and drain of the transistor can be symmetric in structure, so there is no physical difference between its source and drain. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. Therefore, the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0077] For example, in specific implementation, in the embodiments of the present disclosure, the initial voltage V output by the initial signal line Vinit i and the voltage V output by the second voltage line VSS s can satisfy the following formula: V i -V s < VEL, so as to avoid the light emitting element 121 from emitting light in the non-light emitting stage (e.g., the initialization stage p1 to be described below). VEL represents the light emitting threshold voltage of the light emitting element 121.

[0078] Next, in conjunction with Figure 2B Describe Figure 2A the working process of the pixel circuit shown.

[0079] For example, as Figure 2BAs shown, Rt represents the reset control signal output by the reset signal line Rt, Ga represents the scan signal output by the scan signal line Ga, EM1 represents the first light emission control signal output by the first light emission control signal line EM1, and EM2 represents the second light emission control signal output by the second light emission control signal line EM2. It should be noted that in the embodiments of this disclosure, the reference numerals Rt, Ga, EM1, EM2, Vda, and VDD represent both signal lines and signals on those signal lines.

[0080] For example, the operation of a pixel circuit in a display frame may include: initialization phase p1, data writing phase p2, first buffer phase p3, second buffer phase p4, and light emission phase p5.

[0081] During the initialization phase p1, the reset control signal Rt and the first light-emitting control signal EM1 are at a low level, while the second light-emitting control signal EM2 and the scan signal Ga are at a high level. Consequently, the first reset transistor T1 is turned on under the control of the low level of the reset control signal Rt, and the second reset transistor T7 is also turned on under the control of the low level of the first light-emitting control signal EM1. This causes the initial voltage V output by the initial signal line Vinit to... i The gate of the driving transistor T3, i.e., the third node N3, can be supplied with power through the first reset transistor T1 and the second reset transistor T7, thereby making the gate voltage of the driving transistor T3 equal to the initial voltage V. i This initializes the gate of the driving transistor T3. Simultaneously, the threshold compensation transistor T2 is turned on under the control of a low level of the reset control signal Rt, and the first light-emitting control transistor T6 is also turned on under the control of a low level of the first light-emitting control signal EM1. This causes the initial voltage V output by the initial signal line Vinit to... i The first electrode of the light-emitting element 121 can be initialized by providing the conduction threshold compensation transistor T2 and the first light-emitting control transistor T6. The second light-emitting control transistor T5 is turned off under the control of the high level of the second light-emitting control signal EM2, and the data writing transistor T4 is turned off under the control of the high level of the scan signal Ga.

[0082] During the data writing phase p2, the reset control signal Rt and the scan signal Ga are at low levels, while the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at high levels. Consequently, the data writing transistor T4 is turned on under the control of the low level of the scan signal Ga, providing the data voltage Vda on the data line Vda to the second terminal of the driving transistor T3, i.e., the second node N2, so that the voltage at the second terminal of the driving transistor T3 is the data voltage Vda. The threshold compensation transistor T2 is turned on under the control of the low level of the reset control signal Rt, allowing the driving transistor T3 to form a diode connection. This allows the voltage Vda at the second terminal of the driving transistor T3 to charge the gate of the driving transistor T3 until the gate voltage of the driving transistor T3 is Vda+Vth. The gate voltage Vda+Vth of the driving transistor T3 is stored through the storage capacitor Cst. The second reset transistor T7 and the first light-emitting control transistor T6 are turned off under the control of the high level of the first light-emitting control signal EM1, and the second light-emitting control transistor T5 is turned off under the control of the high level of the second light-emitting control signal EM2.

[0083] During the first buffer phase p3, the scan signal Ga is low, while the reset control signal Rt, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 are high. Consequently, the data writing transistor T4 is turned on under the control of the low level of the scan signal Ga, providing the data voltage Vda on the data line Vda to the second terminal of the driving transistor T3, ensuring that the voltage at the second terminal of the driving transistor T3 remains the data voltage Vda. The first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of the high level of the reset control signal Rt. The second reset transistor T7 and the first light-emitting control transistor T6 are turned off under the control of the high level of the first light-emitting control signal EM1, and the second light-emitting control transistor T5 is turned off under the control of the high level of the second light-emitting control signal EM2.

[0084] It should be noted that by making the scan signal Ga low in the first buffer stage p3, the data writing transistor T4 can remain on to allow for more complete charging.

[0085] During the second buffer phase p4, the second light-emitting control signal EM2 is at a low level, while the reset control signal Rt, the first light-emitting control signal EM1, and the scan signal Ga are at a high level. Consequently, the second light-emitting control transistor T5 is turned on under the control of the high level of the second light-emitting control signal EM2. This allows the second light-emitting control transistor T5 to provide the first voltage VDD output from the first voltage line VDD to the second terminal of the driving transistor T3, making the voltage at the second terminal of the driving transistor T3 equal to the first voltage VDD. This allows for pre-charging of the second terminal of the driving transistor T3 through the first voltage line VDD. The first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of the high level of the reset control signal Rt. The second reset transistor T7 and the first light-emitting control transistor T6 are turned off under the control of the high level of the first light-emitting control signal EM1. The data writing transistor T4 is turned off under the control of the high level of the scan signal Ga.

[0086] It should be noted that by making the first light-emitting control signal EM1 high in the second buffer stage p4, the first light-emitting control transistor T6 can be turned off. This allows the voltage of the gate of the driving transistor T3 to be further stabilized, that is, the current generated by the driving transistor T3 to be further stabilized before being supplied to the light-emitting element 121, thereby further improving the light-emitting stability of the light-emitting element 121.

[0087] During the light-emitting phase p5, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at low levels, while the reset control signal Rt and the scan signal Ga are at high levels. Therefore, the second light-emitting control transistor T5 is turned on under the control of the low level of the second light-emitting control signal EM2. This allows the second light-emitting control transistor T5 to provide the first voltage VDD output from the first voltage line VDD to the second terminal of the driving transistor T3, making the voltage at the second terminal of the driving transistor T3 equal to the first voltage VDD. At this time, the voltage at the second terminal of the driving transistor T3 is the first voltage VDD. Based on the holding effect of the storage capacitor Cst, the gate voltage of the driving transistor T3 is Vda + Vth. This allows the driving transistor T3 to be in a saturated state, thereby generating a driving current Ids: Ids = K*((Vda + Vth - VDD) - Vth). 2 =K*(Vda-VDD) 2K is a structural constant related to the process and design. The first light-emitting control transistor T6 is turned on under the control of a low level of the first light-emitting control signal EM1, thereby connecting the first electrode of the driving transistor T3 with the first electrode of the light-emitting element 121, allowing the driving current Ids to flow into the light-emitting element 121 to drive it to emit light. The first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of a high level of the reset control signal Rt, and the data writing transistor T4 is turned off under the control of a high level of the scan signal Ga.

[0088] It should be noted that the information provided in this disclosure... Figure 2B The circuit timing diagram shown is merely illustrative. The specific timing of the pixel circuit can be set according to the actual application scenario, and this disclosure does not impose any specific limitations on it.

[0089] Figure 3 This is a schematic diagram of the layout of a pixel circuit provided for some embodiments of this disclosure.

[0090] Figure 3 for Figure 2A The schematic diagram of the pixel circuit layout shows that the display substrate 100 may include an active semiconductor layer, a first conductive layer, a second conductive layer, a source / drain metal layer, and an anode layer. For example, each pixel circuit 120 includes an active semiconductor layer, a first conductive layer, a second conductive layer, a source / drain metal layer, and an anode layer. For example, the various components (transistors T1-T7 and storage capacitors, etc.) and various signal lines of the pixel circuit 120 are disposed in the active semiconductor layer, the first conductive layer, the second conductive layer, the source / drain metal layer, and the anode layer. In the direction perpendicular to the substrate 10, the active semiconductor layer is located between the substrate 10 and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, the second conductive layer is located between the first conductive layer and the source / drain metal layer, and the source / drain metal layer is located between the second conductive layer and the anode layer. It should be noted that... Figure 3 The stacking relationship between the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layers in only one pixel circuit is shown.

[0091] For example, such as Figure 3 As shown, the first light emission control signal line EM1, the scanning signal line Ga, and the second light emission control signal line EM2 extend along the first direction X and are arranged along the second direction Y, which is not parallel to the first direction X. In the second direction Y, the scanning signal line Ga is located between the first light emission control signal line EM1 and the second light emission control signal line EM2.

[0092] For example, in some embodiments, the first direction X and the second direction Y are perpendicular to each other. The first direction X may be parallel to the horizontal direction, and the second direction Y may be parallel to the vertical direction.

[0093] For example, such as Figure 3 As shown, in the second direction Y, the orthographic projection of the first light-emitting control signal line EM1 on the substrate 10 and the orthographic projection of the second light-emitting control signal line EM2 on the substrate 10 are located on both sides of the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst on the substrate 10.

[0094] For example, in the second direction Y, the orthographic projection of the scan signal line Ga onto the substrate and the orthographic projection of the second light-emitting control signal line EM2 onto the substrate are located on opposite sides of the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst onto the substrate. That is, the orthographic projection of the first light-emitting control signal line EM1 onto the substrate and the orthographic projection of the scan signal line Ga onto the substrate are located on the same side of the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst onto the substrate. Figure 3 The upper side is the center, and the orthographic projection of the second light-emitting control signal line EM2 on the substrate is located on the other side of the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst on the substrate, for example. Figure 3 The middle is the lower side.

[0095] For example, such as Figure 3 As shown, the reset signal line Rt extends along the first direction X. In the second direction Y, the reset signal line Rt is located on the side of the first light emission control signal line EM1 away from the scan signal line Ga. That is, in the second direction, the orthogonal projection of the first light emission control signal line EM1 on the substrate 10 is located between the orthogonal projection of the reset signal line Rt on the substrate 10 and the orthogonal projection of the scan signal line Ga on the substrate 10.

[0096] For example, such as Figure 3 As shown, in the second direction Y, from top to bottom, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 are arranged sequentially. This disclosure is not limited thereto; in other embodiments, in the second direction Y, from bottom to top, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 are arranged sequentially.

[0097] For example, Figure 3The solid rectangular boxes in the diagram illustrate the various portions where the first conductive layer overlaps with the active semiconductor layer. The reset signal line Rt, the first light-emitting control signal line EM1, the scan signal line Ga, and the second light-emitting control signal line EM2 are all located within the first conductive layer. The active semiconductor layers within each solid rectangular box represent the active layers of transistors T1-T7. For example, the reset signal line Rt overlaps with the active semiconductor layer to define the active layer of the first reset transistor T1 and the active layer of the threshold compensation transistor T2; the first light-emitting control signal line EM1 overlaps with the active semiconductor layer to define the active layer of the first light-emitting control transistor T6 and the active layer of the second reset transistor T7; the scan signal line Ga overlaps with the active semiconductor layer to define the active layer of the data writing transistor T4; the second light-emitting control signal line EM2 overlaps with the active semiconductor layer to define the active layer of the second light-emitting control transistor T5; and the first electrode plate (not shown) of the storage capacitor Cst overlaps with the active semiconductor layer to define the active layer of the driving transistor T3.

[0098] For example, such as Figure 3 As shown, the initial signal line Vinit includes a first sub-initial signal line Vinit1 and a second sub-initial signal line Vinit2. The first sub-initial signal line Vinit1 extends along a first direction X, and the second sub-initial signal line Vinit2 extends along a second direction Y. The first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are electrically connected. The initial signal line Vinit is wired in a grid pattern on the substrate, having a mesh structure. That is, the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are arranged in a grid pattern on the entire display substrate. As a result, the initial signal line Vinit has a lower resistance and a lower voltage drop (IR drop), making the distribution of the initial signal line Vinit on the substrate more uniform. This improves the stability of the initial voltage provided by the initial signal line Vinit, ensuring the initialization effect of the gate of the driving transistor T3 and the first electrode of the light-emitting element 121 in the initialization stage p1.

[0099] For example, such as Figure 3 As shown, the first voltage line VDD includes a first sub-voltage line VDD1 and a second sub-voltage line VDD2, which are electrically connected. The first sub-voltage line VDD1 extends along a second direction Y, and the second sub-voltage line VDD2 extends along a first direction X. The first voltage line VDD is wired in a grid pattern on the substrate, meaning that the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are arranged in a grid pattern across the entire display substrate. This results in lower resistance and lower voltage drop of the first voltage line VDD, thereby improving the stability of the power supply voltage provided by the first voltage line VDD.

[0100] For example, the second sub-voltage line VDD2 and the second electrode plate CC2 of the storage capacitor Cst are integrally formed.

[0101] For example, such as Figure 3 As shown, the data line Vda, the first sub-voltage line VDD1, and the second sub-initial signal line Vinit2 all extend along the second direction Y and are arranged along the first direction X. Figure 3 In the example shown, in the first direction X, the first sub-voltage line VDD1 is located between the data line Vda and the second sub-initial signal line Vinit2.

[0102] Figure 4A-4M This is a schematic diagram showing the layout of the various structural layers of a pixel circuit provided in some embodiments of this disclosure.

[0103] For example, in some embodiments, the pixel circuits of multiple sub-pixels 12 are arranged in an array along a first direction X and a second direction Y. The following is in conjunction with the appendix... Figure 4A-4M This describes the positional relationship of the various components of the pixel circuit on the substrate in this embodiment. Figure 4A-4M The example shown is Figure 2A Taking pixel circuit 120 as an example. In Figure 4A-4M In the diagram, the area represented by the rectangular dashed box is the region corresponding to one pixel circuit 120. Figure 4A-4M The layout of the region corresponding to the eight pixel circuits arranged in two rows and four columns is shown.

[0104] For example, such as Figure 4A-4MAs shown, each pixel circuit 120 may include an active semiconductor layer 310, a first insulating layer (not shown), a first conductive layer 320, a second insulating layer (not shown), a second conductive layer 330, a third insulating layer 410, a source / drain metal layer 340, a planarization layer 420, and an anode layer 350. The active semiconductor layer 310, the first insulating layer (not shown), the first conductive layer 320, the second insulating layer (not shown), the second conductive layer 330, the third insulating layer 410, the source / drain metal layer 340, the planarization layer 420, and the anode layer 350 are sequentially disposed on a substrate. In other words, in the direction perpendicular to the substrate, the active semiconductor layer 310 is located between the substrate and the first conductive layer 320, the first conductive layer 320 is located between the active semiconductor layer 310 and the second conductive layer 330, the second conductive layer 330 is located between the first conductive layer 320 and the source / drain metal layer 340, the planarization layer 420 is located on the side of the source / drain metal layer 340 away from the substrate, that is, between the source / drain metal layer 340 and the anode layer 350, and the anode layer 350 is located on the side of the planarization layer 420 away from the source / drain metal layer 340. A first insulating layer is located between the active semiconductor layer 310 and the first conductive layer 320, a second insulating layer is located between the first conductive layer 320 and the second conductive layer 330, and a third insulating layer 410 is located between the second conductive layer 330 and the source / drain metal layer 340.

[0105] For example, the first insulating layer, the second insulating layer, the third insulating layer 410, and the planarization layer 420 are all made of insulating materials, such as inorganic insulating materials like silicon nitride, silicon oxide, and silicon oxynitride, or other suitable materials. The materials used to prepare the first insulating layer, the second insulating layer, the third insulating layer 410, and the planarization layer 420 can be the same, or at least some of the layers in the first insulating layer, the second insulating layer, the third insulating layer 410, and the planarization layer 420 can be made of different materials; this disclosure does not impose any limitations on this.

[0106] Figure 4A The active semiconductor layer 310 of the plurality of pixel circuits 120 is shown. The active semiconductor layer 310 can be patterned on a substrate using semiconductor material. The active semiconductor layer 310 can be used to fabricate the active layer of the driving transistor T3, the active layer of the first reset transistor T1, the active layer of the threshold compensation transistor T2, the active layer of the data writing transistor T4, the active layer of the second light-emitting control transistor T5, the active layer of the first light-emitting control transistor T6, and the active layer of the second reset transistor T7. The active layer of each transistor may include a source region, a drain region, and a channel region between the source and drain regions. The channel region is used to form the channel of the transistor.

[0107] For example, Figure 4A The solid rectangular boxes in the diagram represent the active layers of each transistor T1-T7. For example... Figure 4AAs shown, the active layers of each transistor T1-T7 are disposed on the same layer, and the active layers of the first reset transistor T1 and the second reset transistor T7 are disposed together. The active layers of the threshold compensation transistor T2 and the first light-emitting control transistor T6 are disposed together. The active layers of the driving transistor T3, the data writing transistor T4, and the second light-emitting control transistor T5 are disposed together.

[0108] For example, such as Figure 4A As shown, in the second direction Y, the active layers of the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the first light-emitting control transistor T6, and the second reset transistor T7 are all located on the first side of the active layer of the driving transistor T3. For example, Figure 4A The upper side is shown; the active layer of the second light-emitting control transistor T5 is located on the second side of the active layer of the driving transistor T3, for example, Figure 4A The lower side is shown.

[0109] For example, the active semiconductor layer 310 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities. In the embodiments of this disclosure, the doped source region corresponds to the source of the transistor (e.g., the first electrode of the transistor), and the doped drain region corresponds to the drain of the transistor (e.g., the second electrode of the transistor).

[0110] For example, a first insulating layer (not shown) is formed on the side of the active semiconductor layer 310 away from the substrate to protect the active semiconductor layer 310. Figure 4B The first conductive layer 320 of the pixel circuit 120 is shown. The first conductive layer 320 is disposed on the side of the first insulating layer away from the active semiconductor layer 310, thereby insulating it from the active semiconductor layer 310. It should be noted that... Figure 4A The solid rectangular boxes in the figure show the various portions where the first conductive layer 320 overlaps with the active semiconductor layer 310.

[0111] For example, the reset signal line Rt, the first light-emitting control signal line EM1, the scan signal line Ga, and the second light-emitting control signal line EM2 are all located in the first conductive layer 320. Furthermore, the first conductive layer 320 may also include the first electrode plate CC1 of the storage capacitor Cst, the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2, the gate of the data writing transistor T4, the gate of the second light-emitting control transistor T5, the gate of the first light-emitting control transistor T6, the gate of the second reset transistor T7, and the gate of the driving transistor T3.

[0112] For example, such as Figure 4BAs shown, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 all extend approximately along the first direction X. In the second direction Y, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 are arranged sequentially. That is, the first light emission control signal line EM1 is located between the reset signal line Rt and the scan signal line Ga, and the scan signal line Ga is located between the first light emission control signal line EM1 and the second light emission control signal line EM2.

[0113] For example, such as Figure 4B As shown, the shapes of the reset signal line Rt and the scan signal line Ga are roughly straight, while the shapes of the first light emission control signal line EM1 and the second light emission control signal line EM2 are roughly curved, for example, wavy.

[0114] For example, the reset signal line Rt is electrically connected to the gate of the first reset transistor T1 and the gate of the threshold compensation transistor T2 to control the first reset transistor T1 and the threshold compensation transistor T2 to be turned on or off; the first light emission control signal line EM1 is electrically connected to the gate of the first light emission control transistor T6 and the gate of the second reset transistor T7 to control the first light emission control transistor T6 and the second reset transistor T7 to be turned on or off; the scan signal line Ga is electrically connected to the gate of the data writing transistor T4 to control the data writing transistor T4 to be turned on or off; the second light emission control signal line EM2 is electrically connected to the gate of the second light emission control transistor T5 to control the second light emission control transistor T5 to be turned on or off.

[0115] Figure 4C This is a schematic diagram showing the stacking position relationship between the active semiconductor layer 310 and the first conductive layer 320.

[0116] For example, in a direction perpendicular to the substrate, the reset signal line Rt at least partially overlaps with the active layer of the first reset transistor T1 and the active layer of the threshold compensation transistor T2; the first light emission control signal line EM1 at least partially overlaps with the active layer of the first light emission control transistor T6 and the active layer of the second reset transistor T7; the scan signal line Ga at least partially overlaps with the active layer of the data writing transistor T4; and the second light emission control signal line EM2 at least partially overlaps with the active layer of the second light emission control transistor T5.

[0117] like Figure 4CAs shown, the reset signal line Rt, the gate of the first reset transistor T1, and the gate of the threshold compensation transistor T2 are integrally provided. The portion of the reset signal line Rt overlapping with the active semiconductor layer 310 serves as the gate of the first reset transistor T1 and the gate of the threshold compensation transistor T2. The first light emission control signal line EM1, the gate of the first light emission control transistor T6, and the gate of the second reset transistor T7 are integrally provided. The portion of the first light emission control signal line EM1 overlapping with the active semiconductor layer 310 serves as the gate of the first light emission control transistor T6 and the gate of the second reset transistor T7. The scan signal line Ga and the gate of the data writing transistor T4 are integrally provided. The portion of the scan signal line Ga overlapping with the active semiconductor layer 310 serves as the gate of the data writing transistor T4. The second light emission control signal line EM2 and the gate of the second light emission control transistor T5 are integrally provided. The portion of the second light emission control signal line EM2 overlapping with the active semiconductor layer 310 serves as the gate of the second light emission control transistor T5. The gate of the driving transistor T3 can be the first electrode plate CC1 of the storage capacitor Cst.

[0118] For example, as Figure 4B shown, the first electrode plate CC1 of the storage capacitor Cst is located between the second light emission control signal line EM2 and the scan signal line Ga. For example, as Figure 4C shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the first electrode plate CC1 of the storage capacitor Cst of the first conductive layer 320 is the active layer of the driving transistor T3, and the shape of the active layer of the driving transistor T3 is in the shape of the Chinese character "ji".

[0119] For example, the active layer of the first reset transistor T1 is a reset active layer, that is, the first reset transistor T1 includes a reset active layer, and the reset active layer includes a first reset active layer portion T11 and a second reset active layer portion T12. For example, as Figure 4C shown, the orthographic projection of the second reset active layer portion T12 on the substrate and the orthographic projection of the reset signal line Rt on the substrate at least partially overlap.

[0120] For example, as Figure 4A and 4C shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the reset signal line Rt of the first conductive layer 320 includes the second reset active layer portion T12, and the second reset active layer portion T12 includes two spaced-apart portions, that is, the first reset transistor T1 is a double-gate transistor. The first reset active layer portion T11 and the second reset active layer portion T12 generally form a U shape as a whole, that is, the first reset transistor T1 is a U-shaped double-gate transistor.

[0121] For example, the active layer of the threshold compensation transistor T2 is a compensation active layer, that is, the threshold compensation transistor T2 includes a compensation active layer, which includes a first compensation active layer portion T21 and a second compensation active layer portion T22. For example, as... Figure 4C As shown, the orthographic projection of the second compensation active layer portion T22 on the substrate and the orthographic projection of the reset signal line Rt on the substrate at least partially overlap.

[0122] For example, such as Figure 4A and 4C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the reset signal line Rt of the first conductive layer 320 includes a second compensation active layer portion T22. The second compensation active layer portion T22 includes two spaced-apart portions, meaning the threshold compensation transistor T2 is a dual-gate transistor. The first compensation active layer portion T21 and the second compensation active layer portion T22 generally form a U-shape, meaning the threshold compensation transistor T2 is a U-shaped dual-gate transistor.

[0123] For example, such as Figure 4A and Figure 4C As shown, the first reset active layer portion T11 and the first compensation active layer portion T21 are arranged sequentially in the first direction X, and the center of the first reset active layer portion T11 and the center of the first compensation active layer portion T21 are approximately located on the same straight line, which is, for example, parallel to the first direction X.

[0124] For example, the shape of the first reset active layer portion T11 is approximately the same as the shape of the first compensation active layer portion T21.

[0125] For example, the first reset transistor T1 includes two gates, and the threshold compensation transistor T2 includes two gates, as shown below. Figure 4C As shown, in the direction perpendicular to the substrate, the reset signal line Rt overlaps with the active semiconductor layer 310 to form four overlapping portions, which are the two gates of the first reset transistor T1 and the two gates of the threshold compensation transistor T2, respectively.

[0126] For example, such as Figure 4AAs shown, the second reset active layer portion T12 includes a first sub-part T121 and a second sub-part T122 spaced apart from each other, and the second compensation active layer portion T22 includes a third sub-part T221 and a fourth sub-part T222 spaced apart from each other. For example, the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are arranged sequentially in the first direction X, and the centers of the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are approximately located on the same straight line, for example, parallel to the first direction X. In the second direction Y, the lengths of the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are approximately equal.

[0127] For example, in the first direction X, the length of the first sub-part T121 is slightly less than the length of the second sub-part T122, and the length of the third sub-part T221 is slightly less than the length of the fourth sub-part T222.

[0128] For example, the shapes of the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are all rectangles.

[0129] For example, such as Figure 4C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the first light-emitting control signal line EM1 of the first conductive layer 320 is the active layer of the first light-emitting control transistor T6 and the active layer of the second reset transistor T7, and the shape of the active layer of the first light-emitting control transistor T6 and the active layer of the second reset transistor T7 are both rectangular.

[0130] For example, such as Figure 4C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the scan signal line Ga of the first conductive layer 320 is the active layer of the data writing transistor T4, and the active layer of the data writing transistor T4 is rectangular in shape.

[0131] For example, such as Figure 4C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 310 covered by the second light-emitting control signal line EM2 of the first conductive layer 320 is the active layer of the second light-emitting control transistor T5, and the active layer of the second light-emitting control transistor T5 is rectangular in shape.

[0132] For example, such as Figure 4CAs shown, in the second direction Y, the gates of the first reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light-emitting control transistor T6, and the second reset transistor T7 are all located on the first side of the gate of the driving transistor T3. For example, Figure 4C As shown above; the gate of the second light-emitting control transistor T5 is located on the second side of the gate of the driving transistor T3, for example, Figure 4C The lower side is shown.

[0133] Figure 4E This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 310, the first conductive layer 320, and the second conductive layer 330.

[0134] For example, a second insulating layer (not shown) is formed on the side of the first conductive layer 320 away from the first insulating layer to protect the first conductive layer 320. Figure 4D The second conductive layer 330 of the pixel circuit 120 is shown. The second conductive layer 330 is formed on the side of the second insulating layer away from the first conductive layer 320. The second conductive layer 330 includes the second electrode plate CC2 of the storage capacitor Cst, the first sub-initial signal line Vinit1, and the second sub-voltage line VDD2. Figure 4E As shown, the first sub-initial signal line Vinit1 and the second sub-voltage line VDD2 both extend along the first direction X and are arranged along the second direction Y. In a direction perpendicular to the substrate, the first electrode plate CC1 and the second electrode plate CC2 of the storage capacitor Cst at least partially overlap to form the storage capacitor Cst. For example, the second sub-voltage line VDD2 is integrally formed with the second electrode plate CC2 of the storage capacitor Cst.

[0135] For example, such as Figure 4D and Figure 4E As shown, the second electrode plate CC2 of the storage capacitor Cst includes a conductive layer via h11. The second electrode of the threshold compensation transistor T2 and the second electrode of the second reset transistor T7 are electrically connected to the first electrode plate CC1 of the storage capacitor Cst, i.e., the gate of the driving transistor DT, through the conductive layer via h11.

[0136] For example, the orthographic projection of the first reset active layer portion T11 on the substrate and the orthographic projection of the initial signal line Vinit on the substrate at least partially overlap, and the orthographic projection of the first compensation active layer portion T21 on the substrate and the orthographic projection of the initial signal line Vinit on the substrate at least partially overlap.

[0137] For example, such as Figure 4D and Figure 4EAs shown, the initial signal line Vinit includes a first sub-initial signal line Vinit1. The orthographic projections of the first reset active layer portion T11 and the first compensation active layer portion Vinit1 on the substrate are both located within the orthographic projection of the first sub-initial signal line Vinit1 on the substrate. In the embodiments of this disclosure, the first sub-initial signal line Vinit1 simultaneously blocks the portions of the active layer of the first reset transistor T1 that are not blocked by the reset signal line Rt and the active layer of the threshold compensation transistor T2 that are not blocked by the reset signal line Rt, without the need for a separate blocking layer. This also reduces the number of traces on the display substrate and lowers costs. Furthermore, using the first sub-initial signal line Vinit1 to block the portions of the active layer of the first reset transistor T1 and the active layer of the threshold compensation transistor T2 that are not blocked by the reset signal line Rt makes the first reset transistor T1 and the threshold compensation transistor T2 more stable.

[0138] Figure 4G This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, and the third insulating layer 410.

[0139] For example, such as Figure 4F As shown, a third insulating layer 410 is formed on the side of the second conductive layer 330 away from the second insulating layer to protect the second conductive layer 330. A plurality of insulating layer vias h21-h31 are formed in the third insulating layer 410. Each of the plurality of insulating layer vias h21-h31 corresponds to a pixel circuit.

[0140] For example, such as Figure 4F and Figure 4G As shown, insulating layer via h21 penetrates the third insulating layer 410 to expose a portion of the first sub-initial signal line Vinit1; insulating layer vias h22-27 and 30-31 penetrate the first, second, and third insulating layers 410 to expose a portion of the active semiconductor layer 310; insulating layer via h28 penetrates the third insulating layer 410 to expose a portion of the second electrode plate CC2 of the storage capacitor Cst; and insulating layer via h29 penetrates the second and third insulating layers 410 to expose a portion of the first electrode plate CC1 of the storage capacitor Cst. For example, the orthographic projection of insulating layer via h29 on the substrate lies within the orthographic projection of conductive layer via h11 on the substrate.

[0141] Figure 4H The source-drain metal layer 340 of the pixel circuit 120 is shown. The source-drain metal layer 340 is disposed on the side of the third insulating layer 410 away from the second conductive layer 330. Figure 4IA schematic diagram showing the stacking position relationship of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the third insulating layer 410 and the source / drain metal layer 340 is shown.

[0142] For example, such as Figure 4H As shown, the source-drain metal layer 340 includes a data line Vda, a first sub-voltage line VDD1, a second sub-initial signal line Vinit2, a first electrode fc1 of a first reset transistor T1, a first electrode fc2 and a second electrode sc2 of a threshold compensation transistor T2, a first electrode fc3 of a driving transistor T3, a first electrode fc4 of a data writing transistor T4, a second electrode sc5 of a second light-emitting control transistor T5, a first electrode fc6 and a second electrode sc6 of a first light-emitting control transistor T6, a second electrode sc7 of a second reset transistor T7, a first connection electrode Co1, a second connection electrode Co2, and a third connection electrode Co3.

[0143] For example, such as Figure 4F , Figure 4H and Figure 4I As shown, the first terminal fc1 of the first reset transistor T1 is connected to the second sub-initial signal line Vinit2. For example, the first terminal fc1 of the first reset transistor T1 is a part of the second sub-initial signal line Vinit2. The first terminal fc1 of the first reset transistor T1 is connected to the source region or drain region in the active semiconductor layer 310 corresponding to the first reset transistor T1 through the insulating layer via h22.

[0144] For example, such as Figure 4F , Figure 4H and Figure 4I As shown, the first electrode fc2 of the threshold compensation transistor T2 and the first electrode fc6 of the first light-emitting control transistor T6 are the same electrode, and are connected to the source or drain region in the active semiconductor layer 310 corresponding to the threshold compensation transistor T2 and the first light-emitting control transistor T6 through an insulating layer via h24. The second electrode sc2 of the threshold compensation transistor T2 is connected to the source or drain region in the active semiconductor layer 310 corresponding to the threshold compensation transistor T2 through an insulating layer via h23.

[0145] For example, the first electrode fc2 of the threshold compensation transistor T2 and the first electrode fc6 of the first light-emitting control transistor T6 are part of the third connection electrode Co3. The second electrode sc2 of the threshold compensation transistor T2 is part of the second connection electrode Co2.

[0146] For example, the second electrode sc6 of the first light-emitting control transistor T6 is connected to the first connection electrode Co1, for example, the second electrode sc6 of the first light-emitting control transistor T6 is a part of the first connection electrode Co1. For example, the second electrode sc6 of the first light-emitting control transistor T6 is connected to the source region or drain region in the active semiconductor layer 310 corresponding to the first light-emitting control transistor T6 through the insulating layer via h27.

[0147] For example, such as Figure 4F , Figure 4H and Figure 4I As shown, the first terminal fc4 of the data writing transistor T4 is connected to the data line Vda. For example, the first terminal fc4 of the data writing transistor T4 is part of the data line Vda. The first terminal fc4 of the data writing transistor T4 is connected to the source region or drain region in the active semiconductor layer 310 corresponding to the data writing transistor T4 through the insulating layer via h25.

[0148] For example, such as Figure 4F , 4H and Figure 4I As shown, the first electrode fc5 of the second light-emitting control transistor T5 is connected to the first sub-voltage line VDD1. For example, the first electrode fc5 of the second light-emitting control transistor T5 is a part of the first sub-voltage line VDD1. The first electrode fc5 of the second light-emitting control transistor T5 is connected to the source region or drain region in the active semiconductor layer 310 corresponding to the second light-emitting control transistor T5 through the insulating layer via h30.

[0149] For example, such as Figure 4F , Figure 4H and Figure 4I As shown, the second electrode sc7 of the second reset transistor T7 is connected to the source or drain region corresponding to the second reset transistor T7 in the active semiconductor layer 310 through the insulating layer via h26. The second electrode sc7 of the second reset transistor T7 is connected to the second connection electrode Co2; for example, the second electrode sc7 of the second reset transistor T7 is a part of the second connection electrode Co2.

[0150] For example, such as Figure 4F , Figure 4H and Figure 4I As shown, the first electrode fc3 of the driving transistor T3 is connected to the source or drain region corresponding to the driving transistor T3 in the active semiconductor layer 310 through the insulating layer via h31. The first electrode fc3 of the driving transistor T3 is connected to the third connection electrode Co3; for example, the first electrode fc3 of the driving transistor T3 is a part of the third connection electrode Co3.

[0151] For example, such as Figure 4F and Figure 4HAs shown, the second connecting electrode Co2 is connected to the first electrode plate CC1 of the storage capacitor Cst, i.e., the gate of the driving transistor T3, through the insulating layer via h29.

[0152] For example, such as Figure 4F and Figure 4H As shown, the second sub-initial signal line Vinit2 is electrically connected to the first sub-initial signal line Vinit1 through an insulating layer via h21.

[0153] For example, such as Figure 4F and Figure 4H As shown, the first sub-voltage line VDD1 is electrically connected to the second sub-voltage line VDD2 through an insulating layer via h28.

[0154] For example, the second terminal of the data writing transistor T4, the first terminal of the second light-emitting control transistor T5, and the second terminal of the driving transistor T3 are integrated into one unit.

[0155] For example, such as Figure 4D and Figure 4H As shown, the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are located on different layers. The second sub-voltage line VDD2 is located on the second conductive layer 330, and the first sub-voltage line VDD1 is located on the source-drain metal layer 340. The first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are also located on different layers. The first sub-initial signal line Vinit1 is located on the second conductive layer 330, and the second sub-initial signal line Vinit2 is located on the source-drain metal layer 340.

[0156] For example, such as Figure 4H As shown, the data line Vda extends approximately along the second direction Y. The first sub-voltage line VDD1, the data line Vda, and the second sub-initial signal line Vinit2 are located on the same layer, namely the source-drain metal layer 340. The first sub-voltage line VDD1, the data line Vda, and the second sub-initial signal line Vinit2 are arranged along the first direction X. In the first direction X, the first sub-voltage line VDD1 is located between the data line Vda and the second sub-initial signal line Vinit2.

[0157] For example, a planarization layer 420 is formed on the side of the source / drain metal layer 340 away from the third insulating layer 410 to protect the source / drain metal layer 340. Figure 4J As shown, the planarization layer 420 includes a first via h100, which penetrates the planarization layer 420. For example, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 121 through the first via h100 penetrating the planarization layer 420.

[0158] Figure 4KThis is a schematic diagram showing the stacking position relationship of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the third insulating layer 410, the source / drain metal layer 340, and the planarization layer 420.

[0159] For example, such as Figure 4K As shown, in the second direction Y, the orthogonal projection of the first via h100 on the substrate is located between the orthogonal projection of the reset signal line Rt on the substrate and the orthogonal projection of the second light-emitting control signal line EM2 on the substrate. In the second direction Y, the first via h100 can be set at any position between the reset signal line Rt and the second light-emitting control signal line EM2. That is, in the embodiments of this disclosure, the setting position of the first via h100 is more flexible and can be adapted to pixel circuits with various pixel arrangements. In addition, the position of the first via h100 can be flexibly adjusted according to the setting position of the first electrode of the light-emitting element 121, so that the first via h100 is closer to the first electrode of the light-emitting element 121, reducing the traces of the first electrode of the light-emitting element 121, and making the connection between the first electrode of the light-emitting element 121 and the second electrode of the first light-emitting control transistor T6 more flexible. Figure 4K As shown, the first via h100 is located near the scan signal line Ga. In the second direction Y, the orthographic projection of the first via h100 on the substrate is approximately between the orthographic projection of the scan signal line Ga on the substrate and the orthographic projection of the second light emission control signal line EM2 on the substrate.

[0160] For example, the orthographic projection of the first via h100 on the substrate is located within the orthographic projection of the first connecting electrode Co1 on the substrate. That is, the first via h100 exposes a part of the first connecting electrode Co1, and the first electrode of the light-emitting element 121 can be connected to the first connecting electrode Co1 through the first via h100.

[0161] Figure 4N This is a schematic diagram of the structure of a source / drain metal layer provided in some other embodiments of this disclosure. Figure 4O This is a schematic diagram of the structure of a planarization layer provided in some other embodiments of this disclosure. Figure 4P This is a schematic diagram illustrating the stacking positional relationship of the active semiconductor layer, the first conductive layer, the second conductive layer, the third insulating layer, the source / drain metal layer, and the planarization layer, provided for other embodiments of this disclosure.

[0162] For example, in other embodiments, in the second direction Y, the orthogonal projection of the first via on the substrate lies between the orthogonal projection of the scan signal line on the substrate and the orthogonal projection of the first light-emitting control signal line on the substrate. For example, as Figure 4PAs shown, in the second direction Y, the orthogonal projection of the first via h100' on the substrate is located between the orthogonal projection of the scan signal line Ga on the substrate and the orthogonal projection of the first light emission control signal line EM1 on the substrate.

[0163] Figure 4N and Figure 4O A schematic diagram of the source / drain metal layer and planarization layer in this embodiment is shown.

[0164] Based on the change in the position of the first via h100', the layout design of one or more layers in the pixel circuit can be changed accordingly, for example, relative to Figure 4H The source and drain metal layers 340 shown are as follows: Figure 4N As shown, the position of the first connection electrode Co1' in the source / drain metal layer 340' changes accordingly. To accommodate the positional change of the first via h100', relative to... Figure 4H The first connecting electrode Co1 shown is as follows: Figure 4N As shown, the first connecting electrode Co1' is closer to the upper side of the figure, that is, closer to the side where the first electrode fc2 of the threshold compensation transistor T2 and the first electrode fc6 of the first light-emitting control transistor T6 are located.

[0165] exist Figure 4N A planarization layer 420' is formed on the side of the source / drain metal layer 340' away from the third insulating layer, for protecting the aforementioned source / drain metal layer 340'. Figure 4O As shown, the planarization layer 420' includes a first via h100' that penetrates the planarization layer 420'. For example, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 121 through the first via h100' that penetrates the planarization layer 420'.

[0166] For example, such as Figure 4P As shown, the orthographic projection of the first via h100' onto the substrate lies within the orthographic projection of the first connecting electrode Co1' onto the substrate. In other words, the first via h100' exposes a portion of the first connecting electrode Co1'. The specific position of the first connecting electrode Co1' can be set according to actual conditions, as long as the position of the first connecting electrode Co1' satisfies the condition that the orthographic projection of the first via h100' onto the substrate lies within the orthographic projection of the first connecting electrode Co1' onto the substrate.

[0167] It should be noted that the positions of the components in the other layers can be set according to the actual situation, which will not be elaborated in this disclosure.

[0168] Figure 4LThe anode layer 350 of the pixel circuit 120 is shown, and the anode layer 350 includes the first electrode (i.e., anode) R / G / B of the light-emitting element 121. It should be noted that... Figure 4L In the image, only the electroluminescent layer in the light-emitting layer is shown, and the other common layers are not shown.

[0169] For example, in some embodiments, multiple subpixels in each row are arranged in an RGBGRGBG pattern, and the subpixels in adjacent rows are staggered by two subpixels. For example, as shown in... Figure 4L As shown, multiple subpixels located in odd-numbered rows (first row) are arranged in RGBGRGBG format, and multiple subpixels located in even-numbered rows (second row) are arranged in BGRGRGBG format. It should be noted that multiple subpixels in the display panel can include red subpixels, blue subpixels, and green subpixels. Figure 4L In the diagram, B represents the first electrode of the light-emitting element in the blue sub-pixel, G represents the first electrode of the light-emitting element in the green sub-pixel, and R represents the first electrode of the light-emitting element in the red sub-pixel. For example, the area of ​​the first electrode of a blue sub-pixel B is larger than the area of ​​the first electrode of a green sub-pixel G, and also larger than the area of ​​the first electrode of a red sub-pixel R.

[0170] Figure 4M This is a schematic diagram showing the stacking relationship of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the third insulating layer 410, the source / drain metal layer 340, the planarization layer 420, and the anode layer 350. For example, as... Figure 4M As shown, the first electrode of the light-emitting element 121 is connected to the first connecting electrode Co1 through the first via h100. The first connecting electrode Co1 is connected to the second electrode sc6 of the first light-emitting control transistor T6, thereby electrically connecting the first electrode of the light-emitting element 121 to the second electrode sc6 of the first light-emitting control transistor T6.

[0171] Figure 5A for Figure 4M A schematic diagram of the cross-sectional structure at point A on the middle line. Figure 5B for Figure 4M A schematic diagram of the cross-sectional structure at point B on the middle line.

[0172] For example, such as Figure 5A and Figure 5B As shown, the substrate 10 includes a multilayer structure (e.g., Figure 5A (Shown as a two-layer structure), all multi-layer structures are made of flexible materials.

[0173] For example, such as Figure 5A and Figure 5BAs shown, a buffer layer 11 is formed on the substrate 10 to prevent external moisture, oxygen, and impurities from entering the pixel circuit 120. For example, the material of the buffer layer 11 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials. Since silicon nitride has a high dielectric constant and excellent hydrophobic properties, it can effectively protect the pixel circuit from moisture corrosion.

[0174] For example, such as Figure 5A and Figure 5B As shown, an active semiconductor layer 310 is formed on the side of the buffer layer 11 away from the substrate 10. Figure 5A The active semiconductor layer 310 shown includes a first reset active layer portion T11 and a first compensation active layer portion T21. Figure 5B The active semiconductor layer 310 shown includes the portion of the active semiconductor layer 310 corresponding to the second electrode of the first light-emitting control transistor T6.

[0175] For example, such as Figure 5A and Figure 5B As shown, a first insulating layer 430 is formed on the side of the active semiconductor layer 310 away from the buffer layer 11, and a first conductive layer 320 is formed on the side of the first insulating layer 430 away from the active semiconductor layer 310. Figure 5A (not shown in the image) Figure 5B The first conductive layer 320 shown includes a portion of the first electrode plate CC1 of the scan signal line Ga and the storage capacitor Cst.

[0176] For example, such as Figure 5A and Figure 5B As shown, a second insulating layer 440 is formed on the side of the first conductive layer 320 away from the first insulating layer 430, and a second conductive layer 330 is formed on the side of the second insulating layer 440 away from the first conductive layer 320. Figure 5A The second conductive layer 330 shown includes a first sub-initial signal line Vinit1. The orthographic projection of the first reset active layer portion T11 on the substrate 10 and the orthographic projection of the first compensation active layer portion T21 on the substrate 10 are both located within the orthographic projection of the first sub-initial signal line Vinit1 on the substrate 10. Thus, in the direction perpendicular to the substrate 10, the first sub-initial signal line Vinit1 can block the first reset active layer portion T11 and the first compensation active layer portion T21. Figure 5B The second conductive layer 330 shown includes a portion of the second electrode plate CC2 for the storage capacitor Cst.

[0177] For example, such as Figure 5A and Figure 5BAs shown, a third insulating layer 410 is formed on the side of the second conductive layer 330 away from the second insulating layer 440, and a source / drain metal layer 340 is formed on the side of the third insulating layer 410 away from the second conductive layer 330. Figure 5A The source-drain metal layer 340 shown includes a first sub-voltage line VDD1 and a second sub-initial signal line Vinit2. The second sub-initial signal line Vinit2 is connected to the first sub-initial signal line Vinit1 through an insulating layer via h21 that penetrates the third insulating layer 410, thereby electrically connecting the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 to each other. Figure 5B The source-drain metal layer 340 shown includes a first connection electrode Co1, which is electrically connected to the portion of the active semiconductor layer 310 corresponding to the second electrode of the first light-emitting control transistor T6 through a second via h200 that penetrates the first insulating layer 430, the second insulating layer 440 and the third insulating layer 410.

[0178] For example, such as Figure 5A and Figure 5B As shown, a planarization layer 420 is formed on the side of the source / drain metal layer 340 away from the third insulating layer 410. An anode layer 350 is formed on the side of the planarization layer 420 away from the source / drain metal layer 340. A pixel defining layer 360 is formed on the side of the anode layer 350 away from the planarization layer 420 and on the planarization layer 420. The pixel defining layer 360 includes a plurality of pixel openings. In a direction perpendicular to the substrate, each pixel opening exposes at least a portion of the first electrode R / G / B of the corresponding light-emitting element. For example, the area of ​​the pixel opening of a blue sub-pixel is larger than the area of ​​the pixel opening of a green sub-pixel and larger than the area of ​​the pixel opening of a red sub-pixel. In some embodiments, the area of ​​the pixel opening of a green sub-pixel may be approximately equal to the area of ​​the pixel opening of a red sub-pixel. In other embodiments, the area of ​​the pixel opening of a green sub-pixel is smaller than the area of ​​the pixel opening of a red sub-pixel.

[0179] For example, the first connecting electrode Co1 is electrically connected to the second electrode of the first light-emitting control transistor T6, for example, they are integrally formed, such as... Figure 5B As shown, the first connecting electrode Co1 is electrically connected to the first electrode of the light-emitting element 120 in the anode layer 350 through the first via h100. Therefore, a jumper design is implemented at the fourth node N4, where the portion of the active semiconductor layer 310 corresponding to the second electrode of the first light-emitting control transistor T6 is first connected to the first connecting electrode Co1 through the second via h200. Then, the first connecting electrode Co1 is electrically connected to the first electrode of the light-emitting element 120 in the anode layer 350 through the first via h100, allowing for more flexible placement of the first via h100.

[0180] For example, in other embodiments, the plurality of sub-pixels 12 include a plurality of sub-pixel pairs, the plurality of sub-pixel pairs being arranged in an array along a first direction X and a second direction Y, each sub-pixel pair including two adjacent sub-pixels in the first direction X, the pixel circuits of the two sub-pixels being mirror-symmetrical along an axis of symmetry parallel to the second direction Y.

[0181] Figure 6A-6M This is a schematic diagram showing the layout of the various structural layers of a pixel circuit provided for other embodiments of this disclosure.

[0182] The following is in conjunction with the appendix Figure 6A-6M This describes the positional relationship of the various components of the pixel circuit on the substrate in this embodiment. Figure 6A-6M The example shown is Figure 2A Taking pixel circuit 120 as an example. In Figure 6A-6M In the diagram, the area represented by the dashed rectangle is the region corresponding to one pixel circuit 120, and the area represented by the dotted rectangle is the region corresponding to one sub-pixel pair of pixel circuits 120. Figure 6A-6M The layout of the region corresponding to the pixel circuits arranged in an array of four sub-pixel pairs in two rows and two columns is shown, which is the layout of the region corresponding to the eight pixel circuits arranged in an array of two rows and four columns.

[0183] It should be noted that, Figure 6A-6M The example shown is the same as Figure 4A-4M The examples shown are essentially the same, except that: Figure 4A-4M In the example shown, multiple sub-pixel arrays are arranged, while Figure 6A-6M The example shown has multiple sub-pixel pairs arranged in an array, with the pixel circuits of the two sub-pixels in each pixel pair set up in a mirror-symmetric configuration. Only the following description is provided. Figure 6A-6M The example shown is the same as Figure 4A-4M The different parts shown will not be described again.

[0184] For example, such as Figure 6A-6M As shown, each pixel circuit 120 may include an active semiconductor layer 510, a first insulating layer (not shown), a first conductive layer 520, a second insulating layer (not shown), a second conductive layer 530, a third insulating layer 610, a source / drain metal layer 540, a planarization layer 620, and an anode layer 550. The active semiconductor layer 510, the first insulating layer (not shown), the first conductive layer 520, the second insulating layer (not shown), the second conductive layer 530, the third insulating layer 610, the source / drain metal layer 540, the planarization layer 620, and the anode layer 550 are sequentially disposed on a substrate.

[0185] For example, the first insulating layer, the second insulating layer, the third insulating layer 610 and the planarization layer 620 are all made of insulating materials, such as inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials.

[0186] Figure 6A The active semiconductor layer 510 of the multiple pixel circuits 120 is shown. Figure 6A The rectangular dashed box shown illustrates the active semiconductor layer 510 of one subpixel in a subpixel pair. The active semiconductor layer 510 can be used to fabricate the active layer of the driving transistor T3, the active layer of the first reset transistor T1, the active layer of the threshold compensation transistor T2, the active layer of the data writing transistor T4, the active layer of the second light-emitting control transistor T5, the active layer of the first light-emitting control transistor T6, and the active layer of the second reset transistor T7. Figure 6A The solid rectangular boxes in the diagram show the active layers of each transistor T1-T7. The relative positions of the active layers of each transistor T1-T7 in the pixel circuit of each sub-pixel pair are shown below. Figure 4A The examples shown are the same, and the repeated parts will not be described again.

[0187] For example, such as Figure 6A As shown, the pixel circuits of the two sub-pixels in each sub-pixel pair are mirror-symmetric with respect to the axis of symmetry RR', which is parallel to the second direction Y.

[0188] For example, a first insulating layer (not shown) is formed on the side of the active semiconductor layer 510 away from the substrate to protect the active semiconductor layer 510. Figure 6B The first conductive layer 520 of the pixel circuit 120 is shown. The first conductive layer 520 is disposed on the side of the first insulating layer away from the active semiconductor layer 510, thereby insulating it from the active semiconductor layer 510. It should be noted that... Figure 6A The solid rectangular boxes in the figure show the various portions where the first conductive layer 520 overlaps with the active semiconductor layer 510.

[0189] For example, the reset signal line Rt, the first light-emitting control signal line EM1, the scan signal line Ga, and the second light-emitting control signal line EM2 are all located in the first conductive layer 520. Furthermore, the first conductive layer 520 may also include the first electrode plate CC1 of the storage capacitor Cst, and the gates of the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, the second reset transistor T7, and the driving transistor T3.

[0190] For example, such as Figure 6BAs shown, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 all extend approximately along the first direction X. In the second direction Y, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga, and the second light emission control signal line EM2 are arranged sequentially.

[0191] Figure 6C This is a schematic diagram showing the stacking position relationship between the active semiconductor layer 510 and the first conductive layer 520.

[0192] For example, the active layer of the first reset transistor T1 is a reset active layer, that is, the first reset transistor T1 includes a reset active layer, which includes a first reset active layer portion T11 and a second reset active layer portion T12. For example, as... Figure 6C As shown, the orthographic projection of the second reset active layer portion T12 on the substrate and the orthographic projection of the reset signal line Rt on the substrate at least partially overlap.

[0193] For example, such as Figure 6A and 6C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 510 covered by the reset signal line Rt of the first conductive layer 520 includes a second reset active layer portion T12. The second reset active layer portion T12 includes two portions spaced apart from each other. The first reset active layer portion T11 and the second reset active layer portion T12 generally form a U-shape, that is, the first reset transistor T1 is a U-shaped dual-gate transistor.

[0194] For example, the active layer of the threshold compensation transistor T2 is a compensation active layer, that is, the threshold compensation transistor T2 includes a compensation active layer, which includes a first compensation active layer portion T21 and a second compensation active layer portion T22. For example, as... Figure 6C As shown, the orthographic projection of the second compensation active layer portion T22 on the substrate and the orthographic projection of the reset signal line Rt on the substrate at least partially overlap.

[0195] For example, such as Figure 6A and 6C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 510 covered by the reset signal line Rt of the first conductive layer 520 includes a second compensation active layer portion T22. The second compensation active layer portion T22 includes two portions spaced apart from each other. The first compensation active layer portion T21 and the second compensation active layer portion T22 generally form a U-shape, that is, the threshold compensation transistor T2 is a U-shaped dual-gate transistor.

[0196] For example, the shape of the first reset active layer portion T11 is approximately the same as the shape of the first compensation active layer portion T21.

[0197] For example, such as Figure 6A As shown, the second reset active layer portion T12 includes a first sub-part T121 and a second sub-part T122 spaced apart from each other, and the second compensation active layer portion T22 includes a third sub-part T221 and a fourth sub-part T222 spaced apart from each other. For example, the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are arranged sequentially in the first direction X, and the centers of the first sub-part T121, the second sub-part T122, the third sub-part T221, and the fourth sub-part T222 are approximately located on the same straight line, for example, parallel to the first direction X.

[0198] Figure 6E This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 310, the first conductive layer 320, and the second conductive layer 330.

[0199] For example, a second insulating layer (not shown) is formed on the side of the first conductive layer 520 away from the first insulating layer to protect the first conductive layer 520. Figure 6D The second conductive layer 530 of the pixel circuit 120 is shown. The second conductive layer 530 is formed on the side of the second insulating layer away from the first conductive layer 520. The second conductive layer 530 includes the second electrode plate CC2 of the storage capacitor Cst, the first sub-initial signal line Vinit1, and the second sub-voltage line VDD2. Figure 6E As shown, the first sub-initial signal line Vinit1 and the second sub-voltage line VDD2 both extend along the first direction X and are arranged along the second direction Y. In a direction perpendicular to the substrate, the first electrode plate CC1 and the second electrode plate CC2 of the storage capacitor Cst at least partially overlap to form the storage capacitor Cst. For example, the second sub-voltage line VDD2 is integrally formed with the second electrode plate CC2 of the storage capacitor Cst.

[0200] For example, such as Figure 6D and Figure 6E As shown, the second electrode plate CC2 of the storage capacitor Cst includes a conductive layer via h11. The second electrode of the threshold compensation transistor T2 and the second electrode of the second reset transistor T7 are electrically connected to the first electrode plate CC1 of the storage capacitor Cst, i.e., the gate of the driving transistor DT, through the conductive layer via h11.

[0201] For example, such as Figure 6D and Figure 6EAs shown, the initial signal line Vinit includes a first sub-initial signal line Vinit1. The orthographic projection of the first reset active layer portion T11 on the substrate and the orthographic projection of the first compensation active layer portion Vinit1 on the substrate are both located within the orthographic projection of the first sub-initial signal line Vinit1 on the substrate. In the embodiments of this disclosure, the first sub-initial signal line Vinit1 simultaneously blocks the portion of the active layer of the first reset transistor T1 that is not blocked by the reset signal line Rt and the portion of the active layer of the threshold compensation transistor T2 that is not blocked by the reset signal line Rt, without the need to separately set a blocking layer to block them. This can reduce the wiring on the display substrate, reduce costs, and make the first reset transistor T1 and the threshold compensation transistor T2 more stable.

[0202] Figure 6G This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 510, the first conductive layer 520, the second conductive layer 530, and the third insulating layer 610.

[0203] For example, such as Figure 6F As shown, a third insulating layer 610 is formed on the side of the second conductive layer 530 away from the second insulating layer to protect the second conductive layer 530. A plurality of insulating layer vias h21-h31 are formed in the third insulating layer 610. Each of the plurality of insulating layer vias h21-h31 corresponds to a pixel circuit.

[0204] For example, such as Figure 6F and Figure 6G As shown, insulating layer via h21 penetrates the third insulating layer 610 to expose a portion of the first sub-initial signal line Vinit1; insulating layer vias h22-27 and 30-31 penetrate the first, second, and third insulating layers 610 to expose a portion of the active semiconductor layer 510; insulating layer via h28 penetrates the third insulating layer 610 to expose a portion of the second electrode plate CC2 of the storage capacitor Cst; and insulating layer via h29 penetrates the second and third insulating layers 610 to expose a portion of the first electrode plate CC1 of the storage capacitor Cst. For example, the orthographic projection of insulating layer via h29 on the substrate lies within the orthographic projection of conductive layer via h11 on the substrate.

[0205] Figure 6H The source-drain metal layer 540 of the pixel circuit 120 is shown. The source-drain metal layer 540 is disposed on the side of the third insulating layer 610 away from the second conductive layer 530. Figure 6I A schematic diagram showing the stacking position relationship of the active semiconductor layer 510, the first conductive layer 520, the second conductive layer 530, the third insulating layer 610, and the source / drain metal layer 540 is shown.

[0206] For example, such as Figure 6H and Figure 6I As shown, the source-drain metal layer 540 includes a data line Vda, a first sub-voltage line VDD1, a second sub-initial signal line Vinit2, a first electrode fc1 of a first reset transistor T1, a first electrode fc2 and a second electrode sc2 of a threshold compensation transistor T2, a first electrode fc3 of a drive transistor T3, a first electrode fc4 of a data write transistor T4, a second electrode sc5 of a second light-emitting control transistor T5, a first electrode fc6 and a second electrode sc6 of a first light-emitting control transistor T6, a second electrode sc7 of a second reset transistor T7, a first connection electrode Co1, a second connection electrode Co2, and a third connection electrode Co3.

[0207] For example, the data line Vda, the first sub-voltage line VDD1, and the second sub-initial signal line Vinit2 are located on the same layer, namely the source-drain metal layer 540. The data line Vda, the first sub-voltage line VDD1, and the second sub-initial signal line Vinit2 are arranged along the first direction X and all extend along the second direction Y. In the first direction X, the data line Vda is located between the first sub-voltage line VDD1 and the second sub-initial signal line Vinit2. It should be noted that this disclosure is not limited to this. In some other embodiments, the first sub-voltage line VDD1 is located between the data line Vda and the second sub-initial signal line Vinit2.

[0208] For example, a planarization layer 620 is formed on the side of the source / drain metal layer 540 away from the third insulating layer 610 to protect the source / drain metal layer 540. Figure 6J As shown, the planarization layer 620 includes a first via h100, which penetrates the planarization layer 420. For example, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 121 through the first via h100 penetrating the planarization layer 420.

[0209] Figure 6K This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 510, the first conductive layer 520, the second conductive layer 530, the third insulating layer 610, the source / drain metal layer 540, and the planarization layer 620.

[0210] For example, such as Figure 6KAs shown, in the second direction Y, the orthogonal projection of the first via h100 on the substrate is located between the orthogonal projection of the reset signal line Rt on the substrate and the orthogonal projection of the second light-emitting control signal line EM2 on the substrate. That is, in the embodiments of this disclosure, the setting position of the first via h100 is more flexible and can adapt to pixel circuits with various pixel arrangements. Furthermore, the position of the first via h100 can be flexibly adjusted according to the setting position of the first electrode of the light-emitting element, thereby making the first via h100 closer to the first electrode of the light-emitting element, reducing the traces of the first electrode of the light-emitting element, and making the connection between the first electrode of the light-emitting element and the second electrode of the first light-emitting control transistor T6 more flexible. Figure 6K As shown, the first via h100 is located near the scan signal line Ga. In the second direction Y, the orthographic projection of the first via h100 on the substrate is approximately between the orthographic projection of the scan signal line Ga on the substrate and the orthographic projection of the second light emission control signal line EM2 on the substrate.

[0211] For example, in other embodiments, in the second direction Y, the orthogonal projection of the first via h100 on the substrate is located between the orthogonal projection of the scan signal line Ga on the substrate and the orthogonal projection of the first light emission control signal line EM1 on the substrate.

[0212] Figure 6L The anode layer 650 of the pixel circuit 120 is shown, and the anode layer 650 includes the first electrode (i.e., anode) R / G / B of the light-emitting element 121. It should be noted that... Figure 6L In the image, only the electroluminescent layer in the light-emitting layer is shown, and the other common layers are not shown.

[0213] For example, multiple sub-pixel pairs include multiple first sub-pixel pairs and multiple second sub-pixel pairs. Each first sub-pixel pair includes one first sub-pixel and one second sub-pixel, and each second sub-pixel pair includes one first sub-pixel and one third sub-pixel. The first sub-pixel can be a green sub-pixel, the second sub-pixel can be a red sub-pixel, and the third sub-pixel can be a blue sub-pixel. In each sub-pixel row (parallel to the first direction X), multiple first sub-pixel pairs and multiple second sub-pixel pairs are arranged alternately, and in each sub-pixel column (parallel to the second direction Y), multiple first sub-pixel pairs and multiple second sub-pixel pairs are also arranged alternately.

[0214] For example, such as Figure 6LAs shown, the four sub-pixel pairs located in two rows and two columns include two first sub-pixel pairs PP1 and two second sub-pixel pairs PP2. The two first sub-pixel pairs PP1 are located in the first row and first column and the second row and second column, respectively, and the two second sub-pixel pairs PP2 are located in the first row and second column and the second row and first column, respectively. The first sub-pixel pair PP1 includes a red sub-pixel R and a green sub-pixel G, and the second sub-pixel pair PP2 includes a blue sub-pixel B and a green sub-pixel G. That is, as... Figure 6L As shown, multiple sub-pixel pairs located in odd-numbered rows (first row) are arranged sequentially in the manner RG(first sub-pixel pair PP1)BG(second sub-pixel pair PP2)RG(first sub-pixel pair PP1)BG(second sub-pixel pair PP2), and multiple sub-pixel pairs located in even-numbered rows (second row) are arranged sequentially in the manner (second sub-pixel pair PP2)RG(first sub-pixel pair PP1)BG(second sub-pixel pair PP2)RG(first sub-pixel pair PP1).

[0215] For example, when the data line Vda is located between the first sub-voltage line VDD1 and the second sub-initial signal line Vinit2 in the first direction X, for two adjacent sub-pixel pairs in the first direction X among multiple sub-pixel pairs, the pixel circuits of the two adjacent sub-pixels in the two sub-pixel pairs in the first direction X are electrically connected to the same first sub-voltage line. Figure 6H and Figure 6L As shown, in one example, two adjacent sub-pixel pairs in the first direction X are respectively the first sub-pixel pair PP1 and the second sub-pixel pair PP2 located in the first row. The two adjacent sub-pixels in the first direction X of the first sub-pixel pair PP1 and the second sub-pixel pair PP2 are respectively a green sub-pixel G in the first sub-pixel pair PP1 and a blue sub-pixel B in the second sub-pixel pair PP2. The pixel circuits of the green sub-pixel G and the blue sub-pixel B are electrically connected to the same first sub-voltage line VDD1', and the first sub-voltage line VDD1' is located between the pixel circuits of the green sub-pixel G and the blue sub-pixel B. In embodiments of this disclosure, by electrically connecting the pixel circuits of adjacent sub-pixels to the same first sub-voltage line, wiring can be saved.

[0216] For example, the pixel circuit of the blue sub-pixel B in the first sub-pixel pair PP1 and the pixel circuit of the green sub-pixel G in the second sub-pixel pair located on the side of the first sub-pixel pair PP1 away from the second sub-pixel pair PP2 are electrically connected to the same first sub-voltage line VDD1. For example, the pixel circuit of the green sub-pixel G in the second sub-pixel pair PP2 and the pixel circuit of the red sub-pixel R in the first sub-pixel pair located on the side of the second sub-pixel pair PP2 away from the first sub-pixel pair PP1 are electrically connected to the same first sub-voltage line VDD1.

[0217] For example, such as Figure 6H and Figure 6L As shown, in another example, two adjacent sub-pixel pairs in the first direction X are the first sub-pixel pair PP1 and the second sub-pixel pair PP2 located in the second row. The two adjacent sub-pixels in the first direction X of the first sub-pixel pair PP1 and the second sub-pixel pair PP2 are a green sub-pixel G in the second sub-pixel pair PP2 and a red sub-pixel R in the first sub-pixel pair PP1. The pixel circuits of the green sub-pixel G and the red sub-pixel R are electrically connected to the same first sub-voltage line VDD1'.

[0218] For example, such as Figure 6H and Figure 6L As shown, in the first row, the second electrode of the second light-emitting control transistor in the pixel circuit of the green sub-pixel G, which is electrically connected to the first sub-voltage line VDD1', and the second electrode of the second light-emitting control transistor in the pixel circuit of the blue sub-pixel B are the same, that is... Figure 6H The electrode sc5' is shown. In addition, the vias h28' and h30' corresponding to the first sub-voltage line VDD1' are also shared by the pixel circuits of the green sub-pixel G in the first sub-pixel pair PP1 and the blue sub-pixel B in the second sub-pixel pair PP2, which are electrically connected to the first sub-voltage line VDD1'.

[0219] For example, such as Figure 6H and Figure 6L As shown, the pixel circuits of the first sub-pixel pair PP1 and the second sub-pixel pair PP2 in the first row are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1'. Similarly, the pixel circuits of the first sub-pixel pair PP1 and the second sub-pixel pair PP2 in the second row are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1'. In other words, the pixel circuits in the first column and the second column are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1'.

[0220] Figure 6M This is a schematic diagram showing the stacking relationship of the active semiconductor layer 510, the first conductive layer 520, the second conductive layer 530, the third insulating layer 610, the source / drain metal layer 540, the planarization layer 620, and the anode layer 550. For example, as... Figure 6M As shown, the first electrode of the light-emitting element 121 is connected to the first connecting electrode Co1 through the first via h100. The first connecting electrode Co1 is connected to the second electrode sc6 of the first light-emitting control transistor T6, thereby electrically connecting the first electrode of the light-emitting element 121 to the second electrode sc6 of the first light-emitting control transistor T6.

[0221] Figure 7A for Figure 6MA schematic diagram of the cross-sectional structure at point A' on the middle line. Figure 7B for Figure 6M A schematic diagram of the cross-sectional structure at the straight line B'.

[0222] For example, such as Figure 7A and Figure 7B As shown, the substrate 10 includes a multilayer structure (e.g., Figure 7A (Shown as a two-layer structure), all multi-layer structures are made of flexible materials.

[0223] For example, such as Figure 7A and Figure 7B As shown, a buffer layer 11 is formed on the substrate 10 to prevent external moisture, oxygen, and impurities from entering the pixel circuit 120. For example, the material of the buffer layer 11 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.

[0224] For example, such as Figure 7A and Figure 7B As shown, an active semiconductor layer 510 is formed on the side of the buffer layer 11 away from the substrate 10. Figure 7A The active semiconductor layer 510 shown includes a first reset active layer portion T11 and a first compensation active layer portion T21. Figure 7B The active semiconductor layer 510 shown includes a portion of the active semiconductor layer 510 corresponding to the second electrode of the first light-emitting control transistor T6.

[0225] For example, such as Figure 7A and Figure 7B As shown, a first insulating layer 630 is formed on the side of the active semiconductor layer 510 away from the buffer layer 11, and a first conductive layer 520 is formed on the side of the first insulating layer 630 away from the active semiconductor layer 510. Figure 5A (not shown in the image) Figure 7B The first conductive layer 520 shown includes a portion of the first electrode plate CC1 for the scan signal line Ga and the storage capacitor Cst.

[0226] For example, such as Figure 7A and Figure 7B As shown, a second insulating layer 640 is formed on the side of the first conductive layer 520 away from the first insulating layer 630, and a second conductive layer 530 is formed on the side of the second insulating layer 640 away from the first conductive layer 520. Figure 7AThe second conductive layer 530 shown includes a first sub-initial signal line Vinit1. The orthographic projection of the first reset active layer portion T11 on the substrate 10 and the orthographic projection of the first compensation active layer portion T21 on the substrate 10 are both located within the orthographic projection of the first sub-initial signal line Vinit1 on the substrate 10. Thus, in the direction perpendicular to the substrate 10, the first sub-initial signal line Vinit1 can block the first reset active layer portion T11 and the first compensation active layer portion T21. Figure 7B The second conductive layer 530 shown includes a portion of the second electrode plate CC2 for the storage capacitor Cst.

[0227] For example, such as Figure 7A and Figure 7B As shown, a third insulating layer 610 is formed on the side of the second conductive layer 530 away from the second insulating layer 640, and a source / drain metal layer 540 is formed on the side of the third insulating layer 610 away from the second conductive layer 530. Figure 7A The source-drain metal layer 540 shown includes a data line Vda and a second sub-initial signal line Vinit2. The second sub-initial signal line Vinit2 is connected to the first sub-initial signal line Vinit1 through an insulating layer via h21 that penetrates the third insulating layer 610, thereby electrically connecting the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 to each other. Figure 7B The source-drain metal layer 540 shown includes a first connection electrode Co1, which is electrically connected to the portion of the active semiconductor layer 510 corresponding to the second electrode of the first light-emitting control transistor T6 through a second via h200 that penetrates the first insulating layer 630, the second insulating layer 640 and the third insulating layer 610.

[0228] For example, such as Figure 7A and Figure 7B As shown, a planarization layer 620 is formed on the side of the source / drain metal layer 540 away from the third insulating layer 610, an anode layer 550 is formed on the side of the planarization layer 620 away from the source / drain metal layer 540, and a pixel defining layer 560 is formed on the side of the anode layer 550 away from the planarization layer 620 and on the planarization layer 620. The pixel defining layer 560 includes a plurality of pixel openings. In a direction perpendicular to the substrate, each pixel opening exposes at least a portion of the first electrode R / G / B of the corresponding light-emitting element.

[0229] For example, the first connecting electrode Co1 is electrically connected to the second electrode of the first light-emitting control transistor T6, for example, they are integrally formed, such as... Figure 7BAs shown, the first connecting electrode Co1 is electrically connected to the first electrode of the light-emitting element 120 in the anode layer 550 through the first via h100. Therefore, a jumper design is implemented at the fourth node N4, where the portion of the active semiconductor layer 510 corresponding to the second electrode of the first light-emitting control transistor T6 is first connected to the first connecting electrode Co1 through the second via h200. Then, the first connecting electrode Co1 is electrically connected to the first electrode of the light-emitting element 120 in the anode layer 550 through the first via h100, allowing for more flexible placement of the first via h100.

[0230] In the above embodiment, the first light-emitting control signal line EM1 is generally curved, but this disclosure is not limited thereto. Figure 8 This is a schematic diagram of the structure of a first conductive layer provided in other embodiments of this disclosure, for example, as shown below. Figure 8 As shown, in some other embodiments, the first light-emitting control signal line EM1 in the first conductive layer 320” is generally linear in shape. Figure 4C and Figure 6C As shown, the line connecting the center of the active layer of the first light-emitting control transistor T6 and the center of the active layer of the second reset transistor T7 is not parallel to either the first direction X or the second direction Y. Figure 8 As shown, the rectangular solid-line frame indicates the overlap between the active layer of the first light-emitting control transistor T6 and the first conductive layer 320”, and the overlap between the active layer of the second reset transistor T7 and the first conductive layer 320”. Based on this, it can be seen that in Figure 8 In the example shown, the line connecting the center of the active layer of the first light-emitting control transistor T6 and the center of the active layer of the second reset transistor T7 is approximately parallel to the first direction X.

[0231] It should be noted that, in this disclosure, the areas indicated by the rectangular dashed boxes and rectangular dotted-line boxes only represent the approximate area of ​​the pixel circuit or the pixel circuit of the sub-pixel pair. The actual area of ​​the pixel circuit is related to the specific placement of transistors and capacitors in the pixel circuit.

[0232] At least one embodiment of this disclosure also provides a display panel. Figure 9 This is a schematic diagram of a display panel provided for at least one embodiment of the present disclosure. Figure 9 As shown, the display panel 800 includes the display substrate 100 provided in any embodiment of this disclosure, for example, Figure 1 The display substrate 100 shown is shown.

[0233] For example, the display panel 800 can be a liquid crystal display panel or an organic light-emitting diode (OLED) display panel. For example, when the display panel 800 is a liquid crystal display panel, the display substrate 100 can be an array substrate or a color filter substrate. When the display panel 800 is an organic light-emitting diode display panel, the display substrate 100 can be an array substrate.

[0234] For example, the display panel 800 can be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel. In addition, the display panel 800 can be not only a flat panel, but also a curved panel, or even a spherical panel.

[0235] For example, the display panel 800 can also have a touch function, that is, the display panel 800 can be a touch display panel.

[0236] For example, the display panel 800 can be used in any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0237] For example, the display panel 800 can be a flexible display panel, thereby meeting various practical application needs. For instance, the display panel 800 can be applied to curved screens, etc.

[0238] It should be noted that the display panel 800 may also include other components, such as data driving circuits and timing controllers, and the embodiments of this disclosure do not limit this. For clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display panel 800. To achieve the basic functions of the display panel 800, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not limit this.

[0239] For the technical effects of the display panel 800 provided in the above embodiments, please refer to the technical effects of the display substrate 100 provided in the embodiments of this disclosure, which will not be repeated here.

[0240] The following points should be noted regarding this disclosure:

[0241] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0242] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0243] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0244] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate substrate and a plurality of sub-pixels, a first voltage line, a data line, a scan signal line, a first light-emitting control signal line and a second light-emitting control signal line arranged on the substrate substrate, Each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit and a data writing sub-circuit, The first light-emitting control sub-circuit is electrically connected to the first end of the driving sub-circuit, the first electrode of the light-emitting element and the first light-emitting control signal line, and is configured to control the connection between the first end of the driving sub-circuit and the first electrode of the light-emitting element to be turned on or turned off under the control of the first light-emitting control signal on the first light-emitting control signal line; The second light-emitting control sub-circuit is electrically connected to the second end of the driving sub-circuit, the first voltage line and the second light-emitting control signal line, and is configured to control the connection between the second end of the driving sub-circuit and the first voltage line to be turned on or turned off under the control of the second light-emitting control signal on the second light-emitting control signal line; The data writing sub-circuit is electrically connected to the second end of the driving sub-circuit, the data line and the scan signal line, and is configured to transmit the data voltage on the data line to the second end of the driving sub-circuit under the control of the scan signal on the scan signal line; The first light-emitting control signal line, the scan signal line and the second light-emitting control signal line extend along a first direction and are arranged along a second direction which is not parallel to the first direction, and in the second direction, the scan signal line is located between the first light-emitting control signal line and the second light-emitting control signal line; The display substrate further includes a reset signal line and an initial signal line arranged on the substrate substrate, The pixel circuit further includes a reset sub-circuit, the reset sub-circuit is electrically connected to the control end of the driving sub-circuit, the initial signal line, the first light-emitting control signal line and the reset signal line, and is configured to transmit the initial voltage on the initial signal line to the control end of the driving sub-circuit under the control of the first light-emitting control signal and the reset control signal on the reset signal line; The reset signal line extends along the first direction, and in the second direction, the reset signal line is located on the side of the first light-emitting control signal line away from the scan signal line, The reset sub-circuit includes a first reset transistor and a second reset transistor, the gate of the first reset transistor is electrically connected to the reset signal line, the first electrode of the first reset transistor is electrically connected to the initial signal line, the second electrode of the first reset transistor is electrically connected to the first electrode of the second reset transistor, the gate of the second reset transistor is electrically connected to the first light-emitting control signal line, and the second electrode of the second reset transistor is electrically connected to the control end of the driving sub-circuit, The first light-emitting control sub-circuit includes a first light-emitting control transistor, a gate electrode of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, a first electrode of the first light-emitting control transistor is electrically connected to the first end of the driving sub-circuit, and a second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, The pixel circuit further includes a threshold compensation sub-circuit, the threshold compensation sub-circuit includes a threshold compensation transistor, a gate electrode of the threshold compensation transistor is electrically connected to the reset signal line, a first electrode of the threshold compensation transistor is electrically connected to the first end of the driving sub-circuit, and a second electrode of the threshold compensation transistor is electrically connected to the control end of the driving sub-circuit, The driving sub-circuit includes a driving transistor, an active layer of the first reset transistor and an active layer of the second reset transistor are integrally arranged, and an active layer of the first light-emitting control transistor and an active layer of the second reset transistor are located on a first side of an active layer of the driving transistor. 2.The display substrate of claim 1, wherein, The pixel circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is electrically connected to the control end of the driving sub-circuit, and a second electrode plate of the storage capacitor is electrically connected to the first voltage line, In the second direction, a normal projection of the first light-emitting control signal line on the substrate and a normal projection of the second light-emitting control signal line on the substrate are located on two sides of a normal projection of the second electrode plate of the storage capacitor on the substrate. 3.The display substrate of claim 2, wherein, In the second direction, a normal projection of the scan signal line on the substrate and a normal projection of the second light-emitting control signal line on the substrate are located on two sides of a normal projection of the second electrode plate of the storage capacitor on the substrate.

4. The display substrate of claim 1, wherein The threshold compensation sub-circuit is electrically connected to the control end and the first end of the driving sub-circuit and the reset signal line, and is configured to control a connection between the first end of the driving sub-circuit and the control end of the driving sub-circuit to be turned on or turned off under control of the reset control signal. 5.The display substrate of claim 4, wherein, The active layer of the first reset transistor is a reset active layer, and the reset active layer includes a first reset active layer part, The threshold compensation transistor includes a compensation active layer, and the compensation active layer includes a first compensation active layer part, A normal projection of the first reset active layer part on the substrate and a normal projection of the initial signal line on the substrate at least partially overlap, A normal projection of the first compensation active layer part on the substrate and a normal projection of the initial signal line on the substrate at least partially overlap. 6.The display substrate of claim 5, wherein, The initial signal line includes a first sub-initial signal line, the first sub-initial signal line extends along the first direction, and a normal projection of the first reset active layer part on the substrate and a normal projection of the first compensation active layer part on the substrate are both located within a normal projection of the first sub-initial signal line on the substrate. 7.The display substrate of claim 6, wherein, The first reset active layer portion and the first compensation active layer portion are arranged in sequence in the first direction. 8.The display substrate of claim 6, wherein, The initial signal line further includes a second sub-initial signal line, the second sub-initial signal line extends along the second direction, and the first sub-initial signal line and the second sub-initial signal line are electrically connected. 9.The display substrate of claim 8, wherein, The display substrate includes an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer, in a direction perpendicular to the substrate substrate, the active semiconductor layer is located between the substrate substrate and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, and the second conductive layer is located between the first conductive layer and the source-drain metal layer, The first sub-initial signal line is located in the second conductive layer, and the second sub-initial signal line is located in the source-drain metal layer. 10.The display substrate of claim 5, wherein, The reset active layer further includes a second reset active layer portion, and the compensation active layer includes a second compensation active layer portion, The second reset active layer portion and the reset signal line at least partially overlap on the substrate substrate, The second compensation active layer portion and the reset signal line at least partially overlap on the substrate substrate, The second reset active layer portion and the second compensation active layer portion are arranged in sequence in the first direction. 11.The display substrate of claim 5, wherein, The first reset transistor and the threshold compensation transistor are both double-gate transistors. 12.The display substrate of claim 4, wherein, The display substrate includes an active semiconductor layer and a first conductive layer, in a direction perpendicular to the substrate substrate, the active semiconductor layer is located between the substrate substrate and the first conductive layer, The reset signal line, the scan signal line, the first light-emitting control signal line, and the second light-emitting control signal line are all located in the first conductive layer. 13.The display substrate of claim 4, wherein, Under the control of the first light-emitting control signal and the reset control signal, the initial voltage is transmitted to the first electrode of the light-emitting element via the reset sub-circuit, the threshold compensation sub-circuit, and the first light-emitting control sub-circuit. 14.The display substrate of claim 4, wherein, The control end of the driving sub-circuit includes the gate of the driving transistor, the first end of the driving sub-circuit includes the first pole of the driving transistor, and the second end of the driving sub-circuit includes the second pole of the driving transistor. The second light-emitting control sub-circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first pole of the second light-emitting control transistor is electrically connected to the second pole of the driving transistor, and the second pole of the second light-emitting control transistor is electrically connected to the first voltage line. The data write sub-circuit includes a data write transistor, the gate of the data write transistor is electrically connected to the scan signal line, the first pole of the data write transistor is electrically connected to the data line, and the second pole of the data write transistor is electrically connected to the second pole of the driving transistor. 15.The display substrate of claim 14, wherein, The display substrate comprises an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer and a planarization layer, in a direction perpendicular to the substrate substrate, the active semiconductor layer is located between the substrate substrate and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, the second conductive layer is located between the first conductive layer and the source-drain metal layer, the planarization layer is located on the side of the source-drain metal layer away from the substrate substrate, The second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a first via hole penetrating through the planarization layer, In the second direction, the orthographic projection of the first via hole on the substrate substrate is located between the orthographic projection of the reset signal line on the substrate substrate and the orthographic projection of the second light-emitting control signal line on the substrate substrate. 16.The display substrate of claim 15, wherein, The display substrate further comprises a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is located between the active semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, and the third insulating layer is located between the second conductive layer and the source-drain metal layer, The part of the active semiconductor layer corresponding to the second electrode of the first light-emitting control transistor is electrically connected to the first connection electrode in the source-drain metal layer through a second via hole penetrating through the first insulating layer, the second insulating layer and the third insulating layer, and the first connection electrode is electrically connected to the second electrode of the first light-emitting control transistor, The first connection electrode is electrically connected to the first electrode of the light-emitting element through the first via hole. 17.The display substrate of claim 15, wherein, In the second direction, the orthographic projection of the first via hole on the substrate substrate is located between the orthographic projection of the scan signal line on the substrate substrate and the orthographic projection of the first light-emitting control signal line on the substrate substrate. 18.The display substrate of claim 1, wherein, The first voltage line comprises a first sub-voltage line and a second sub-voltage line, the first sub-voltage line and the second sub-voltage line are electrically connected, the first sub-voltage line extends along the second direction, and the second sub-voltage line extends along the first direction.

19. The display substrate of claim 18, wherein, The pixel circuits of the plurality of sub-pixels are arranged in an array along the first direction and the second direction. 20.The display substrate of claim 19, wherein, The initial signal line comprises a first sub-initial signal line and a second sub-initial signal line, the first sub-initial signal line extends along the first direction, the second sub-initial signal line extends along the second direction, and the first sub-initial signal line and the second sub-initial signal line are electrically connected, The data line extends along the second direction, The first sub-voltage line, the data line and the second sub-initial signal line are located in the same layer, the data line, the first sub-voltage line and the second sub-initial signal line are arranged along the first direction, and in the first direction, the first sub-voltage line is located between the data line and the second sub-initial signal line.

21. The display substrate of claim 18, wherein, The plurality of sub-pixels comprises a plurality of sub-pixel pairs, the plurality of sub-pixel pairs are arranged in an array along the first direction and the second direction, Each of the sub-pixel pairs comprises two sub-pixels adjacent to each other in the first direction, pixel circuits of the two sub-pixels being mirror-symmetrical along a symmetry axis parallel to the second direction.

22. The display substrate of claim 21, wherein, The initial signal line comprises a first sub-initial signal line and a second sub-initial signal line, the first sub-initial signal line extending along the first direction, the second sub-initial signal line extending along the second direction, the first sub-initial signal line and the second sub-initial signal line being electrically connected, The data line extends along the second direction, The first sub-voltage line, the data line and the second sub-initial signal line are located in the same layer, the data line, the first sub-voltage line and the second sub-initial signal line are arranged along the first direction, and in the first direction, the data line is located between the first sub-voltage line and the second sub-initial signal line.

23. The display substrate of claim 22, wherein, For two sub-pixel pairs adjacent to each other in the first direction among the plurality of sub-pixel pairs, Pixel circuits of two sub-pixels of the two sub-pixel pairs adjacent to each other in the first direction are electrically connected to the same first sub-voltage line.

24. The display substrate according to any one of claims 1-23, wherein, The first light-emitting control signal line has a shape of a curved shape or a straight line shape.

25. The display substrate according to any one of claims 1-23, wherein, The first direction and the second direction are perpendicular to each other.

26. A display panel comprising the display substrate according to any one of claims 1-25.

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