Display substrate, preparation method thereof and display device

Abstract

A display substrate is provided, comprising: a substrate (30) and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer and a third conductive layer disposed on the substrate (30). The first semiconductor layer at least includes: an active layer of at least one second semiconductor transistor of a shift register unit. The first conductive layer at least includes: a control electrode of at least one second semiconductor transistor of the shift register unit, a first electrode of at least one capacitor. The second semiconductor layer at least includes: an active layer of at least one first semiconductor transistor of the shift register unit. The second conductive layer at least includes: a control electrode of at least one first semiconductor transistor of the shift register unit, a second electrode of at least one capacitor. The third conductive layer at least includes: a first electrode and a second electrode of at least one first semiconductor transistor and at least one second semiconductor transistor of the shift register unit.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as ultra-thinness, wide viewing angle, active emission, high brightness, continuously adjustable emission color, low cost, fast response speed, low power consumption, wide operating temperature range, and flexible display capabilities. They have gradually become a promising next-generation display technology and are receiving increasing attention. Based on different driving methods, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a display area and a peripheral area surrounding the display area. The peripheral area is provided with a gate driving circuit, which includes a plurality of cascaded shift register units. Each shift register unit includes at least one first semiconductor transistor, at least one second semiconductor transistor, and at least one capacitor. The first and second semiconductor transistors have opposite doping types. In a direction perpendicular to the display substrate, the display substrate includes: a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of at least one second semiconductor transistor of the shift register unit. The first conductive layer includes at least: a control electrode of at least one second semiconductor transistor of the shift register unit and a first electrode of at least one capacitor. The second semiconductor layer includes at least: an active layer of at least one first semiconductor transistor of the shift register unit. The second conductive layer includes at least: a control electrode of at least one first semiconductor transistor of the shift register unit and a second electrode of at least one capacitor. The third conductive layer includes at least: at least one first semiconductor transistor and at least one first electrode and second electrode of the shift register unit.

[0006] In some exemplary embodiments, the first conductive layer further includes: a third output terminal of the shift register unit; the second semiconductor layer is located on the side of the third output terminal away from the first semiconductor layer.

[0007] In some exemplary embodiments, the second semiconductor transistor includes a first transistor and a second transistor, and the first semiconductor transistor includes a third transistor and a fourth transistor.

[0008] In some exemplary embodiments, the first conductive layer further includes: a first output terminal and a second output terminal of the shift register unit. The control electrode of the second transistor and the second output terminal are integrally formed, the control electrode of the first transistor is located between the control electrode of the second transistor and the second output terminal, and the third output terminal is located on the side of the first transistor's control electrode away from the second output terminal.

[0009] In some exemplary embodiments, the extension directions of the first output terminal, the second output terminal, and the third output terminal are parallel to each other.

[0010] In some exemplary embodiments, the active layer of the third transistor and the active layer of the fourth transistor are located on the side of the third output terminal away from the first transistor and the second transistor, and the active layer of the third transistor and the active layer of the fourth transistor are an integral structure.

[0011] In some exemplary embodiments, the integrated structure of the active layer of the third transistor and the active layer of the fourth transistor is in the shape of a "U".

[0012] In some exemplary embodiments, the second terminal of the second transistor, the second terminal of the third transistor, and the second terminal of the fourth transistor are integrally formed and connected to the third output terminal.

[0013] In some exemplary embodiments, the second conductive layer further includes a control signal line. The third conductive layer further includes a fourth connection electrode; the fourth connection electrode is connected to the control electrode of the first transistor, the control electrode of the fourth transistor, and the control signal line.

[0014] In some exemplary embodiments, the third conductive layer further includes a first power line and a second power line. The first electrode of the first transistor is connected to the first power line, and the first electrodes of the third transistor and the fourth transistor are connected to the second power line.

[0015] In some exemplary embodiments, the third conductive layer further includes a first clock signal line and a second clock signal line. The first clock signal line, the second clock signal line, the first power line, and the second power line extend in parallel directions and are perpendicular to the extension direction of the control signal line.

[0016] In some exemplary embodiments, the shift register unit includes: an input circuit, a first control circuit, a second control circuit, and an output circuit. The input circuit is connected to a first clock signal line, a second clock signal line, a first input terminal, a first power supply line, a first control node, and a second control node. It is configured to provide a signal from the first input terminal to the second control node under the control of the first clock signal line, and to provide a signal from the first clock signal line or the first power supply line to the first control node under the control of the second clock signal line, the first input terminal, and the second control node. The first control circuit is connected to the first control node, the second control node, the first power supply line, the second power supply line, and a first output terminal. It is configured to provide a signal from the first power supply line or the second power supply line to the first output terminal under the control of the first and second control nodes. The second control circuit is connected to the first power supply line, the second power supply line, the first output terminal, and a second output terminal. It is configured to provide an effective level signal of the first power supply line or the second power supply line to the second output terminal under the control of the first output terminal. The output circuit is connected to a control signal line, a first power line, a second power line, a second output terminal, and a third output terminal. It is configured to output a valid level signal of either the first or second power line to the third output terminal under the control of the control signal line and the second output terminal. Within one frame, the duration of the valid level signal provided by the third output terminal is greater than the duration of the valid level signal provided by the second output terminal.

[0017] In some exemplary embodiments, the output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The control electrode of the first transistor is connected to a control signal line, its first electrode is connected to a first power supply line, and its second electrode is connected to the first electrode of the second transistor. The control electrode of the second transistor is connected to a second output terminal, and its second electrode is connected to a third output terminal. The control electrode of the third transistor is connected to the second output terminal, its first electrode is connected to a second power supply line, and its second electrode is connected to a third output terminal. The control electrode of the fourth transistor is connected to a control signal line, its first electrode is connected to a second power supply line, and its second electrode is connected to a third output terminal.

[0018] In some exemplary embodiments, the second control circuit includes a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is connected to a first output terminal, the first electrode of the fifth transistor is connected to a first power supply line, and the second electrode of the fifth transistor is connected to a second output terminal. The control electrode of the sixth transistor is connected to the first output terminal, the first electrode of the sixth transistor is connected to a second power supply line, and the second electrode of the sixth transistor is connected to a second output terminal. The fifth transistor is a second semiconductor transistor, and the sixth transistor is a first semiconductor transistor.

[0019] In some exemplary embodiments, the fifth transistor is located on the side of the first transistor and the second transistor that is close to the first control circuit, and the sixth transistor is located on the side of the third transistor that is close to the first control circuit.

[0020] In some exemplary embodiments, the first electrode of the first transistor, the first electrode of the fifth transistor, and the first power line are integral structures; the second electrode of the fifth transistor and the second electrode of the sixth transistor are integral structures and are connected to the control electrode of the third transistor, the control electrode of the second transistor, and the second output terminal.

[0021] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0022] On the other hand, this disclosure provides a method for fabricating a display substrate, used to fabricate the display substrate as described above. The fabrication method includes: providing a substrate; forming a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer on the substrate in a peripheral region surrounding a display area. The first semiconductor layer includes at least: an active layer of at least one second semiconductor transistor of a shift register unit of a gate driving circuit; the first conductive layer includes at least: a control electrode of at least one second semiconductor transistor of the shift register unit and a first electrode of at least one capacitor; the second semiconductor layer includes at least: an active layer of at least one first semiconductor transistor of the shift register unit; the second conductive layer includes at least: a control electrode of at least one first semiconductor transistor of the shift register unit and a second electrode of at least one capacitor; the third conductive layer includes at least: a first electrode and a second electrode of at least one first semiconductor transistor and at least one second semiconductor transistor of the shift register unit.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0025] Figure 1 This is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure;

[0026] Figure 2This is a schematic diagram of the output circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0027] Figure 3 This is an equivalent circuit diagram of the output circuit of the shift register unit of at least one embodiment of the present disclosure;

[0028] Figure 4 This is an equivalent circuit diagram of the second control circuit of the shift register unit in at least one embodiment of the present disclosure;

[0029] Figure 5 This is an equivalent circuit diagram of the input circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0030] Figure 6 This is an equivalent circuit diagram of the first control circuit of the shift register unit in at least one embodiment of the present disclosure;

[0031] Figure 7 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0032] Figure 8 for Figure 7 The timing diagram of the shift register unit shown is shown below;

[0033] Figure 9 A flowchart illustrating a method for driving a shift register unit according to at least one embodiment of this disclosure;

[0034] Figure 10 This is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0035] Figure 11 This is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure;

[0036] Figure 12 This is an equivalent circuit diagram of the second shift register unit of at least one embodiment of the present disclosure;

[0037] Figure 13 for Figure 12 The timing diagram of the second shift register unit is shown below;

[0038] Figure 14 This is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure;

[0039] Figure 15 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] Figure 16 This is a schematic diagram of the pixel circuit structure of at least one embodiment of the present disclosure;

[0041] Figure 17This is another schematic diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0042] Figure 18 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] Figure 19 for Figure 18 The timing diagram of the pixel circuit shown is shown below.

[0044] Figure 20 This is a top view of a sub-pixel of the display area of ​​at least one embodiment of the present disclosure;

[0045] Figure 21 for Figure 20 A cross-sectional view along the QQ direction;

[0046] Figure 22 This is a top view of a sub-pixel after the formation of the first semiconductor layer, according to at least one embodiment of this disclosure;

[0047] Figure 23 This is a top view of a sub-pixel after the formation of the first conductive layer, according to at least one embodiment of this disclosure;

[0048] Figure 24 This is a top view of a sub-pixel after the formation of the second semiconductor layer, according to at least one embodiment of this disclosure;

[0049] Figure 25 This is a top view of a sub-pixel after the formation of the second conductive layer, according to at least one embodiment of this disclosure;

[0050] Figure 26 This is a top view of a sub-pixel after the formation of the fifth insulating layer, according to at least one embodiment of this disclosure;

[0051] Figure 27 This is a top view of a sub-pixel after the formation of the third conductive layer, according to at least one embodiment of this disclosure;

[0052] Figure 28 This is another top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure;

[0053] Figure 29 for Figure 28 A cross-sectional view along the HH direction;

[0054] Figure 30 This is a top view of a sub-pixel after the formation of the fifth insulating layer, according to at least one embodiment of this disclosure;

[0055] Figure 31 This is a top view of a sub-pixel after the formation of the third conductive layer, according to at least one embodiment of this disclosure;

[0056] Figure 32This is a top view of a sub-pixel after the formation of the seventh insulating layer, according to at least one embodiment of this disclosure;

[0057] Figure 33 This is a top view of a sub-pixel after the formation of the fourth conductive layer, according to at least one embodiment of this disclosure;

[0058] Figure 34 This is a schematic diagram showing the connection between the gate driving circuit and the pixel circuit in at least one embodiment of the present disclosure;

[0059] Figure 35 This is a top view of a first shift register unit according to at least one embodiment of the present disclosure;

[0060] Figure 36 for Figure 35 A cross-sectional view along the PP direction;

[0061] Figure 37 This is a top view of a first shift register unit after the formation of a first semiconductor layer, according to at least one embodiment of the present disclosure;

[0062] Figure 38 This is a top view of a first shift register unit after the formation of the first conductive layer, according to at least one embodiment of the present disclosure.

[0063] Figure 39 This is a top view of the first shift register unit after the formation of the second semiconductor layer, according to at least one embodiment of the present disclosure;

[0064] Figure 40 This is a top view of the first shift register unit after the formation of the second conductive layer, according to at least one embodiment of the present disclosure;

[0065] Figure 41 This is a top view of the first shift register unit after the formation of the fifth insulating layer, according to at least one embodiment of the present disclosure;

[0066] Figure 42 This is a top view of the first shift register unit after the formation of the third conductive layer, according to at least one embodiment of the present disclosure;

[0067] Figure 43 This is an equivalent circuit diagram of the third shift register unit of at least one embodiment of the present disclosure;

[0068] Figure 44 for Figure 43 The timing diagram of the third shift register unit is shown below;

[0069] Figure 45 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0070] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0071] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0072] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. The term “multiple” in this disclosure refers to two or more quantities.

[0073] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0074] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There is no particular limitation on the term "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0075] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0076] In this disclosure, to distinguish the two electrodes of a transistor other than the gate, one electrode is referred to as the first electrode and the other as the second electrode. The first electrode can be either the source or the drain, and the second electrode can be either the drain or the source. Furthermore, the gate of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0077] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0078] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0079] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0080] In this disclosure, the effective level signal includes the level signal that turns on the transistor. For example, the effective level signal for turning on a P-type transistor is a low-level signal, and the effective level signal for turning on an N-type transistor is a high-level signal.

[0081] This disclosure provides a shift register unit and its driving method, a gate driving circuit, a display substrate, and a display device. The shift register unit of this embodiment can provide various gate driving signals to the pixel circuit to improve the performance of the pixel circuit.

[0082] Figure 1 This is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure. Figure 1As shown, the shift register unit provided in this embodiment includes an input circuit, a first control circuit, a second control circuit, and an output circuit. The input circuit is connected to a first clock signal line CK1, a second clock signal line CB1, a first input terminal INPUT1, a first power supply line VGH, a first control node P1, and a second control node P2. It is configured to provide the signal of the first input terminal INPUT1 to the second control node P2 under the control of the first clock signal line CLK1, and to provide the signal of the first clock signal line CK1 or the first power supply line VGH to the first control node P1 under the control of the second clock signal line CB1, the first input terminal INPUT1, and the second control node P2. The first control circuit is connected to the first power supply line VGH, the second power supply line VGL, the first control node P1, the second control node P2, and a first output terminal OUT1. It is configured to provide the signal of the first power supply line VGH or the second power supply line VGL to the first output terminal OUT1 under the control of the first control node P1 and the second control node P2. The second control circuit is connected to the first power line VGH, the second power line VGL, the first output terminal OUT1, and the second output terminal OUT2. It is configured to provide a valid power level signal of either the first power line VGH or the second power line VGL to the second output terminal OUT2 under the control of the first output terminal OUT1. The output circuit is connected to the first power line VGH, the second power line VGL, the control signal line CSL, the second output terminal OUT2, and the third output terminal OUT3. It is configured to output a valid power level signal of either the first power line VGH or the second power line VGL to the third output terminal OUT3 under the control of the second output terminal OUT2 and the control signal line CSL. Within one frame, the duration of the valid power level signal provided by the third output terminal OUT3 is greater than the duration of the valid power level signal provided by the second output terminal OUT2.

[0083] In some exemplary embodiments, the first power line VGH can continuously provide a high-level signal, and the second power line VGL can continuously provide a low-level signal. In some examples, the effective level signal provided by the third output terminal OUT3 is the low-level signal provided by the second power line VGL, and the effective level signal provided by the second output terminal OUT2 can be the high-level signal provided by the first power line VGH. However, this embodiment is not limited in this respect.

[0084] In some exemplary embodiments, the input signals of the first input terminal INPUT1, the first clock signal line CK1, the second clock signal line CB1, and the control signal line CSL can be pulse signals.

[0085] In some exemplary embodiments, the output signals of the first output terminal OUT1 and the second output terminal OUT2 are out of phase. For example, the first input terminal of the first-stage shift register unit can be connected to the first initial signal line; the first output terminal of the nth-stage shift register unit can be connected to the first input terminal of the (n+1)th-stage shift register unit to provide an input signal to the (n+1)th-stage shift register unit, where n is an integer greater than 0. The output signal provided by the second output terminal can be configured to control the turning on of the N-type transistor (e.g., oxide thin-film transistor) in the pixel circuit. However, this embodiment is not limited in this respect.

[0086] In some exemplary embodiments, the second output terminal OUT2 and the third output terminal OUT3 provide valid level signals of opposite polarities, and within one frame, the third output terminal OUT3 intermittently outputs a valid level signal of either the first power line VGH or the second power line VGL. In some examples, the output signal of the third output terminal can be the result of a NAND of the output signal of the second output terminal and a signal provided by a control signal line. For example, the output signal of the third output terminal can be configured to control the activation of a P-type transistor (e.g., a low-temperature polycrystalline silicon thin-film transistor) in a pixel circuit. However, this embodiment is not limited to this.

[0087] In some exemplary embodiments, the valid level signal provided to the third output terminal OUT3 within one frame time includes: a first time period and a second time period. The first time period is configured to output a valid level signal of the second power line VGL to the third output terminal OUT3 under the control of the control signal line CSL. The second time period is configured to output a valid level signal of the second power line VGL to the third output terminal OUT3 under the control of the second output terminal OUT2. In some examples, the duration of the second time period is longer than the duration of the first time period. In some examples, the duration of the second time period is approximately equal to the duration for which the second output terminal OUT2 provides a valid level signal.

[0088] In this exemplary embodiment, a variety of different output signals can be obtained through the first output terminal, the second output terminal, and the third output terminal of the shift register unit. These output signals can be provided to the pixel circuit as gate drive signals to improve the performance of the pixel circuit.

[0089] Figure 2 This is a schematic diagram of the output circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 2As shown in this exemplary embodiment, the output circuit of the shift register unit includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is connected to a control signal line CSL, a first power supply line VGH, a second output terminal OUT2, and a third output terminal OUT3, and is configured to provide a valid level signal of the first power supply line VGH to the third output terminal OUT3 under the control of the control signal line CSL and the second output terminal OUT2. The second output sub-circuit is connected to a control signal line CSL, a second power supply line VGL, a second output terminal OUT2, and the third output terminal OUT3, and is configured to provide a valid level signal of the second power supply line VGL to the third output terminal OUT3 under the control of the control signal line CSL and the second output terminal OUT2.

[0090] This exemplary embodiment allows the output signal of the third output terminal to be different from the output signals of the first and second output terminals through the first and second output sub-circuits, thereby enabling the provision of various gate drive signals to the pixel circuit.

[0091] Figure 3 This is an equivalent circuit diagram of the output circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 3 As shown, the output circuit of the shift register unit provided in this exemplary embodiment includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit includes a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is connected to the control signal line CSL, the first electrode of the first transistor T1 is connected to the first power supply line VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is connected to the second output terminal OUT2, and the second electrode of the second transistor T2 is connected to the third output terminal OUT3. The second output sub-circuit includes a third transistor T3 and a fourth transistor T4. The control electrode of the third transistor T3 is connected to the second output terminal OUT2, the first electrode of the third transistor T3 is connected to the second power supply line VGL, and the second electrode of the third transistor T3 is connected to the third output terminal OUT3. The control electrode of the fourth transistor T4 is connected to the control signal line CSL, the first electrode of the fourth transistor T4 is connected to the second power supply line VGL, and the second electrode of the fourth transistor T4 is connected to the third output terminal OUT3.

[0092] In this exemplary embodiment, Figure 3 An exemplary structure of the output circuit is shown. It will be readily understood by those skilled in the art that the implementation of the output circuit is not limited to this, as long as it can achieve its function.

[0093] Figure 4 This is an equivalent circuit diagram of the second control circuit of the shift register unit according to at least one embodiment of the present disclosure. Figure 4As shown, the second control circuit in the shift register unit provided in this exemplary embodiment includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is connected to the first output terminal OUT1, the first electrode of the fifth transistor T5 is connected to the first power supply line VGH, and the second electrode of the fifth transistor T5 is connected to the second output terminal OUT2. The control electrode of the sixth transistor T6 is connected to the first output terminal OUT1, the first electrode of the sixth transistor T6 is connected to the second power supply line VGL, and the second electrode of the sixth transistor T6 is connected to the second output terminal OUT2.

[0094] In this exemplary embodiment, Figure 4 An exemplary structure of the second control circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second control circuit is not limited to this, as long as it can achieve its function.

[0095] Figure 5 This is an equivalent circuit diagram of the input circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 5 As shown, the input circuit of the shift register unit provided in this exemplary embodiment includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a first capacitor C1. The control electrode of the seventh transistor T7 is connected to the second electrodes of the eighth transistor T8 and the ninth transistor T9. The first electrode of the seventh transistor T7 is connected to the first clock signal line CK1, and the second electrode of the seventh transistor T7 is connected to the first control node P1. The control electrode of the eighth transistor T8 is connected to the first input terminal INPUT1, and the first electrode of the eighth transistor T8 is connected to the first power supply line VGH. The control electrode of the ninth transistor T9 is connected to the second clock signal line CB1, and the first electrode of the ninth transistor T9 is connected to the first power supply line VGH. The control electrode of the tenth transistor T10 is connected to the first clock signal line CK1, the first electrode of the tenth transistor T10 is connected to the first input terminal INPUT1, and the second electrode of the tenth transistor T10 is connected to the second control node P2. The control electrode of the eleventh transistor T11 is connected to the second control node P2, the first electrode of the eleventh transistor T11 is connected to the first power line VGH, and the second electrode of the eleventh transistor T11 is connected to the first control node P1. The first electrode of the first capacitor C1 is connected to the control electrode of the seventh transistor T7, and the second electrode of the first capacitor C1 is connected to the first electrode of the seventh transistor T7.

[0096] In this exemplary embodiment, Figure 5 An exemplary structure of the input circuit is shown. It will be readily understood by those skilled in the art that the implementation of the input circuit is not limited to this, as long as it can achieve its function.

[0097] Figure 6This is an equivalent circuit diagram of the first control circuit of the shift register unit according to at least one embodiment of the present disclosure. Figure 6 As shown, the first control circuit in the shift register unit provided in this embodiment includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second capacitor C2, and a third capacitor C3. The control electrode of the twelfth transistor T12 is connected to the second power supply line VGL, the first electrode of the twelfth transistor T12 is connected to the second control node P2, and the second electrode of the twelfth transistor T12 is connected to the control electrode of the thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is connected to the second power supply line VGL, and the second electrode of the thirteenth transistor T13 is connected to the first output terminal OUT1. The control electrode of the fourteenth transistor T14 is connected to the first control node P1, the first electrode of the fourteenth transistor T14 is connected to the first power supply line VGH, and the second electrode of the fourteenth transistor T14 is connected to the first output terminal OUT1. The first electrode of the second capacitor C2 is connected to the control electrode of the thirteenth transistor T13, and the second electrode of the second capacitor C2 is connected to the first output terminal OUT1. The first electrode of the third capacitor C3 is connected to the control electrode of the fourteenth transistor T14, and the second electrode of the third capacitor C3 is connected to the first power supply line VGH.

[0098] In this exemplary embodiment, Figure 6 An exemplary structure of the first control circuit is shown. It will be readily understood by those skilled in the art that the first control circuit can be implemented in any way that achieves its function.

[0099] Figure 7 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure. Figure 7 As shown, the shift register unit provided in this exemplary embodiment includes: an input circuit, a first control circuit, a second control circuit, and an output circuit. The output circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The second control circuit includes: a fifth transistor T5 and a sixth transistor T6. The input circuit includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a first capacitor C1. The first control circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second capacitor C2, and a third capacitor C3.

[0100] In this exemplary embodiment, the control electrode of the first transistor T1 is connected to the control signal line CSL, the first electrode of the first transistor T1 is connected to the first power supply line VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is connected to the second output terminal OUT2, and the second electrode of the second transistor T2 is connected to the third output terminal OUT3. The control electrode of the third transistor T3 is connected to the second output terminal OUT2, the first electrode of the third transistor T3 is connected to the second power supply line VGL, and the second electrode of the third transistor T3 is connected to the third output terminal OUT3. The control electrode of the fourth transistor T4 is connected to the control signal line CSL, the first electrode of the fourth transistor T4 is connected to the second power supply line VGL, and the second electrode of the fourth transistor T4 is connected to the third output terminal OUT3. The control electrode of the fifth transistor T5 is connected to the first output terminal OUT1, the first electrode of the fifth transistor T5 is connected to the first power supply line VGH, and the second electrode of the fifth transistor T5 is connected to the second output terminal OUT2. The control electrode of the sixth transistor T6 is connected to the first output terminal OUT1, the first electrode of the sixth transistor T6 is connected to the second power supply line VGL, and the second electrode of the sixth transistor T6 is connected to the second output terminal OUT2. The control electrode of the seventh transistor T7 is connected to the second electrodes of the eighth transistor T8 and the ninth transistor T9. The first electrode of the seventh transistor T7 is connected to the first clock signal line CK1 and the second electrode of the seventh transistor T7 is connected to the first control node P1. The control electrode of the eighth transistor T8 is connected to the first input terminal INPUT1 and the first power supply line VGH. The control electrode of the ninth transistor T9 is connected to the second clock signal line CB1 and the first electrode of the ninth transistor T9 is connected to the first power supply line VGH. The control electrode of the tenth transistor T10 is connected to the first clock signal line CK1, the first electrode of the tenth transistor T10 is connected to the first input terminal INPUT1, and the second electrode of the tenth transistor T10 is connected to the second control node P2. The control electrode of the eleventh transistor T11 is connected to the second control node P2, the first electrode of the eleventh transistor T11 is connected to the first power supply line VGH, and the second electrode of the eleventh transistor T11 is connected to the first control node P1. The control electrode of the twelfth transistor T12 is connected to the second power supply line VGL, the first electrode of the twelfth transistor T12 is connected to the second control node P2, and the second electrode of the twelfth transistor T12 is connected to the control electrode of the thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is connected to the second power supply line VGL, and the second electrode of the thirteenth transistor T13 is connected to the first output terminal OUT1. The control electrode of the fourteenth transistor T14 is connected to the first control node P1, the first electrode of the fourteenth transistor T14 is connected to the first power supply line VGH, and the second electrode of the fourteenth transistor T14 is connected to the first output terminal OUT1.The first electrode of the first capacitor C1 is connected to the control electrode of the seventh transistor T7, and the second electrode of the first capacitor C1 is connected to the first electrode of the seventh transistor T7. The first electrode of the second capacitor C2 is connected to the control electrode of the thirteenth transistor T13, and the second electrode of the second capacitor C2 is connected to the first output terminal OUT1. The first electrode of the third capacitor C3 is connected to the control electrode of the fourteenth transistor T14, and the second electrode of the third capacitor C3 is connected to the first power supply line VGH.

[0101] In some exemplary embodiments, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are first semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 to the fourteenth transistor T14 are second semiconductor transistors, with opposite doping types for the first and second semiconductor types. In some examples, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are N-type thin-film transistors, such as oxide thin-film transistors, for example, indium gallium zinc oxide (IGZO) thin-film transistors. The first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 to the fourteenth transistor T14 are P-type thin-film transistors, such as low-temperature polysilicon (LTPS) thin-film transistors. Furthermore, embodiments of this disclosure may select either bottom-gate or top-gate thin-film transistors, as long as the switching function can be achieved. This embodiment is not limited in this respect.

[0102] The technical solution of this disclosure embodiment is further illustrated below through the working process of the shift register unit. The following description takes the working process of the first-stage shift register unit as an example. The first input terminal INPUT1 of the first-stage shift register unit is connected to the first initial signal line STV1. Figure 8 for Figure 7 The timing diagram of the shift register unit is shown. Figure 7 and Figure 8 As shown, the shift register unit of this exemplary embodiment includes 14 transistor units (i.e., first transistor T1 to fourteenth transistor T14), 3 capacitor units (i.e., first capacitor C1 to third capacitor C3), 4 input terminals (i.e., first clock signal line CK1, second clock signal line CB2, first input terminal INPUT1, and control signal line CSL), 3 output terminals (i.e., first output terminal OUT1, second output terminal OUT2, and third output terminal OUT3), and 2 power supply terminals (i.e., first power supply line VGH and second power supply line VGL). The first power supply line VGH continuously provides a high-level signal, and the second power supply line VGL continuously provides a low-level signal.

[0103] In some examples, the output signal of the second output terminal OUT2 can be configured to enable the N-type thin-film transistor in the pixel circuit, and the output signal of the third output terminal OUT3 can be configured to enable the P-type thin-film transistor in the pixel circuit. However, this disclosure is not limited thereto.

[0104] The operation of the shift register unit provided in this exemplary embodiment includes the following eight stages.

[0105] In the first stage t11, the first clock signal line CK1 receives a low-level signal, the second clock signal line CB1 receives a high-level signal, the first initial signal line STV1 receives a high-level signal, and the control signal line CSL receives a high-level signal. The tenth transistor T10 is turned on, pulling the potential of the second control node P2 high. The eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are turned off, the seventh transistor T7 is turned on, and the potential of the first control node P1 is pulled low. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high-level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low-level signal. The second transistor T2 and the fourth transistor T4 are turned on, the first transistor T1 and the third transistor T3 are turned off, and the third output terminal OUT3 outputs a low-level signal.

[0106] In the second stage t12, the first clock signal line CK1 receives a high-level signal, the second clock signal line CB1 receives a low-level signal, the first initial signal line STV1 receives a low-level signal, and the control signal line CSL receives a low-level signal. The eighth transistor T8 and the ninth transistor T9 are turned on, while the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 are turned off. The first control node P1 remains at a low potential, and the second control node P2 remains at a high potential. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, while the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high-level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low-level signal. The third transistor T3 and the fourth transistor T4 are turned off, while the first transistor T1 and the second transistor T2 are turned on, and the third output terminal OUT3 outputs a high-level signal.

[0107] In the third stage t13, the first clock signal line CK1 receives a low-level signal, the second clock signal line CB1 receives a high-level signal, the first initial signal line STV1 receives a low-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is turned on, pulling the potential of the second control node P2 low. The eighth transistor T8 and the eleventh transistor T11 are turned on, the seventh transistor T7 and the ninth transistor T9 are turned off, and the potential of the first control node P1 is pulled high. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low-level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high-level signal. The first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a low-level signal.

[0108] In stage t14, the first clock signal line CK1 receives a high-level signal, the second clock signal line CB1 receives a low-level signal, the first initial signal line STV1 receives a low-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is off, and the second control node P2 remains at a low potential. The eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are on, the seventh transistor T7 is off, and the first control node P1 remains at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are on, the fourteenth transistor T14 is off, and the first output terminal OUT1 outputs a low-level signal. The fifth transistor T5 is on, the sixth transistor T6 is off, and the second output terminal OUT2 outputs a high-level signal. The first transistor T1 and the third transistor T3 are on, the second transistor T2 and the fourth transistor T4 are off, and the third output terminal OUT3 outputs a low-level signal.

[0109] In stage t15, the first clock signal line CK1 receives a low-level signal, the second clock signal line CB1 receives a high-level signal, the first initial signal line STV1 receives a low-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is turned on, and the second control node P2 remains at a low potential. The eighth transistor T8 and the eleventh transistor T11 are turned on, the ninth transistor T9 and the seventh transistor T7 are turned off, and the first control node P1 remains at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low-level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high-level signal. The second transistor T2 and the fourth transistor T4 are turned off, the first transistor T1 and the third transistor T3 are turned on, and the third output terminal OUT3 outputs a low-level signal.

[0110] In stage t16, the first clock signal line CK1 receives a high-level signal, the second clock signal line CB1 receives a low-level signal, the first initial signal line STV1 receives a high-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is off, and the second control node P2 remains at a low potential. The eighth transistor T8 and the seventh transistor T7 are off, the ninth transistor T9 and the eleventh transistor T11 are on, and the first control node P1 remains at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are on, the fourteenth transistor T14 is off, and the first output terminal OUT1 outputs a low-level signal. The fifth transistor T5 is on, the sixth transistor T6 is off, and the second output terminal OUT2 outputs a high-level signal. The second transistor T2 and the fourth transistor T4 are off, the first transistor T1 and the third transistor T3 are on, and the third output terminal OUT3 outputs a low-level signal.

[0111] In stage 7 (t17), the first clock signal line CK1 receives a low-level signal, the second clock signal line CB1 receives a high-level signal, the first initial signal line STV1 receives a high-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is turned on, pulling the potential of the second control node P2 high. The eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are turned off, the seventh transistor T7 is turned on, and the potential of the first control node P1 is pulled low. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high-level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low-level signal. The first transistor T1 and the second transistor T2 are turned on, the third transistor T3 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a high-level signal.

[0112] In stage 8 (t18), the first clock signal line CK1 receives a high-level signal, the second clock signal line CB1 receives a low-level signal, the first initial signal line STV1 receives a high-level signal, and the control signal line CSL receives a low-level signal. The tenth transistor T10 is off, and the second control node P2 remains at a high potential. The eighth transistor T8, the seventh transistor T7, and the eleventh transistor T11 are off, the ninth transistor T9 is on, and the first control node P1 remains at a low potential. The twelfth transistor T12 and the fourteenth transistor T14 are on, the thirteenth transistor T13 is off, and the first output terminal OUT1 outputs a high-level signal. The fifth transistor T5 is off, the sixth transistor T6 is on, and the second output terminal OUT2 outputs a low-level signal. The first transistor T1 and the second transistor T2 are on, the third transistor T3 and the fourth transistor T4 are off, and the third output terminal OUT3 outputs a high-level signal.

[0113] After stage t18, stages t17 and t18 can be repeated until the first input terminal INPUT1 receives a low-level signal and the control signal line CSL receives a high-level signal, then the process restarts from stage 1.

[0114] Based on the above-described shift register unit's operation, from the third stage t13 to the sixth stage t16, the first output terminal OUT1 outputs a low-level signal, the second output terminal OUT2 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal. Furthermore, in the first stage t11, the third output terminal OUT3 also outputs a low-level signal. Within one frame, the third output terminal OUT3 intermittently outputs low-level signals. The output signals provided by the first output terminal OUT1 and the second output terminal OUT2 are out of phase. The effective level signal provided by the second output terminal OUT2 is a high-level signal, and the effective level signal provided by the third output terminal OUT3 is a low-level signal. Moreover, within one frame, the duration of the low-level signal output by the third output terminal OUT3 is greater than the duration of the high-level signal output by the second output terminal OUT2.

[0115] This disclosure also provides a method for driving a shift register unit. Figure 9 This is a flowchart illustrating a driving method for a shift register unit according to an embodiment of this disclosure. Figure 9 As shown, the driving method for the shift register unit provided in this embodiment is applied to the shift register unit provided in the above embodiment. The driving method provided in this embodiment may include the following multiple steps.

[0116] Step S101: Under the control of the first clock signal line, the input circuit provides the signal of the first input terminal to the second control node, and under the control of the second clock signal line, the first input terminal and the second control node, provides the signal of the first clock signal line or the first power line to the first control node.

[0117] Step S102: Under the control of the first control node and the second control node, the first control circuit provides a signal of the first power line or the second power line to the first output terminal.

[0118] Step S103: Under the control of the first output node, the second control circuit provides an effective level signal of the first power supply terminal or the second power supply line to the second output node;

[0119] Step S104: Under the control of the control signal line and the second output terminal, the output circuit outputs an effective level signal of the first power line or the second power line to the third output terminal; within one frame, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

[0120] In some exemplary embodiments, step S104 may include: under the control of the control signal line, the output circuit outputs a valid level signal of the second power line to the third output terminal during a first time period within a frame; under the control of the second output terminal, the output circuit outputs a valid level signal of the second power line to the third output terminal during a second time period within a frame, which is separated from the first time period. In this exemplary embodiment, the first time period and the second time period within a frame are not continuous, and a valid level signal of the first power line can be output to the third output terminal between the first time period and the second time period. In some examples, the duration of the first time period is shorter than the duration of the second time period.

[0121] The driving method, structure, and operation of the shift register unit provided in this exemplary embodiment have been described in the above embodiments and will not be repeated here.

[0122] This disclosure also provides a gate driving circuit. Figure 10 This is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Figure 10 As shown, the gate drive circuit provided in this exemplary embodiment includes multiple cascaded first shift register units GOA1. The first shift register unit GOA1 is the shift register unit provided in the above embodiment, and its implementation principle and effect are similar, so it will not be described again here.

[0123] In this exemplary embodiment, as Figure 10 As shown, the first input terminal INPUT1 of the first stage first shift register unit is connected to the first initial signal line STV1. The first input terminal of the (n+1)th stage first shift register unit is connected to the first output terminal of the nth stage first shift register unit, where n is an integer greater than 0.

[0124] Figure 11 This is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Figure 11As shown, the gate drive circuit provided in this exemplary embodiment includes: multiple cascaded first shift register units GOA1 and multiple cascaded second shift register units GOA2. The first shift register unit GOA1 is the shift register unit provided in the above embodiment, and its implementation principle and effect are similar, so it will not be described again here. The second shift register unit GOA2 includes: a second input terminal INPUT2, a fourth output terminal OUT4, and a fifth output terminal OUT5. The second input terminal of the first-stage second shift register unit is connected to the second initial signal line STV2; the second input terminal of the (n+1)th-stage second shift register unit is connected to the fourth output terminal of the nth-stage second shift register unit. The fifth output terminal of the nth-stage second shift register unit is connected to the control signal line CSL of the nth-stage first shift register unit. Here, n is an integer greater than 0. In this exemplary embodiment, the second shift register unit provides control signals to the first shift register unit through the control signal line. However, this embodiment is not limited in this respect.

[0125] Figure 12 This is an equivalent circuit diagram of the second shift register unit according to at least one embodiment of the present disclosure. Figure 12As shown, the second shift register unit provided in this exemplary embodiment includes: fifteenth transistor T15 to twenty-fourth transistor T24, a fourth capacitor C4, and a fifth capacitor C5. The control electrode of the fifteenth transistor T15 is connected to the third clock signal line CK2, the first electrode of the fifteenth transistor T15 is connected to the second input terminal INPUT2, and the second electrode of the fifteenth transistor T15 is connected to the fourth control node P4. The control electrode of the sixteenth transistor T16 is connected to the fourth control node P4, the first electrode of the sixteenth transistor T16 is connected to the third clock signal line CK2, and the second electrode of the sixteenth transistor T16 is connected to the third control node P3. The control electrode of the seventeenth transistor T17 is connected to the third clock signal line CK2, the first electrode of the seventeenth transistor T17 is connected to the second power supply line VGL, and the second electrode of the seventeenth transistor T17 is connected to the third control node P3. The control electrode of the eighteenth transistor T18 is connected to the third control node P3, the first electrode of the eighteenth transistor T18 is connected to the first power supply line VGH, and the second electrode of the eighteenth transistor T18 is connected to the fourth output terminal OUT4. The control electrode of the nineteenth transistor T19 is connected to the second electrode of the twenty-second transistor T22. The first electrode of the nineteenth transistor T19 is connected to the fourth clock signal line CB2. The second electrode of the nineteenth transistor T19 is connected to the fourth output terminal OUT4. The control electrode of the twentieth transistor T20 is connected to the third control node P3. The first electrode of the twentieth transistor T20 is connected to the first power supply line VGH. The second electrode of the twentieth transistor T20 is connected to the first electrode of the twenty-first transistor T21. The control electrode of the twenty-first transistor T21 is connected to the fourth clock signal line CB2. The second electrode of the twentieth transistor T21 is connected to the fourth control node P4. The control electrode of the twenty-second transistor T22 is connected to the second power supply line VGL. The first electrode of the twenty-second transistor T22 is connected to the fourth control node P4. The second electrode of the twenty-second transistor T22 is connected to the control electrode of the nineteenth transistor T19. The control electrode of the twenty-third transistor T23 is connected to the fourth output terminal OUT4. The first electrode of the twenty-third transistor T23 is connected to the second power supply line VGL. The second electrode of the twenty-third transistor T23 is connected to the fifth output terminal OUT5. The control electrode of the 24th transistor T24 is connected to the fourth output terminal OUT4. The first electrode of the 24th transistor T24 is connected to the first power supply line VGH. The second electrode of the 24th transistor T24 is connected to the fifth output terminal OUT5. The first electrode of the fourth capacitor C4 is connected to the control electrode of the 18th transistor T18. The second electrode of the fourth capacitor C4 is connected to the first power supply line VGH. The first electrode of the fifth capacitor C5 is connected to the control electrode of the 19th transistor T19. The second electrode of the fifth capacitor C5 is connected to the fourth output terminal OUT4.

[0126] In some examples, the twenty-third transistor T23 in the second shift register unit is an N-type transistor, such as an oxide thin-film transistor; the remaining transistors in the second shift register unit are P-type transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, this embodiment is not limited to this.

[0127] The following explanation uses the operation of the first-stage second shift register unit as an example. The second input terminal INPUT2 of the first-stage second shift register unit is connected to the second initial signal line STV2. Figure 13 for Figure 12 The timing diagram of the second shift register unit is shown. Figure 12 and Figure 13 As shown, the second shift register unit in this exemplary embodiment includes 10 transistor units (i.e., the fifteenth transistor T15 to the twenty-fourth transistor T24), 2 capacitor units (i.e., the fourth capacitor C4 and the fifth capacitor C5), 3 input terminals (i.e., the third clock signal line CK2, the fourth clock signal line CB2, and the second input terminal INPUT2), 2 output terminals (i.e., the fourth output terminal OUT4 and the fifth output terminal OUT5), and 2 power supply terminals (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH continuously provides a high-level signal, and the second power supply line VGL continuously provides a low-level signal.

[0128] In some examples, the output signal of the fourth output terminal OUT4 and the output signal of the fifth output terminal OUT5 are out of phase. The output signal of the fourth output terminal OUT4 can be configured to turn on the P-type transistor in the pixel circuit, and the output signal of the fifth output terminal OUT5 can be configured to turn on the N-type transistor in the pixel circuit. However, this disclosure is not limited thereto.

[0129] The operation of the second shift register unit provided in this exemplary embodiment includes the following five stages.

[0130] In the first stage t21, the third clock signal line CK2 receives a high-level signal, the fourth clock signal line CB2 receives a low-level signal, and the second initial signal line STV2 receives a high-level signal. Transistors T17 (17th), T15 (15th), T16 (16th), and T19 (19th) are off, while transistors T20 (20th), T21 (21st), T22 (22nd), and T18 (18th) are on. The fourth output terminal OUT4 outputs a high-level signal. Transistor T23 (23rd) is on, transistor T24 (24th) is off, and the fifth output terminal OUT5 outputs a low-level signal.

[0131] In the second stage t22, the third clock signal line CK2 receives a low-level signal, the fourth clock signal line CB2 receives a high-level signal, and the second initial signal line STV2 receives a low-level signal. Transistors T15, T17, T16, T22, T20, T18, and T19 are turned on, while transistor T21 is turned off, and the fourth output terminal OUT4 outputs a high-level signal. Transistor T23 is turned on, while transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low-level signal.

[0132] In the third stage t23, the third clock signal line CK2 receives a high-level signal, the fourth clock signal line CB2 receives a low-level signal, and the second initial signal line STV2 receives a high-level signal. The fifteenth transistor T15, the seventeenth transistor T17, the twentieth transistor T20, and the eighteenth transistor T18 are cut off; the sixteenth transistor T16, the twenty-first transistor T21, the twenty-second transistor T22, and the nineteenth transistor T19 are turned on; and the fourth output terminal OUT4 outputs a low-level signal. The twenty-third transistor T23 is cut off, the twenty-fourth transistor T24 is turned on, and the fifth output terminal OUT5 outputs a high-level signal.

[0133] In the fourth stage t24, the third clock signal line CK2 receives a low-level signal, the fourth clock signal line CB2 receives a high-level signal, and the second initial signal line STV2 receives a high-level signal. Transistors T15, T17, T16, T20, T18, T22, and T19 are turned on, while transistor T21 is turned off, and the fourth output terminal OUT4 outputs a high-level signal. Transistor T23 is turned on, while transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low-level signal.

[0134] In the fifth stage t25, the third clock signal line CK2 receives a high-level signal, the fourth clock signal line CB2 receives a low-level signal, and the second initial signal line STV2 receives a high-level signal. The fifteenth transistor T15, the seventeenth transistor T17, the sixteenth transistor T16, and the nineteenth transistor T19 are cut off; the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the eighteenth transistor T18 are turned on, and the fourth output terminal OUT4 outputs a high-level signal. The twenty-third transistor T23 is turned on, the twenty-fourth transistor T24 is cut off, and the fifth output terminal OUT5 outputs a low-level signal.

[0135] After the fifth stage t25, the fourth stage t24 and the fifth stage t25 can be repeated until the second input terminal INPUT2 inputs a low-level signal, and then start again.

[0136] According to the working process of the second shift register unit described above, in the third stage, the fourth output terminal OUT4 outputs a low-level signal, and the fifth output terminal OUT5 outputs a high-level signal. In the remaining stages, the fourth output terminal OUT4 outputs a high-level signal, and the fifth output terminal OUT5 outputs a low-level signal. In this exemplary embodiment, the output signals provided by the fourth output terminal OUT4 and the fifth output terminal OUT5 of the second shift register unit are out of phase. The output signal of the fifth output terminal of the nth stage second shift register unit can be provided to the nth stage first shift register unit via the control signal line CSL.

[0137] In some examples, the clock signal periods provided by the third and fourth clock signal lines can be the same, and can also be the same as the clock signal periods provided by the first and second clock signal lines. Based on the above-described operation of the second and first shift register units, it is known that the duration of the effective level signal provided by the fifth output terminal of the second shift register unit is less than the duration of the effective level signal provided by the third output terminal of the first shift register unit. The effective level signal provided by the third output terminal of the first shift register unit can be configured to control the threshold voltage compensation duration of the pixel circuit, and the effective level signal provided by the fifth output terminal of the second shift register unit can be configured to control the data signal writing duration of the pixel circuit. By separately controlling the threshold voltage compensation and data signal writing of the pixel circuit, fast data writing and sufficient threshold voltage compensation can be achieved, thereby reducing display defects and improving display quality.

[0138] Figure 14 This is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Figure 14As shown, the gate drive circuit provided in this exemplary embodiment includes: multiple cascaded first shift register units GOA1 and multiple cascaded second shift register units GOA2. The first shift register unit GOA1 is the shift register unit provided in the above embodiment, and its implementation principle and effect are similar, so it will not be described again here. The second shift register unit GOA2 includes: a second input terminal INPUT2, a fourth output terminal OUT4, and a fifth output terminal OUT5. The second input terminal of the first-stage second shift register unit is connected to the second initial signal line STV2; the second input terminal of the (n+1)th-stage second shift register unit is connected to the fourth output terminal of the nth-stage second shift register unit. The fourth output terminal of the nth-stage second shift register unit is connected to the control signal line CSL of the nth-stage first shift register unit. Here, n is an integer greater than 0. In some examples, the first transistor in the first shift register unit can be an N-type transistor, and the fourth transistor can be a P-type transistor. In this exemplary embodiment, the second shift register unit provides control signals to the first shift register unit through the control signal line. However, this embodiment is not limited to this. The remaining structure of the second shift register unit and the first shift register unit in this exemplary embodiment can be found in the description of the foregoing embodiments, and will not be repeated here.

[0139] Figure 15 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 15 As shown, the display substrate of this exemplary embodiment includes a display area AA and a peripheral area BB located around the display area AA. The display area AA includes at least a plurality of regularly arranged pixel units, a plurality of gate lines extending along a first direction X (e.g., including scan lines, reset signal lines, and light emission control lines), a plurality of data lines and power lines extending along a second direction Y. The first direction X and the second direction Y are located in the same plane, and the first direction X is perpendicular to the second direction Y.

[0140] In some examples, a pixel unit within the display area AA may include three sub-pixels: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels: a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0141] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0142] In some examples, the peripheral area BB may be equipped with a timing controller, a data driving circuit, and a gate driving circuit. The gate driving circuit may be located on opposite sides of the display area AA, while the timing controller and data driving circuit may be located on one side of the display area AA. However, this embodiment is not limited to this.

[0143] In some examples, the data driving circuit can provide data signals to the sub-pixels via data lines. The gate driving circuit can provide scan signals to the sub-pixels via scan lines, reset signals via reset signal lines, and light emission control signals via light emission control lines. The timing controller can provide drive signals to the data driving circuit and the gate driving circuit. The operation of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide the data driving circuit with grayscale data specifying the grayscale level to be displayed in the sub-pixels. The data driving circuit can provide the data signal corresponding to the potential of the grayscale data of the sub-pixels to the sub-pixels of the row selected by the gate driving circuit via data lines.

[0144] Figure 16 This is a schematic diagram of the pixel circuit structure according to at least one embodiment of the present disclosure. Figure 16As shown, the pixel circuit of this exemplary embodiment includes: a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a level holding sub-circuit, a light emission control sub-circuit, a first initialization sub-circuit, and a second initialization sub-circuit. The data writing sub-circuit is connected to the data line DATA, the first scan line GT1, and the second node N2, and is configured to write the signal of the data line DATA to the storage sub-circuit under the control of the first scan line GT1. The driving sub-circuit is connected to the third power line VDD, the first node N1, and the third node N3, and is configured to output a driving current to the light emission control sub-circuit through the third node N3 under the control of the first node N1. The storage sub-circuit is connected to the first node N1 and the second node N2. The level holding sub-circuit is connected to the third power line VDD and the second node N2, and is configured to maintain the potential of the second node N2. The compensation sub-circuit is connected to the second scan line GT2, the first node N1, and the third node N3, and is configured to compensate the threshold voltage of the driving sub-circuit under the control of the second scan line GT2. The first initialization subcircuit is connected to the first reset signal line RST1, the initial voltage line INT, and the first node N1, and is configured to initialize the first node N1 under the control of the first reset signal line RST1. The second initialization subcircuit is connected to the second reset signal line RST2, the reference voltage line REF, and the second node N2, and is configured to initialize the second node N2 under the control of the second reset signal line RST2. The light-emitting control subcircuit is connected to the light-emitting control line EM, the third node N3, and the first electrode of the light-emitting element, and is configured to drive the light-emitting element to emit light according to the driving current under the control of the light-emitting control line EM. The second electrode of the light-emitting element is connected to the fourth power supply line VSS.

[0145] In some examples, the light-emitting element can be an organic light-emitting diode (OLED), the first electrode can be the anode, and the second electrode can be the cathode. However, this embodiment is not limited to this.

[0146] In some examples, the write duration of the data writing subcircuit to the storage subcircuit is less than the threshold voltage compensation duration of the compensation subcircuit to the drive subcircuit. This exemplary embodiment controls the data voltage write duration and the threshold voltage compensation duration separately. This allows for reducing the data voltage write duration while ensuring the threshold voltage compensation duration, thereby improving the refresh rate to support applications in high-resolution products. Furthermore, it allows for increasing the threshold voltage compensation duration to ensure sufficient compensation and reduce display defects.

[0147] Figure 17 This is another schematic diagram of the pixel circuit structure according to at least one embodiment of the present disclosure. Figure 17As shown, the pixel circuit of this exemplary embodiment includes: a driving sub-circuit, a light emission control sub-circuit, a data writing sub-circuit, a storage sub-circuit, a level holding sub-circuit, a compensation sub-circuit, a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit. The data writing sub-circuit is connected to the data line DATA, the first scan line GT1, and the second node N2, and is configured to write the signal of the data line DATA to the storage sub-circuit under the control of the first scan line GT1. The driving sub-circuit is connected to the third power line VDD, the first node N1, and the third node N3, and is configured to output a driving current to the light emission control sub-circuit through the third node N3 under the control of the first node N1. The storage sub-circuit is connected to the first node N1 and the second node N2. The level holding sub-circuit is connected to the third power line VDD and the second node N2, and is configured to maintain the potential of the second node N2. The compensation sub-circuit is connected to the second scan line GT2, the first node N1, and the third node N3, and is configured to compensate the threshold voltage of the driving sub-circuit under the control of the second scan line GT2. The first initialization sub-circuit is connected to the first reset signal line RST1, the initial voltage line INT, and the first node N1, and is configured to initialize the first node N1 under the control of the first reset signal line RST1. The second initialization sub-circuit is connected to the second reset signal line RST2, the reference voltage line REF, and the second node N2, and is configured to initialize the second node N2 under the control of the second reset signal line RST2. The light emission control sub-circuit is connected to the light emission control line EM, the third node N3, and the first electrode of the light emission element, and is configured to drive the light emission element to emit light according to the driving current under the control of the light emission control line EM. The second electrode of the light emission element is connected to the fourth power supply line VSS. The third initialization sub-circuit is connected to the first electrode of the light emission element, the initial voltage line INT, and the third reset signal line RST3, and is configured to initialize the light emission element under the control of the third reset signal line RST3. The third reset signal line RST3(n) connected to the pixel circuit of the nth row sub-pixel is configured to be connected to the second reset signal line RST2(n+1) driving the pixel circuit of the (n+1)th row sub-pixel. However, this embodiment is not limited in this respect. In some examples, the third initialization sub-circuit can be connected to the first pole, the initial voltage line, and the second reset signal line of the light-emitting element, and configured to initialize the light-emitting element under the control of the second reset signal line.

[0148] Figure 18 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 18As shown, the pixel circuit of this exemplary embodiment includes: a driving sub-circuit, a light emission control sub-circuit, a data writing sub-circuit, a storage sub-circuit, a level holding sub-circuit, a compensation sub-circuit, a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit. The data writing sub-circuit includes: a data writing transistor M4; the control electrode of the data writing transistor M4 is connected to the first scan line GT1, the first electrode of the data writing transistor M4 is connected to the data line DATA, and the second electrode of the data writing transistor M4 is connected to the second node N2. The driving sub-circuit includes: a driving transistor M3; the control electrode of the driving transistor M3 is connected to the first node N1, the first electrode of the driving transistor M3 is connected to the third power supply terminal VDD, and the second electrode of the driving transistor M3 is connected to the third node N3. The storage sub-circuit includes: a storage capacitor Cst; the first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the second node N2. The level holding sub-circuit includes: a voltage regulator capacitor Crt; the first electrode of the voltage regulator capacitor Crt is connected to the third power supply terminal VDD, and the second electrode of the voltage regulator capacitor Crt is connected to the second node N2. The compensation sub-circuit includes: a compensation transistor M2; the control electrode of the compensation transistor M2 is connected to the second scan line GT2, the first electrode of the compensation transistor M2 is connected to the first node N1, and the second electrode of the compensation transistor M2 is connected to the third node N3. The light-emitting control sub-circuit includes: a light-emitting control transistor M6; the control electrode of the light-emitting control transistor M6 is connected to the light-emitting control line EM, the first electrode of the light-emitting control transistor M6 is connected to the third node N3, and the second electrode of the light-emitting control transistor M6 is connected to the first electrode of the light-emitting element EL. The second electrode of the light-emitting element EL is connected to the fourth power supply line VSS. The first initialization sub-circuit includes: a first initialization transistor M1; the control electrode of the first initialization transistor M1 is connected to the first reset signal line RST1, the first electrode of the first initialization transistor M1 is connected to the initial voltage line INT, and the second electrode of the first initialization transistor M1 is connected to the first node N1. The second initialization sub-circuit includes: a second initialization transistor M5; the control electrode of the second initialization transistor M5 is connected to the second reset signal line RST2, the first electrode of the second initialization transistor M5 is connected to the reference voltage line REF, and the second electrode of the second initialization transistor M5 is connected to the second node N2. The third initialization sub-circuit includes: a third initialization transistor M7; the control electrode of the third initialization transistor M7 is connected to the third reset signal line, the first electrode of the third initialization transistor M7 is connected to the initial voltage line INT, and the second electrode of the third initialization transistor M7 is connected to the first electrode of the light-emitting element EL. The third reset signal line connected to the pixel circuit of the nth row sub-pixel is configured to be connected to the second reset signal line RST2(n+1) of the pixel circuit driving the (n+1)th row sub-pixel.

[0149] In some exemplary embodiments, the compensation transistor M2 and the first initialization transistor M1 of the pixel circuit are first semiconductor transistors, while the driving transistor M3, data writing transistor M4, light-emitting control transistor M6, second initialization transistor M5, and third initialization transistor M7 are second semiconductor transistors; the doping types of the first and second semiconductor transistors are opposite. In some examples, the compensation transistor M2 and the first initialization transistor M1 of the pixel circuit are N-type thin-film transistors, such as oxide thin-film transistors, for example, IGZO thin-film transistors; and the driving transistor M3, data writing transistor M4, light-emitting control transistor M6, second initialization transistor M5, and third initialization transistor M7 of the pixel circuit are P-type thin-film transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, this embodiment is not limited to this.

[0150] The following example uses N-type thin-film transistors (TFTs) for the compensation transistor M2 and the first initialization transistor M1 in the pixel circuit, while the remaining transistors are P-type TFTs. Figure 18 The operation of the pixel circuit shown is illustrated by way of example. Figure 19 for Figure 18 The timing diagram of the pixel circuit shown is as follows. Figure 18 As shown, the pixel circuit of this exemplary embodiment includes 7 transistor units (M1 to M7), 2 capacitor units (i.e., storage capacitor Cst to voltage regulator capacitor Crt), 9 input terminals (i.e., data line DATA, first scan line GT1, second scan line GT2, light emission control line EM, first reset signal line RST1, second reset signal line RST2, second reset signal line RST2(n+1), reference voltage line REF, initial voltage line INT), and 2 power supply terminals (i.e., third power supply line VDD and fourth power supply line VSS). The third power supply line VDD continuously provides a high-level signal, and the fourth power supply line VSS continuously provides a low-level signal.

[0151] In this exemplary embodiment, such as Figure 18 and Figure 19 As shown, the operation of the pixel circuit includes the following stages.

[0152] In the first stage S1, i.e., the reset stage, the first reset signal line RST1 provides a high-level signal, the first initialization transistor M1 is turned on, and the voltage V at the first node N1... N1 The initial voltage Vint is provided for the initial voltage line INT. The second reset signal line RST2 provides a low-level signal, the second initialization transistor M5 is turned on, and the voltage V at the second node N2... N2The reference voltage Vref provided by the reference voltage line REF resets the storage capacitor Cst, clearing the original data voltage in Cst. The first scan line GT1 provides a high-level signal, cutting off the data writing transistor M4; the second scan line GT2 provides a low-level signal, cutting off the compensation transistor M2; the light-emitting control line EM provides a high-level signal, cutting off the light-emitting control transistor M6. The control electrode voltage of the driving transistor M3 (i.e., the voltage V1 at the first node N1)... N1 The initial voltage Vint is provided by the initial voltage line INT, and the voltage V at the second node N2 is... N2 The reference voltage is Vref. The second reset signal line RST2(n+1) provides a high-level signal, and the third initialization transistor M7 is turned off.

[0153] In the second stage S2, the compensation stage, the first reset signal line RST1 provides a low-level signal, and the first initialization transistor M1 is turned off. The second reset signal line RST2 provides a low-level signal, and the second initialization transistor M5 is turned on, increasing the voltage V at the second node N2. N2 The reference voltage Vref remains. The first scan line GT1 provides a high-level signal, turning off the data writing transistor M4. The second scan line GT2 provides a high-level signal, turning on the compensation transistor M2. The light-emitting control line EM provides a high-level signal, turning off the light-emitting control transistor M6. The second reset signal line RST2(n+1) provides intermittent low-level signals, turning on the third initialization transistor M7, providing the initial voltage Vint provided by the initial voltage line INT to the first terminal of the light-emitting element EL, thus initializing the first terminal of the light-emitting element EL.

[0154] At the start of the second stage S2, the voltage V supplied by the third power line VDD is... VDD When the voltage difference between the first node N1 and the threshold voltage Vth of the driving transistor M3 is greater than that of the driving transistor M3, the driving transistor M3 turns on, and the voltage of the third power line VDD flows into the first node N1 through the driving transistor M3 and the compensation transistor M2. Because the compensation transistor M2 has a longer conduction time, the threshold voltage of the driving transistor M3 can be adequately compensated. When the voltage Vth of the first node N1... N1 Increase to V VDD When +Vth, the driving transistor M3 is turned off, and at this time the voltage V at the first node N1 is... N1 For V VDD +Vth, the voltage V at the second node N2 N2 Let Vref be the reference voltage, and the voltage difference between the first node N1 and the second node N2 be V. VDD +Vth-Vref.

[0155] In the third stage, S3, the write stage, the first reset signal line RST1 provides a low-level signal, and the first initialization transistor M1 is turned off; the second reset signal line RST2 provides a high-level signal, and the second initialization transistor M5 is turned off. The second scan line GT2 provides a high-level signal, and the compensation transistor M2 is turned off. The light-emitting control line EM provides a high-level signal, and the light-emitting control transistor M6 is turned off. When the first scan line GT1 provides a low-level signal, the data write transistor M4 is turned on, and the signal provided by the data line DATA is written to the second node N2, i.e., the voltage V of the second node N2. N2 When the voltage is converted to data voltage Vdata, the first capacitor C1 will exhibit a bootstrap effect to maintain a constant voltage difference across its terminals. Therefore, the voltage at the first node N1 will ultimately become V due to the capacitor's bootstrap effect. VDD +Vth+Vdata-Vref, to maintain the voltage difference between the first node N1 and the second node N2 at V. VDD +Vth-Vref.

[0156] In the fourth stage, S4, the light-emitting stage, the first reset signal line RST1 provides a low-level signal, and the first initialization transistor M1 is turned off. The second reset signal line RST2 provides a high-level signal, and the second initialization transistor M5 is turned off. The first scan line GT1 provides a high-level signal, and the data writing transistor M4 is turned off. The second scan line GT2 provides a low-level signal, and the compensation transistor M2 is turned off. The second reset signal line RST2(n+1) provides a high-level signal, and the third initialization transistor M7 is turned off. The light-emitting control line EM provides a low-level signal, and the light-emitting control transistor M6 is turned on. The voltage difference between the third power supply line VDD and the first node N1 is Vth + Vdata - Vref, which is greater than the threshold voltage Vth of the driving transistor M3. At this time, the driving transistor M3 is turned on, and the light-emitting element EL emits light under the drive of the driving transistor M3. The light-emitting current of the light-emitting element EL is:

[0157] I = 1 / 2 uC ox W / L(Vgs-Vth) 2 =1 / 2uC ox W / L(V N1 -V VDD -Vth) 2

[0158] =1 / 2uC ox W / L(V VDD +Vth+Vdata-Vref-V VDD -Vth) 2

[0159] =1 / 2uC ox W / L(Vdata-Vref) 2

[0160] Where u is the channel mobility of the driving transistor, and C ox Vgs is the channel capacitance per unit area of ​​the driving transistor, W and L are the channel width and channel length of the driving transistor, respectively, and Vgs is the gate-source voltage of the driving transistor (i.e., the difference between the gate voltage and the source voltage of the driving transistor).

[0161] Therefore, it can be seen that the luminous current I and the power supply voltage V of the third power line are related. VDD It is independent of the threshold voltage Vth, and depends only on the data voltage Vdata provided by the data line DATA and the reference voltage Vref provided by the reference voltage line REF. This eliminates the influence of the threshold voltage of the driving transistor on the driving current, thereby ensuring uniform display brightness of the display substrate and improving the display effect.

[0162] In this example, the voltage V of the first node N1 in the different stages described above... N1 Voltage V at the second node N2 N2 As shown in Table 1.

[0163] Table 1

[0164] Phase 1 S1 Phase 2 S2 Phase 3 S3 Phase 4 S4 <![CDATA[V N1 ]]> Vint <![CDATA[V VDD +Vth]]> <![CDATA[V VDD +Vth+Vdata-Vref]]> <![CDATA[V VDD +Vth+Vdata-Vref <!-- 18 -->]]> <![CDATA[V N2 ]]> Vref Vref Vdata Vdata

[0165] In this exemplary embodiment, the effective level signal provided by the first scan line controls the writing duration of the data voltage provided by the data line (i.e., the conduction duration of the data writing transistor), with a narrow pulse width; the effective level signal provided by the second scan line controls the compensation duration of the threshold voltage (i.e., the conduction duration of the compensation transistor), with a wide pulse width. That is, the data voltage writing duration is less than the threshold voltage compensation duration, thereby reducing the data voltage writing duration and increasing the refresh rate while satisfying the threshold voltage compensation duration. Moreover, the effective level signal provided by the third reset signal line controls the initialization duration of the light-emitting element, which is greater than the sum of the data voltage writing duration and the threshold voltage compensation duration, increasing the initialization duration and thus improving the lifespan of the light-emitting element, thereby improving the lifespan of the display substrate.

[0166] Figure 20 This is a top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure. Figure 21 for Figure 20 A cross-sectional view along the QQ direction. (See diagram below.) Figure 20 and Figure 21As shown, the display area of ​​the display substrate in this exemplary embodiment includes: a substrate 30, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate 30. A first insulating layer 31 is disposed between the substrate 30 and the first semiconductor layer. A second insulating layer 32 is disposed between the first conductive layer and the first semiconductor layer. A third insulating layer 33 is disposed between the first conductive layer and the second semiconductor layer. A fourth insulating layer 34 is disposed between the second semiconductor layer and the second conductive layer. A fifth insulating layer 35 is disposed between the second conductive layer and the third conductive layer. In some examples, a planarization layer, an anode layer, an organic insulating layer, a cathode layer, and an encapsulation layer are disposed on the side of the fifth insulating layer 35 away from the substrate 30. However, this embodiment is not limited to this.

[0167] In this exemplary embodiment, Figure 20 The third initialization transistor M7, as illustrated, is included in the pixel circuit of the (n-1)th row of sub-pixels, while the remaining transistors (i.e., M1 to M6) are included in the pixel circuit of the nth row of sub-pixels. Figure 20 The third initialization transistor M7 is connected to the first electrode of the light-emitting element of the (n-1)th row sub-pixel, and the light-emitting control transistor M6 is connected to the first electrode of the light-emitting element of the nth row sub-pixel.

[0168] Figure 22 This is a top view of a sub-pixel after the formation of the first semiconductor layer, according to at least one embodiment of this disclosure. Figures 20 to 22 As shown, the first semiconductor layer of the display area in this exemplary embodiment includes at least: an active layer 540 for a data writing transistor M4, an active layer 530 for a driving transistor M3, an active layer 550 for a second initialization transistor M5, an active layer 570 for a third initialization transistor M7, and an active layer 560 for a light-emitting control transistor M6. The active layer 530 of the driving transistor M3 and the active layer 560 of the light-emitting control transistor M6 are integrally formed.

[0169] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polycrystalline silicon. In some examples, the active layer may include a channel region, a first doped region, and a second doped region. The channel region may be undoped and has semiconductor properties. The first and second doped regions may be located on opposite sides of the channel region and are doped with impurities, thus exhibiting conductivity. The impurities may vary depending on the type of transistor.

[0170] In some exemplary implementations, such as Figure 22As shown, the active layer 540 of the data writing transistor M4 includes a channel region 540a and a first doped region 540b and a second doped region 540c located at both ends of the channel region 540a. The active layer 530 of the driving transistor M3 includes a channel region 530a and a first doped region 530b and a second doped region 530c located at both ends of the channel region 530a. The active layer 550 of the second initialization transistor M5 includes a channel region 550a and a first doped region 550b and a second doped region 550c located at both ends of the channel region 550a. The active layer 570 of the third initialization transistor M7 includes a channel region 570a and a first doped region 570b and a second doped region 570c located at both ends of the channel region 570a. The active layer 560 of the light-emitting control transistor M6 includes a channel region 560a and a first doped region 560b and a second doped region 560c located at both ends of the channel region 560a. The second doped region 530c of the active layer 530 of the driving transistor M3 is connected to the second doped region 560b of the active layer 560 of the light-emitting control transistor M6.

[0171] In some exemplary embodiments, the first or second doped region of the active layer can be interpreted as the source or drain electrode of a transistor. For example, the source electrode of driving transistor M3 can correspond to the first doped region 530b, which is doped with impurities, surrounding the channel region 530a of the active layer 530; the drain electrode of driving transistor M3 can correspond to the second doped region 530c, which is doped with impurities, surrounding the channel region 530a of the active layer 530. Additionally, portions of the active layer between transistors can be interpreted as doped wiring, which can be used to electrically connect transistors.

[0172] Figure 23 This is a top view of a sub-pixel after the formation of the first conductive layer, according to at least one embodiment of this disclosure. Figures 20 to 23 As shown, the first conductive layer of the display area in this exemplary embodiment includes at least: a control electrode 541 of a data writing transistor M4, a control electrode 561 of a light-emitting control transistor M6, a control electrode 551 of a second initialization transistor M5, a control electrode 571 of a third initialization transistor M7, a control electrode 531 of a driving transistor M3, a first scan line GT1, a second reset signal line RST2, a light-emitting control line EM, a first electrode 581 of a storage capacitor Cst, and a first electrode 591 of a voltage regulator capacitor Crt. The first scan line GT1 provides a first scan signal, the second reset signal line RST2 provides a second reset signal, and the light-emitting control line EM provides a light-emitting control signal.

[0173] In some exemplary embodiments, the control electrode 531 of the driving transistor M3 and the first electrode 581 of the storage capacitor Cst are integrated into one structure. The light-emitting control line EM and the control electrode 561 of the light-emitting control transistor M6 are integrated into one structure. The control electrode 551 of the second initialization transistor M5 and the second reset signal line RST2 are integrated into one structure, and the control electrode 571 of the third initialization transistor M7 of the pixel circuit of the (n-1)th row sub-pixel is integrated into one structure with the second reset signal line RST2 connected to the pixel circuit of the nth row sub-pixel.

[0174] Figure 24 This is a top view of a sub-pixel forming a second semiconductor layer according to at least one embodiment of this disclosure. Figures 20 to 24 As shown, the second semiconductor layer of the display area in this exemplary embodiment includes at least: an active layer 520 of the compensation transistor M2 and an active layer 510 of the first initialization transistor M1. The active layer 520 of the compensation transistor M2 and the active layer 510 of the first initialization transistor M1 are an integral structure. In this exemplary embodiment, the material of the second semiconductor layer may include a metal oxide, such as IGZO.

[0175] Figure 25 This is a top view of a sub-pixel after the formation of the second conductive layer, according to at least one embodiment of this disclosure. Figures 20 to 25 As shown, the second conductive layer of the display area in this exemplary embodiment includes at least: a control electrode 521 of a compensation transistor M2, a control electrode 511 of a first initialization transistor M1, a first reset signal line RST1, a second scan line GT2, a reference voltage line REF, a second electrode 582 of a storage capacitor Cst, and a second electrode 592 of a voltage regulator capacitor Crt. The first reset signal line RST1 provides a first reset signal, the second scan line GT2 provides a second scan signal, and the reference voltage line REF provides a reference voltage.

[0176] In some exemplary embodiments, the first reset signal line RST1 and the control electrode 511 of the first initialization transistor M1 are integrally formed. The second scan line GT2 and the control electrode 521 of the compensation transistor M2 are integrally formed. The second electrode 582 of the storage capacitor Cst and the second electrode 592 of the voltage regulator capacitor Crt are integrally formed. The second electrode 582 of the storage capacitor Cst has a cutout region H. The orthographic projection of the cutout region H on the substrate lies within the orthographic projection of the first electrode 581 of the storage capacitor Cst on the substrate.

[0177] Figure 26 This is a top view of a sub-pixel after the formation of the fifth insulating layer, according to at least one embodiment of this disclosure. Figures 20 to 26As shown, a plurality of vias are formed on the fifth insulating layer of the display area in this exemplary embodiment. The plurality of vias includes at least: first vias K19 to K26, second vias D19 to D22, third vias V6 to V8, and fourth vias F13 to F15. The fifth insulating layer 35, fourth insulating layer 34, third insulating layer 33, and second insulating layer 32 within the first vias are etched away, exposing the surface of the first semiconductor layer. The fifth insulating layer 35, fourth insulating layer 34, and third insulating layer 33 within the second vias are etched away, exposing the surface of the first conductive layer. The fifth insulating layer 35 and fourth insulating layer 34 within the third vias are etched away, exposing the surface of the second semiconductor layer. The fifth insulating layer 35 within the fourth vias is etched away, exposing the surface of the second conductive layer.

[0178] Figure 27 This is a top view of a sub-pixel after the formation of the third conductive layer, according to at least one embodiment of this disclosure. Figures 20 to 27 As shown, the third conductive layer of the display area in this exemplary embodiment includes at least: a third power line VDD, a data line DATA, an initial voltage line INT, a second electrode 533 of a driving transistor M3, a first electrode 522 and a second electrode 523 of a compensation transistor M2, a first electrode 512 of a first initialization transistor M1, a first electrode 552 and a second electrode 553 of a second initialization transistor M5, a second electrode 543 of a data writing transistor M4, and a scan line connection electrode 600. The data line DATA provides a data signal, and the initial voltage line INT provides an initial voltage. The first electrode 522 of the compensation transistor M2 and the second electrode 533 of the driving transistor M3 are integrally formed.

[0179] In some exemplary embodiments, the third power line VDD, data line DATA, and initial voltage line INT extend along the second direction Y. The first electrode 512 of the first initialization transistor M1 is connected to the first doped region 510b of the active layer 510 of the first initialization transistor M1 via a third via V8, and to the first doped region 570b of the active layer 570 of the third initialization transistor M7 via a first via K26. The initial voltage line INT is connected to the first doped region 570b of the active layer 570 of the third initialization transistor M7 via a first via K25. The first electrode 512 of the first initialization transistor M1 is connected to the initial voltage line INT via the first doped region 570b of the active layer 570 of the third initialization transistor M7. The first electrode 522 of the compensation transistor M2 is connected to the first doped region 520b of the active layer 520 of the compensation transistor M2 via a third via V6. The second electrode 523 of the compensation transistor M2 is connected to the second doped region 520c of the active layer 520 of the compensation transistor M2 through the third via V7, and to the first electrode 581 of the storage capacitor Cst through the second via D19. The second electrode 533 of the driving transistor M3 is connected to the second doped region 530c of the active layer 530 of the driving transistor M3 through the first via K20. The third power line VDD is connected to the first doped region 530b of the active layer 530 of the driving transistor M3 through the first via K19, and is also connected to the first electrode 591 of the voltage regulator capacitor Crt through the second via D20. The first electrode 552 of the second initialization transistor M5 is connected to the first doped region 550b of the active layer 550 of the second initialization transistor M5 through the first via K23, and to the reference voltage line REF through the fourth via F15. The second electrode 553 of the second initialization transistor M5 is connected to the second doped region 550c of the active layer 550 of the second initialization transistor M5 through the first via K24, and to the second electrode 582 of the storage capacitor Cst through the fourth via F14. The second electrode 543 of the data writing transistor M4 is connected to the second doped region 540c of the active layer 540 of the data writing transistor M4 through the first via K21, and to the second electrode 592 of the voltage regulator capacitor Crt through the fourth via F13. The data line DATA is connected to the first doped region 540b of the active layer 540 of the data writing transistor M4 through the first via K22. The scan line connection electrode 600 is connected to the first scan line GT1 through the second via D21, and to the control electrode 541 of the data writing transistor M4 through the second via D22. In some examples, the second doped region 560c of the active layer 560 of the light-emitting control transistor M6 can be connected to the first electrode of the light-emitting element of the sub-pixel in the same row. The second doped region 570c of the active layer 570 of the third initialization transistor M7 can be connected to the first electrode of the light-emitting element of the sub-pixel in the previous row.

[0180] In the pixel circuit provided in this exemplary embodiment, the compensation transistor M2 and the first initialization transistor M1 are IGZO thin-film transistors with extremely low leakage current, which results in a longer voltage holding time for the storage capacitor during low-frequency driving. Data voltage writing and threshold voltage compensation are controlled by the first scan line and the second scan line, respectively. The data voltage writing time is short, and the threshold voltage compensation time is long, which can satisfy fast data writing and sufficient threshold voltage compensation during high-frequency driving.

[0181] Figure 28 This is another top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure. Figure 29 for Figure 28 A schematic cross-sectional view along the HH direction. (See diagram below.) Figure 28 and Figure 29 As shown, the display area of ​​the display substrate in this exemplary embodiment includes: a substrate 30, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate 30. A first insulating layer 31 is disposed between the substrate 30 and the first semiconductor layer. A second insulating layer 32 is disposed between the first semiconductor layer and the first conductive layer. A third insulating layer 33 is disposed between the first conductive layer and the second semiconductor layer. A fourth insulating layer 34 is disposed between the second semiconductor layer and the second conductive layer. A fifth insulating layer 35 is disposed between the second conductive layer and the third conductive layer. A sixth insulating layer 36 and a seventh insulating layer 37 are sequentially disposed between the third conductive layer and the fourth conductive layer.

[0182] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0183] In some exemplary embodiments, the first insulating layer 31 to the sixth insulating layer 36 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first insulating layer 31 and the third insulating layer 33 are referred to as buffer layers, with the first insulating layer 31 configured to improve the substrate's resistance to water and oxygen; the second insulating layer 32 and the fourth insulating layer 34 are referred to as gate insulating (GI) layers, the fifth insulating layer 35 is referred to as interlayer insulating (ILD) layers, and the sixth insulating layer 36 is referred to as a passivation layer. The seventh insulating layer 37 may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The seventh insulating layer 37 is referred to as the first planarization layer. In some examples, the side of the fourth conductive layer away from the substrate 30 is sequentially provided with a second planarization layer, an anode layer, an organic insulating layer, a cathode layer, and an encapsulation layer. However, this embodiment is not limited to this.

[0184] In this exemplary embodiment, Figure 28 The third initialization transistor M7, as illustrated, is included in the pixel circuit of the (n-1)th row of sub-pixels, while the remaining transistors (i.e., M1 to M6) are included in the pixel circuit of the nth row of sub-pixels. Figure 28 The third initialization transistor M7 is connected to the first electrode of the light-emitting element of the (n-1)th row sub-pixel, and the light-emitting control transistor M6 is connected to the first electrode of the light-emitting element of the nth row sub-pixel.

[0185] A top view of the first semiconductor layer of the display area in this exemplary embodiment can be referred to. Figure 22 As shown, the top view of the first conductive layer can be referred to Figure 23 As shown, the top view of the second semiconductor layer can be referred to Figure 24 As shown, the top view of the second conductive layer can be referred to Figure 25 As shown, it will not be elaborated further here.

[0186] Figure 30 This is a top view of a sub-pixel after the formation of the fifth insulating layer, according to at least one embodiment of this disclosure. Figures 28 to 30 as well as Figures 22 to 25As shown, a plurality of vias are formed on the fifth insulating layer of the display area in this exemplary embodiment. The plurality of vias includes at least: first vias K19 to K28, second vias D19 to D22, third vias V6 to V8, and fourth vias F13 to F15. The fifth insulating layer 35, fourth insulating layer 34, third insulating layer 33, and second insulating layer 32 within the first vias are etched away, exposing the surface of the first semiconductor layer. The fifth insulating layer 35, fourth insulating layer 34, and third insulating layer 33 within the second vias are etched away, exposing the surface of the first conductive layer. The fifth insulating layer 35 and fourth insulating layer 34 within the third vias are etched away, exposing the surface of the second semiconductor layer. The fifth insulating layer 35 within the fourth vias is etched away, exposing the surface of the second conductive layer.

[0187] Figure 31 This is a top view of a sub-pixel after the formation of the third conductive layer, according to at least one embodiment of this disclosure. Figures 28 to 31 as well as Figures 22 to 25 As shown, the third conductive layer of the display area in this exemplary embodiment includes at least: a data line DATA, an initial voltage line INT, a second electrode 533 of a driving transistor M3, a first electrode 522 and a second electrode 523 of a compensation transistor M2, a first electrode 512 of a first initialization transistor M1, a first electrode 552 and a second electrode 553 of a second initialization transistor M5, a second electrode 543 of a data writing transistor M4, a second electrode 562 of a light-emitting control transistor M6, a second electrode 573 of a third initialization transistor M7, a scan line connection electrode 600, and a power connection line 601. The data line DATA provides a data signal, and the initial voltage line INT provides an initial voltage. The first electrode 522 of the compensation transistor M2 and the second electrode 533 of the driving transistor M3 are integrally formed.

[0188] In some exemplary embodiments, the power connection line 601, the data line DATA, and the initial voltage line INT extend along the second direction Y. The first electrode 512 of the first initialization transistor M1 is connected to the first doped region 510b of the active layer 510 of the first initialization transistor M1 via a third via V8, and to the first doped region 570b of the active layer 570 of the third initialization transistor M7 via a first via K26. The initial voltage line INT is connected to the first doped region 570b of the active layer 570 of the third initialization transistor M7 via a first via K25. The first electrode 512 of the first initialization transistor M1 is connected to the initial voltage line INT via the first doped region 570b of the active layer 570 of the third initialization transistor M7. The first electrode 522 of the compensation transistor M2 is connected to the first doped region 520b of the active layer 520 of the compensation transistor M2 via a third via V6. The second electrode 523 of the compensation transistor M2 is connected to the second doped region 520c of the active layer 520 of the compensation transistor M2 through the third via V7, and to the first electrode 581 of the storage capacitor Cst through the second via D19. The second electrode 533 of the driving transistor M3 is connected to the second doped region 530c of the active layer 530 of the driving transistor M3 through the first via K20. The power connection line 601 is connected to the first doped region 530b of the active layer 530 of the driving transistor M3 through the first via K19, and is also connected to the first electrode 591 of the voltage regulator capacitor Crt through the second via D20. The first electrode 552 of the second initialization transistor M5 is connected to the first doped region 550b of the active layer 550 of the second initialization transistor M5 through the first via K23, and to the reference voltage line REF through the fourth via F15. The second electrode 553 of the second initialization transistor M5 is connected to the second doped region 550c of the active layer 550 of the second initialization transistor M5 through the first via K24, and to the second electrode 582 of the storage capacitor Cst through the fourth via F14. The second electrode 543 of the data writing transistor M4 is connected to the second doped region 540c of the active layer 540 of the data writing transistor M4 through the first via K21, and to the second electrode 592 of the voltage regulator capacitor Crt through the fourth via F13. The data line DATA is connected to the first doped region 540b of the active layer 540 of the data writing transistor M4 through the first via K22. The scan line connection electrode 600 is connected to the first scan line GT1 through the second via D21, and to the control electrode 541 of the data writing transistor M4 through the second via D22. The second electrode 563 of the light-emitting control transistor M6 is connected to the second doped region 560c of the active layer 560 of the light-emitting control transistor M6 through the first via K28. The second electrode 573 of the third initialization transistor M7 is connected to the second doped region 570c of the active layer 570 of the third initialization transistor M7 through the first via K27.

[0189] Figure 32 This is a top view of a sub-pixel after the formation of the seventh insulating layer, according to at least one embodiment of this disclosure. Figures 28 to 32 as well as Figures 22 to 25 As shown, a plurality of vias are formed on the seventh insulating layer of the display area in this exemplary embodiment. The plurality of vias includes at least five vias J1 to J4. The seventh insulating layer 37 and the sixth insulating layer 36 within the fifth vias are etched away, exposing the surface of the third conductive layer. Specifically, the fifth via J1 exposes the surface of the second electrode 573 of the third initialization transistor M7. The fifth via J2 exposes the surface of the second electrode 563 of the light-emitting control transistor M6. The fifth vias J3 and J4 are arranged sequentially along the second direction Y and expose the surface of the power connection line 601.

[0190] Figure 33 This is a top view of a sub-pixel after the formation of the fourth conductive layer, according to at least one embodiment of this disclosure. Figures 28 to 33 as well as Figures 22 to 25 As shown, the fourth conductive layer of the display area in this exemplary embodiment includes at least: a third power line VDD, a first anode connection electrode 701, and a second anode connection electrode 702. The third power line VDD extends in the first direction X and the second direction Y to form a mesh structure to reduce resistance. The third power line VDD is connected to the power connection line 601 through fifth vias J3 and J4. The first anode connection electrode 701 is connected to the second electrode 573 of the third initialization transistor M7 through the fifth via J1. The second anode connection electrode 702 is connected to the second electrode 563 of the light-emitting control transistor M6 through the fifth via J2. In some examples, the first anode connection electrode 701 may be connected to the first electrode of the light-emitting element of the previous row of sub-pixels, and the second anode connection electrode 702 may be connected to the first electrode of the light-emitting element of the current row of sub-pixels.

[0191] In some exemplary embodiments, the gate driving circuit in the peripheral region can provide a first scan signal, a second scan signal, a first reset signal, a second reset signal, and a light emission control signal to the pixel circuit in the display region. In some examples, the gate driving circuit may include: a plurality of cascaded first shift register units, a plurality of cascaded second shift register units, and a plurality of cascaded third shift register units. The first shift register units can provide a second scan signal to the pixel circuit in the display region through a second scan line and a second reset signal to the pixel circuit through a second reset signal line; the second shift register units can provide a first scan signal to the pixel circuit in the display region through a first scan line and a first reset signal to the pixel circuit through a first reset signal line; the third shift register units can provide a light emission control signal to the pixel circuit in the display region through a light emission control line.

[0192] Figure 34This is a schematic diagram showing the connection between the gate driving circuit and the pixel circuit in at least one embodiment of this disclosure. Figure 34 As shown, the first shift register unit RST2_GOA(n) of the nth stage can provide the second reset signal RST2(n) and the second scan signal GT2(n) to the pixel circuit of the nth row sub-pixel PL(n). The second shift register unit RST1_GOA(n) of the nth stage can provide the first reset signal RST1(n) to the pixel circuit of the nth row sub-pixel PL(n), and the first scan signal GT1(n-2) to the pixel circuit of the (n-2)th row sub-pixel PL(n-2). The third shift register unit EM_GOA(n) of the nth stage can provide the light emission control signal EM(n) to the pixel circuit of the nth row sub-pixel PL(n). Here, n is an integer greater than 0.

[0193] In some exemplary embodiments, the equivalent circuit diagram of the first shift register unit can be as follows: Figure 7 As shown, the equivalent circuit diagram of the second shift register unit can be obtained as follows: Figure 12 As shown. The connection relationship between the first shift register unit and the second shift register unit can be as follows: Figure 11 As shown. However, this embodiment is not limited in this respect.

[0194] In some exemplary embodiments, the third output of the nth-stage first shift register unit is connected to the second reset signal line of the pixel circuit driving the nth row of sub-pixels, and also to the third reset signal line driving the (n-1)th row of sub-pixels. The second output of the nth-stage first shift register unit is connected to the second scan line of the pixel circuit driving the nth row of sub-pixels. The fifth output of the nth-stage second shift register unit is connected to the first reset signal line of the pixel circuit driving the nth row of sub-pixels, and the fourth output of the nth-stage second shift register unit is connected to the first scan line of the pixel circuit driving the (n-2)th row of sub-pixels.

[0195] The gate drive circuit provided in this exemplary embodiment has a simplified structure and can provide a variety of different gate drive signals to the pixel circuit through three shift register units, thereby improving the performance of the pixel circuit.

[0196] Figure 35 This is a top view of a first shift register unit according to at least one embodiment of the present disclosure. Figure 36 for Figure 35 A cross-sectional view along the PP direction is shown. The equivalent circuit diagram of the first shift register unit in this exemplary embodiment is shown below. Figure 7As shown. Among them, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 in the first shift register unit are N-type transistors and are IGZO thin film transistors, while the remaining transistors in the first shift register unit are P-type transistors and are low-temperature polycrystalline silicon thin film transistors.

[0197] In some exemplary implementations, such as Figure 35 and Figure 36 As shown, in a plane perpendicular to the display substrate, the peripheral region of the display substrate may include: a substrate 30, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate 30. A first insulating layer 31 is disposed between the substrate 30 and the first semiconductor layer. A second insulating layer 32 is disposed between the first conductive layer and the first semiconductor layer. A third insulating layer 33 is disposed between the first conductive layer and the second semiconductor layer. A fourth insulating layer 34 is disposed between the second semiconductor layer and the second conductive layer. A fifth insulating layer 35 is disposed between the second conductive layer and the third conductive layer. However, this embodiment is not limited to this. In some examples, the display area may include: a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer sequentially disposed on the substrate.

[0198] Figure 37 This is a top view of a first shift register unit after the formation of the first semiconductor layer, according to at least one embodiment of this disclosure. Figures 35 to 37 As shown, the first semiconductor layer in the peripheral region may have a bent or folded shape. The first semiconductor layer in the peripheral region includes at least: an active layer 110 of the first transistor T1, an active layer 120 of the second transistor T2, an active layer 150 of the fifth transistor T5, an active layer 170 of the seventh transistor T7, an active layer 180 of the eighth transistor T8, an active layer 190 of the ninth transistor T9, an active layer 200 of the tenth transistor T10, an active layer 210 of the eleventh transistor T11, an active layer 220 of the twelfth transistor T12, an active layer 230 of the thirteenth transistor T13, and an active layer 240 of the fourteenth transistor T14.

[0199] In some exemplary embodiments, the active layer 110 of the first transistor T1 and the active layer 120 of the second transistor T2 are integral structures, for example, in an elongated shape. The active layer 180 of the eighth transistor T8 and the active layer 190 of the ninth transistor T9 are integral structures, for example, in a U-shape. The active layer 200 of the tenth transistor T10 and the active layer 220 of the twelfth transistor T12 are integral structures, for example, in a └ shape.

[0200] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include a channel region, a first doped region, and a second doped region. The channel region may be undoped and has semiconductor properties. The first and second doped regions may be located on opposite sides of the channel region and are doped with impurities, thus exhibiting conductivity. The impurities may vary depending on the type of transistor. The first or second doped region of the active layer can be interpreted as the source or drain electrode of the transistor. For example, the source electrode of the first transistor T1 may correspond to the first doped region 110b, which is doped with impurities, surrounding the channel region 110a of the active layer 110; the drain electrode of the first transistor T1 may correspond to the second doped region 110c, which is doped with impurities, surrounding the channel region 110a of the active layer 110. Additionally, portions of the active layer between transistors can be interpreted as doped wiring that can be used to electrically connect transistors.

[0201] Figure 38 This is a top view of a first shift register unit after the formation of the first conductive layer, according to at least one embodiment of this disclosure. Figures 35 to 38 As shown, the first conductive layer in the peripheral region includes at least: the control electrode 111 of the first transistor T1, the control electrode 121 of the second transistor T2, the control electrode 151 of the fifth transistor T5, the control electrode 171 of the seventh transistor T7, the control electrode 181 of the eighth transistor T8, the control electrode 191 of the ninth transistor T9, the control electrode 201 of the tenth transistor T10, the control electrode 211 of the eleventh transistor T11, the control electrode 221 of the twelfth transistor T12, the control electrode 231 of the thirteenth transistor T13, the control electrode 241 of the fourteenth transistor T14, the first electrode 251 of the first capacitor C1, the first electrode 261 of the second capacitor C2, the first electrode 271 of the third capacitor C3, the first connecting electrode 281, the first output terminal OUT1, the second output terminal OUT2, and the third output terminal OUT3.

[0202] In some exemplary embodiments, the control electrode 121 and the second output terminal OUT2 of the second transistor T2 can be an integral structure. The control electrode 111 of the first transistor T1 is located between the control electrode 121 of the second transistor T2 and the second output terminal OUT2. The extension directions of the control electrode 111 of the first transistor T1, the control electrode 121 of the second transistor T2, and the second output terminal OUT2 are parallel to each other. The third output terminal OUT3 is located on the side of the control electrode 121 of the second transistor T2 away from the control electrode 111 of the first transistor T1. The extension direction of the third output terminal OUT3 is parallel to the extension direction of the control electrode 111 of the first transistor T1. The first output terminal OUT1 is located on the side of the control electrode 151 of the fifth transistor T5 away from the second output terminal OUT2. The first output terminal OUT1 is, for example, of a "┐" shape.

[0203] In some exemplary embodiments, the control electrode 171 of the seventh transistor T7 and the first electrode 251 of the first capacitor C1 can be an integral structure. The control electrode 231 of the thirteenth transistor T13 and the first electrode 261 of the second capacitor C2 can be an integral structure. The control electrode 241 of the fourteenth transistor T14 and the first electrode 271 of the third capacitor C3 can be an integral structure. The control electrode 221 of the twelfth transistor T12 and the first connection electrode 281 are an integral structure.

[0204] Figure 39 This is a top view of the first shift register unit after the formation of the second semiconductor layer, according to at least one embodiment of this disclosure. Figures 35 to 39 As shown, the second semiconductor layer in the peripheral region can have a bent or folded shape. The second semiconductor layer in the peripheral region includes at least: an active layer 130 of the third transistor T3, an active layer 140 of the fourth transistor T4, and an active layer 160 of the sixth transistor T6. In some examples, the material of the second semiconductor layer includes IGZO.

[0205] In some exemplary embodiments, the active layer 130 of the third transistor T3 and the active layer 140 of the fourth transistor T4 are integral structures, for example, in an "U" shape. The active layer 130 of the third transistor T3 includes a channel region 130a, a first doped region 130b and a second doped region 130c located on both sides of the channel region 130a. The active layer 140 of the fourth transistor T4 includes a channel region 140a, a first doped region 140b and a second doped region 140c located on both sides of the channel region 140a. The second doped region 130c of the active layer 130 of the third transistor T3 and the second doped region 140c of the active layer 140 of the fourth transistor T4 are connected. The active layers 130 of the third transistor T3 and the active layer 140 of the fourth transistor T4 are located on the side of the third output terminal OUT3 away from the second output terminal OUT2. The active layer 160 of the sixth transistor T6 is located on the side of the active layer 130 of the third transistor T3 near the first electrode 261 of the second capacitor C2. The active layer 160 of the sixth transistor T6 includes a channel region 160a, a first doped region 160b and a second doped region 160c located on both sides of the channel region 160a.

[0206] Figure 40 This is a top view of the first shift register unit after the formation of the second conductive layer, according to at least one embodiment of this disclosure. Figures 35 to 40 As shown, the second conductive layer in the peripheral region includes at least: the control electrode 131 of the third transistor T3, the control electrode 141 of the fourth transistor T4, the control electrode 161 of the sixth transistor T6, the second electrode 252 of the first capacitor C1, the second electrode 262 of the second capacitor C2, the second electrode 272 of the third capacitor C3, the second connection electrode 282, the third connection electrode 283, and the control signal line CSL.

[0207] In some exemplary embodiments, the projection of the second electrode 262 of the second capacitor C2 onto the substrate covers the projection of the first electrode 261 of the second capacitor C2 onto the substrate. Similarly, the projection of the second electrode 272 of the third capacitor C3 onto the substrate covers the projection of the first electrode 271 of the third capacitor C3 onto the substrate. The projection of the control signal line CSL onto the substrate is located on the side of the first connection electrode 281 that is away from the projection of the first connection electrode 281 onto the substrate. The extending directions of the second connection electrode 282 and the third connection electrode 283 are parallel to each other.

[0208] Figure 41 This is a top view of the first shift register unit after the formation of the fifth insulating layer, according to at least one embodiment of this disclosure. Figures 35 to 41 As shown, a plurality of vias are formed on the fifth insulating layer 35 in the peripheral region. The plurality of vias includes at least: first vias K11 to K18, second vias D1 to D18, third vias V1 to V5, and fourth vias F1 to F12. The fifth insulating layer 35, fourth insulating layer 34, third insulating layer 33, and second insulating layer 32 within the first vias K11 to K18 are etched away, exposing the surface of the first semiconductor layer. The fifth insulating layer 35, fourth insulating layer 34, and third insulating layer 33 within the second vias D1 to D18 are etched away, exposing the surface of the first conductive layer. The fifth insulating layer 35 and fourth insulating layer 34 within the third vias V1 to V5 are etched away, exposing the surface of the second semiconductor layer. The fifth insulating layer 35 within the fourth vias F1 to F12 is etched away, exposing the surface of the second conductive layer.

[0209] Figure 42 This is a top view of the first shift register unit after the formation of the third conductive layer, according to at least one embodiment of this disclosure. Figures 35 to 42As shown, the third conductive layer in the peripheral region includes at least: a first electrode 112 of the first transistor T1, a second electrode 123 of the second transistor T2, a first electrode 132 and a second electrode 133 of the third transistor T3, a first electrode 142 and a second electrode 143 of the fourth transistor T4, a first electrode 152 and a second electrode 153 of the fifth transistor T5, a first electrode 162 and a second electrode 163 of the sixth transistor T6, a first electrode 172 and a second electrode 173 of the seventh transistor T7, a first electrode 182 of the eighth transistor T8, and a first electrode 192 and a second electrode 193 of the ninth transistor T9. The first electrode 202 of the tenth transistor T10, the first electrode 212 and the second electrode 213 of the eleventh transistor T11, the first electrode 222 and the second electrode 223 of the twelfth transistor T12, the first electrode 232 and the second electrode 233 of the thirteenth transistor T13, the first electrode 242 and the second electrode 243 of the fourteenth transistor T14, the fourth connection electrode 284, the fifth connection electrode 285, the sixth connection electrode 286, the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the first power supply line VGH, and the second power supply line VGL.

[0210] In some exemplary embodiments, the first electrode 112 of the first transistor T1 is connected to the first doped region 110b of the active layer 110 of the first transistor T1 through a first via K1. The second electrode 123 of the second transistor T2 is connected to the second doped region 120c of the active layer 120 of the second transistor T2 through a first via K2, and is connected to the third output terminal OUT3 through a second via D3. The fourth connection electrode 284 is connected to the control electrode 141 of the first transistor T1 through a second via D1, to the control electrode 141 of the fourth transistor T4 through a fourth via F1, and to the control signal line CSL through a fourth via F4. The first electrode 142 of the fourth transistor T4 is connected to the first doped region 140b of the active layer 140 of the fourth transistor T4 through a third via V2, and is connected to the first connection electrode 281 through a second via D6. The first electrode 132 of the third transistor T3 is connected to the first doped region 130b of the active layer 130 of the third transistor T3 through the third via V3, and is connected to the first connection electrode 281 through the second via D7. The second electrode 133 of the third transistor T3 is connected to the second doped region 130c of the active layer 130 of the third transistor T3 and the second doped region 140c of the active layer 140 of the fourth transistor T4 through the third via V1. The second electrode 123 of the second transistor T2, the second electrode 133 of the third transistor T3, and the second electrode 143 of the fourth transistor T4 are integrally structured.

[0211] In some exemplary embodiments, the first electrode 152 of the fifth transistor T5 is connected to the first doped region 150b of the active layer 150 of the fifth transistor T5 through a first via K3. The second electrode 153 of the fifth transistor T5 is connected to the second doped region 150c of the active layer 150 of the fifth transistor T5 through a first via K4, and is connected to the control electrode 121 and the second output terminal OUT2 of the second transistor T2 through a second via D2. The first electrode 162 of the sixth transistor T6 is connected to the first doped region 160b of the active layer 160 of the sixth transistor T6 through a third via V4, and is connected to the first connection electrode 281 through a second via D8. The second electrode 163 of the sixth transistor T6 is connected to the second doped region 160c of the active layer 160 of the sixth transistor T6 through a third via V5, and is connected to the control electrode 131 of the third transistor T3 through a fourth via F2. The second electrodes 153 of the fifth transistor T5 and 163 of the sixth transistor T6 are integrally formed.

[0212] In some exemplary embodiments, the first electrode 172 of the seventh transistor T7 is connected to the first doped region 170b of the active layer 170 of the seventh transistor T7 through the first via K6, to the second electrode 252 of the first capacitor C1 through the fourth via F5, and to the control electrode 201 of the tenth transistor T10 through the second via D12. The second electrode 173 of the seventh transistor T7 is connected to the second doped region 170c of the active layer 170 of the seventh transistor T7 through the first via K5, and to the control electrode 241 of the fourteenth transistor T14 through the second via D18. The first electrode 182 of the eighth transistor T8 is connected to the first doped region 180b of the active layer 180 of the eighth transistor T8 through the first via K7, and to the third connection electrode 283 through the fourth via F9. The sixth connection electrode 286 is connected to the control electrode 181 of the eighth transistor T8 through the second via D10, and to the second connection electrode 282 through the fourth via F7. The first electrode 192 of the ninth transistor T9 is connected to the first doped region 190b of the active layer 190 of the ninth transistor T9 through the first via K8. The second electrode 193 of the ninth transistor T9 is connected to the second doped region 190c of the active layer 190 of the ninth transistor T9 through the first via K9, and is connected to the first electrode 251 of the first capacitor C1 through the second via D9. The second clock signal line CB1 is connected to the control electrode 191 of the ninth transistor T9 through the second via D11. The first electrode 202 of the tenth transistor T10 is connected to the first doped region 200b of the active layer 200 of the tenth transistor T10 through the first via K10, and is connected to the second connection electrode 282 through the fourth via F6. The first electrode 202 of the tenth transistor T10 is integrated with the first input terminal INPUT1. The first clock signal line CK1 is connected to the control electrode 201 of the tenth transistor T10 through the second via D13. The first electrode 212 of the eleventh transistor T11 is connected to the first doped region 201b of the active layer 201 of the eleventh transistor T11 through the first via K12, and is connected to the third connection electrode 283 through the fourth via F8. The second electrode 213 of the eleventh transistor T11 is connected to the second doped region 201c of the active layer 201 of the eleventh transistor T11 through the first via K11. The second electrode 173 of the seventh transistor T7 and the second electrode 213 of the eleventh transistor T11 are of the same structure.

[0213] In some exemplary embodiments, the first electrode 222 of the twelfth transistor T12 is connected to the first doped region 220b of the active layer 220 of the twelfth transistor T12 through a first via K13, and to the control electrode 211 of the eleventh transistor T11 through a second via D14. The second electrode 223 of the twelfth transistor T12 is connected to the second doped region 220c of the active layer 220 of the twelfth transistor T12 through a first via K14, and to the control electrode 231 of the thirteenth transistor T13 through a second via D17. The first electrode 232 of the thirteenth transistor T13 is connected to the first doped region 230b of the active layer 230 of the thirteenth transistor T13 through three side-by-side first vias K15, and to the first connection electrode 281 through a second via D16. The second electrode 233 of the thirteenth transistor T13 is connected to the second doped region 230c of the active layer 230 of the thirteenth transistor T13 through three side-by-side first vias K16, and to the second electrode 262 of the second capacitor C2 through three side-by-side fourth vias F10. The first electrode 242 of the fourteenth transistor T14 is connected to the first doped region 240b of the active layer 240 of the fourteenth transistor T14 through three side-by-side first vias K17, and to the third connection electrode 283 through a fourth via F9. The second electrode 243 of the fourteenth transistor T14 is connected to the second doped region 240c of the active layer 240 of the fourteenth transistor T14 through three side-by-side first vias K18. The second electrode 243 of the fourteenth transistor T14 and the second electrode 233 of the thirteenth transistor T13 are of a single integrated structure.

[0214] In some exemplary embodiments, the second power line VGL is connected to the first connection electrode 281 through the second via D15. The first power line VGH is connected to the second electrode 272 of the second capacitor C2 through three vertically arranged fourth vias F12. The first power line VGH is integrally structured with the first electrode 122 of the first transistor T1, the first electrode 152 of the fifth transistor T5, the first electrode 182 of the eighth transistor T8, the first electrode 192 of the ninth transistor T9, and the first electrode 242 of the fourteenth transistor.

[0215] In some exemplary embodiments, the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the second power supply line VGL, and the first power supply line VGH extend in parallel directions and perpendicular to the extension direction of the control signal line CSL. For example, the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the second power supply line VGL, and the first power supply line VGH are arranged sequentially in a horizontal direction and all extend in a vertical direction; the control signal line CSL extends in a horizontal direction.

[0216] The first shift register unit provided in this exemplary embodiment can provide a second reset signal and a second scan signal to the pixel circuit of the display area. The second reset signal provided by the first shift register unit in this exemplary embodiment can maintain the voltage of the second node of the pixel circuit during the reset phase and the compensation phase.

[0217] Figure 43 This is an equivalent circuit diagram of the third shift register unit of at least one embodiment of this disclosure. Figure 43As shown, the third shift register unit provided in this exemplary embodiment includes: transistors T25 to T34, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The control electrode of transistor T25 is connected to the fifth clock signal line CK3, the first electrode of transistor T25 is connected to the third input terminal INPUT3, and the second electrode of transistor T25 is connected to the sixth control node P6. The control electrode of transistor T26 is connected to the sixth control node P6, the first electrode of transistor T26 is connected to the fifth clock signal line CK3, and the second electrode of transistor T26 is connected to the fifth control node P5. The control electrode of transistor T27 is connected to the fifth clock signal line CK3, the first electrode of transistor T27 is connected to the second power supply line VGL, and the second electrode of transistor T27 is connected to the fifth control node P5. The control electrode of transistor T28 is connected to the sixth clock signal line CB3, the first electrode of transistor T28 is connected to the second electrode of transistor T29, and the second electrode of transistor T28 is connected to the sixth control node P6. The control electrode of transistor T29 is connected to the fifth control node P5, and its first electrode is connected to the first power supply line VGH. The control electrode of transistor T30 is connected to the fifth control node P5, its first electrode is connected to the sixth clock signal line CB3, and its second electrode is connected to the first electrode of transistor T31. The control electrode of transistor T31 is connected to the sixth clock signal line CB3, and its second electrode is connected to the seventh control node P7. The control electrode of transistor T32 is connected to the sixth control node P6, its first electrode is connected to the first power supply line VGH, and its second electrode is connected to the seventh control node P7. The control electrode of transistor T33 is connected to the seventh control node P7, its first electrode is connected to the first power supply line VGH, and its second electrode is connected to the sixth output terminal OUT6. The control electrode of the 34th transistor T34 is connected to the sixth control node P6. The first electrode of the 34th transistor T34 is connected to the second power supply line VGL, and the second electrode of the 34th transistor T34 is connected to the sixth output terminal OUT6. The first electrode of the sixth capacitor C6 is connected to the control electrode of the 30th transistor T30, and the second electrode of the sixth capacitor C6 is connected to the second electrode of the 30th transistor T30. The first electrode of the seventh capacitor C7 is connected to the control electrode of the 33rd transistor T33, and the second electrode of the seventh capacitor C7 is connected to the first power supply line VGH. The first electrode of the eighth capacitor C8 is connected to the control electrode of the 34th transistor T34, and the second electrode of the eighth capacitor C8 is connected to the sixth clock signal line CB3.

[0218] The following explanation uses the example of transistors T25 to T34, all of which are P-type transistors, as an example. The explanation will focus on the first-stage third shift register unit. The third input terminal INPUT3 of the first-stage third shift register unit is connected to the third initial signal line STV3. Figure 44 for Figure 43 The timing diagram of the third shift register unit is shown. Figure 43 and Figure 44 As shown, the third shift register unit of this exemplary embodiment includes 10 transistor units (i.e., the twenty-fifth transistor T25 to the thirty-fourth transistor T34), 3 capacitor units (i.e., the sixth capacitor C6 to the eighth capacitor C8), 3 input terminals (i.e., the fifth clock signal line CK3, the sixth clock signal line CB3, and the third input terminal INPUT3), 1 output terminal (i.e., the sixth output terminal OUT6), and 2 power supply terminals (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH continuously provides a high-level signal, and the second power supply line VGL continuously provides a low-level signal.

[0219] like Figure 43 and Figure 44 As shown, the operation of the third shift register unit in this exemplary embodiment includes the following stages.

[0220] In the first stage t31, the fifth clock signal line CK3 provides a high-level signal, the sixth clock signal line CB3 provides a high-level signal, and the third initial signal line STV3 provides a high-level signal. Transistors T25, T27, T28, T29, T30, T31, and T33 are cut off, while transistors T26, T32, and T34 are turned on. The sixth output terminal OUT6 outputs a low-level signal.

[0221] In the second stage t32, the fifth clock signal line CK3 provides a low-level signal, the sixth clock signal line CB3 provides a high-level signal, and the third initial signal line STV3 provides a high-level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-ninth transistor T29, and the thirtieth transistor T30 are turned on, while the twenty-sixth transistor T26, the twenty-eighth transistor T28, the thirty-first transistor T31, the thirty-second transistor T32, the thirty-fourth transistor T34, and the thirty-third transistor T33 are turned off. The sixth output terminal OUT6 outputs a low-level signal.

[0222] In the third stage (t33), the fifth clock signal line CK3 provides a high-level signal, the sixth clock signal line CB3 provides a low-level signal, and the third initial signal line STV3 provides a high-level signal. Transistors T25 (25), T27 (27), T26 (26), T32 (32), and T34 (34) are cut off, while transistors T28 (28), T29 (29), T30 (30), T32 (31), and T33 (33) are turned on. The sixth output terminal OUT outputs a high-level signal.

[0223] In the fourth stage (t34), the fifth clock signal line CK3 provides a low-level signal, the sixth clock signal line CB3 provides a high-level signal, and the third initial signal line STV3 provides a high-level signal. Transistors T25, T27, T29, T30, and T33 are turned on, while transistors T26, T28, T31, T32, and T34 are turned off. The sixth output terminal OUT6 provides a high-level signal.

[0224] In the fifth stage (t35), the fifth clock signal line CK3 provides a high-level signal, the sixth clock signal line CB3 provides a low-level signal, and the third initial signal line STV3 provides a low-level signal. Transistors T25, T26, T27, T32, and T34 are cut off, while transistors T28, T29, T30, T31, and T33 are turned on. The sixth output terminal OUT6 provides a high-level signal.

[0225] In stage t36, the fifth clock signal line CK3 provides a low-level signal, the sixth clock signal line CB3 provides a high-level signal, and the third initial signal line STV3 provides a low-level signal. Transistors T25, T26, T27, T32, and T34 are turned on, while transistors T28, T29, T30, T31, and T33 are turned off. The sixth output terminal OUT6 provides a low-level signal.

[0226] In stage 7 (t37), the fifth clock signal line CK3 provides a high-level signal, the sixth clock signal line CB3 provides a low-level signal, and the third initial signal line STV3 provides a low-level signal. Transistors T25 (25), T27 (27), T29 (29), T30 (30), and T33 (33) are cut off; transistors T26 (26), T31 (31), T32 (32), and T34 (34) are turned on. The sixth output terminal OUT6 provides a low-level signal.

[0227] After the seventh stage, the sixth and seventh stages can be repeated until the third input terminal INPUT3 receives a low-level signal, and then the process can start again from the first stage.

[0228] The third shift register unit provided in this exemplary embodiment provides a light emission control signal to the pixel circuit through a light emission control line.

[0229] The structure of a display substrate is illustrated below using an example of its fabrication process. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using one or more of spraying and spin coating; and etching can be performed using one or more of dry and wet etching. A "thin film" refers to a thin film of a material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0230] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0231] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations, such as Figures 20 to 27 as well as Figures 35 to 42 As shown. The fabrication process of this exemplary embodiment is described using a sub-pixel of the display area and a first shift register unit of the peripheral area as an example, and the equivalent circuit diagram of the pixel circuit of the sub-pixel is shown below. Figure 18 As shown, the equivalent circuit diagram of the first shift register unit is as follows: Figure 7 As shown.

[0232] (1) A flexible substrate is prepared on a glass carrier.

[0233] In some exemplary embodiments, the substrate 30 includes a first flexible layer 30A, a first inorganic material layer 30B, a second flexible layer 30C, and a second inorganic material layer 30D stacked on a glass carrier. The first flexible layer 30A and the second flexible layer 30C can be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film. The first inorganic material layer 30B and the second inorganic material layer 30D can be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first inorganic material layer 30B and the second inorganic material layer 30D are also referred to as barrier layers.

[0234] In some exemplary embodiments, the substrate fabrication process may include: firstly, coating a layer of polyimide onto a glass substrate, curing it to form a first flexible layer; then depositing a barrier film on the first flexible layer to form a first barrier layer covering the first flexible layer; then coating another layer of polyimide on the first barrier layer, curing it to form a second flexible layer; and finally depositing a barrier film on the second flexible layer to form a second barrier layer covering the second flexible layer, thus completing the fabrication of the substrate 30. After this process, both the display area and the peripheral area include the substrate 30, such as... Figure 21 and Figure 36 As shown.

[0235] (2) Forming the pattern of the first semiconductor layer.

[0236] In some exemplary embodiments, a first insulating film and a first semiconductor film are sequentially deposited on a substrate 30. The first semiconductor film is patterned using a patterning process to form a first insulating layer 31 covering the entire substrate 30, and a first semiconductor layer pattern disposed on the first insulating layer 31, such as... Figure 22 and Figure 37 As shown. In some examples, the first semiconductor layer pattern includes at least an active layer of multiple P-type transistors in the pixel circuit and the first shift register unit. The active layer may include a channel region, a source region, and a drain region. The channel region may be undoped and have semiconductor properties. The source and drain regions may be on opposite sides of the channel region and are doped with impurities, thus becoming conductive. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor thin film may be polycrystalline silicon.

[0237] (3) Form the pattern of the first conductive layer.

[0238] In some exemplary embodiments, a second insulating film and a first metal film are sequentially deposited on the substrate 30 on which the aforementioned pattern is formed. The first metal film is patterned using a patterning process to form a second insulating layer 32 covering the pattern of the first semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer 32, such as... Figure 23 and Figure 38 As shown. In some examples, the first conductive layer pattern includes at least: control electrodes of multiple P-type transistors in the pixel circuit and the first shift register unit, first electrodes of multiple capacitors in the pixel circuit and the first shift register unit, a light emission control line EM providing a light emission control signal to the pixel circuit, a first scan line GT1 providing a first scan signal to the pixel circuit, a second reset signal line RST2 providing a second reset signal to the pixel circuit, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal OUT3 of the first shift register unit.

[0239] (4) Forming a second semiconductor layer pattern.

[0240] In some exemplary embodiments, a third insulating film and a second semiconductor film are sequentially deposited on the substrate 30 on which the aforementioned pattern is formed. The second semiconductor film is patterned using a patterning process to form a third insulating layer 33 covering the first conductive layer, and a second semiconductor layer pattern disposed on the third insulating layer 33, such as... Figure 24 and Figure 39 As shown. In some examples, the second semiconductor layer pattern includes at least an active layer of pixel circuitry and multiple N-type transistors in the first shift register unit. In some examples, the material of the second semiconductor thin film may be IGZO.

[0241] (5) Forming the pattern of the second conductive layer.

[0242] In some exemplary embodiments, a fourth insulating film and a second metal film are sequentially deposited on the substrate 30 on which the aforementioned pattern is formed. The second metal film is patterned using a patterning process to form a fourth insulating layer 34 covering the second semiconductor layer, and a second conductive layer pattern disposed on the fourth insulating layer 34, such as... Figure 25 and Figure 40 As shown. In some examples, the second conductive layer pattern includes at least: control electrodes of a plurality of N-type transistors in the pixel circuit and the first shift register unit, second electrodes of a plurality of capacitors in the pixel circuit and the first shift register unit, a first reset signal line RST1 providing a first reset signal to the pixel circuit, a second scan line GT2 providing a second scan signal to the pixel circuit, a reference voltage line REF providing a reference voltage to the pixel circuit, and a control signal line CSL providing a control signal to the first shift register unit.

[0243] (6) Form the fifth insulating layer pattern.

[0244] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer 35 pattern covering the second conductive layer, such as... Figure 26 and Figure 41 As shown. In some examples, a plurality of vias are formed on the fifth insulating layer 35. The plurality of vias includes at least: first vias K1 to K26 exposing the first semiconductor layer, second vias D1 to D22 exposing the first conductive layer, third vias V1 to V8 exposing the second semiconductor layer, and fourth vias F1 to F15 exposing the second conductive layer. The fifth insulating layer 35, the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32 in the first vias K1 to K26 are etched away; the fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the second vias D1 to D22 are etched away; the fifth insulating layer 35 and the fourth insulating layer 34 in the third vias V1 to V8 are etched away; and the fifth insulating layer 35 in the fourth vias F1 to F15 is etched away.

[0245] (7) Forming the pattern of the third conductive layer.

[0246] In some exemplary embodiments, a third metal thin film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the third metal thin film is patterned by a patterning process to form a third conductive layer pattern on the fifth insulating layer 35, such as... Figure 27 and Figure 42 As shown. In some examples, the third conductive layer pattern includes at least: the first and second terminals of a plurality of P-type transistors and a plurality of N-type transistors in the pixel circuit and the first shift register unit; an initial voltage line INT that provides an initial voltage to the pixel circuit; a data line DATA that provides a data signal to the pixel circuit; a third power supply line VDD that provides a power supply voltage to the pixel circuit; a first initial signal line STV1 connected to the first shift register unit; a first clock signal line CK1; a second clock signal line CK2; a first power supply line VGH and a second power supply line VGL; and a plurality of connection electrodes in the pixel circuit and the first shift register unit.

[0247] (8) The planarization layer, anode layer, pixel definition layer, organic light-emitting layer, cathode layer and encapsulation layer are formed in sequence.

[0248] In some exemplary embodiments, a planarization film is coated on a substrate with the aforementioned pattern, and a planarization layer pattern is formed by masking, exposing, and developing the planarization film. Subsequently, an anode film is deposited on the substrate with the aforementioned pattern, and the anode film is patterned using a patterning process to form an anode pattern on the planarization layer. Then, a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL) pattern is formed using a masking, exposing, and developing process. The pixel definition layer is formed in each sub-pixel of the display area, and each sub-pixel has a pixel opening exposing the anode. Subsequently, an organic light-emitting layer is formed within the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Next, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode pattern. The cathode is connected to both the organic light-emitting layer and a second power line. Finally, an encapsulation layer is formed on the cathode, which may include a stacked structure of inorganic / organic / inorganic materials. In some possible implementations, the cathode can be connected to the second power line in various ways, such as by laser drilling.

[0249] In some exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the fourth insulating layer 34, and the fifth insulating layer 35 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single-layer, multi-layer, or composite layer. The first insulating layer 31 and the third insulating layer 33 are referred to as buffer layers, the first insulating layer 31 being configured to improve the substrate's resistance to water and oxygen; the second insulating layer 32 and the fourth insulating layer 34 are referred to as gate insulating (GI) layers, and the fifth insulating layer 35 is referred to as an interlayer insulating (ILD) layer. The planarization layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited in this respect. For example, the anode can be made of a reflective material such as a metal, and the cathode can be made of a transparent conductive material.

[0250] The structure and fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased as needed. For example, after forming the third conductive layer, a sixth insulating layer, a first planarization layer, a fourth conductive layer, a second planarization layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer pattern can be formed sequentially. Alternatively, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, and a third conductive layer can be formed sequentially on a substrate; for example, an N-type thin-film transistor can employ a bottom-gate structure. However, this embodiment is not limited to these methods.

[0251] The preparation process of this exemplary embodiment can be realized using currently mature preparation equipment, is well compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0252] The display substrate provided in this exemplary embodiment provides various gate drive signals to the pixel circuit through the gate drive circuit, which can improve the performance of the pixel circuit and enable the pixel circuit to meet both low-frequency (e.g., about 1Hz) and high-frequency (e.g., about 140Hz) driving requirements. For example, low-frequency driving can be used to save power when the electronic product is in standby mode or during e-reading, while high-frequency driving can be used in gaming mode.

[0253] Figure 45 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 45 As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 is the display substrate provided in the aforementioned embodiment. The display substrate 910 can be an OLED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0254] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure and features thereof can be combined to obtain new embodiments.

[0255] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: The display area and the peripheral area surrounding the display area are provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units. Each shift register unit includes at least one first semiconductor transistor, at least one second semiconductor transistor, and at least one capacitor. In a direction perpendicular to the display substrate, the display substrate includes: a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer and a third conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of at least one second semiconductor transistor of the shift register unit; The first conductive layer includes at least: the control electrode of at least one second semiconductor transistor of the shift register unit, and the first electrode of at least one capacitor; The second semiconductor layer includes at least: an active layer of at least one first semiconductor transistor of the shift register unit; The second conductive layer includes at least: the control electrode of at least one first semiconductor transistor of the shift register unit, and the second electrode of at least one capacitor; The third conductive layer includes at least: at least one first semiconductor transistor and at least one first electrode and second electrode of a second semiconductor transistor in the shift register unit; The first conductive layer further includes a first output terminal, a second output terminal, and a third output terminal of the shift register unit; the output signals of the first output terminal and the second output terminal are out of phase, and the second output terminal and the third output terminal provide effective level signals with opposite polarities.

2. The display substrate according to claim 1, wherein, The first semiconductor transistor and the second semiconductor transistor are of different types.

3. The display substrate according to claim 1, wherein, The second semiconductor layer is located on the side of the third output terminal away from the first semiconductor layer.

4. The display substrate according to claim 3, wherein, The second semiconductor transistor includes a first transistor and a second transistor, and the first semiconductor transistor includes a third transistor and a fourth transistor.

5. The display substrate according to claim 4, wherein, The control electrode of the second transistor and the second output terminal are integrally formed. The control electrode of the first transistor is located between the control electrode of the second transistor and the second output terminal. The third output terminal is located on the side of the control electrode of the first transistor away from the second output terminal.

6. The display substrate according to claim 5, wherein, The extension directions of the first output terminal, the second output terminal, and the third output terminal are parallel to each other.

7. The display substrate according to claim 4, wherein, The active layers of the third transistor and the fourth transistor are located on the side of the third output terminal away from the first transistor and the second transistor, and the active layers of the third transistor and the fourth transistor are an integral structure.

8. The display substrate according to claim 7, wherein, The integrated structure of the active layer of the third transistor and the active layer of the fourth transistor is in the shape of a "U".

9. The display substrate according to claim 4, wherein, The second terminal of the second transistor, the second terminal of the third transistor, and the second terminal of the fourth transistor are integrated into a single structure and connected to the third output terminal.

10. The display substrate according to any one of claims 4 to 9, wherein, The second conductive layer further includes: control signal lines; The third conductive layer further includes a fourth connecting electrode; the fourth connecting electrode is connected to the control electrode of the first transistor, the control electrode of the fourth transistor, and the control signal line.

11. The display substrate according to claim 10, wherein, The third conductive layer further includes: a first power line and a second power line; The first terminal of the first transistor is connected to the first power line, and the first terminals of the third transistor and the fourth transistor are connected to the second power line.

12. The display substrate according to claim 11, wherein, The third conductive layer further includes: a first clock signal line and a second clock signal line, wherein the extension directions of the first clock signal line, the second clock signal line, the first power line and the second power line are parallel to each other and perpendicular to the extension direction of the control signal line.

13. The display substrate according to claim 1, wherein, The shift register unit includes: an input circuit, a first control circuit, a second control circuit, and an output circuit; The input circuit is connected to a first clock signal line, a second clock signal line, a first input terminal, a first power supply line, a first control node, and a second control node. It is configured to provide a signal from the first input terminal to the second control node under the control of the first clock signal line, and to provide a signal from the first clock signal line or the first power supply line to the first control node under the control of the second clock signal line, the first input terminal, and the second control node. The first control circuit is connected to the first control node, the second control node, the first power line, the second power line and the first output terminal, and is configured to provide a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node. The second control circuit is connected to the first power line, the second power line, the first output terminal, and the second output terminal, and is configured to provide an effective level signal of the first power line or the second power line to the second output terminal under the control of the first output terminal. The output circuit is connected to a control signal line, a first power line, a second power line, a second output terminal, and a third output terminal. It is configured to output an effective level signal of the first power line or the second power line to the third output terminal under the control of the control signal line and the second output terminal. Within one frame, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

14. The display substrate according to claim 13, wherein, The output circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the control electrode of the first transistor is connected to a control signal line, the first electrode of the first transistor is connected to a first power supply line, and the second electrode of the first transistor is connected to the first electrode of the second transistor; the control electrode of the second transistor is connected to a second output terminal, and the second electrode of the second transistor is connected to a third output terminal. The control electrode of the third transistor is connected to the second output terminal, the first electrode of the third transistor is connected to the second power supply line, and the second electrode of the third transistor is connected to the third output terminal; the control electrode of the fourth transistor is connected to the control signal line, the first electrode of the fourth transistor is connected to the second power supply line, and the second electrode of the fourth transistor is connected to the third output terminal.

15. The display substrate according to claim 14, wherein, The second control circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first output terminal, the first electrode of the fifth transistor is connected to the first power supply line, and the second electrode of the fifth transistor is connected to the second output terminal. The control electrode of the sixth transistor is connected to the first output terminal, the first electrode of the sixth transistor is connected to the second power line, and the second electrode of the sixth transistor is connected to the second output terminal. The fifth transistor is a second semiconductor transistor, and the sixth transistor is a first semiconductor transistor.

16. The display substrate according to claim 15, wherein, The fifth transistor is located on the side of the first transistor and the second transistor that is closer to the first control circuit, and the sixth transistor is located on the side of the third transistor that is closer to the first control circuit.

17. The display substrate according to claim 16, wherein, The first electrode of the first transistor, the first electrode of the fifth transistor, and the first power line are integrated into one structure; the second electrode of the fifth transistor and the second electrode of the sixth transistor are integrated into one structure and are connected to the control electrode of the third transistor, the control electrode of the second transistor, and the second output terminal.

18. A display device comprising a display substrate as claimed in any one of claims 1 to 17.

19. A method for preparing a display substrate, used to prepare a display substrate as described in any one of claims 1 to 17, the method comprising: Provide a substrate; In the peripheral region surrounding the display area, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are formed on the substrate. The first semiconductor layer includes at least: an active layer of at least one second semiconductor transistor of the shift register unit of the gate drive circuit; the first conductive layer includes at least: a control electrode of at least one second semiconductor transistor of the shift register unit and a first electrode of at least one capacitor; the second semiconductor layer includes at least: an active layer of at least one first semiconductor transistor of the shift register unit; the second conductive layer includes at least: a control electrode of at least one first semiconductor transistor of the shift register unit and a second electrode of at least one capacitor; the third conductive layer includes at least: a first electrode and a second electrode of at least one first semiconductor transistor and at least one second semiconductor transistor of the shift register unit.

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