General constraint information for video coding

Abstract

A method, apparatus, and non-transitory computer-readable storage medium for decoding a video signal are provided. A decoder receives at least one constraint flag. The at least one constraint flag can indicate whether a slice is an intra slice. The decoder obtains a first reference picture I (0) and a second reference picture I (1) associated with a video block in a bitstream. The decoder obtains a first prediction sample I (0) (i,j) of the video block from a reference block in the first reference picture I (0) (i,j). The decoder obtains a second prediction sample I (1) (i,j) of the video block from a reference block in the second reference picture I (1) (i,j). The decoder obtains a bi-prediction sample based on the at least one constraint flag, the first prediction sample I (0) (i,j), and the second prediction sample I (1) (i,j).

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to provisional application No. 63 / 025,153 filed on May 14, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to video coding and compression; more specifically, this application relates to general constraint information applicable to video bitstreams of one or more video coding standards. Background Technology

[0004] Various video coding techniques can be used to compress video data. Video coding is performed according to one or more video coding standards. Examples of video coding standards include Universal Video Coding (VVC), Joint Explore Test Model (JEM), High Efficiency Video Coding (H.265 / HEVC), High-Level Video Coding (H.264 / AVC), Moving Picture Experts Group (MPEG) coding, and so on. Video coding typically uses prediction methods that utilize redundancy present in video images or sequences (e.g., inter-frame prediction, intra-frame prediction, etc.). A key goal of video coding technology is to compress video data to a lower bitrate while avoiding or minimizing video quality degradation. Summary of the Invention

[0005] Examples of this disclosure provide methods and apparatus for encoding general constraint information in video coding.

[0006] According to a first aspect of this disclosure, a method for decoding a video signal is provided. The method may include: a decoder receiving at least one constraint flag. The at least one constraint flag may indicate whether a stripe is an intra-frame stripe. The decoder may also obtain a first reference picture I associated with a video block in the bitstream. (0) Second reference image I (1) In terms of display order, the first reference image I (0) It can be before the current image, and the second reference image I (1) It can be after the current image. The decoder can also be from the first reference image I. (0) The reference block in the video block obtains the first prediction sample I of the video block. (0) (i,j). i and j can represent the coordinates of a sample point relative to the current image. The decoder can also obtain coordinates from the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i,j). The decoder can also be based on the at least one constraint flag and the first prediction sample I.(0) (i,j) and the second prediction sample I (1) (i,j) obtain a bi-prediction sample.

[0007] According to a second aspect of the disclosure, a computing device is provided. The computing device can include one or more processors, and a non-transitory computer-readable memory having stored therein instructions executable by the one or more processors. The one or more processors can be configured to receive at least one constraint flag. The at least one constraint flag can indicate whether a slice is an intra slice. The one or more processors can be further configured to obtain a first reference picture I (0) and a second reference picture I (1) , in display order, the first reference picture I (0) may precede a current picture, and the second reference picture I (1) may follow the current picture. The one or more processors can be further configured to obtain, from a reference block in the first reference picture I (0) , a first prediction sample I (0) (i,j) for the video block, where i and j can represent coordinates of a sample with the current picture. The one or more processors can be further configured to obtain, from a reference block in the second reference picture I (1) , a second prediction sample I (1) (i,j) for the video block. The one or more processors can be further configured to obtain a bi-prediction sample based on the at least one constraint flag, the first prediction sample I (0) (i,j) and the second prediction sample I (1) (i,j).

[0008] According to a third aspect of the disclosure, a non-transitory computer-readable storage medium having stored therein instructions is provided. When the instructions are executed by one or more processors, the instructions can cause the one or more processors to receive at least one constraint flag. The at least one constraint flag can indicate whether a slice is an intra slice. The instructions can cause the one or more processors to obtain a first reference picture I (0) and a second reference picture I (1) , in display order, the first reference picture I (0) may precede a current picture, and the second reference picture I (1) may follow the current picture. The instructions can further cause the one or more processors to obtain, from a reference block in the first reference picture I (0) , a first prediction sample I (0)(i,j). i and j can represent coordinates of a sample and the current picture. The instructions can also cause the one or more processors to obtain second prediction samples I (1) (i,j) of the video block from a reference block in the second reference picture I (1) (i,j). The instructions can also cause the one or more processors to obtain bi-prediction samples based on the at least one constraint flag, the first prediction sample I (0) (i,j), and the second prediction sample I (1) (i,j).

[0009] It is to be understood that the above general description and the following detailed description are exemplary and explanatory only and are not intended to be restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are incorporated herein and constitute a part of the specification, illustrate examples consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0011] Figure 1 is a block diagram of an encoder according to an example of the present disclosure.

[0012] Figure 2 is a block diagram of a decoder according to an example of the present disclosure.

[0013] Figure 3A is a diagram showing block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0014] Figure 3B is a diagram showing block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0015] Figure 3C is a diagram showing block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0016] Figure 3D is a diagram showing block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0017] Figure 3E is a diagram showing block partitioning in a multi-type tree structure according to an example of the present disclosure.

[0018] Figure 4 is a method for decoding a video signal according to an example of the present disclosure.

[0019] Figure 5 is a method for decoding a video signal according to an example of the present disclosure.

[0020] Figure 6A method for decoding a video signal according to an example of the present disclosure.

[0021] Figure 7 A diagram showing a computing environment coupled with a user interface according to an example of the present disclosure. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to embodiments, some examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers represent the same or similar elements unless the context clearly dictates otherwise. The embodiments set forth in the following description do not represent all of the embodiments consistent with the present disclosure. Instead, they are merely examples consistent with aspects related to the present disclosure as recited in the appended claims.

[0023] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any possible combinations of one or more of the associated listed items.

[0024] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various information, the information should not be limited by these terms. These terms are only used to distinguish one category of information from another. For example, without departing from the scope of the present disclosure, first information can be termed as second information; likewise, second information can also be termed as first information. As used herein, the term "if' can be understood to mean "when" or "in response to a decision" or "in response to a determination" depending on the context.

[0025] The first version of the HEVC standard was finalized in October 2013, which provides approximately 50% bitrate savings or equivalent perceptual quality compared to the previous generation video coding standard, H.264 / MPEG AVC. Although the HEVC standard provides significant coding improvement over its predecessor, there is evidence that higher coding efficiency can be achieved compared to HEVC using additional coding tools. On this basis, both VCEG and MPEG started the exploration of new coding techniques for future video coding standardization. In October 2015, ITU-T VECG and ISO / IEC MPEG formed a joint video exploration team (JVET) to start important studies on advanced techniques that can significantly improve coding efficiency. The JVET maintains a reference software called joint exploration model (JEM) by integrating several additional coding tools on top of the HEVC test model (HM).

[0026] In October 2017, ITU-T and ISO / IEC issued a joint call for proposals (CfP) on video compression beyond HEVC. In April 2018, 23 CfP replies were received and evaluated at the 10th JVET meeting, showing approximately 40% improvement in compression efficiency over HEVC. Based on such evaluation results, the JVET started a new project to develop a new generation of video coding standard, named Versatile Video Coding (VVC). In the same month, a reference software codebase called VVC test model (VTM) was established to demonstrate the reference implementation of the VVC standard.

[0027] Like HEVC, VVC is built on a block-based hybrid video coding framework.

[0028] Figure 1 A general diagram of a block-based video encoder for VVC is shown. Specifically, Figure 1 A typical encoder 100 is shown. The encoder 100 has a video input 110, a motion compensation 112, a motion estimation 114, an intra / inter mode decision 116, a block predictor 140, an adder 128, a transformer 130, a quantizer 132, prediction-related information 142, an intra prediction 118, a picture buffer 120, an inverse quantizer 134, an inverse transformer 136, an adder 126, a memory 124, a loop filter 122, an entropy encoder 138, and a bitstream 144.

[0029] In the encoder 100, video frames are partitioned into a plurality of video blocks for processing. For each given video block, a prediction is formed based on either an inter prediction method or an intra prediction method.

[0030] The prediction residual, representing the difference between the current video block (part of video input 110) and its predictor (part of block predictor 140), is sent from adder 128 to transformer 130. The transform coefficients are then sent from transformer 130 to quantizer 132 for entropy reduction. The quantized coefficients are then fed to entropy encoder 138 to generate the compressed video bitstream. As Figure 1 As shown in FIG. 1, prediction-related information 142 (e.g., video block partition information, motion vectors (MVs), reference picture indices, and intra prediction modes) from intra / inter mode decision 116 is also fed through entropy encoder 138 and saved into the compressed bitstream 144. Compressed bitstream 144 comprises the video bitstream.

[0031] In encoder 100, circuitry related to the decoder is also needed in order to reconstruct the pixels for prediction. First, the prediction residual is reconstructed by inverse quantization 134 and inverse transformation 136. This reconstructed prediction residual is combined with block predictor 140 to generate the unfiltered reconstructed pixels of the current video block.

[0032] Spatial prediction (or "intra prediction") uses pixels of already coded neighboring blocks in the same video frame as the current video block (referred to as reference samples) to predict the current video block.

[0033] Temporal prediction (also referred to as "inter prediction") uses reconstructed pixels from already coded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in video signals. The temporal prediction signal for a given coding unit (CU) or coding block is typically signaled by one or more MVs that indicate the amount and direction of motion between the current CU and its temporal reference. Further, if multiple reference pictures are supported, an additional reference picture index is sent that identifies from which reference picture in the reference picture store the temporal prediction signal comes.

[0034] Motion estimation 114 receives video input 110 and a signal from picture buffer 120 and outputs a motion estimation signal to motion compensation 112. Motion compensation 112 receives video input 110, a signal from picture buffer 120, and a motion estimation signal from motion estimation 114 and outputs a motion compensation signal to intra / inter mode decision 116.

[0035] After performing spatial and / or temporal prediction, intra / inter mode decision 116 in the encoder 100 selects the best prediction mode, e.g., based on rate-distortion optimization methods. The block predictor 140 is then removed from the current video block, and the resulting prediction residual is de-correlated using a transformer 130 and quantization 132. The resulting quantized residual coefficients are inverse quantized by inverse quantization 134 and inverse transformed by inverse transform 136 to form a reconstructed residual, which is then added back to the predicted block to form a reconstructed signal for the CU. Further in-loop filtering 122 (e.g., a deblocking filter, sample adaptive offset (SAO), and / or adaptive loop filter (ALF)) can be applied to the reconstructed CU before it is placed into the reference picture store of the picture buffer 120 and used to code future video blocks. To form the output video bitstream 144, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy encoding unit 138 for further compression and packing to form the bitstream.

[0036] Figure 1 A block diagram of a general block-based hybrid video coding system is given. The input video signal is processed on a block-by-block basis, referred to as a coding unit (CU). In VTM-1.0, a CU can reach 128x128 pixels. However, unlike HEVC, which partitions a block based on a quad-tree only, in VVC, a coding tree unit (CTU) is split into CUs based on quad-tree / binary-tree / ternary-tree to adapt to different local features. In addition, the concept of multiple partition unit types in HEVC is removed, i.e., there is no longer a separation of CUs, prediction units (PUs), and transform units (TUs) in VVC; instead, each CU always serves as the basic unit for prediction and transform without further partitioning. In the multi-type tree structure, a CTU is first partitioned by a quad-tree structure. Then, each quad-tree leaf node can be further partitioned by binary and ternary tree structures.

[0037] As shown in Figure 3A , 3B , 3C, 3D, and 3E, there are five types of partitioning, quad partition, horizontal binary partition, vertical binary partition, horizontal ternary partition, and vertical ternary partition.

[0038] Figure 3A According to the present disclosure, a diagram is shown for depicting quad partitioning of a block in a multi-type tree structure.

[0039] Figure 3B According to the present disclosure, a diagram is shown for depicting vertical binary partitioning of a block in a multi-type tree structure.

[0040] Figure 3CAccording to this disclosure, a diagram is shown for depicting block-level binary partitioning in a multi-type tree structure.

[0041] Figure 3D According to this disclosure, a diagram is shown for depicting block vertical ternary partitioning in a multi-type tree structure.

[0042] Figure 3E According to this disclosure, a diagram is shown for depicting block-level ternary partitioning in multi-type tree structures.

[0043] exist Figure 1 In the encoder, spatial prediction and / or temporal prediction can be performed. Spatial prediction (or "intra-frame prediction") uses pixels from samples (called reference samples) of coded adjacent blocks in the same video picture / strip to predict the current video block. Spatial prediction reduces the spatial redundancy inherent in the video signal. Temporal prediction (also known as "inter-frame prediction" or "motion-compensated prediction") uses reconstructed pixels from coded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in the video signal. The temporal prediction signal for a given CU is typically signaled by one or more motion vectors (MVs) indicating the amount and direction of motion between the current CU and its temporal reference. Additionally, if multiple reference pictures are supported, a reference picture index is sent to identify which reference picture in the reference picture memory the temporal prediction signal originates from. After spatial and / or temporal prediction, a mode decision block in the encoder selects the optimal prediction mode (e.g., based on a rate-distortion optimization method). The prediction block is then subtracted from the current video block, and the prediction residual is decorrelated and quantized using a transform. The quantized residual coefficients undergo inverse quantization and inverse transform to form the reconstructed residuals, which are then added back to the prediction block to form the reconstructed CU signal. Further loop filtering (e.g., deblocking filter, Sample Adaptive Offset (SAO), and Adaptive Loop Filter (ALF)) can be applied to the reconstructed CU before it is stored in the reference image and used to encode future video blocks. To form the output video bitstream, the coding mode (inter-frame or intra-frame), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit for further compression and packing to form the bitstream.

[0044] Figure 2 A general block diagram of a video decoder for VVC is shown. Specifically, Figure 2 A typical block diagram of decoder 200 is shown. Decoder 200 has a bitstream 210, entropy decoding 212, inverse quantization 214, inverse transform 216, adder 218, intra / inter-frame mode selection 220, intra-frame prediction 222, memory 230, loop filter 228, motion compensation 224, image buffer 226, prediction-related information 234, and video output 232.

[0045] The decoder 200 is similar to the reconstruction related parts in the encoder 100. Figure 1 In the decoder 200, the input video bitstream 210 is first decoded by an entropy decoder 212 to derive quantized coefficient levels and prediction related information. The quantized coefficient levels are then processed by an inverse quantization 214 and an inverse transform 216 to obtain reconstructed prediction residuals. A block predictor mechanism implemented in an intra / inter mode selector 220 is configured to perform intra prediction 222 or motion compensation 224 based on the decoded prediction information. A set of unfiltered reconstructed pixels is obtained by adding the reconstructed prediction residuals from the inverse transform 216 to the prediction output generated by the block predictor mechanism using an adder 218.

[0046] The reconstructed blocks can be further passed through a loop filter 228 before being stored in a picture buffer 226 used for reference picture storage. The reconstructed video in the picture buffer 226 can be sent out to drive a display device, as well as for predicting future video blocks. In the case where the loop filter 228 is turned on, filtering operations are performed on these reconstructed pixels to derive the final reconstructed video output 232.

[0047] Figure 2 A general block diagram of a block-based video decoder is given. The video bitstream is first entropy decoded at an entropy decoding unit. The coding mode and prediction information are sent to a spatial prediction unit (if intra coded) or a temporal prediction unit (if inter coded) to form a prediction block. The residual transform coefficients are sent to an inverse quantization unit and an inverse transform unit to reconstruct a residual block. The prediction block and the residual block are then added together. The reconstructed block can be further passed through a loop filter before being stored in a reference picture store. The reconstructed video in the reference picture store is then sent out to drive a display device, as well as for predicting future video blocks.

[0048] In general, the basic intra prediction scheme applied in VVC is kept the same as in HEVC, except that several modules are further extended and / or improved, such as the matrix weighted intra prediction (MIP) coding mode, the intra sub-partition (ISP) coding mode, the extended intra prediction with wide-angle intra directions, the position dependent intra prediction combination (PDPC), and the 4-tap intra interpolation. The main focus of this disclosure is to improve the existing general constraint information design in the VVC standard. The relevant background knowledge is elaborated in the following sections.

[0049] As with HEVC, VVC uses a bitstream structure based on Network Abstraction Layer (NAL) units. The coded bitstream is partitioned into NAL units, which should be smaller than the maximum transport unit size when transmitted over a lossy packet network. Each NAL unit consists of a NAL unit header and a following NAL unit payload. There are two conceptual classes of NAL units. Video Coding Layer (VCL) NAL units contain coded sample data (e.g., coded slice NAL units), while non-VCL NAL units contain metadata that typically belongs to multiple coded pictures, or the association with a single coded picture would be meaningless (e.g., parameter set NAL units), or the information is not needed for the decoding process (e.g., SEI NAL units).

[0050] VVC inherits the parameter set concept from HEVC with some modifications and additions. Parameter sets can be part of the video bitstream or received by the decoder by other means (including out-of-band transmission using a reliable channel, hard-coded in the encoder and decoder, etc.). Parameter sets contain an identification that is directly or indirectly referenced from the slice header, which will be discussed in more detail later. The referencing process is called “activation”. Activation is done per picture or per sequence depending on the parameter set type. The concept of activation by reference is introduced, among other reasons, because in the case of out-of-band transmission, implicit activation by the location of the information in the bitstream (as with other syntax elements of the video codec) is not available.

[0051] Video Parameter Set (VPS) is introduced to convey information applicable to multiple layers and sub-layers. VPS is introduced to address these shortcomings and to enable a clean and scalable high-level design of multi-layer codecs. Each layer of a given video sequence refers to the same VPS, regardless of whether they have the same or different Sequence Parameter Sets (SPS).

[0052] In VVC, SPS contains information applicable to all slices of a coded video sequence. A coded video sequence starts with an Instantaneous Decoding Refresh (IDR) picture or a BLA picture or a CRA picture that is the first picture in the bitstream and includes all subsequent pictures that are not IDR or BLA pictures. A bitstream consists of one or more coded video sequences. The content of SPS can be roughly subdivided into six categories: 1) self-reference (its own ID); 2) decoder operating point related information (profile, level, picture size, number of sub-layers, etc.); 3) flags to enable certain tools in the profile and, if a tool is enabled, related coding tool parameters; 4) information to limit the structure flexibility and transform coefficient coding; 5) temporal scalability control; and 6) visual usability information (VUI) that includes HRD information.

[0053] For decoder operation point related information in SPS, there is a list of constraint flags indicating properties that cannot be violated throughout the bitstream. These constraint flags are encapsulated into their own syntax structure general_constraint_info(). The syntax and related semantics of general constraint information in current VVC draft specification are specified in Table 1 and Table 2, respectively.

[0054] Table 1. General constraint information semantics

[0055]

[0056]

[0057]

[0058] Table 2. General constraint information semantics

[0059]

[0060]

[0061]

[0062]

[0063]

[0064] The picture parameter set (PPS) of VVC contains information that can change between pictures. The information contained in PPS is roughly comparable to a part of PPS in HEVC, which includes: 1) self-reference; 2) initial picture control information, such as initial quantization parameter (QP), multiple flags indicating the usage or existence of certain tools or control information in slice header; and 3) tile information.

[0065] The slice header contains information that can change between slices, as well as such picture-related information that is relatively small or only related to a specific slice or picture type. The size of slice header can be significantly larger than PPS, especially when tile or wavefront entry point offset is present in slice header and RPS, explicitly signaling prediction weights or reference picture list modification.

[0066] Improvements on general constraint information

[0067] In current VVC, no_sbt_constraint_flag is signaled in general constraint information without any constraint. However, the feature controlled by flag no_sbt_constraint_flag only applies to the case that the slice is inter slice. Therefore, the value of no_sbt_constraint_flag shall be equal to 1 when the slice is intra slice.

[0068] Similarly, no_act_constraint_flag and no_chroma_qp_offset_constraint_flag are signaled in general constraint information without any constraint. However, the features controlled by flags no_act_constraint_flag and no_chroma_qp_offset_constraint_flag only apply to the case that the chroma format is not monochrome. Therefore, the values of these two flags shall be equal to 1 when the chroma format is monochrome.

[0069] Similarly, in another example, no_mixed_nalu_types_in_pic_constraint_flag is signaled in general constraint information without any constraint. However, the feature controlled by flag no_mixed_nalu_types_in_pic_constraint_flag only applies to the case that the picture has at least two subpictures. Therefore, the value of no_mixed_nalu_types_in_pic_constraint_flag shall be equal to 1 when the picture has one subpicture.

[0070] Similarly, in another example, no_prof_constraint_flag is signaled in general constraint information without any constraint. However, the feature controlled by flag no_prof_constraint_flag only applies to the case that the affine mode is enabled. Therefore, the value of no_prof_constraint_flag shall be equal to 1 when the affine mode is disabled.

[0071] Similarly, in another example, no_bdpcm_constraint_flag is signaled in general constraint information without any constraint. However, the feature controlled by flag no_bdpcm_constraint_flag only applies to the case that the transform skip mode is enabled. Therefore, the value of no_bdpcm_constraint_flag shall be equal to 1 when the transform skip mode is disabled.

[0072] It should also be observed that in the current VVC, several coding tools are missing in the general constraint information syntax. These coding tool flags should be added to provide the same general constraint control as other tools.

[0073] Proposed method

[0074] In the present disclosure, in order to solve the problems as pointed out in the “Problem Statement” section, methods are provided to simplify and / or further improve the existing design of high-level syntax. It is worth noting that the methods of the present disclosure can be applied individually or jointly.

[0075] Since the feature controlled by the flag no_sbt_constraint_flag only applies to the case that the slice is inter-switch, according to the method of the present disclosure, it is proposed to add a constraint that the value of no_sbt_constraint_flag must be equal to 1 when the slice is an intra slice. The decoding process example of VVC draft is shown in Table 3 below. The changes of VVC draft are shown in bold and italic.

[0076] Table 3. Proposed flag

[0077]

[0078] Figure 4 A method for decoding a video signal according to the present disclosure is shown. For example, the method can be applied to a decoder.

[0079] At step 410, the decoder can receive at least one constraint flag. The at least one constraint flag indicates whether the slice is an intra slice.

[0080] At step 412, the decoder can obtain a first reference picture I (0) and a second reference picture I (1) associated with a video block in the bitstream. In display order, the first reference picture I (0) may precede the current picture, and the second reference picture I (1) may follow the current picture.

[0081] At step 414, the decoder can obtain a first prediction sample I (0) (i,j) of the video block from a reference block in the first reference picture I (0) . i and j represent the coordinates of a sample with the current picture.

[0082] At step 416, the decoder can obtain a second prediction sample I (1) (i,j) of the video block from a reference block in the second reference picture I (1) .

[0083] In step 418, the decoder can determine the bi-predicted samples based on the at least one constraint flag, the first prediction samples I (0) (i,j) and the second prediction samples I (1) (i,j).

[0084] Since the features controlled by the flags no_act_constraint_flag and no_chroma_qp_offset_constraint_flag only apply when the chroma format is not monochrome, according to the method of the present disclosure, it is proposed to add the following constraint: when the chroma format is monochrome, the values of the two flags must be equal to 1. An example of the decoding process of the VVC draft is shown in Table 4 below. Changes to the VVC draft are shown in bold and italic.

[0085] Table 4. Proposed flags

[0086]

[0087] Figure 5 A method for decoding a video signal according to the present disclosure is shown. For example, the method can be applied to a decoder.

[0088] In step 510, the decoder can determine that the no_act_constraint_flag flag is equal to 1 in response to determining that the max_chroma_format_constraint_idc value is equal to 0.

[0089] In step 512, the decoder can determine that the no_chroma_qp_offset_constraint_flag flag is equal to 1 in response to determining that the max_chroma_format_constraint_idc value is equal to 0.

[0090] Another example of the decoding process on the VVC draft is illustrated in Table 5 below. Changes to the VVC draft are shown in bold and italic.

[0091] Table 5. Proposed flags

[0092]

[0093] Since the feature controlled by the flag no_mixed_nalu_types_in_pic_constraint_flag only applies when a picture has at least two sub-pictures, according to the method of the present disclosure, it is proposed to add the following constraint: when a picture has one sub-picture, the value of no_mixed_nalu_types_in_pic_constraint_flag must be equal to 1. The decoding process example of VVC draft is shown in Table 6 below. Changes to VVC draft are shown in bold and italic.

[0094] Table 6. Proposed flag

[0095]

[0096] Since the feature controlled by the flag no_prof_constraint_flag only applies when affine mode is enabled, according to the method of the present disclosure, it is proposed to add the following constraint: when affine mode is disabled, the value of no_prof_constraint_flag must be equal to 1. The decoding process example of VVC draft is shown in Table 7 below. Changes to VVC draft are shown in bold and italic.

[0097] Table 7. Proposed flag

[0098]

[0099] Since the feature controlled by the flag no_bdpcm_constraint_flag only applies when transform skip mode is enabled, according to the method of the present disclosure, it is proposed to add the following constraint: when transform skip mode is disabled, the value of no_bdpcm_constraint_flag must be equal to 1. The decoding process example of VVC draft is shown in Table 8 below. Changes to VVC draft are shown in bold and italic.

[0100] Table 8. Proposed flag

[0101]

[0102] Several coding tools are missing in the general constraint information syntax. These coding tool flags should be added to provide the same general constraint control as other tools.

[0103] In current VVC, sps conformance window flag equal to 1 indicates the following conformance clipping window offset parameters in SPS. According to the present disclosure, it is proposed to add a flag no_conformance_window_constraint_flag for the clipping function in general constraint information syntax to provide the same general constraint control as other tools. The decoding process example of VVC draft is shown in Table 9 and 10 below. The changes to VVC draft are shown in bold and italic.

[0104] Table 9. Proposed flag

[0105]

[0106] Table 10. Proposed flag

[0107]

[0108] In current VVC, sps_weighted_pred_flag equal to 1 specifies that weighted prediction can be applied to P slices referring to this SPS. sps_weighted_pred_flag equal to 0 specifies that weighted prediction is not applied to P slices referring to this SPS. According to the present disclosure, it is proposed to add a syntax element no_weighted_pred_constraint_flag in general constraint information syntax to provide the same general constraint control as other syntax. The decoding process example of VVC draft is illustrated in Table 11 and Table 12 below. The changes to VVC draft are shown in bold and italic. In addition, given that weighted prediction is only applicable when inter coding tools are allowed to be used. Therefore, it is proposed to add a bitstream conformance constraint that the value of no_weighted_pred_constrant_flag shall be equal to 1 when only intra coding is allowed to be used to code the sequence.

[0109] Table 11. Proposed flag

[0110]

[0111] Table 12. Proposed flag

[0112]

[0113] In current VVC, sps_weighted_bipred_flag equal to 1 specifies that explicit weighted prediction can be applied to B slices referring to this SPS. sps_weighted_bipred_flag equal to 0 specifies that explicit weighted prediction is not applied to B slices referring to this SPS. According to the present disclosure, it is proposed to add a syntax element no_weighted_bipred_constraint_flag in general constraint information syntax to provide the same general constraint control as other syntaxes. The decoding process example of VVC draft is illustrated in Table 13 and Table 14 below. The changes to VVC draft are shown in bold and italic. In addition, it is proposed to add a bitstream conformance constraint: when only intra coding is allowed to code a sequence, the value of no_weight_bipred_constraint_flag shall be equal to 1.

[0114] Table 13. Proposed flag

[0115]

[0116] Table 14. Proposed flag

[0117]

[0118] In current VVC, sps_virtual_boundaries_enabled_flag equal to 1 specifies that disabling in-loop filtering across virtual boundaries is enabled and can be applied to coded pictures in a CLVS. sps_virtual_boundaries_enabled_flag equal to 0 specifies that disabling in-loop filtering across virtual boundaries is disabled and not applied to coded pictures in a CLVS. In-loop filtering operations include the deblocking filter, the sample adaptive offset filter, and the adaptive loop filter operations. According to the present disclosure, it is proposed to add a syntax element no_virtual_boundaries_constraint_flag in general constraint information syntax to provide the same general constraint control as other syntaxes. The decoding process example of VVC draft is shown in Table 6 below. The changes to VVC draft are shown in bold and italic.

[0119] Table 15. Proposed flag

[0120]

[0121] Table 16. Proposed flag

[0122]

[0123] In the current VVC draft, there are two flags signaled in the general constraint information syntax table, i.e., no_ref_pic_resampling_constraint_flag and no_res_change_in_clvs_constraint_flag. The first flag indicates whether the reference picture resampling function is allowed in the coded sequence, while the second flag indicates whether the resolution of pictures in the coded sequence is allowed to be adjusted. Given that the resolution of pictures can be different from each other only when the reference picture resampling is enabled, it is suggested to add a bitstream conformance constraint that when the value of no_ref_pic_resampling_constraint_flag is equal to 1, the value of no_res_change_in_clvs_constraint_flag should be equal to 1, as follows. Meanwhile, given that the reference picture resampling is an inter coding function, it cannot be applied when only intra coding is allowed. Therefore, another bitstream conformance constraint is added that to restrict the value of no_ref_pic_resampling_constraint_flag should be equal to 1 in the case that only intra coding tools are allowed to be used.

[0124] no_ref_pic_resampling_constraint_flag equal to 1 specifies that sps_ref_pic_resampling_enabled_flag shall be equal to 0. no_ref_pic_resampling_constraint_flag equal to 0 does not impose this constraint. When intra only constraint flag is equal to 1, the value of no_ref_pic_resampling_constraint_flag shall be equal to 1.

[0125] no_res_change_in_clvs_constraint_flag equal to 1 specifies that sps_res_change_in_clvs_allowed_flag shall be equal to 0. no_res_change_in_clvs_constraint_flag equal to 0 does not impose this constraint. When the value of no_ref_pic_resampling_constraint_flag is equal to 1, the value of no_res_change_in_clvs_constraint_flag shall be equal to 1.

[0126] Figure 6 A method for decoding a video signal is shown in accordance with the present disclosure. For example, the method can be applied to a decoder.

[0127] In step 610, the decoder can receive a bitstream including a VPS, an SPS, a PPS, a picture header, and a slice header for encoding video data.

[0128] In step 612, the decoder can decode the VPS.

[0129] In step 614, the decoder can decode the SPS, and can decode general constraint information in the SPS.

[0130] In step 616, the decoder can decode the PPS.

[0131] In step 618, the decoder can decode the picture header.

[0132] In step 620, the decoder can decode the slice header.

[0133] In step 622, the decoder can decode the video data based on the VPS, the SPS, the PPS, the picture header, and the slice header.

[0134] The above-described methods can be implemented using an apparatus including one or more circuits such as application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements. The apparatus can use circuits in combination with other hardware or software components to perform the above-described methods. Each of the modules, sub-modules, units, or sub-units disclosed above can be implemented at least partially using one or more circuits.

[0135] Figure 7 A computing environment 710 coupled with a user interface 760 is shown. The computing environment 710 can be part of a data processing server. The computing environment 710 includes a processor 720, a memory 740, and an I / O interface 750.

[0136] The processor 720 generally controls the overall operation of the computing environment 710, such as operations associated with displays, data acquisition, data communication, and image processing. The processor 720 can include one or more processors to execute instructions to perform all or some of the steps in the above-described methods. In addition, the processor 720 can include one or more modules that facilitate the interaction between the processor 720 and other components. The processor can be a central processing unit (CPU), a microprocessor, a microcontroller, a GPU, or the like.

[0137] Memory 740 is configured to store various types of data to support operation of computing environment 710. Memory 740 can include predetermined software 742. Examples of such data include instructions for any applications or methods for operating on computing environment 710, video data sets, image data, and the like. Memory 740 can be implemented by using any type of volatile or non-volatile storage devices or a combination thereof (e.g., static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic storage, flash memory, magnetic or optical disks).

[0138] I / O interface 750 provides an interface between processor 720 and peripheral interface modules (e.g., a keyboard, a click wheel, buttons, etc.). The buttons can include, but are not limited to, a home button, a start scanning button, and a stop scanning button. I / O interface 750 can be coupled with encoders and decoders.

[0139] In some embodiments, a non-transitory computer readable storage medium is also provided, including a plurality of programs (e.g., included in memory 740) executable by processor 720 in computing environment 710 for performing the methods described above. For example, the non-transitory computer readable storage medium can be a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disc, an optical data storage device, etc.

[0140] A non-transitory computer readable storage medium has stored therein a plurality of programs for execution by a computing device having one or more processors, wherein, when the plurality of programs are executed by the one or more processors, cause the computing device to perform the motion prediction method described above.

[0141] In some embodiments, computing environment 710 can be implemented using one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), graphics processing units (GPUs), controllers, micro-controllers, microprocessors, or other electronic components, either alone or in any combination, to perform the methods described above.

[0142] Other examples of the disclosure will be apparent to those of ordinary skill in the art having the benefit of this description and the teachings herein. The application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice in the art to which the application pertains. The teachings of the specification and the examples herein provided are to be construed as exemplary only.

[0143] It should be understood that the present disclosure is not limited to the exact examples described and shown in the drawings, and that various modifications and changes can be made without departing from the scope of protection.

Claims

1. A method for decoding a video signal, comprising: The decoder receives constraint flags, wherein at least one of the constraint flags indicates whether a stripe is an intra-frame stripe, and wherein the constraint flags further include a no_weighted_pred_constraint_flag flag to indicate whether the sps_weighted_pred_flag flag should be equal to 0, the sps_weighted_pred_flag flag indicating that weighted prediction should not be applied to the P-stripes of the reference sequence parameter set SPS by being equal to 0 and indicating that weighted prediction should be applied to the P-stripes of the reference SPS by being equal to 1; and At the decoder, the video signal is decoded based on at least one constraint flag and the no_weighted_pred_constraint_flag flag.

2. The method according to claim 1, wherein, The at least one constraint flag is the intra_only_constraint_flag flag.

3. The method according to claim 1, wherein, The constraint flags include the no_virtual_boundaries_constraint_flag flag, which indicates whether the operation of disabling loop filtering across virtual boundaries is disabled in the coding layer video sequence (CLVS).

4. The method according to claim 3, further comprising: In response to determining that the no_virtual_boundaries_constraint_flag flag is equal to 1, the sps_virtual_boundaries_enabled_flag flag is determined to be equal to 0.

5. The method according to claim 1, wherein, The constraint flags include: The `no_ref_pic_resampling_constraint_flag` flag indicates whether reference image resampling is allowed in the encoded sequence, and The no_res_change_in_clvs_constraint_flag flag is used to indicate whether adjusting the resolution of images in the encoded sequence is allowed.

6. A computing device, comprising: One or more processors; and A non-transitory computer-readable storage medium storing instructions executable by the one or more processors, wherein the one or more processors are configured to: Receive constraint flags, wherein at least one of the constraint flags indicates whether a stripe is an intra-frame stripe, and wherein the constraint flags further include a no_weighted_pred_constraint_flag flag to indicate whether the sps_weighted_pred_flag flag should be equal to 0, the sps_weighted_pred_flag flag indicating that weighted prediction should not be applied to the P-stripes of the reference sequence parameter set SPS by being equal to 0 and indicating that weighted prediction should be applied to the P-stripes of the reference SPS by being equal to 1; and The video signal is decoded based on at least one of the constraint flags and the no_weighted_pred_constraint_flag flag.

7. The computing device according to claim 6, wherein, The at least one constraint flag is the intra_only_constraint_flag flag.

8. The computing device according to claim 6, wherein, The constraint flags include the no_virtual_boundaries_constraint_flag flag, which indicates whether the operation of disabling loop filtering across virtual boundaries is disabled in the coding layer video sequence (CLVS).

9. The computing device according to claim 8, wherein, The one or more processors are further configured to: In response to determining that the no_virtual_boundaries_constraint_flag flag is equal to 1, the sps_virtual_boundaries_enabled_flag flag is determined to be equal to 0.

10. The computing device according to claim 6, wherein, The constraint flags include: The `no_ref_pic_resampling_constraint_flag` flag indicates whether reference image resampling is allowed in the encoded sequence, and The no_res_change_in_clvs_constraint_flag flag is used to indicate whether adjusting the resolution of images in the encoded sequence is allowed.

11. A non-transitory computer-readable storage medium storing a plurality of programs executable by a computing device having one or more processors, wherein when the plurality of programs are executed by the one or more processors, the computing device performs an action including: The decoder receives constraint flags, wherein at least one of the constraint flags indicates whether a stripe is an intra-frame stripe, and wherein the constraint flags further include a no_weighted_pred_constraint_flag flag to indicate whether the sps_weighted_pred_flag flag should be equal to 0, the sps_weighted_pred_flag flag indicating that weighted prediction should not be applied to the P-stripes of the reference sequence parameter set SPS by being equal to 0 and indicating that weighted prediction should be applied to the P-stripes of the reference SPS by being equal to 1; and At the decoder, the video signal is decoded based on at least one constraint flag and the no_weighted_pred_constraint_flag flag.

12. The non-transitory computer-readable storage medium according to claim 11, wherein, The at least one constraint flag is the intra_only_constraint_flag flag.

13. The non-transitory computer-readable storage medium according to claim 11, wherein, The constraint flags include the no_virtual_boundaries_constraint_flag flag, which indicates whether the operation of disabling loop filtering across virtual boundaries is disabled in the coding layer video sequence (CLVS).

14. The non-transitory computer-readable storage medium according to claim 13, wherein, The plurality of programs further cause the computing device to perform the following operations: In response to determining that the no_virtual_boundaries_constraint_flag flag is equal to 1, the sps_virtual_boundaries_enabled_flag flag is determined to be equal to 0.

15. The non-transitory computer-readable storage medium according to claim 11, wherein, The constraint flags include: The `no_ref_pic_resampling_constraint_flag` flag indicates whether reference image resampling is allowed in the encoded sequence, and The no_res_change_in_clvs_constraint_flag flag is used to indicate whether adjusting the resolution of images in the encoded sequence is allowed.

16. A computer program product comprising computer instructions, wherein, When executed by one or more processors, the computer instructions cause the one or more processors to perform any of the methods according to claims 1 to 5.

Images