Op-amp test system pin identification self-learning method

Abstract

This invention provides a self-learning method for pin identification in an operational amplifier (op-amp) test system. The method includes selecting one pin of a test chip as the current test pin and the remaining pins as pins under test; inputting a first test command; when the output voltage meets a first condition, marking the pin with the lowest reference potential and the unknown pin; inputting a second test command; when the output voltage meets a second condition, marking the power supply pin and the unknown pin; eliminating pins based on the pin arrangement constraints of the test chip to obtain the operational amplifier functional pins; shorting two of these pins; inputting a sine wave signal to the remaining pins; when the waveform amplitude and phase are the same, defining the input and output terminals; and then performing a reverse 1x amplification test to obtain the corresponding positions of the non-inverting and inverting input terminals. This invention can automatically identify the functional configuration definitions of each pin of the test chip through logical judgment.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically to a self-learning method for pin identification in operational amplifier testing systems. Background Technology

[0002] With the rapid development of automation control, the functions of control chips are becoming increasingly complex and diverse, with the chips themselves implementing numerous complex functions. Externally, these functions are primarily achieved through pin multiplexing, a time-division multiplexing approach. Both chip functions and the multiplexing of external pins are becoming increasingly complex.

[0003] Chip testing methods lag significantly behind chip development. This means that after chip manufacturing is completed, time is needed to design new testing methods that are compatible with it, which indirectly increases the testing cost of chips. Summary of the Invention

[0004] In view of this, the problem to be solved by the present invention is to provide a self-learning method for pin identification in operational amplifier test systems.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a self-learning method for pin identification in an operational amplifier test system, comprising the following steps:

[0006] S1: Each pin of the test chip has a corresponding PIN number. Select one pin of the test chip as the current test pin and the remaining pins as the pins to be tested. Input the first test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the first judgment condition. If it does, mark the current test pin as the lowest reference potential pin and mark the pin to be tested as an unknown pin; otherwise, change the current test pin and repeat the step to execute S2.

[0007] S2: Select one unknown pin as the current test pin, and the remaining unknown pins as the pins to be tested. Input the second test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the second judgment condition. If yes, mark the current test pin as a power supply pin and the pin to be tested as an unknown pin; otherwise, change the current test pin and repeat the step, then execute S3:

[0008] S3: Obtain the PIN number of the lowest reference potential pin, power supply pin, and unknown pin, and obtain the investigation number according to the pin layout constraints of the test chip. Remove the pin corresponding to the investigation number from the unknown pins, and record the remaining pins as operational amplifier function pins.

[0009] S4: Short-circuit the two operational amplifier function pins, input a sine wave signal to the remaining operational amplifier function pins, and when the waveform amplitudes and phases of the two operational amplifier pins are the same, define the two operational amplifier pins as input terminals and the remaining operational amplifier function pins as output terminals. Then perform a reverse 1x amplification test to obtain the corresponding positions of the non-inverting input terminal and the inverting input terminal.

[0010] In this invention, preferably, the first test command is set to ground the external test pin, keep the pin under test in an open circuit state, and input a 100μA positive current to the test pin.

[0011] In this invention, preferably, the first determination condition is that the output voltage of the current pin under test to the test pin is the same, and the output voltage is 0.7V or 0.4V.

[0012] In this invention, preferably, the second test command grounds the lowest reference potential pin externally, keeps the unknown pin in an open circuit state, shorts the current test pin with the lowest reference potential pin, and inputs a 100μA negative current to the test pin.

[0013] In this invention, preferably, the second determination condition is that the output voltage of the current pin under test to the test pin is the same, and the output voltage is 0.7V or 0.4V.

[0014] In this invention, preferably, the reverse 1x amplification test process specifically involves grounding one pin of the operational amplifier's functional pin and connecting the other pin of the operational amplifier's functional pin to an external matching resistor 1x amplification test system. When the waveform at the output terminal has the same amplitude but opposite phase to the waveform at the input terminal, one pin of the operational amplifier's functional pin is defined as the non-inverting input terminal, and the other pin of the operational amplifier's functional pin is defined as the inverting input terminal.

[0015] The advantages and positive effects of this invention are as follows: Since the peripheral configuration resources of each pin of the test chip of this invention are completely identical, it can be compatible with all chip configurations. There is no need to consider the arrangement order of the chip pins. By sending test instructions to the test chip through the host computer, the lowest reference potential pin is first found through logical judgment. Then, the power supply pin is found based on the lowest reference potential pin. Finally, the pin function attributes of the positive and negative input terminals and the output terminal of the op-amp are determined. This allows the automatic identification of the function of each pin of the test chip and the assignment of the corresponding pin function configuration definition. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0017] Figure 1 This is a flowchart illustrating the pin identification self-learning method for the operational amplifier test system of the present invention.

[0018] Figure 2 This is a pin diagram of the 8-pin test chip for the pin identification self-learning method of the operational amplifier test system of the present invention;

[0019] Figure 3 This is a pin diagram of the 14-pin test chip for the pin identification self-learning method of the operational amplifier test system of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that when a component is described as "fixed to" another component, it can be directly on the other component or may have a component in between. When a component is considered "connected to" another component, it can be directly connected to the other component or may have a component in between. When a component is considered "set on" another component, it can be directly set on the other component or may have a component in between. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] like Figure 1 As shown, the present invention provides a self-learning method for pin identification in an operational amplifier test system, comprising the following steps:

[0024] S1: Each pin of the test chip has a corresponding PIN number. Select one pin of the test chip as the current test pin and the remaining pins as the pins to be tested. Input the first test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the first judgment condition. If it does, mark the current test pin as the lowest reference potential pin and mark the pin to be tested as an unknown pin; otherwise, change the current test pin and repeat the step to execute S2.

[0025] S2: Select one unknown pin as the current test pin, and the remaining unknown pins as the pins to be tested. Input the second test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the second judgment condition. If yes, mark the current test pin as a power supply pin and the pin to be tested as an unknown pin; otherwise, change the current test pin and repeat the step, then execute S3:

[0026] S3: Obtain the PIN number of the lowest reference potential pin, power supply pin, and unknown pin, and obtain the investigation number according to the pin layout constraints of the test chip. Remove the pin corresponding to the investigation number from the unknown pins, and record the remaining pins as operational amplifier function pins.

[0027] S4: Short-circuit the two operational amplifier function pins, input a sine wave signal to the remaining operational amplifier function pins, and when the waveform amplitudes and phases of the two operational amplifier pins are the same, define the two operational amplifier pins as input terminals and the remaining operational amplifier function pins as output terminals. Then perform a reverse 1x amplification test to obtain the corresponding positions of the non-inverting input terminal and the inverting input terminal.

[0028] In this embodiment, the first test command is further configured to ground the external test pin, keep the pin under test in an open circuit state, and input a 100μA positive current to the test pin.

[0029] In this embodiment, the first determination condition is that the output voltage of the current pin under test to the test pin is the same, and the output voltage is 0.7V or 0.4V.

[0030] In this embodiment, the second test command further grounds the lowest reference potential pin externally, keeps the unknown pin in an open circuit state, shorts the current test pin with the lowest reference potential pin, and inputs a 100μA negative current to the test pin.

[0031] In this embodiment, the second determination condition is that the output voltage of the current pin under test to the test pin is the same, and the output voltage is 0.7V or 0.4V.

[0032] In this embodiment, the reverse 1x amplification test process is further defined as follows: one pin of the operational amplifier's functional pin is grounded, and the other pin of the operational amplifier's functional pin is connected to an external matching resistor in the 1x amplification test system. When the waveform at the output terminal has the same amplitude but opposite phase to the waveform at the input terminal, one pin of the operational amplifier's functional pin is defined as the non-inverting input terminal, and the other pin of the operational amplifier's functional pin is defined as the inverting input terminal.

[0033] The working principle and process of this invention are as follows: During testing, a host computer pre-selects one pin from the various pins of the test chip as the current test pin, and the remaining pins are the pins to be tested. A first test command is input to the test chip. Specifically, the first test command is to ground the current test pin externally, keep the pin to be tested in an open circuit state, input a 100μA positive current to the current test pin, test and save the output voltage, and determine whether the output voltage meets the first judgment condition. Specifically, the first judgment condition is that the output voltage of the pin to be tested to the test pin is the same, and the output voltage is 0.7V or 0.4V. The current test pin that meets the first judgment condition is marked as the lowest reference potential pin, specifically marked as GND or VEE. The current pin to be tested is marked as an unknown pin. Through data analysis, based on the anti-static design of the test chip, each functional pin has a pull-down Schottky protection diode. Each diode is connected to the GND pin of the test chip or the relative lowest reference pin. Therefore, based on this characteristic, only one pin will have the same output voltage of approximately 0.7V or 0.4V to all other pins. This indicates that the pin number corresponding to this pin is either the GND pin or the VEE pin.

[0034] Figure 3 The diagram illustrates the pinout of a 14-pin chip. After identifying the lowest reference potential pin, one of the unknown pins is selected as the new current test pin, and the remaining unknown pins are designated as the pins under test. A second test command is input to the test chip. This command grounds the lowest reference potential pin externally, keeping the unknown pins open. The current test pin is then shorted to the lowest reference potential pin, and a 100μA negative current is input to it. The output voltage is tested and saved. The second condition is whether the output voltage of the pin under test is the same as that of the current test pin (0.7V or 0.4V). If so, the current test pin is marked as a power supply pin, and the pin under test is marked as an unknown pin. Otherwise, the current test pin is replaced, and the process is repeated to identify the power supply pin in the test chip. Data analysis reveals that, based on the chip's electrostatic discharge (ESD) protection design, each functional pin contains a pull-up Schottky diode. Each diode is connected to the chip's VCC pin. Therefore, based on this characteristic, if there is only one PIN pin, all PIN pins will have the same output voltage of about 0.7V or 0.4V to it. This can be used to determine that this PIN pin is the VCC pin.

[0035] Next, the remaining operational amplifier's functional pins, such as the non-inverting input VIN+, inverting input VIN-, and outputs VOUT and VG, are identified by obtaining and using the pin numbers of the lowest reference potential pin, power supply pin, and unknown pins. Based on the pin layout constraints of the test chip, a check number is obtained. The pin corresponding to the check number is then removed from the unknown pins, and the remaining pins are recorded as operational amplifier functional pins. For example... Figure 2 As shown, the pin arrangement constraint of the test chip is that VG+ / VG- must be placed on the corresponding end of the test chip, such as PIN number 1 and PIN number 8, or PIN number 4 and PIN number 5. If VEE or VCC has already occupied any of the PIN pins, then VG+ / VG- should be on the other side. After this check, the operational amplifier only has the non-inverting input terminal VIN+, the inverting input terminal VIN-, and the output terminal VOUT, which are denoted as the operational amplifier functional pins.

[0036] Utilizing the follower and inverting amplification principles of operational amplifiers, follower circuits are built using external configurations. Two operational amplifier pins are shorted, and a sine wave is input to the remaining operational amplifier pins. When the waveform amplitudes and phases of the two operational amplifier pins are the same, these two pins are defined as input terminals, and the remaining operational amplifier pins are defined as output terminals. However, the definitions of the non-inverting input VIN+ and the inverting input VIN- may not be accurate. Therefore, a one-fold inverting amplification test is performed to verify the corresponding positions of the non-inverting and inverting input terminals. Specifically, the reverse 1x amplification test process involves grounding one input pin of the operational amplifier's functional pin and connecting the other input pin to an external matching resistor in the 1x amplification test system. When the output waveform has the same amplitude but opposite phase to the input waveform, one input pin of the operational amplifier's functional pin is defined as the non-inverting input, and the other input pin as the inverting input. This allows for the determination of the correct positions of the non-inverting input VIN+, the inverting input VIN-, and the output VOUT. This enables the system to send test commands from the host computer to the test chip, perform logical judgments to first locate the lowest reference potential pin, then locate the power supply pin based on the lowest reference potential pin, and finally determine the pin functions of the two inputs and the output of the operational amplifier. This allows for the automatic identification of the function of each pin of the test chip and the assignment of corresponding pin function configurations. The peripheral configuration resources of each pin of the test chip in this invention are completely identical, thus ensuring compatibility with all chip configurations without considering the pin arrangement order.

[0037] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A self-learning method for pin identification in an operational amplifier testing system, characterized in that, Includes the following steps: S1: Each pin of the test chip has a corresponding PIN number. Select one pin of the test chip as the current test pin and the other pins as the current pins to be tested. Input the first test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the first judgment condition. If it does, mark the current test pin as the lowest reference potential pin and mark the current pin to be tested as an unknown pin. Otherwise, change the current test pin and repeat the step, then execute S2; S2: Select one unknown pin as the current test pin, and the remaining unknown pins as the pins to be tested. Input the second test command to the test chip, test and save its output voltage, and determine whether the output voltage meets the second judgment condition. If yes, mark the current test pin as a power supply pin and the pin to be tested as an unknown pin; otherwise, change the current test pin and repeat the step, then execute S3: S3: Obtain the PIN number of the lowest reference potential pin, power supply pin, and unknown pin, and obtain the investigation number according to the pin layout constraints of the test chip. Remove the pin corresponding to the investigation number from the unknown pins, and record the remaining pins as operational amplifier function pins. S4: Short-circuit the two operational amplifier function pins, input a sine wave signal to the remaining operational amplifier function pins, and when the waveform amplitude and phase of the two operational amplifier pins are the same, define the two operational amplifier pins as input terminals and the remaining operational amplifier function pins as output terminals. Then perform a reverse 1x amplification test to obtain the corresponding positions of the non-inverting input terminal and the inverting input terminal. The reverse 1x amplification test process specifically involves grounding one pin of the operational amplifier's functional pin and connecting the other pin of the operational amplifier's functional pin to an external matching resistor in a 1x amplification test system. When the output waveform has the same amplitude but opposite phase to the input waveform, one pin of the operational amplifier's functional pin is defined as the non-inverting input, and the other pin of the operational amplifier's functional pin is defined as the inverting input.

2. The self-learning method for pin identification in an operational amplifier test system according to claim 1, characterized in that, The first test command is set to ground the current test pin externally, keep the current pin under test in an open circuit state, and input a 100μA positive current to the current test pin.

3. The self-learning method for pin identification in an operational amplifier test system according to claim 1, characterized in that, The first criterion is that the output voltage of the pin under test to the test pin is the same, and the output voltage is 0.7V or 0.4V.

4. The self-learning method for pin identification in an operational amplifier test system according to claim 1, characterized in that, The second test command grounds the lowest reference potential pin externally, keeps the unknown pin in an open circuit state, shorts the current test pin with the lowest reference potential pin, and inputs a 100μA negative current to the current test pin.

5. The self-learning method for pin identification in an operational amplifier test system according to claim 1, characterized in that, The second criterion is that the output voltage of the current pin under test to the current test pin is the same, and the output voltage is 0.7V or 0.4V.

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