Systems, methods, and apparatus for utilization-aware memory allocation

Abstract

A method can include receiving, from a process, a memory allocation request for a memory system, the memory system including a first channel having a first channel utilization and a second channel having a second channel utilization; selecting the first channel based on the first channel utilization and the second channel utilization; and allocating a memory page from the first channel to the process. The selecting can include selecting the first channel based on a balanced random policy. The selecting can include generating a ticket based on a random number and a total number of free pages, comparing the ticket to a number of free pages of the first channel, and selecting the first channel based on the comparison. The selecting can include selecting the first channel based on a least used channel policy.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 221,468, filed on July 13, 2021, entitled “Systems, Methods, and Apparatus for Flash Core and Channel Aware Memory Allocator,” which is incorporated by reference. Technical Field

[0003] The present disclosure relates generally to memory systems and, more particularly, to systems, methods, and devices for utilization-aware memory allocation. Background Art

[0004] A memory allocation scheme may allocate one or more pages of device attached memory to a process, such as a program, application, service, etc., in response to an allocation request from the process. The process may specify an amount of memory to be allocated and one or more devices from which the memory may be allocated. The memory allocation scheme may select the one or more pages of memory from the specified devices based on the amount of memory requested in the allocation request.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0006] A method for memory allocation may include receiving a memory allocation request from a process for a memory system, the memory system including a first channel having a first channel utilization and a second channel having a second channel utilization; selecting the first channel based on the first channel utilization and the second channel utilization; and allocating memory pages from the first channel to the process. The selection may include selecting the first channel based on a balanced random policy. The selection may include generating a ticket based on a random number and a number of free pages, comparing the ticket to the number of free pages of the first channel, and selecting the first channel based on the comparison. The selection may include selecting the first channel based on a least used channel policy. The selection may include comparing a first number of free pages of the first channel with a second number of free pages of the second channel, and selecting the first channel based on the comparison. A page frame number of the memory page from the first channel may include a channel identifier portion. The memory allocation request may include a requested order, and the allocating may include checking a first set of one or more page lists, wherein the one or more page lists of the first set may be based on a first order and arranged by channel. A first list of the one or more page lists of the first set corresponding to the first channel may include entries for pages of the requested order, and the allocating may further include allocating the pages of the requested order from the first list of the one or more page lists of the first set to the process. The allocating may further include examining a second set of one or more page lists, wherein the one or more page lists of the second set may be based on a second order and arranged by channel. The first list of the one or more page lists of the second set corresponding to the first channel may include entries for pages of the requested order, and the allocating may further include allocating the pages of the requested order from the first list of the one or more page lists of the second set to the process. The memory system may include a first media core and a second media core, the first channel may be associated with the first media core, and the second channel may be associated with the second media core. The memory system may include a first device having a first device utilization and a second device having a second device utilization, the first channel and the second channel may be associated with the first device, and the method may further include selecting the first device for the memory allocation request based on the first device utilization and the second device utilization.

[0007] A system can include a storage device, a host, and channel selection logic, the storage device including a device interface, a first channel having a first channel utilization, and a second channel having a second channel utilization, the host including a host interface in communication with the device interface and a memory allocator configured to receive a memory allocation request from a process, the channel selection logic configured to select the first channel based on the first channel utilization and the second channel utilization based on the memory allocation request and allocate a memory page of the first channel to the process. The storage device can be a first storage device having a first device utilization, the system can further include a second storage device having a second device utilization, wherein the memory allocator can include device selection logic configured to select the first storage device for the memory allocation request based on the first device utilization and the second device utilization. The device interface can include a memory consistency interface, the host interface can include a memory consistency interface. The memory page can be configured as a device-attached memory. The storage device can include a first media core and a second media core, the first channel can be associated with the first media core, the second channel can be associated with the second media core.

[0008] An apparatus can include a memory allocator configured to receive a memory allocation request from a process, the memory allocator including channel selection logic configured to select a first memory channel based on a first channel utilization of the first memory channel and a second channel utilization of a second memory channel and allocate one or more memory pages from the first memory channel to the process. The first memory channel can be associated with a first device having a first device utilization, the second memory channel can be associated with a second device having a second device utilization, the memory allocator can further include device selection logic configured to select the first device for the memory allocation request based on the first device utilization and the second device utilization. The memory allocator can further include page allocation logic configured to allocate the one or more memory pages from the first memory channel based on an order of the memory allocation request. BRIEF DESCRIPTION OF DRAWINGS

[0009] The drawings are not necessarily drawn to scale, and throughout the drawings, for illustrative purposes, elements of similar structure or function may generally be represented by similar reference numerals or portions thereof. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming obscure, not all components, connections, etc. may be shown, and not all components may have reference numerals. However, the pattern of component configuration can be easily seen from the drawings. The drawings, together with the description, illustrate example embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] Figure 1 An embodiment of a memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0011] Figure 2A An embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0012] Figure 2B An embodiment of a utilization-aware memory allocation scheme with a memory allocator according to an example embodiment of the present disclosure is shown.

[0013] Figure 3 An example embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0014] Figure 4A An example embodiment of a fully interleaved page frame numbering scheme according to an example embodiment of the present disclosure is shown.

[0015] Figure 4B An example embodiment of a page frame numbering scheme with multiple consecutive pages belonging to the same channel according to an example embodiment of the present disclosure is shown.

[0016] Figure 4C An example embodiment of a page frame numbering scheme with non-interleaved mapping according to an example embodiment of the present disclosure is shown.

[0017] Figure 5 An example embodiment of a storage device architecture according to an example embodiment of the present disclosure is shown.

[0018] Figure 6 An example embodiment of a balanced random channel selection method according to an example embodiment of the present disclosure is shown.

[0019] Figure 7 An example embodiment of a method for implementing a balanced random channel selection strategy according to an example embodiment of the present disclosure is shown.

[0020] Figure 8An example embodiment of a least used channel first service channel selection method according to an example embodiment of the present disclosure is shown.

[0021] Figure 9 An example embodiment of a method for implementing a least used channel first service channel selection policy according to an example embodiment of the present disclosure is shown.

[0022] Figure 10A An example embodiment of a page frame numbering scheme with multiple consecutive pages belonging to the same channel according to an example embodiment of the present disclosure is shown.

[0023] Figure 10B FIG. 1 shows a diagram illustrating a process of performing a page allocation operation after a page allocation operation according to an exemplary embodiment of the present disclosure. Figure 10A An example embodiment of a page frame numbering scheme is shown in FIG.

[0024] Figure 11 An example embodiment of a buddy memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0025] Figure 12 An example embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0026] Figure 13A An embodiment of an address interleaving scheme according to an example embodiment of the present disclosure is shown.

[0027] Figure 13B Another embodiment of an address interleaving scheme according to an example embodiment of the present disclosure is shown.

[0028] Figure 14A An embodiment of an addressing scheme with device interleaving according to an example embodiment of the present disclosure is shown.

[0029] Figure 14B An embodiment of an addressing scheme with device interleaving and channel interleaving according to an example embodiment of the present disclosure is shown.

[0030] Figure 15 An example embodiment of a host device that may be used to implement a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown.

[0031] Figure 16 An example embodiment of a storage device that may be used to implement a page relocation scheme for garbage collection operations according to an example embodiment of the present disclosure is shown.

[0032] Figure 17 An embodiment of a method for page management in a memory system operation according to an example embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] In some memory systems, memory pages may be allocated in a manner that may result in an uneven distribution of pages among memory channels in one or more memory devices. The uneven distribution of pages may degrade performance, for example, by increasing tail latency, reducing bandwidth utilization, reducing channel parallelism, etc.

[0034] In a memory allocation scheme according to an example embodiment of the present disclosure, allocated memory pages can be distributed relatively evenly across memory channels. Memory pages can be distributed, for example, by allocating pages in channels that may have lower utilization. Depending on implementation details, this can distribute input and / or output (I / O) traffic of memory pages in a manner that can improve system performance, for example, by increasing bandwidth utilization and / or channel parallelism. Furthermore, depending on implementation details, distributing I / O traffic across memory channels based on utilization can, for example, alleviate tail latency by balancing workloads across memory channels.

[0035] In some embodiments, a host may include a memory allocator configured to implement a utilization-aware allocation scheme that can allocate memory pages across channels in one or more devices. Each device may have one or more media cores (e.g., flash memory cores), and each media core may have one or more memory channels.

[0036] In some embodiments, the memory allocator may include device selection logic, channel selection logic, and / or page allocation logic. In response to a memory allocation request, the device selection logic may select one of a plurality of devices based on the relative utilization of each device. After the device selection logic selects a device for the allocation request, the channel selection logic may select a channel within the device based on the relative utilization of each channel. Because channels within a device may be associated with multiple media cores, selecting a channel may also involve selecting a media core. After the channel selection logic selects a channel for the memory allocation request, the page allocation logic may allocate one or more pages within the channel based on, for example, the level or order of the request (e.g., the number of memory pages requested).

[0037] Channel allocation schemes according to example embodiments of the present disclosure may implement any suitable strategy for distributing memory allocations across channels based on their relative utilization. For example, a balanced random strategy may use random numbers to spread allocations across multiple channels in a manner that favors channels with more free pages. As another example, a least used channel first service strategy may allocate memory pages to channels with the highest number of free pages.

[0038] In some embodiments, one or more devices may be connected to one or more hosts via a memory coherent interconnect. The one or more devices may be configured as, for example, device attached memory.

[0039] The principles disclosed herein have independent utility and can be embodied individually, and not every embodiment can utilize every principle. However, these principles can also be embodied in various combinations, some of which can amplify the benefits of each principle in a synergistic manner.

[0040] Figure 1 An embodiment of a memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 1 The system shown may include a host 102 and one or more storage devices (SD) 104, which may be represented as SD 1, ..., SD n. Each storage device 104 may include a host core 106 and one or more media cores 108, which may be represented as Media Core 0, Media Core 1, ..., Media Core n. The host core 106 may communicate with the host 102, for example, via a memory coherent interconnect and / or protocol as described below.

[0041] Each media core 108 may control access to one or more memory channels 110, each of which may include memory pages arranged, for example, in blocks. The memory channels 110 associated with each media core 108 may be designated as Ch1, Ch2, ..., Chn.

[0042] Figure 1 The illustrated storage device 104, media core 108, and memory channel 110, as well as any other storage device, media core, and / or memory channel disclosed herein, may be implemented with any memory storage medium. For example, in some embodiments, the storage device 104 may be implemented as a solid-state drive (SSD), the media core 108 may be implemented as a flash memory core, and the memory channel 110 may be implemented with flash memory (e.g., NAND flash memory). However, the principles of the present disclosure may be implemented with any type of storage device using any type of storage medium, including any other type of solid-state media, magnetic media, optical media, etc. For example, in some embodiments, the storage device may be implemented as an SSD based on persistent memory (such as cross-grid non-volatile memory, memory with bulk resistance change, phase change memory (PCM), etc., or any combination thereof).

[0043] Some or all of the storage media (e.g., flash memory) of storage device 104 can be configured as device-attached memory 112 accessible to host 102 (e.g., using a virtual addressing scheme). Device-attached memory 112 can include regions 114 corresponding to storage devices SD 1, SD 2, ..., SD n. Host 102 can access storage device 104 via interconnect 113, which, in some embodiments, can be implemented using a memory semantic and / or memory coherent interconnect such as Compute Express Link (CXL) and / or using a memory coherent protocol such as CXL.mem. However, embodiments may also be implemented using any other interface and / or protocol, including cache coherent and / or memory semantic interfaces and / or protocols such as Gen-Z, Coherent Accelerator Processor Interface (CAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc.

[0044] The host 102 may include a memory allocator 116 that may receive a memory allocation request 118 from a process, such as a program, application, service, kernel, or the like. The memory allocation request 118 may specify the number of pages requested. The number of pages requested may correspond to an order (also referred to as a level) of requests for a buddy memory allocation scheme. In some embodiments, the memory allocation request 118 may also specify a storage device 104 (e.g., at a node, region, etc.) from which to allocate memory. In some embodiments, the memory allocation request 118 may rely on the memory allocator 116 to select a device based on, for example, the relative load of each device.

[0045] In some embodiments, memory allocator 116 may implement a separate buddy memory allocation scheme for each of storage devices SD 1, SD 2, ..., SD n. Thus, after device 104 has been selected (e.g., by memory allocator 116 or by a process issuing request 118), one or more pages 120 may be allocated from the selected device 104 based on the number of pages requested (e.g., the level or order of the request) without knowing from which of the one or more channels 110 the memory is allocated.

[0046] In some embodiments, the memory allocator 116 may select one of the media cores 108 from which to allocate memory 120 for the request 118 (e.g., the media core 108 may be statically mapped), but may not know from which of the one or more channels 110 associated with the selected media core 108 the memory 120 is allocated. For example, the selected media core 108 may dynamically map one or more allocated memory pages 120 to one or more of its channels (e.g., Ch1, Ch2, . . . , Chn) using a logical block address to physical block address (LBA-to-PBA or LBA2PBA) mapping scheme. (If the storage device 104 is implemented as a flash-based SSD having a flash core, the LBA-to-PBA mapping scheme may be implemented, for example, by a flash translation layer (FTL) in one or more flash cores.)

[0047] Therefore, the host 102 may not know from which channel of the one or more channels 110 the requested memory 120 is allocated. In addition, pages may be allocated in a manner that may result in Figure 1 The allocated pages are allocated in an unevenly distributed manner as shown. Allocated pages and / or blocks are represented by shading, an example of which is represented by 122. Unallocated pages and / or blocks are represented by non-shading, an example of which is represented by 124.

[0048] Reference Figure 1 The memory channels 110 are shown as a bar graph, where the shaded portion represents the percentage of channel memory allocated. The final total memory allocation for each media core 108 is provided as a percentage.

[0049] In some embodiments and depending on implementation details, such as Figure 1 The uneven distribution of pages and / or blocks shown in SD 1 and SD n in the system may degrade the overall performance of the system, for example, by reducing bandwidth utilization and / or channel parallelism. Referring to Media Core 0 of SD 1 as an example, Ch2 may have significantly more allocated pages than Ch1. Therefore, if a first process attempts to access (e.g., read and / or write) a page in Ch1, there is a relatively high probability that a second process is already accessing (e.g., reading and / or writing) another page in Ch2. Therefore, before the first process can continue its access, the first process may wait until the second process's access is completed. In addition, because Ch2 may be more intensively used, Ch2 may enter garbage collection earlier and / or more frequently than Ch1. This may cause tail latency for the first process and / or reduce bandwidth utilization and / or channel parallelism.

[0050] In some embodiments, to implement static mapping of multiple media cores 108 within a device 104, the memory allocator 116 may provide an address to the device 104 in which one or more bits may specify a media core 108. Thus, in a device 104 having four media cores 108, two bits of the address may identify the media core 108. In such an embodiment, the memory allocator may not provide any address bits for channels because the selected media core 108 may dynamically map one or more allocated memory pages 120 to one or more of its channels (e.g., Ch1, Ch2, . . . , Chn) using an LBA-to-PBA mapping scheme.

[0051] Figure 2A An embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 2A In the illustrated embodiment, one or more storage devices 204 can be configured (e.g., mapped) to one or more corresponding regions 214 of device-attached memory 212. Each storage device 204 can include one or more media cores 208 (denoted as Media Core 0, Media Core 1, ..., Media Core n), and each media core 208 can have one or more memory channels 210 (denoted as Ch1, Ch2, ..., Chn).

[0052] The memory allocation request 218 may be serviced in a manner that may spread (e.g., evenly distribute) the memory allocation across the devices 204, media cores 208, and / or channels 210 based on, for example, the relative utilization (e.g., percentage of allocated memory) of the devices 204, media cores 208, and / or channels 210. In some embodiments, the memory allocation request 218 may be serviced by device selection logic, channel selection logic, and / or page allocation logic, which may be located, for example, at one or more hosts.

[0053] In some embodiments, spreading memory allocations across storage devices 204, media cores 208, and / or channels 210 can result in more evenly distributed traffic (e.g., read and / or write operations) for the allocated pages, as shown by media core traffic 226 and / or channel traffic 228. Depending on implementation details, this can reduce tail latency and / or improve bandwidth utilization and / or channel parallelism.

[0054] Figure 2B An embodiment of a utilization-aware memory allocation scheme with a memory allocator according to an example embodiment of the present disclosure is shown. Figure 2BThe illustrated system may include a host 202, a system memory 205, and one or more storage devices 204, represented as SD0, ..., SDn. The one or more storage devices 204 may be configured (e.g., mapped) as one or more corresponding regions 214 of device-attached memory 212. The system memory 205 (e.g., host memory that may be implemented using dynamic random access memory (DRAM)) and the device-attached memory 212 may be arranged in a physical memory map 215. In some embodiments, the regions 214 of the device-attached memory 212 may be placed into logically contiguous memory regions of the physical memory map 215.

[0055] The host 202 may include a memory allocator 216 that may manage some or all of the physical memory mapping 215. The memory allocator 216 may receive memory allocation requests 218 from one or more processes 203 (such as programs, applications, services, kernels, etc.) and service the requests 218 by allocating one or more pages of memory 220 to the process that sent the request 218. The memory allocator 216 may include device selection logic 230, channel selection logic 209, and / or page allocation logic 211 that may spread (e.g., evenly distribute) memory allocations across the storage devices 204 and / or one or more channels within the storage devices 204.

[0056] In some embodiments, in response to the memory allocation request 218, the device selection logic 230 may select one of the devices 204 from which to allocate the requested memory 220 based on the relative utilization of each device. For example, the device selection logic 230 may select one of the devices 204 based on the relative percentage utilization of each device 204 (e.g., the requested memory may be allocated from the device 204 having the lowest percentage utilization).

[0057] After device selection logic 230 selects one of devices 204, channel selection logic may select one or more channels within the selected device 204 from which to allocate the requested memory 220. For example, channel selection logic 209 may select channels based on a balanced random policy, a least used channel policy, etc.

[0058] After the channel selection logic 209 selects one or more channels within the selected device 204, the page allocation logic 211 may allocate one or more pages of memory 220 from the selected one or more channels. For example, the channel selection logic 211 may search for and allocate n consecutive pages of memory, where n is the number of requested pages (e.g., the requested level or order), but only in the one or more channels selected by the channel selection logic 209.

[0059] Figure 3 An example embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 3 The illustrated system may include a host 302 and one or more storage devices (SDs) 304, which may be represented as SD 1, ..., SD n. The host 302 may include a memory allocator 316 that may receive memory allocation requests 318 from processes such as programs, applications, services, kernels, etc., and service the requests 318 by allocating one or more pages of memory 320 to the process that sent the requests 318.

[0060] Some or all of the storage media of storage device 304 may be configured as device-attached memory 312 accessible to host 302 (e.g., using a virtual addressing scheme). Device-attached memory 312 may include regions 314 corresponding to storage devices SD1, SD2, ..., SDn, respectively. In some embodiments, device-attached memory 312 may be arranged in a physical memory map 315 that may include system memory (e.g., host memory) 305.

[0061] Host 302 may access storage device 304 via interconnect 313, which in some embodiments may be implemented using a memory semantic and / or memory coherent interconnect (such as Compute Express Link (CXL)) and / or using a memory coherent protocol (such as CXL.mem). However, embodiments may also be implemented using any other interface and / or protocol.

[0062] One or more of the storage devices 304 may include a host core 306 and one or more media cores 308. Each media core 308 may control access to one or more memory channels 310, each of which may include, for example, memory pages arranged in blocks. In this example, the media cores 308 may be represented as MediaCore 0, MediaCore 1, ..., MediaCoren, and the memory channels 310 may be designated as Ch1, Ch2, ..., Chn. In some embodiments, the media cores 308 may be implemented as flash memory cores, and the channels 310 may be implemented using flash memory, but any other type of storage medium and / or media core may be used.

[0063] The memory allocator 316 may include device selection logic 330, channel selection logic 309 and / or page allocation logic 311, which may allocate allocated memory pages 320 to one or more storage devices 304, media cores 308 and / or memory channels 310 in a manner that can spread (e.g., evenly distribute) the allocated memory pages 320 across the memory channels 310.

[0064] In some embodiments, in response to the memory allocation request 318, the device selection logic 330 may select one of the plurality of storage devices 304 based on the relative utilization (e.g., percentage of memory allocated) of each storage device 304. In some embodiments, the process that issues the memory allocation request 318 may select the storage device 304.

[0065] After a device 304 has been selected for a memory allocation request 318 (e.g., by a memory allocator 316 or by a process issuing the request 318), channel selection logic 309 may select a channel 310 within the selected device 304 based on the relative utilization of each channel 310. For example, the channel selection logic 309 may select a channel based on a balanced random policy, a least used channel policy, etc.

[0066] Because one or more of the devices 304 can have multiple media cores 308, selecting a channel 310 can also involve selecting a media core 308. Thus, in some embodiments, the memory allocator 316 can provide an address to the memory device 304 in which one or more bits can specify the selected media core 308 and one or more bits can specify the selected memory channel 310. For example, in a device 304 having four media cores 308 (each having eight memory channels 310), the address can include five bits to specify the selected memory channel 310—two bits to specify the media core 308 and three bits to specify the memory channels 310 within the media core 308.

[0067] Thus, in some embodiments, both the media core 308 and the memory channel 310 may be configured as follows: Figure 3 The depicted images are statically mapped because the selected media core 308 and / or memory channel 310 may be determined by the channel selection logic 309 .

[0068] In some embodiments, the host memory management scheme may include a host-side memory map that may include the base addresses and / or memory sizes of regions 314 corresponding to storage devices SD 1, SD 2, ..., SD n. For example, in an embodiment where one or more storage devices 304 each have a 16GB capacity, host memory 305 may occupy an address range of 0 to 1GB, region 314 associated with SD 1 may occupy a range of 1GB to 17GB, region 314 associated with SD 2 may occupy a range of 17GB to 33GB, and so on. Thus, the storage device number may not be included in the address provided by memory allocator 316. However, in other embodiments, the address may include one or more bits to specify the device 304.

[0069] After the channel selection logic 309 selects one or more channels within the selected device 304, the page allocation logic 311 may allocate one or more pages of memory 320 from the selected one or more channels 310. For example, the channel selection logic 311 may search for and allocate n consecutive pages of memory, where n is the number of requested pages (e.g., the requested level or order), but only in the one or more channels selected by the channel selection logic 309.

[0070] In some embodiments, one or more of the media cores 308 may include mapping logic 317 that may implement an LBA-to-PBA mapping scheme to dynamically allocate mapping pages within one or more memory channels 310 .

[0071] By spreading the allocated memory pages 320 across devices 304, media cores 308, and / or memory channels 310, Figure 3 The illustrated embodiment may provide Figure 3 A more even distribution of allocated memory pages is shown. Allocated pages and / or blocks are shaded, an example of which is shown as 322. Unallocated pages and / or blocks are not shaded, an example of which is shown as 324. A more even distribution of allocated memory can also be referred to as Figure 3 SD n is evident in , where the memory channels 310 are shown as a bar graph, with the shaded portion representing the percentage of channel memory allocated. The final total memory allocation for each media core 308 is provided as a percentage.

[0072] Depending on implementation details, this relatively even distribution of allocated memory pages may provide a more even distribution of memory input and / or output operations (I / O), which in turn may reduce tail latency, improve bandwidth utilization, and / or increase channel parallelism.

[0073] For illustrative purposes,Figure 3 A logical view of the allocated pages and / or blocks within each memory channel 310 may be provided. Thus, the allocated pages and / or blocks may be shown in a contiguous position. However, based on the LBA-to-PBA mapping scheme within each channel 310, the allocated pages and / or blocks within each memory channel 310 may be distributed across the memory channels in any manner while still maintaining a balance (e.g., even distribution) across the memory channels 310.

[0074] For illustrative purposes, device selection logic 330, channel selection logic 309, and / or page allocation logic 311 may be shown and / or described as being located at the host 302. However, in other embodiments, some or all of this logic may be implemented at any location. For example, some or all of the logic may be located at the host 302, at one or more host cores 306, at one or more media cores 308, or at any other location within one or more storage devices 304, or distributed in any combination thereof.

[0075] Figure 4A An example embodiment of a fully interleaved page frame numbering scheme according to an example embodiment of the present disclosure is shown. Figure 4A In the illustrated page frame number (PFN), the 64-bit address 429 may include a 4-bit channel identifier portion 436 (also referred to as a channel ID, CH ID, or Ch ID).

[0076] The channel ID 436 may include two core identifier bits 438 (also referred to as core ID bits, Mcore ID bits (for media cores), and / or Fcore ID bits (for flash cores)). These two core ID bits may identify the specific media core 408 to which the page is mapped.

[0077] The channel ID 436 may also include two channel identifier bits 440 (also referred to as channel ID bits, Ch ID bits, or CH ID bits) that may identify the specific channel to which the page is mapped.

[0078] The 4-bit channel identifier portion 436 may be located in the four least significant bits of the PFN to implement a fully interleaved memory map, such as with Figure 4A The dielectric core 408 and channels 410 of the PFN arrangement are shown.

[0079] Figure 4B An example embodiment of a page frame numbering scheme with multiple consecutive pages belonging to the same channel according to an example embodiment of the present disclosure is shown. Figure 4B The embodiment shown may be similar to Figure 4AThe embodiment shown, however, may have the channel ID 442 aligned with bits 1 to 4 of the PFN to implement a memory mapping where two consecutive pages of memory may belong to the same channel, such as with Figure 4B The PFN arrangement is shown as shown in FIG4 . The two core identifier bits 444 can be aligned with bits 3 and 4 of the PFN, and the two channel identifier bits 446 can be aligned with bits 1 and 2 of the PFN. Therefore, due to channel interleaving, adjacent pages can belong to different channels.

[0080] Figure 4C An example embodiment of a page frame numbering scheme with non-interleaved mapping according to an example embodiment of the present disclosure is shown. Figure 4C The embodiment shown may be similar to Figure 4A and Figure 4B However, it is possible to have a channel ID 448 with core identifier bits 450 and channel identifier bits 452 that can be split between different regions of the PFN 429 to achieve the same as having Figure 4C The PFN arrangement shown has a dielectric core 408 and channels 410 shown with a non-interleaved mapping.

[0081] Figure 4A 、 Figure 4B and / or Figure 4C The illustrated embodiments can be used, for example, to implement static mapping of memory pages to memory channels and / or media cores and / or dynamic mapping of memory pages within memory channels in any of the embodiments of the utilization-aware memory allocation scheme disclosed herein. Figure 4A 、 Figure 4B and / or Figure 4C The illustrated embodiments may be illustrated with a specific number of core ID bits, channel ID bits, etc., but any number of bits and / or bit positions may be used to implement any type of memory mapping at specific bit locations.

[0082] Figure 5 An example embodiment of a storage device architecture according to an example embodiment of the present disclosure is shown. Figure 5 The illustrated embodiment may be used to implement any utilization-aware memory allocation scheme disclosed herein. For example, it may be used to implement the storage device 204 and / or Figure 3 Any of the storage devices 304 shown.

[0083] Reference Figure 5, the storage device 504 may include a host core 506 and one or more media cores 508 represented as Media Core 0, Media Core 1, ..., Media Core 3. One or more of the media cores 508 may control access to one or more memory channels 510 represented as Ch1, Ch2, ..., Ch15.

[0084] The host core 506 may communicate with the host, for example, over any type of interconnect (eg, a memory coherent interconnect such as CXL) and / or using any type of protocol (eg, a coherent protocol such as CXL.mem).

[0085] One or more of the media cores 508 may include LBA-to-PBA mapping logic 517 that may dynamically map the logical block addresses of allocated memory pages to physical block addresses within the memory channel 510 .

[0086] In some embodiments, the media core 508 and / or the memory channel 510 may be configured as Figure 5 508 and / or memory channel 510. Figure 5 In the example embodiment shown, the storage device 504 may include four media cores 508, and each media core 508 may have four memory channels 510. Thus, the address provided by the memory allocator may include four bits to specify the selected memory channel—two bits to specify the media core 508 and two bits to specify the memory channel 510.

[0087] In some embodiments, the media core 508 may be implemented as a flash memory core and the channel 510 may be implemented with flash memory, but any other type of storage medium and / or media core may be used. Figure 5 The illustrated memory device 504 may be implemented with four media cores 508, each of which may have four memory channels 510, however, any number of media cores 508 and / or memory channels 510 may be used.

[0088] Figure 6 An example embodiment of a balanced random channel selection method according to an example embodiment of the present disclosure is shown. Figure 6 The illustrated embodiment can be used, for example, to implement any channel selection logic disclosed herein. Figure 6In the embodiment shown, there may be four memory channels, Channel 0, Channel 1, Channel 2, and Channel 3, however, in other embodiments, any number of channels may be used. At the start of the method, Channel 0, Channel 1, Channel 2, and Channel 3 may have 1000, 3000, 1500, and 500 free pages, respectively. Thus, there may be a total of 6000 free pages. In order to select a channel from which to allocate memory pages, the method may create a ticket 654 by generating a random number (e.g., a random number between zero and the total number of free pages) and calculating the random number modulo (%) the total number of free pages. In this example, ticket = random number % 6000. The ticket may then be used to select a channel (which may be referred to as a target channel) as shown by arrow 655, using a balanced random strategy (e.g., Figure 7 The strategy shown) allocates memory pages from this channel.

[0089] Figure 7 An example embodiment of a method for implementing a balanced random channel selection strategy according to an example embodiment of the present disclosure is shown. Figure 7 The illustrated embodiment may be used, for example, to implement any channel selection logic disclosed herein.

[0090] The method may begin at operation 702. At operation 704, the value of the ticket may be initialized by calculating a random number modulo the total number of free pages across all channels. At operation 706, the channel identifier (ID) may be initialized to zero. At operation 708, the method may compare the value of the ticket with the number of free pages in Channel 0 (Page_count[ID], where ID=0). If the value of the ticket is greater than the number of free pages in Channel 0, the method may proceed to operation 710, where the number of free pages in Channel 0 may be subtracted from the value of the ticket. At operation 712, the method may increment the channel identifier (ID) to move to the next channel. The method may then return to operation 708 and loop through operations 710 and 712 until the value of the ticket is less than or equal to the number of free pages in the current channel identified by the channel identifier (ID). If, at operation 708, the value of the ticket is less than or equal to the number of free pages in the current channel, the method may proceed to operation 714, where the number of free pages in the channel indicated by the current channel identifier (ID) may be decremented by 1. The method may then end at operation 716 by returning the channel identifier (ID) as the channel from which to allocate the next page of memory.

[0091] Each time a channel is selected from which to allocate one or more pages of memory, the Figure 7 The method shown.

[0092] Figure 8 An example embodiment of a least used channel first service channel selection method according to an example embodiment of the present disclosure is shown. Figure 8 The Least Used Channel First Service (LUCFS) policy shown can be used, for example, to implement any channel selection logic disclosed herein. Figure 8 In the embodiment shown, there may be four memory channels, Channel 0, Channel 1, Channel 2, and Channel 3. However, in other embodiments, any number of channels may be used. At the start of the method, Channel 0, Channel 1, Channel 2, and Channel 3 may have 1000, 3000, 1500, and 500 free pages, respectively. Therefore, there may be a total of 6000 free pages. Figure 8 The method shown can use LUCFS policies such as Figure 9 The strategy shown) selects the least used channel as shown by arrow 657, such as the channel with the highest number of free pages.

[0093] Figure 9 An example embodiment of a method for implementing a least used channel first service channel selection policy according to an example embodiment of the present disclosure is shown. Figure 9 The illustrated embodiment may be used, for example, to implement any channel selection logic disclosed herein.

[0094] The method may begin at operation 902. At operation 904, the method may initialize variables Most_count, ID, and Temp_ID to zero. At operation 906, the method may compare Temp_ID with Channel_count, which may represent the total number of channels. If Temp_ID is less than Channel_count, the method may proceed to operation 908, where it may compare Most_count with Page_count[ID], which may represent the number of free pages in the channel indicated by the channel identifier (ID). If Most_count is less than Page_count[ID], the method may proceed to operation 910, where Most_count may be set to the number of free pages in the current channel. At operation 912, the value of ID may be set to Temp_ID. The method may then proceed to operation 914.

[0095] However, if at operation 908 , most_count is greater than or equal to the number of free pages in the current channel, the method may proceed to operation 914 .

[0096] At operation 914, the value of Temp_ID may be incremented by one, and the method may return to operation 906. The method may continue to loop through operations 908 and 914, and possibly through operations 910 and 912, until the value of Temp_ID is greater than or equal to Channel_count at operation 906. The method may then proceed to operation 916, where the number of free pages in the channel indicated by the current channel identifier (ID) may be decremented by one. The method may then end at operation 918 by returning the channel identifier (ID) as the channel from which to allocate the next page of memory.

[0097] Each time a channel is selected from which to allocate one or more pages of memory, the Figure 9 The method shown.

[0098] Figure 10A An example embodiment of a page frame numbering scheme according to an example embodiment of the present disclosure is shown. Figure 10A The embodiment shown can be used, for example, using the above Figure 4B This is achieved by the described scheme in which two consecutive pages belong to the same channel. Figure 10A The illustrated embodiment can be used, for example, to implement Figure 11 and Figure 12 The memory allocation scheme shown.

[0099] Reference Figure 10A , as indicated by the corresponding PFN, the first 32 pages of contiguous memory can be arranged in a 0 Continuous pages, 2 1 Continuous pages, 2 2 Continuous pages, 2 3 Continuous pages and 2 4 The allocated pages (PFN 4 and PFN 10 in this example) are shaded. Figure 10A In the example shown, there are a total of 16 memory channels (represented by ChID 0 to ChID 15), and two consecutive pages belong to each channel. Therefore, the first 32 pages of memory (PFN 0 to PFN 15) are mapped in pairs to the 16 memory channels. This pattern can continue for the next 32 pages of memory (PFN 32 to PFN 63), which can be mapped in pairs to the 16 memory channels.

[0100] Figure 11 An example embodiment of a buddy memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 11 The embodiment shown can be used, for example, Figure 1 The embodiment shown is implemented. Figure 11In the embodiment shown, there may be a total of 16 memory channels, and unallocated pages (e.g., Figure 10A The unallocated pages shown in FIG. 2 can be arranged into a hierarchy of free page groups, where each order (level) of the hierarchy corresponds to a number of consecutive free pages. Thus, individual free pages 5 and 11 can be placed at order 2. 0 (2 0 = 1 continuous free page), page groups 6-7 and 8-9 can be placed in order 2 1 (2 1 = 2 consecutive free pages), page groups 0 to 3 and 12 to 15 can be placed in order 2 2 (2 2 = 4 consecutive free pages), page groups 16 to 31 can be placed in order 2 4 (2 4 = 16 consecutive free pages).

[0101] At operation 1102, Figure 11 The illustrated scheme may receive a memory allocation request for a single page from a process (also referred to as a caller). The allocation request may specify a specific device (e.g., in a specific region and / or at a specific node). At operation 1104, the scheme may call the memory allocation function alloc_pages(order) based on the order of the request (e.g., the number of pages requested). At operation 1106, the scheme may select a specific page to service the memory allocation request. Because Figure 11 The illustrated scheme may implement a buddy memory allocation scheme so that it may attempt to allocate the requested number of pages from the lowest order of the hierarchy, regardless of the channel to which one or more pages may belong. Thus, because the request received at operation 1104 is for a single page, Figure 11 The scheme shown can be obtained from order (level) 2 0 However, in response to a subsequent memory allocation request for a single page of memory, Figure 11 The scheme shown may select page 11 which may be located in the same memory channel as page 5. Thus, Figure 11 The illustrated scheme may result in an uneven distribution of allocated memory pages among the memory channels.

[0102] Figure 12 An example embodiment of a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 12 The embodiment shown can be used, for example, Figure 2A 、 Figure 2B 、 Figure 3 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8and / or Figure 9 Any one of the embodiments shown can be implemented.

[0103] exist Figure 12 In the illustrated embodiment, unallocated pages (e.g., the unallocated pages shown in FIG. 10 ) can be arranged in lists based on the channel in which the pages are located. The lists can then be arranged into a hierarchy based on the number of consecutive free pages in each list. Thus, at level 2 0 There can be 16 lists at order 2 1 There can be 16 lists at order 2 2 There can be 8 lists at order 2 3 There can be 4 lists at order 2 4 There can be 2 lists at order 2 5 There can be 1 list at a channel. The numbers in the box to the right of the channel number represent the free pages in the corresponding channel. These free pages are arranged into groups with the number of consecutive free pages corresponding to the order of the list.

[0104] Order 2 0 and order 2 1 There can be the same number of lists because in a dynamic mapping scheme, two pages can belong to each consecutive channel.Thus, the channel ID 1244 of the PFN 1229 of the requested page can be aligned with bits 1 to 4 of the PFN.

[0105] At operation 1202, the scheme may receive an allocation request 1218 for one or more pages of device memory and select a storage device from which to allocate the requested memory, for example, based on relative utilization of a plurality of storage devices. Operation 1202 may be performed, for example, by any device selection logic disclosed herein (e.g., device selection logic 230 and / or Figure 3 In the example, Figure 12 In the illustrated embodiment, it can be assumed that the device selection logic has already selected the storage device where Ch 0 to Ch 15 are located.

[0106] At operation 1204 , the scheme may call a memory allocation function alloc_pages(order) based on the order of the request (eg, the number of pages requested).

[0107] At operation 1206, the scheme may call channel selection logic to select a particular channel within the selected storage device from which to service the memory allocation request. Operation 1206 may be performed, for example, by any channel selection logic disclosed herein (e.g., channel selection logic 209 and / or Figure 3For purposes of illustration, the request in this example embodiment may be for a single page of memory, and the channel selected by the channel select operation may be Ch ID (11).

[0108] To select the memory page to allocate, the page allocation logic may begin at stage 2. 0 , and at order 2 0 The list is checked at order 2 to find a free memory page in channel 11. For example, in some embodiments, the page allocation logic can use the channel ID as an index into a table of multiple lists or a list of multiple lists to apply the logic directly to the list of the corresponding channel. 0 There may be no free page found for channel 11 at (level 0), so the page allocation logic can proceed to order 2 1 (Level 1) to find a free memory page in channel 11. Because for order 2 1 Channel 11 at the top may not find a free page, so the page allocation logic can continue to travel up the hierarchy until it finds a free page in channel 11, or until it reaches the highest order (2 5 or level 5), in which case the page allocation logic may return a failure indication rather than the allocated page.

[0109] By using the channel ID as an index to check the list of free memory pages, the index can be adjusted for each order by shifting it right by one bit. 2 To check at order 2, Ch ID (11) can be shifted right by one bit to become Ch ID (5), which can be the correct index to use to check the list of free pages in channel 11. Ch ID (5) can then be shifted right to Ch ID (2), and then right to Ch ID (1) to check order 2, respectively. 3 and 2 4 At order 2 5 There may be only one list to check, so indexing may not be necessary. 0 and 2 1 Because the mapping scheme can map two consecutive pages belonging to each channel.

[0110] In this example, the page allocation logic can be in channel 11 at order 2 4 16 consecutive free pages (PFN 16 to PFN 31) are located at the address. The page allocation logic can select one of the free pages associated with channel 11 (e.g., PFN 22 or PFN 23) and return the allocated page to the requesting process. The page allocation logic can then update Figure 10A The PFN mapping shown is to reflect the Figure 10BShows the status of the selected page at the time of allocation.

[0111] therefore, Figure 12 The embodiment shown may select one of pages PFN 16 to PFN 31 instead of Figure 11 PFN 5 is selected as in the embodiment shown. Depending on the implementation details, this may provide Figure 11 Compared to the embodiment shown, the distribution is more uniform. Figure 11 The illustrated embodiment tends to allocate single pages starting at the bottom of the hierarchy, which can cause page allocations to become clustered in the channels where those pages are likely to be located.

[0112] As another example, if the channel selection logic selects channel 0 (Ch ID(0)) for allocating a single page of memory at operation 1206, the page allocation logic may begin at order 2. 0 (level 0) to find a free page. Because at level 2 0 There are no free pages in the list for channel 0, so the page allocation logic can proceed to order 2 1 (Level 1) to find a free memory page in channel 0. (No shifting is performed between levels 0 and 1.) Because at level 2 1 There may not be a free page found for channel 0, so the page allocation logic can proceed to order 2 2 (Level 2). (Shifting by zero as an index may simply result in zero.) 2 At this point, the page allocation logic can find Page 0 and Page 1 in the list for Channel 0. Therefore, the page allocation logic can allocate either Page 0 or Page 1 and then update the PFN map shown in Figure 10 to reflect the state of the selected page at the time of allocation. (PFN 2 and PFN 3 in the list for Ch0-Ch1 are associated with Channel 1.)

[0113] Figure 12 The page allocation operations shown may be performed, for example, by any page allocation logic disclosed herein (e.g., page allocation logic 211 and / or Figure 3 This is accomplished by the page allocation logic 311 shown.

[0114] Figure 13A An embodiment of an address interleaving scheme according to an example embodiment of the present disclosure is shown. Figure 13AThe illustrated embodiment shows data 1302 at a 4-bit memory address 1304 in a physical memory map. The two lower-order bits (also referred to as the least significant bits (LSBs)) of each 4-bit address can provide the address of a module. The two higher-order bits (also referred to as the most significant bits (MSBs)) of each 4-bit address can provide the address of a row within a module. For example, at the 4-bit address 0001 (containing the data "20"), the two lower-order bits 01 represent module 01, and the two higher-order bits 00 represent row 00 in module 01.

[0115] Figure 13B Another embodiment of an address interleaving scheme according to an example embodiment of the present disclosure is shown. Figure 13B The illustrated embodiment shows the same data 1302 at the 4-bit memory address 1304 shown in FIG13. However, Figure 13B In the illustrated embodiment, the two inner bits (e.g., the second and third bits) of the 4-bit address provide the address of the module, and the two outer bits (e.g., the first and fourth bits) of the 4-bit address provide the address of a row within the module. For example, at the 4-bit address 0001 (containing the data "20"), the two inner bits 00 represent module 00, and the two outer bits 01 represent row 01 within module 00.

[0116] Figure 13A and Figure 13B The illustrated embodiments of the interleaving scheme can be used, for example, to implement interleaving in a memory system according to example embodiments of the present disclosure. For example, in some embodiments of the memory system, address bits of a module can be used for a device (e.g., a device bit), and address bits of a row within a module can be used for a channel within a device (e.g., a channel bit).

[0117] Figure 14A An embodiment of a device interleaving scheme according to an example embodiment of the present disclosure is shown. Figure 14A The illustrated embodiment may include a host 1402, a system memory 1405, and one or more storage devices 1404, represented as SD 0, ..., SD n. The one or more storage devices 1404 may be mapped as device attached memory 1412 in a physical memory map 1415, which may include the system memory 1405 (e.g., host memory that may be implemented with DRAM).

[0118] pass Figure 14A As shown, with device interleaving enabled, consecutive pages of the physical memory map 1415 may belong to different storage devices 1404. (The pages represented as SD 0, ..., SD n in the physical memory map 1415 belong to storage devices SD 0, ..., SD n, respectively.) This can be done withFigure 2B In contrast to the embodiment shown, Figure 2B In the illustrated embodiment, each device 204 may be mapped to a separate region 214 of device attached memory 212 in a physical memory map 215 .

[0119] Figure 14A The scheme shown can be used, for example, with any memory allocator having the device selection logic disclosed herein, such as Figure 2B and Figure 3 Memory allocator shown).

[0120] Figure 14B Embodiments of device and channel interleaving schemes according to example embodiments of the present disclosure are shown. Figure 14B The illustrated embodiment may include a host 1402, a system memory 1405, and one or more storage devices 1404, represented as SD 0, ..., SD n. The one or more storage devices 1404 may be mapped as device attached memory 1412 in a physical memory map 1415, which may include the system memory 1405 (e.g., host memory that may be implemented with DRAM).

[0121] and Figure 14A Same as the device interleaving scheme shown, Figure 14B The illustrated scheme may include device interleaving, where consecutive pages of the physical memory map 1415 may belong to different storage devices 1404. However, Figure 14B The illustrated scheme may also include channel interleaving, where the channels within each device may be as follows Figure 14B 1404 are remapped to consecutive channel addresses. In such an embodiment, device selection logic may not be required. Instead, channel selection logic may select any channel across some or all devices 1404.

[0122] Figure 14B The scheme shown can be used, for example, with any memory allocator having the channel selection logic disclosed herein, such as Figure 2B and Figure 3 Memory allocator shown).

[0123] In some embodiments, one or more storage devices in a memory system according to an example embodiment of the present disclosure may implement Figures 4A-4C 、 Figures 13A-13B and / or Figures 14A-14BThe address interleaving schemes disclosed herein may be one or more of the address interleaving schemes described herein. The address interleaving scheme may be determined, for example, by the storage device and / or by a basic input / output system (BIOS). In some embodiments, the storage device may report to the host one or more address interleaving schemes that it may be using. A memory allocator in the host (which may include, for example, device selection logic, channel selection logic, and / or page allocation logic) may then coordinate any utilization-aware memory allocation scheme disclosed herein with the one or more address interleaving schemes used by the storage device. Depending on implementation details, this may enable the memory allocator to more efficiently manage the utilization-aware memory allocation scheme.

[0124] Figure 15 An example embodiment of a host device that may be used to implement a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown. Figure 15 The illustrated host device 1500 may include a processor 1502 (which may include a memory controller 1504 ), a system memory 1506 , device selection logic 1508 , virtual memory logic 1510 , a memory allocator 1512 , and / or an interconnect interface 1514 (which may be implemented using CXL, for example). Figure 15 Any or all of the components shown may communicate via one or more system buses 1516. In some embodiments, Figure 15 The illustrated host device 1500 can be used to implement any host functionality disclosed herein, including utilization-based device and / or channel selection. In some embodiments, Figure 15 One or more of the components shown may be implemented using other components. For example, in some embodiments, one or more of the device selection logic 1508, the virtual memory logic 1510, and / or the memory allocator 1512 may be implemented, for example, by the processor 1502 executing instructions stored in the system memory 1506 or other memory.

[0125] Figure 16 An example embodiment of a storage device that can be used to implement a utilization-aware memory allocation scheme according to an example embodiment of the present disclosure is shown. The storage device 1600 may include a device controller 1602 , a media conversion layer 1604 , a storage medium 1606 , and an interconnect interface 1608 . Figure 16 The components shown may communicate via one or more device buses 1610. In some embodiments where flash memory may be used for some or all of the storage media 1606, the media translation layer 1604 may be partially or completely implemented as a flash translation layer (FTL). Figure 16The illustrated storage device 1600 can be used to implement any of the device-side functionality related to the utilization-aware memory allocation disclosed herein. For example, the device controller 1602 and / or the media translation layer 1604 can be used to implement some or all of the core selection logic, the channel selection logic, the page allocation logic, etc.

[0126] Any of the functionality described herein (including with respect to Figures 1-17 Any of the host functionality, device functionality, etc. described, such as the device selection logic, the channel selection logic, the page allocation logic, etc., can be implemented in hardware, software, or any combination thereof, including instructions stored in any type of memory, including the following: combinational logic, sequential logic, one or more timers, counters, registers, state machines, volatile memory (such as DRAM and / or static random access memory (SRAM)), non-volatile memory, and / or any combination thereof, complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), central processing units (CPUs) (such as complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as ARM processors)), graphics processing units (GPUs), neural processing units (NPUs), etc. In some embodiments, one or more components can be implemented as a system on a chip (SOC).

[0127] Any of the storage devices disclosed herein can be implemented using any connector configuration (such as serial ATA (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), U.2, etc.) in any form factor (such as 3.5-inch, 2.5-inch, 1.8-inch, M.2, enterprise and data center SSD form factor (EDSFF), NF1, etc.).

[0128] Any of the storage devices disclosed herein can be implemented and / or used in conjunction with, in whole or in part, a server chassis, a server rack, a data room, a data center, an edge data center, a mobile edge data center, and / or any combination thereof.

[0129] Any storage device disclosed herein may communicate via any interface and / or protocol including Peripheral Component Interconnect Express (PCIe), Nonvolatile Memory Express (NVMe), NVMe-over-fabric (NVMe-oF), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, etc., or any combination thereof.

[0130] Figure 17 An embodiment of a method for memory allocation according to an example embodiment of the present disclosure is shown. The method may begin at operation 1702. At operation 1704, the method may receive a memory allocation request for a memory system from a process, the memory system including a first channel having a first channel utilization and a second channel having a second channel utilization. In some embodiments, the first channel and the second channel may be implemented, for example, in a storage device. At operation 1706, the method may select the first channel based on the first channel utilization and the second channel utilization. In some embodiments, the first channel may be selected based on a balanced random strategy, a least used channel priority service strategy, etc. At operation 1708, the method may allocate memory pages from the first channel to the process. In some embodiments, the allocated pages may be dynamically mapped within the first channel. The method may end at operation 1710.

[0131] Figure 17 The illustrated embodiments and all other embodiments described herein are example operations and / or components. In some embodiments, some operations and / or components may be omitted and / or other operations and / or components may be included. In addition, in some embodiments, the temporal and / or spatial order of operations and / or components may change. Although some components and / or operations may be shown as separate components, in some embodiments, some components and / or operations shown separately may be integrated into a single component and / or operation, and / or may be shown as a single component and / or operation. Some components and / or operations may be implemented with multiple components and / or operations.

[0132] Some of the embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to these or any other specific details. For example, a function may be described as being implemented by certain components, but in other embodiments, the function may be distributed across different systems and components in different locations and with various user interfaces. Some embodiments have been described as having specific processes, operations, etc., but these terms also encompass embodiments in which a specific process, operation, etc. may be implemented by multiple processes, operations, etc., or in which multiple processes, operations, etc. may be integrated into a single process, step, etc. Reference to a component or element may refer to only a portion of the component or element. For example, reference to a block may refer to the entire block or one or more sub-blocks. Terms such as "first" and "second" may be used in this disclosure and claims solely to distinguish the items they modify and may not indicate any spatial or temporal order unless otherwise apparent from the context. In some embodiments, reference to an item may refer to at least a portion of the item; for example, "based on" may mean "based at least in part on," etc. Reference to a first element may not imply the existence of a second element. The principles disclosed herein have independent utility and can be embodied independently, and not every embodiment may utilize every principle. However, these principles can also be embodied in various combinations, some of which can amplify the benefits of the individual principles in a synergistic manner.

[0133] According to the inventive principle disclosed in this patent, the above-mentioned various details and embodiments can be combined to produce another embodiment. Because the inventive principle disclosed in this patent can be modified in arrangement and details without departing from the concept of the invention, these changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method for memory allocation, the method comprising: receiving a memory allocation request for a memory system from a process, the memory system including a first channel having a first channel utilization and a second channel having a second channel utilization; wherein the memory system includes one or more memory pages arranged in a first page group and a second page group, wherein the first page group and the second page group correspond to a number of unallocated pages; performing a first selection of the first channel based on the first channel utilization and the second channel utilization; performing a second selection of a first page group based on the first selection, wherein the first page group includes the first channel; and allocating a memory page from a first page group to the process, The first option includes: The ticket value is initialized by calculating a random number modulo the total number of free pages across all channels. Compare the ticket's value to the number of free pages in the first pass, and If the value of the ticket is less than or equal to the number of free pages in the first channel, the first channel is selected. 2 . The method of claim 1 , wherein performing the first selection comprises selecting the first channel based on an amount of free memory in the first channel, an amount of free memory in the second channel, and a random number.

3. The method of claim 1 , wherein performing the first selection comprises: Generates a value based on a random number and the number of free pages; Compare this value with the number of free pages in the first channel; as well as A first channel is selected based on the comparison. The method of claim 1 , wherein performing the first selection comprises selecting the first channel based on a least used channel policy.

5. The method of claim 1 , wherein performing the first selection comprises: comparing a first number of free pages of the first channel with a second number of free pages of the second channel; as well as A first channel is selected based on the comparison. The method of claim 1 , wherein the page frame number of the memory page from the first page group includes a channel identifier portion.

7. The method according to claim 1, wherein: The memory allocation request includes a requested order; and The allocating includes examining a first set of one or more page lists, wherein the one or more page lists of the first set are based on a first order and arranged by channel.

8. The method according to claim 7, wherein: A first list of the one or more page lists of the first set corresponding to the first channel includes entries for pages of the requested order; and The allocating further includes allocating the page of the requested order from a first list of the one or more page lists of the first set to the process. 9 . The method of claim 7 , wherein the allocating further comprises examining a second set of one or more page lists, wherein the one or more page lists of the second set are based on a second order and arranged by channel.

10. The method according to claim 9, wherein: A first list of the one or more page lists of the second set corresponding to the first channel includes entries for pages of the requested order; and The allocating further includes allocating the page of the requested order from a first list of the one or more page lists of the second set to the process.

11. The method according to claim 1 , wherein: The memory system includes a first media core and a second media core; The first channel is associated with the first dielectric core; and The second channel is associated with the second dielectric core.

12. The method of claim 1, wherein: The memory system includes a first device having a first device utilization and a second device having a second device utilization; The first channel and the second channel are associated with the first device; as well as The method also includes selecting a first device for the memory allocation request based on the first device utilization and the second device utilization.

13. A system for memory allocation, comprising: The first storage device includes: a first channel having a first channel utilization; and a second channel having a second channel utilization; a second storage device; and Channel selection logic, configured as: performing a first selection of the first storage device based on the memory allocation request, a first channel utilization of the first storage device, and a second channel utilization of the second storage device; performing a second selection of a first page group based on the memory allocation request, the first selection, the first channel utilization, and the second channel utilization, wherein the first page group includes the first channel and wherein the first page group corresponds to the number of unallocated pages; and Allocate memory pages for the first page group, The first option includes: The ticket value is initialized by calculating a random number modulo the total number of free pages across all channels. Compare the ticket's value to the number of free pages in the first pass, and If the value of the ticket is less than or equal to the number of free pages in the first channel, the first channel is selected.

14. The system of claim 13, wherein: The first memory device includes a first memory coherence interface; and The second memory device includes a second memory coherence interface.

15. The system of claim 14, wherein the memory page is configured as device attached memory.

16. The system of claim 13, wherein: The first storage device includes a first media core and a second media core; The first channel is associated with the first dielectric core; and The second channel is associated with the second dielectric core.

17. An apparatus comprising: A memory allocator is configured to receive a memory allocation request from a process, the memory allocator including channel selection logic configured to: selecting the first memory channel based on a first channel utilization of the first memory channel, a second channel utilization of the second memory channel, and a random policy; as well as performing selection of a first page group based on a first memory channel, wherein the first page group includes the first memory channel and wherein the first page group corresponds to the number of unallocated pages; and allocating one or more memory pages from a first page group to the process, The selecting of the first memory channel includes: The ticket value is initialized by calculating a random number modulo the total number of free pages across all channels. Compare the ticket's value to the number of free pages in the first pass, and If the value of the ticket is less than or equal to the number of free pages in the first channel, the first channel is selected.

18. The apparatus according to claim 17, wherein: The first memory channel is associated with a first device having a first device utilization; The second memory channel is associated with a second device having a second device utilization; as well as The memory allocator also includes device selection logic configured to select the first device for the memory allocation request based on the first device utilization and the second device utilization.

19. The apparatus of claim 17, wherein the memory allocator further comprises page allocation logic configured to allocate the one or more memory pages from the first page group based on an order of the memory allocation request.

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