Receiver, Memory, and Testing Method

Abstract

An embodiment of the present invention provides a receiver, a memory, and a test method. The receiver includes: a signal receiving module, which includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is used to receive a reference signal, and the gate of the second MOS transistor is used to receive a data signal to output a comparison signal, where the comparison signal is used to represent the magnitude relationship between the voltage value of the reference signal and the voltage value of the data signal; an adjustment module, which includes a third MOS transistor. The source of the third MOS transistor is connected to the source of the first MOS transistor, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the gate of the third MOS transistor is used to receive an adjustment signal. The embodiment of the present invention is beneficial to expanding the range of the effective recognition window of the data signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductors, and particularly to a receiver, a memory, and a test method. Background Art

[0002] Under normal circumstances, during the product design process, signal integrity simulation and testing of the memory are required, mainly from the aspects of signal quality and signal timing for inspection and verification.

[0003] An important step in memory testing is the RMT test (Rank Margining Test). The parameters obtained from the RMT test include TxV- and TxV+, and these two parameters are used to characterize the maximum window within which the data receiver of the memory can correctly identify the data signal in the voltage direction. At high speeds, due to the deterioration of the data signal quality, the maximum window characterized by the above parameters will shrink. To expand the maximum window, generally, a CTLE (Continuous Time Linear Equalizer) equalizer and a DFE (Decision Feedback Equalization) equalizer are used. Summary of the Invention

[0004] Embodiments of the present invention provide a receiver, a memory, and a test method, which are beneficial to expanding the range of the effective identification window of the data signal.

[0005] To solve the above problems, an embodiment of the present invention provides a receiver, including: a signal receiving module, including a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor is used to receive a reference signal, the gate of the second MOS transistor is used to receive a data signal to output a comparison signal, and the comparison signal is used to characterize the magnitude relationship between the voltage value of the reference signal and the voltage value of the data signal; an adjustment module, including a third MOS transistor, the source of the third MOS transistor is connected to the source of the first MOS transistor, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the gate of the third MOS transistor is used to receive an adjustment signal.

[0006] Correspondingly, an embodiment of the present invention further provides a memory including the receiver of any one of the above.

[0007] Accordingly, an embodiment of the present invention further provides a testing method, including: providing the receiver described in any one of the above; controlling the third MOS transistor to be cut off; inputting a data signal to the signal receiving module and adjusting the voltage value of the reference signal according to a first step length to obtain a plurality of comparison signals, denoted as first comparison signals; if the magnitude relationship represented by the comparison signal is the same as the magnitude relationship between the data signal and the reference signal, it is denoted as a valid signal; obtaining a first voltage value range of the reference signal corresponding to all the valid signals in the first comparison signals, and obtaining the intermediate value and the minimum value of the first voltage value range, where the minimum value is denoted as the first minimum value; inputting the data signal to the signal receiving module and adjusting the voltage value of the reference signal according to the first step length, and when the voltage value of the reference signal is less than or equal to the intermediate value, inputting an adjustment signal to turn on the third MOS transistor to obtain a plurality of comparison signals, denoted as second comparison signals; obtaining a second voltage value range of the reference signal corresponding to all the valid signals in the second comparison signals, and obtaining the minimum value of the second voltage value range, denoted as the second minimum value.

[0008] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0009] In the above technical solution, the third MOS transistor is connected in parallel with the first MOS transistor, and the current value flowing through the third MOS transistor is controlled by the voltage value of the adjustment signal. If the third MOS transistor is controlled to receive the adjustment signal when the first MOS transistor is turned on, the conduction current corresponding to the reference signal changes from the conduction current of the first MOS transistor itself to the sum of the conduction current of the first MOS transistor and the conduction current of the third MOS transistor. In other words, the conduction current that originally required a relatively large reference signal voltage can now be achieved with a relatively small reference signal voltage. Thus, it is beneficial to lower the minimum value of the voltage window for the receiver to correctly identify the data signal, thereby expanding the voltage window.

[0010] In addition, controlling the aspect ratio of the first MOS transistor and the aspect ratio of the third MOS transistor to be greater than 4 is beneficial to enabling the third MOS transistor to only play a fine-tuning role and avoiding the setting of the third MOS transistor from weakening or even partially invalidating the function of the first MOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0012] Figure 1 It is a schematic structural diagram of the receiver provided by the embodiment of the present invention;

[0013] Figure 2 A testing method provided by an embodiment of the present invention;

[0014] Figure 3 A shmoo diagram provided by an embodiment of the present invention;

[0015] Figure 4 Another testing method provided by an embodiment of the present invention. Detailed implementation manners

[0016] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0017] Referring to Figure 1 , the receiver includes: a signal receiving module 10, including a first MOS transistor M1 and a second MOS transistor M2. The gate of the first MOS transistor M1 is used to receive a reference signal 10a, and the gate of the second MOS transistor M2 is used to receive a data signal 10b to output a comparison signal 10c, and the comparison signal 10c is used to represent the magnitude relationship between the voltage value of the reference signal 10a and the voltage value of the data signal 10b; an adjustment module 20, including a third MOS transistor M3. The source of the third MOS transistor M3 is connected to the source of the first MOS transistor M1, the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1, and the gate of the third MOS transistor M3 is used to receive an adjustment signal 20a.

[0018] In some embodiments, the ratio of the aspect ratio of the first MOS transistor M1 to the aspect ratio of the third MOS transistor M3 is greater than 4. In this way, it is beneficial to make the third MOS transistor M3 only play a fine-tuning role, avoid the setting of the third MOS transistor M3 from weakening or even partially invalidating the function of the first MOS transistor M1, and make the first MOS transistor M1 dominate the adjustment of the voltage value of the reference signal 10a.

[0019] In some embodiments, the adjustment module 20 further includes an adjustment unit 21 configured to receive an external signal 20b and an adjustment code 20c to output an adjustment signal 20a; the external signal 20b is used to generate the adjustment signal 20a, and each adjustment code 20c corresponds to a voltage value of the adjustment signal 20a. When the parameters of the third MOS transistor M3 and the voltage value of the adjustment signal 20a are determined, the conduction degree of the third MOS transistor M3 is determined; when the circuit structure connected to the third MOS transistor M3 is determined, the conduction degree of the third MOS transistor M3 corresponds to a conduction current. That is to say, each adjustment code 20c corresponds to a conduction current of the third MOS transistor M3.

[0020] Specifically, the adjustment unit 21 includes: an operational amplifier 211 and a plurality of series resistors (not labeled). The operational amplifier 211 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is configured to receive the external signal 20b. A first resistor unit 212 is connected in series between the inverting input terminal and the output terminal. The first resistor unit 212 includes a first number of resistors connected in series. A second resistor unit 213 is connected in series between the inverting input terminal and the ground terminal. The second resistor unit 213 includes a second number of resistors connected in series; a variable resistor unit (not shown) configured to receive the adjustment code 20c and control the connection between the gate of the third MOS transistor M3 and the remote end of a resistor. It should be noted that each resistor has a near-ground end and a remote end. If there is current passing through the resistor, the voltage of the remote end is greater than the voltage of the near-ground end; in addition, the first number and the second number are natural numbers greater than or equal to 1. It should be noted that although the gate of the third MOS transistor M3 in the receiver shown in Figure 1 is connected to the first resistor unit 212, in fact, the gate of the third MOS transistor M3 can be connected to the remote end of any resistor in the first resistor unit 212 and the second resistor unit 213.

[0021] In this embodiment, the external signal 20b is the reference signal 10a. In this way, there is no need to set a dedicated external signal 20b, and the reference signal 10a can be reused, which is beneficial to saving circuit area; at the same time, since the voltage of the inverting input terminal of the operational amplifier 211 is equal to the voltage of the non-inverting input terminal, if the reference signal 10a is set as the external signal 20b, the voltage value of the adjustment signal 20a is adjusted centered on the voltage value of the reference signal 10a, and the difference between the voltage value of the adjustment signal 20a and the voltage value of the reference signal 10a is small. The VGS adjustment difficulty of the third MOS transistor M3 is low. In this way, it is beneficial to ensure that the third MOS transistor M3 can be turned on when the first MOS transistor M1 is turned on, and the conduction current of the third MOS transistor M3 can be finely adjusted.

[0022] In some embodiments, the receiver further includes a control module 30, connected to the enable terminal of the adjustment unit 21, for receiving a first code 30a and a second code 30b, and outputting an enable signal 30c. Each first code 30a corresponds to a voltage value of the reference signal 10a, and the second code 30b corresponds to a preset voltage. The enable signal 30c is used to turn off or enable the adjustment unit 21. If the control module 30 is in an enabled state and the voltage value corresponding to the first code 20a is less than the preset voltage, the enable signal 30c enables the adjustment unit 21.

[0023] In some embodiments, the control module 30 is further configured to receive a switch signal 30d, and the switch signal 30d is used to turn off or enable the control module 30. The switch signal has an on level and an off level. If the switch signal 30d is at the on level, the control module 30 is enabled. If the switch signal 30d is at the off level, the control module 30 is turned off. Among them, the on level can be one of a high level or a low level, and the off level can be the other of a high level or a low level. In this article, the on level is taken as an example of a high level and the off level is taken as an example of a low level for illustration.

[0024] In some embodiments, the receiver further includes an auxiliary unit 40, connected to the third MOS transistor M3, for receiving the enable signal 30c. If the enable signal 30c is at a first level, the enable signal 30c enables the adjustment unit 21 and turns on the third MOS transistor M3. If the enable signal 30c is at a second level, the enable signal 30c turns off the adjustment unit 21 and turns off the third MOS transistor M3.

[0025] In some embodiments, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are NMOS transistors, the first level is a low level, and the second level is a high level. The auxiliary unit 40 includes a fourth MOS transistor M4, and the fourth MOS transistor M4 is an NMOS transistor. The gate of the fourth MOS transistor M4 is used to receive the enable signal 30c, the drain is connected to the gate of the third MOS transistor M3, and the source is grounded. That is to say, when the enable signal 30c is at a low level, the adjustment unit 21 is enabled, the fourth MOS transistor M4 is turned off, and the gate of the third MOS transistor M3 is controlled by the adjustment signal 20a. When the enable signal 30c is at a high level, the adjustment unit 21 is turned off, the fourth MOS transistor M4 is turned on, and the gate voltage of the third MOS transistor M3 is pulled low so that the third MOS transistor M3 is turned off.

[0026] In some embodiments, the receiver further includes a reference signal generator 40, configured to receive the first code 30a and generate a reference signal 10a with a corresponding voltage value based on the first code 30a. The reference signal 10a generated by the reference signal generator 40 can be input to the gate of the first MOS transistor M1 and / or the non-inverting input terminal of the operational amplifier 211.

[0027] In some embodiments, the signal receiving module 10 includes: a signal amplifying unit 11, including a first MOS transistor M1 and a second MOS transistor M2, and having a first output terminal (not labeled) and a second output terminal (not labeled), the first output terminal is used to output a reference amplified signal 11a, the second output terminal is used to output a data amplified signal 11b, and the absolute value of the difference between the voltage values of the reference amplified signal 11a and the data amplified signal 11b is greater than the absolute value of the difference between the voltage values of the reference signal 10a and the data signal 10b; a data comparison unit 12, the first input terminal of the data comparison unit 12 is used to receive the reference amplified signal 11a, the second input terminal of the data comparison unit 12 is used to receive the data amplified signal 11b, and the output terminal of the data comparison unit 12 is used to output a comparison signal 10c.

[0028] In some embodiments, the types and sizes of the first MOS transistor M1 and the second MOS transistor M2 are the same; the drain of the first MOS transistor M1 is used to connect to a first load R1, the drain of the second MOS transistor M2 is used to connect to a second load R2, and the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to the same current source.

[0029] In this embodiment, a third MOS transistor M3 is connected in parallel with the first MOS transistor M1, and the current value flowing through the third MOS transistor is controlled by the voltage value of an adjustment signal. If the third MOS transistor M3 is controlled to receive the adjustment signal when the first MOS transistor M1 is conducting, then the conduction current corresponding to the reference signal 10a changes from the conduction current of the first MOS transistor M1 itself to the sum of the conduction current of the first MOS transistor M1 and the conduction current of the third MOS transistor M3. In other words, the conduction current that originally required the reference signal 10a to have a relatively large voltage value can now be achieved by the reference signal 10a with a relatively small voltage value. Thus, it is beneficial to lower the minimum value of the voltage window for the receiver to correctly identify the data signal, thereby expanding the voltage window.

[0030] Correspondingly, an embodiment of the present invention further provides a memory, including the receiver described in any one of the above. The memory including the above receiver has a relatively large data recognition window, which is beneficial for passing the RMT test during the product design process.

[0031] Correspondingly, an embodiment of the present invention further provides a test method for obtaining the voltage value of an adjustment signal to be determined. Refer to Figures 1 to 3 , the test method includes the following steps:

[0032] Step S11: Provide the receiver described in any one of the above and control the third MOS transistor to be cut off.

[0033] By controlling the third MOS transistor M3 to be turned off, the initial data recognition window of the signal receiving module 10 can be detected. The data recognition window refers to the situation where the representative data signal 10b obtained by scanning the reference signal 10a can be correctly recognized when the waveform of the data signal 10b is fixed. The data recognition window is generally represented by a shmoo diagram, where TxV+ represents the maximum voltage value of the data recognition window, and TxV- represents the minimum voltage value of the data recognition window.

[0034] Furthermore, scanning the reference signal 10 a refers to adjusting the voltage value of the reference signal 10 a in an order from small to large or from large to small according to a specific step size.

[0035] Step S12: inputting a data signal into the signal receiving module and adjusting the voltage value of the reference signal according to the first step to obtain a comparison signal, which is recorded as a first comparison signal.

[0036] Each comparison signal 10c is used to represent the magnitude relationship between a voltage value of the reference signal 10a and the voltage value of the data signal 10b. During the scanning process of the reference signal 10a, multiple comparison signals 10c, i.e., multiple first comparison signals, can be obtained. Due to factors such as the waveform integrity of the data signal 10b and the resolution of the signal receiving module, some comparison signals 10c may not accurately represent the magnitude relationship between the voltage values of the data signal 10b and the reference signal 10a. Only some comparison signals 10c can correctly represent the magnitude relationship. Therefore, herein, a comparison signal 10c is considered valid if the magnitude relationship represented by it is the same as the magnitude relationship between the data signal 10b and the reference signal 10a.

[0037] Step S13: obtaining a voltage value range of the reference signal corresponding to all valid signals in the first comparison signal, recorded as a first voltage value range, and obtaining an intermediate value and a minimum value of the first voltage value range, recorded as a first minimum value.

[0038] The comparison signal 10c is generated based on the reference signal 10a and the data signal 10b. Each comparison signal 10c has a corresponding reference signal 10a. The voltage value range of the reference signal 10a corresponding to the valid signal in the comparison signal forms a shmoo diagram. When the third MOS transistor M3 is turned off and the reference signal 10a is scanned, the obtained shmoo diagram represents the initial data recognition window of the signal receiving module 10. Figure 3 Left: The initial data recognition window has a maximum value and an intermediate value T mid and minimum values, the maximum value is recorded as the first maximum value TxV+1, and the minimum value is recorded as the first minimum value TxV-1.

[0039] Step S14: Input a data signal into the signal receiving module and adjust the voltage value of the reference signal according to the first step length. When the voltage value of the reference signal is less than or equal to the intermediate value, input an adjustment signal to turn on the third MOS transistor to obtain a plurality of comparison signals, denoted as the second comparison signals.

[0040] During the process of obtaining the second comparison signals, the waveform of the data signal 10b is fixed, and only when the voltage value of the reference signal 10a is less than or equal to the intermediate value T mid is the third MOS transistor M3 controlled to turn on, which is beneficial to avoiding the third MOS transistor M3 from simultaneously pulling down the maximum value and the minimum value of the data recognition window, that is, the first maximum value TxV + 1 and the first minimum value TxV - 1, so that the setting of the third MOS transistor M3 only pulls down the first minimum value TxV - 1, thereby expanding the voltage range of the data recognition window.

[0041] Step S15: Obtain the voltage value range of the reference signal corresponding to all valid signals in the second comparison signals, denoted as the second voltage value range, and obtain the minimum value of the second voltage value range, denoted as the second minimum value.

[0042] The purpose of this step is to verify whether the setting of the adjustment signal realizes the pulling down of the voltage minimum value in the data recognition window, and to measure the relationship between the voltage value of the adjustment signal and the pulling down amplitude. If, as Figure 3 shown in the right figure, the minimum value of the data recognition window is further pulled down to the second minimum value TxV - 2, then it is determined that the voltage minimum value in the data recognition window is further pulled down; in addition, the pulling down amplitude can be either a voltage difference or a ratio value. The voltage difference can be calculated by subtracting the second minimum value TxV - 2 from the first minimum value TxV - 1, and the ratio value can be calculated by dividing the difference between the first minimum value TxV - and the second minimum value TxV - 2 by the difference between the first maximum value TxV + 1 and the first minimum value TxV - 1. In this article, it is described that the pulling down amplitude refers to the voltage difference.

[0043] In some embodiments, it is necessary to control the voltage value of the adjustment signal 2OA so that the difference between the pulled - down minimum value and the first minimum value TxV - 1 is greater than or equal to a preset threshold. Therefore, after obtaining the second minimum value TxV - 2, the following steps are further included:

[0044] Step S16, determine whether the difference between the second minimum value TxV - 2 and the first minimum value TxV - 1 is greater than or equal to the preset threshold.

[0045] If the difference is greater than or equal to the preset threshold, it indicates that the current voltage value of the adjustment signal 20a meets the requirements, then record the current voltage value of the adjustment signal 20a and end the test process; if it is less than the preset threshold, then it is necessary to adjust the voltage value of the adjustment signal 20a to further pull down the voltage minimum value of the data recognition window, that is, execute step S17.

[0046] Step S17: adjusting the voltage value of the adjustment signal according to the second step length to obtain a comparison signal, which is recorded as the Nth comparison signal.

[0047] After adjusting the voltage of the adjustment signal 20a once according to the second step size, the data signal 10b is input to the signal receiving module 10 and the voltage of the reference signal 10a is adjusted according to the first step size to obtain a corresponding comparison signal 10c, which is recorded as the Nth comparison signal. N is a natural number greater than or equal to 3, and the value of N increases with the number of times the adjustment signal 20a is adjusted. In other words, each time the voltage of the adjustment signal 20a is adjusted according to the second step size, the voltage of the reference signal 10a needs to be re-scanned (assuming that the waveform of the data signal 10b is fixed and continuously input).

[0048] The second step size can be either a positive value or a negative value. That is, the voltage value of the adjustment signal 20a can be adjusted in a decreasing trend or in a decreasing trend. In the embodiment of the present invention, the voltage value of the adjustment signal 20a is adjusted in a decreasing trend. In this way, before the voltage value of the adjustment signal 20a meets the requirement, the conduction current of the third MOS transistor M3 is relatively low, ensuring that the third MOS transistor M3 only serves a fine-tuning function.

[0049] In addition, the voltage value adjustment of the adjustment signal 20a is independent of the input time of the adjustment signal 20a. In the process of scanning the voltage value of the reference signal 10a, the adjustment signal 20a is always adjusted when the voltage value of the reference signal 10a is less than or equal to the intermediate value T mid In the case of , it is input to the gate of the third MOS tube M3. Figure 1 Taking the receiver shown in FIG. as an example, after the voltage value of the adjustment signal 20a does not meet the requirement, the operational amplifier 211 is turned off and the output of the adjustment signal 20a is stopped. The resistance variable unit controls the gate of the third MOS transistor M3 to be connected to the remote end of another resistor according to the new adjustment code 20c. The new adjustment code 20c corresponds to the voltage value of the adjustment signal 20a adjusted according to the second step size. After the connection relationship of the third MOS transistor M3 is adjusted, the voltage value of the reference signal 10a is rescanned, and when the voltage value of the reference signal 10a is less than or equal to the intermediate value T mid The operational amplifier 211 is enabled at this time. At this time, the adjustment unit 21 outputs a new adjustment signal 20a according to the new adjustment code 20c to obtain the comparison signal 10c.

[0050] Step S18: obtaining a voltage value range of the reference signal corresponding to all valid signals in the Nth comparison signal, recorded as the Nth voltage value range, and obtaining a minimum value of the Nth voltage value range, recorded as the Nth minimum value.

[0051] This step is similar to step S16 and is used to verify whether the voltage value adjustment in the previous step can meet the requirements, that is, whether the difference between the first minimum value TxV-1 and the Nth minimum value is greater than or equal to the preset threshold.

[0052] Step S19: Determine whether the difference between the first minimum value and the Nth minimum value is greater than or equal to the preset threshold.

[0053] If it is greater than or equal to the preset threshold, it means that the voltage value of the adjustment signal 20a corresponding to the Nth comparison signal meets the requirements. The current voltage value of the adjustment signal 20a can be recorded and the test can be terminated. If it is less than the preset threshold, steps S17 and step 18 are looped, that is, the voltage value of the adjustment signal 20a is repeatedly adjusted according to the second step length until the difference between the Nth minimum value corresponding to the Nth comparison signal and the first minimum value TxV-1 is greater than or equal to the preset threshold.

[0054] In some embodiments, it is necessary to control the voltage value of the adjustment signal 20a so that the data recognition window has the smallest minimum value. Specifically, if after adjusting the voltage value of the adjustment signal 20a, the minimum value of the data recognition window is greater than or equal to the previous minimum value, it is considered that the previous minimum value has reached the limit value and cannot be further pulled down. At the same time, although theoretically the second minimum value TxV-2 is less than the first minimum value TxV-1, in order to improve the accuracy of the test, it is necessary to verify the actual voltage value of the second minimum value TxV-2. Therefore, after obtaining the second minimum value TxV-2, refer to Figure 4 , the following steps also need to be performed:

[0055] Step S20: Determine whether the second minimum value is greater than or equal to the first minimum value.

[0056] If the second minimum value TxV-2 is greater than or equal to the first minimum value TxV-1, it means that the setting of the adjustment signal 20a has not played a role. At this time, the test is aborted and the reason is checked. If the second minimum value TxV-2 is less than the first minimum value TxV-1, it means that the setting of the adjustment signal 20a is working properly. At this time, it is necessary to detect whether the second minimum value TxV-2 is the limit value of the minimum value of the data recognition window.

[0057] Step S21: Adjust the voltage value of the adjustment signal according to the second step length to obtain a comparison signal, denoted as the third comparison signal

[0058] Step S22: Obtain the voltage value range of the reference signals corresponding to all valid signals in the third comparison signal, and obtain the minimum value of the voltage value range, denoted as the third minimum value.

[0059] Steps S21 and S22 are used to obtain the third minimum value. By comparing the magnitude relationship between the third minimum value and the second minimum value TxV-2, it can be determined whether the second minimum value TxV-2 is the limit value of the minimum value.

[0060] Step S23: Determine whether the third minimum value is greater than or equal to the second minimum value TxV-2.

[0061] If the third minimum value is greater than or equal to the second minimum value TxV-2, it is considered that the minimum value of the data recognition window cannot be further lowered, and the second minimum value TxV-2 has reached the limit value of the minimum value. If the third minimum value is less than the second minimum value TxV-2, it indicates that there is still room to further lower the minimum value of the data recognition window. At this time, the voltage value of the adjustment signal 20a needs to be adjusted again according to the second step size until the Nth minimum value corresponding to the Nth comparison signal is greater than or equal to the (N-1)th minimum value. Here, N is a natural number greater than or equal to 4.

[0062] The specific steps are as follows: Step S24: Adjust the voltage value of the adjustment signal again according to the second step size to obtain a comparison signal, denoted as the Nth comparison signal. Step S25: Obtain the voltage value range of the reference signals corresponding to all valid signals in the N comparison signals, and obtain the minimum value of the voltage value range, denoted as the Nth minimum value. S26: Determine whether the Nth minimum value is greater than or equal to the (N-1)th minimum value. If the Nth minimum value is greater than or equal to the (N-1)th minimum value, it indicates that the (N-1)th minimum value has reached the limit value of the minimum value. At this time, record the voltage value of the adjustment signal 20a and end the test. If the Nth minimum value is less than the (N-1)th minimum value, it indicates that the minimum value of the data recognition window may be further lowered. At this time, loop through steps S24 to S26 until the Nth minimum value is greater than or equal to the (N-1)th minimum value. At this time, the (N-1)th minimum value is considered the limit minimum value of the data recognition window.

[0063] In this embodiment, a test method is provided to test the influence of the setting of the adjustment signal on the minimum value of the data recognition window. In other words, it tests whether the setting of the adjustment signal broadens the voltage value range of the data recognition window and determines the voltage value of the adjustment signal that meets the requirements of the data recognition window voltage value range to ensure that the receiver has a larger data recognition window.

[0064] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present invention. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. A receiver, characterized in that, Comprising: A signal receiving module, including a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is used to receive a reference signal, and the gate of the second MOS transistor is used to receive a data signal to output a comparison signal, where the comparison signal is used to characterize the magnitude relationship between the voltage value of the reference signal and the voltage value of the data signal; An adjustment module, including a third MOS transistor. The source of the third MOS transistor is connected to the source of the first MOS transistor, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the gate of the third MOS transistor is used to receive an adjustment signal; The adjustment module further includes: An adjustment unit, configured to receive an external signal and an adjustment code to output the adjustment signal; The external signal is used to generate the adjustment signal, and each adjustment code corresponds to a voltage value of the adjustment signal.

2. The receiver according to claim 1, wherein The ratio of the aspect ratio of the first MOS transistor to the aspect ratio of the third MOS transistor is greater than 4.

3. The receiver according to claim 1, characterized in that, The adjustment unit includes: An operational amplifier and a plurality of series resistors. The operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is used to receive the external signal, a first number of resistors are connected in series between the inverting input terminal and the output terminal, and a second number of resistors are connected in series between the inverting input terminal and the ground terminal; A variable resistance unit, configured to receive the adjustment code and control the connection between the gate of the third MOS transistor and the remote end of one of the resistors according to the adjustment code.

4. The receiver according to claim 1, wherein, The external signal is the reference signal.

5. The receiver according to claim 1, characterized in that, It further includes: A control module, connected to the enable terminal of the adjustment unit, configured to receive a first code and a second code, and output an enable signal. Each first code corresponds to a voltage value of the reference signal, the second code corresponds to a preset voltage, and the enable signal is used to turn off or enable the adjustment unit; If the control module is in an enabled state and the voltage value corresponding to the first code is less than the preset voltage, the enable signal enables the adjustment unit.

6. The receiver according to claim 5, characterized in that, The control module is further configured to receive a switch signal, where the switch signal is used to turn off or enable the control module.

7. The receiver according to claim 5, characterized in that, It further includes: An auxiliary unit, connected to the gate of the third MOS transistor, configured to receive the enable signal; If the enable signal is at a first level, the enable signal enables the adjustment unit and turns on the third MOS transistor. If the enable signal is at a second level, the enable signal turns off the adjustment unit and turns off the third MOS transistor.

8. The receiver according to claim 7, wherein The first MOS transistor, the second MOS transistor, and the third MOS transistor are NMOS transistors. The first level is a low level, and the second level is a high level; the auxiliary unit includes: a fourth MOS transistor, which is an NMOS transistor. The gate of the fourth MOS transistor is used to receive the enable signal, the drain is connected to the gate of the third MOS transistor, and the source is grounded.

9. The receiver according to claim 5, wherein, It further includes: A reference signal generator, configured to receive the first code and generate the reference signal with a corresponding voltage value based on the first code.

10. The receiver according to claim 1, wherein The signal receiving module includes: The signal amplification unit includes the first MOS transistor and the second MOS transistor, and has a first output terminal and a second output terminal. The first output terminal is used to output a reference amplified signal, and the second output terminal is used to output a data amplified signal. The absolute value of the difference between the voltage values of the reference amplified signal and the data amplified signal is greater than the absolute value of the difference between the voltage values of the reference signal and the data signal. The data comparison unit, the first input terminal of the data comparison unit is used to receive the reference amplified signal, the second input terminal of the data comparison unit is used to receive the data amplified signal, and the output terminal of the data comparison unit is used to output the comparison signal.

11. The receiver according to claim 9, characterized in that The types and sizes of the first MOS transistor and the second MOS transistor are the same; the drain of the first MOS transistor is used to connect to a first load, the drain of the second MOS transistor is used to connect to a second load, and the sources of the first MOS transistor and the second MOS transistor are connected to the same current source.

12. A memory, characterized in that, It includes the receiver according to any one of claims 1 to 11.

13. A testing method, characterized in that, It includes: Providing the receiver according to any one of claims 1 to 11; Controlling the third MOS transistor to be cut off; Inputting a data signal to the signal receiving module and adjusting the voltage value of the reference signal according to a first step length to obtain a plurality of comparison signals, denoted as the first comparison signals; If the magnitude relationship represented by the comparison signal is the same as the magnitude relationship between the data signal and the reference signal, it is denoted as a valid signal; Obtaining the voltage value range of the reference signal corresponding to all the valid signals in the first comparison signals, denoted as the first voltage value range, and obtaining the intermediate value and the minimum value of the first voltage value range, and the minimum value is denoted as the first minimum value; Inputting the data signal to the signal receiving module and adjusting the voltage value of the reference signal according to the first step length, and when the voltage value of the reference signal is less than or equal to the intermediate value, inputting an adjustment signal to turn on the third MOS transistor to obtain a plurality of comparison signals, denoted as the second comparison signals; Obtaining the voltage value range of the reference signal corresponding to all the valid signals in the second comparison signals, denoted as the second voltage value range, and obtaining the minimum value of the second voltage value range, denoted as the second minimum value.

14. The test method according to claim 13, wherein If the difference between the second minimum value and the first minimum value is less than a preset threshold, adjust the voltage value of the adjustment signal according to a second step length until the difference between the Nth minimum value corresponding to the Nth comparison signal and the first minimum value is greater than or equal to the preset threshold, where N is a natural number greater than or equal to 3.

15. The test method according to claim 13, wherein After obtaining the second minimum value, adjust the voltage value of the adjustment signal according to the second step length to obtain the comparison signal, denoted as the third comparison signal; Obtain the voltage value range of the reference signal corresponding to all the valid signals in the third comparison signal, denoted as the third voltage value range, and obtain the minimum value of the third voltage value range, denoted as the third minimum value; if the third minimum value is greater than or equal to the second minimum value, record the voltage value of the adjustment signal and terminate the test; if the third minimum value is less than the second minimum value, adjust the voltage value of the adjustment signal again according to the second step size until the Nth minimum value corresponding to the Nth comparison signal is greater than or equal to the (N - 1)th minimum value, where N is a natural number greater than or equal to 4.

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