An in-aircraft bus network intermediate node

Abstract

The present invention belongs to the technical field of the security and reliability design of embedded computer systems, and particularly relates to an in-aircraft bus network intermediate node, which includes a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip; the present invention maximally suppresses the fault spread phenomenon caused by the physical layer faults of 1394B bus nodes to the entire network, so that the 1394B bus can be applied in systems with higher security and reliability requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of the security and reliability design of embedded computer systems, and particularly relates to an in-aircraft bus network intermediate node. Background Art

[0002] The 1394B serial bus has a communication rate of over 100 megabits. Devices are connected in a cascaded manner, and in the logical layer, it can form network topologies such as daisy chains and trees. It has two significant features. First, it can form a physical loop connection. After identifying the loop physical path, the connection of the formed loop can be automatically disconnected. If a network disconnection occurs in other nodes during real-time operation, the physical layer can be reset and restarted, and the original loop connection segment can be used to reorganize the network to build a topology to achieve the integrity of communication among network nodes, with the reliability of one-time fault tolerance. Second, since the physical connection for networking uses the node port cascading method, there is no need to add additional data communication switching devices for the construction of the entire network, which enables control of factors such as the complexity, cost, and weight of the network system. Therefore, the 1394B bus is very suitable for the application of embedded systems. Although the 1394B already has the ability of one-time fault tolerance, it still has deficiencies in embedded application scenarios with higher requirements for reliability and security. The 1394B bus relies on node port cascading for networking, and network data communication needs to be realized through node forwarding, that is, the data received by one port within a node needs to be forwarded to another port within the node through a physical layer protocol chip before it can be circulated in the network. This brings a problem. If the physical layer protocol chip of a node fails, or a failure occurs within the node itself resulting in the inability of the physical layer to forward data, the disconnection of the node will cause the entire network to break. Summary of the Invention

[0003] In view of this, the present invention proposes an in-aircraft bus network intermediate node to maximize the suppression of the fault spread phenomenon caused by the physical layer fault of the 1394B bus node to the entire network, so that the 1394B bus can be applied in systems with higher security and reliability requirements.

[0004] To achieve the above technical objectives, the specific technical solutions adopted by the present invention are as follows:

[0005] An in-aircraft bus network intermediate node includes a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip;

[0006] The physical layer port is connected to the in-aircraft bus, and is used to convert the bus signal of the in-aircraft bus into an electrical signal recognizable by the physical layer protocol chip, and is also used to convert the electrical signal into a bus signal;

[0007] A physical layer protocol chip for performing protocol decoding, data identification, and data forwarding on the electrical signal;

[0008] The network intermediate node further includes a valid indication circuit and a bypass switch;

[0009] When one of the physical layer ports fails, the valid indication circuit outputs an indication signal;

[0010] After receiving the indication signal, the bypass switch disconnects the bus transmission between the failed physical layer port and the bus and transfers it to the bypass physical layer port.

[0011] Further, the bypass switch is provided with seven pins. The seventh pin is connected to the control end of the valid indication circuit. The first pin and the fourth pin are connected to the on-board bus. The second pin and the fifth pin are connected to the data transmission ports of the physical layer ports. The first pin is used to selectively connect to the second pin or the third pin of the bypass switch based on the control of the valid indication circuit. The fourth pin is used to selectively connect to the fifth pin or the sixth pin of the bypass switch based on the control of the valid indication circuit. The third pin and the sixth pin are connected to the bypass physical layer port.

[0012] Further, the physical layer protocol chip is a 1394B bus node physical layer protocol chip; the physical layer port is a 1394B bus node physical layer port 0; the bypass physical layer port is a 1394B bus node physical layer port 1; the bypass switch includes switches K1, K2, K3, and K4; the valid indication circuit is a 1394B bus node valid indication circuit;

[0013] Further, the connection relationships among the 1394B bus node physical layer protocol chip, the 1394B bus node physical layer port 0, the 1394B bus node physical layer port 1, switches K1, K2, K3, K4, and the 1394B bus node valid indication circuit are as follows:

[0014] The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 0 with signals TPA+, TPA-, TPB+, and TPB-;

[0015] The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 1 with signals TPA+, TPA-, TPB+, and TPB-;

[0016] The valid indication signals output by the 1394B bus node valid indication circuit are connected to pin 7 of switch K1, pin 7 of switch K2, pin 7 of switch K3, and pin 7 of switch K4;

[0017] When the valid indication signal indicates a valid state, switches K1, K2, K3, and K4 each internally connect pin 1 to their respective internal normally open contact pin 2, and switches K1, K2, K3, and K4 each internally connect pin 4 to their respective internal normally open contact pin 5;

[0018] When the valid indication signal indicates an invalid state, switches K1, K2, K3, and K4 each internally connect pin 1 to their respective internal normally closed contact pin 3, and switches K1, K2, K3, and K4 each internally connect pin 4 to their respective internal normally closed contact pin 6;

[0019] The name of pin 1 of switch K1 is defined to connect to 0_TPA+, pin 2 of K1 connects to the 0_TPA+ signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPA+ signal is associated with its TPA+ inside the physical layer port 0 interface of the 1394B bus node; the name of pin 4 of switch K1 is defined to connect to 0_TPA-, pin 5 of K1 connects to the 0_TPA- signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPA- signal is associated with its TPA- inside the physical layer port 0 interface of the 1394B bus node;

[0020] The name of pin 1 of switch K2 is defined to connect to 0_TPB+, pin 2 of K2 connects to the 0_TPB+ signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPB+ signal is associated with its TPB+ inside the physical layer port 0 interface of the 1394B bus node; the name of pin 4 of switch K2 is defined to connect to 0_TPB-, pin 5 of K2 connects to the 0_TPB- signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPB- signal is associated with its TPB- inside the physical layer port 0 interface of the 1394B bus node;

[0021] The name of pin 1 of switch K3 is defined to connect to 0_TPA+, pin 2 of K3 connects to the 0_TPA+ signal of the port 0 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPA+ signal is associated with its TPA+ inside the physical layer port 1 interface of the 1394B bus node; the name of pin 4 of switch K3 is defined to connect to 1_TPA-, pin 5 of K3 connects to the 1_TPA- signal of the port 1 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPA- signal is associated with its TPA- inside the physical layer port 1 interface of the 1394B bus node;

[0022] The pin 1 of switch K4 is defined to connect to 1_TPB+. The pin 2 of K4 is connected to the port 1_TPB+ signal of the port 1 interface of the physical layer port of the 1394B bus node. The port 1_TPB+ signal is associated with its TPB+ inside the port 1 interface of the physical layer port of the 1394B bus node. The pin 4 of switch K4 is defined to connect to 1_TPB-. The pin 5 of K4 is connected to the port 1_TPB- signal of the port 1 interface of the physical layer port of the 1394B bus node. The port 1_TPB- signal is associated with its TPB- inside the port 1 interface of the physical layer port of the 1394B bus node.

[0023] The pin 3 of switch K1 is connected to the pin 3 of switch K4. The pin 6 of K1 is connected to the pin 6 of K4. The pin 3 of switch K2 is connected to the pin 3 of switch K3. The pin 6 of K2 is connected to the pin 6 of K3. Brief Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0025] Figure 1 It is a schematic diagram of the principle of an in-aircraft bus network intermediate node in a specific embodiment of the present invention. Detailed Embodiments

[0026] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0027] The following specific examples illustrate the implementation manners of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of them. The present disclosure can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0028] Note that the following description relates to various aspects of embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device can be implemented and this method can be practiced using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0029] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present disclosure schematically. The diagrams only show the components related to the present disclosure and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects described can be practiced without these specific details.

[0031] In one embodiment of the present invention, an in-aircraft bus network intermediate node is proposed, which includes a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip;

[0032] The physical layer port is connected to the in-aircraft bus and is used to convert the bus signal of the in-aircraft bus into an electrical signal that the physical layer protocol chip can recognize, and is also used to convert the electrical signal into a bus signal;

[0033] The physical layer protocol chip is used to perform protocol decoding, data identification, and data forwarding on the electrical signal;

[0034] The network intermediate node further includes a valid indication circuit and a bypass switch;

[0035] The valid indication circuit outputs an indication signal when one of the physical layer ports fails;

[0036] After receiving the indication signal, the bypass switch disconnects the bus transmission between the failed physical layer port and the bus and transfers it to the bypass physical layer port.

[0037] In this embodiment, the bypass switch is provided with seven pins. The seventh pin is connected to the control end of the valid indication circuit. The first pin and the fourth pin are connected to the on-board bus. The second pin and the fifth pin are connected to the data transmission ports of the physical layer ports. The first pin is used to selectively connect to the second pin or the third pin of the bypass switch based on the control of the valid indication circuit. The fourth pin is used to selectively connect to the fifth pin or the sixth pin of the bypass switch based on the control of the valid indication circuit. The third pin and the sixth pin are connected to the bypass physical layer port.

[0038] In this embodiment, as Figure 1 shown, the physical layer protocol chip is a 1394B bus node physical layer protocol chip; the physical layer port is the 1394B bus node physical layer port 0; the bypass physical layer port is the 1394B bus node physical layer port 1; the bypass switch includes switches K1, K2, K3, and K4; the valid indication circuit is a 1394B bus node valid indication circuit;

[0039] In this embodiment, as Figure 1 shown, the connection relationships among the 1394B bus node physical layer protocol chip, the 1394B bus node physical layer port 0, the 1394B bus node physical layer port 1, switches K1, K2, K3, K4, and the 1394B bus node valid indication circuit are as follows:

[0040] The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 0 with signals TPA+, TPA-, TPB+, and TPB-;

[0041] The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 1 with signals TPA+, TPA-, TPB+, and TPB-;

[0042] The valid indication signals output by the 1394B bus node valid indication circuit are connected to pin 7 of switch K1, pin 7 of switch K2, pin 7 of switch K3, and pin 7 of switch K4;

[0043] When the valid indication signal indicates a valid state, switches K1, K2, K3, and K4 internally connect pin 1 to the normally open contact pin 2 inside each of them, and switches K1, K2, K3, and K4 internally connect pin 4 to the normally open contact pin 5 inside each of them;

[0044] When the valid indication signal indicates an invalid state, switches K1, K2, K3, and K4 internally connect pin 1 to the normally closed contact pin 3 inside each of them, and switches K1, K2, K3, and K4 internally connect pin 4 to the normally closed contact pin 6 inside each of them;

[0045] The pin 1 of switch K1 is defined to connect to 0_TPA+. The pin 2 of K1 connects to the port 0_TPA+ signal of the physical layer port 0 interface of the 1394B bus node. The port 0_TPA+ signal is associated with its TPA+ inside the physical layer port 0 interface of the 1394B bus node. The pin 4 of switch K1 is defined to connect to 0_TPA-. The pin 5 of K1 connects to the port 0_TPA- signal of the physical layer port 0 interface of the 1394B bus node. The port 0_TPA- signal is associated with its TPA- inside the physical layer port 0 interface of the 1394B bus node.

[0046] The pin 1 of switch K2 is defined to connect to 0_TPB+. The pin 2 of K2 connects to the port 0_TPB+ signal of the physical layer port 0 interface of the 1394B bus node. The port 0_TPB+ signal is associated with its TPB+ inside the physical layer port 0 interface of the 1394B bus node. The pin 4 of switch K2 is defined to connect to 0_TPB-. The pin 5 of K2 connects to the port 0_TPB- signal of the physical layer port 0 interface of the 1394B bus node. The port 0_TPB- signal is associated with its TPB- inside the physical layer port 0 interface of the 1394B bus node.

[0047] The pin 1 of switch K3 is defined to connect to 0_TPA+. The pin 2 of K3 connects to the port 0_TPA+ signal of the physical layer port 1 interface of the 1394B bus node. The port 1_TPA+ signal is associated with its TPA+ inside the physical layer port 1 interface of the 1394B bus node. The pin 4 of switch K3 is defined to connect to 1_TPA-. The pin 5 of K3 connects to the port 1_TPA- signal of the physical layer port 1 interface of the 1394B bus node. The port 1_TPA- signal is associated with its TPA- inside the physical layer port 1 interface of the 1394B bus node.

[0048] The pin 1 of switch K4 is defined to connect to 1_TPB+. The pin 2 of K4 connects to the port 1_TPB+ signal of the physical layer port 1 interface of the 1394B bus node. The port 1_TPB+ signal is associated with its TPB+ inside the physical layer port 1 interface of the 1394B bus node. The pin 4 of switch K4 is defined to connect to 1_TPB-. The pin 5 of K4 connects to the port 1_TPB- signal of the physical layer port 1 interface of the 1394B bus node. The port 1_TPB- signal is associated with its TPB- inside the physical layer port 1 interface of the 1394B bus node.

[0049] The pin 3 of switch K1 connects to the pin 3 of switch K4. The pin 6 of switch K1 connects to the pin 6 of switch K4. The pin 3 of switch K2 connects to the pin 3 of switch K3. The pin 6 of switch K2 connects to the pin 6 of switch K3.

[0050] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An in-aircraft bus network intermediate node, characterized in that It includes a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer protocol chip; The physical layer port is connected to the on-board bus, and is used to convert the bus signals of the on-board bus into electrical signals recognizable by the physical layer protocol chip, and is also used to convert the electrical signals into bus signals; The physical layer protocol chip is used to perform protocol decoding, data recognition, and data forwarding on the electrical signals; The network intermediate node further includes a valid indication circuit and a bypass switch; The valid indication circuit outputs an indication signal when one of the physical layer ports fails; After receiving the indication signal, the bypass switch disconnects the bus transmission between the failed physical layer port and the bus and transfers it to the bypass physical layer port; Wherein, the bypass switch is provided with seven pins, the seventh pin is connected to the control end of the valid indication circuit, the first pin and the fourth pin are connected to the on-board bus, the second pin and the fifth pin are connected to the data transmission ports of the physical layer port, the first pin is used to selectively connect the second pin or the third pin of the bypass switch based on the control of the valid indication circuit, the fourth pin is used to selectively connect the fifth pin or the sixth pin of the bypass switch based on the control of the valid indication circuit, and the third pin and the sixth pin are connected to the bypass physical layer port; Wherein, the physical layer protocol chip is a 1394B bus node physical layer protocol chip; the physical layer port is a 1394B bus node physical layer port 0; the bypass physical layer port is a 1394B bus node physical layer port 1; the bypass switch includes switches K1, K2, K3, and K4; the valid indication circuit is a 1394B bus node valid indication circuit; Wherein, the connection relationships among the 1394B bus node physical layer protocol chip, the 1394B bus node physical layer port 0, the 1394B bus node physical layer port 1, switches K1, K2, K3, K4, and the 1394B bus node valid indication circuit are as follows: The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 0 with signals TPA+, TPA-, TPB+, and TPB-; The 1394B bus node physical layer protocol chip is interface-connected to the 1394B bus node physical layer port 1 with signals TPA+, TPA-, TPB+, and TPB-; The valid indication signals output by the 1394B bus node valid indication circuit are connected to the pin 7 of switch K1, the pin 7 of switch K2, the pin 7 of switch K3, and the pin 7 of switch K4.

2. The in-aircraft bus network intermediate node according to claim 1, wherein When the valid indication signal indicates a valid state, switches K1, K2, K3, and K4 respectively connect pin 1 to the normally open contact pin 2 inside themselves, and switches K1, K2, K3, and K4 respectively connect pin 4 to the normally open contact pin 5 inside themselves; When the valid indication signal indicates an invalid state, inside each of switches K1, K2, K3, and K4, pin 1 is connected to normally-closed contact pin 3 inside itself, and pin 4 is connected to normally-closed contact pin 6 inside itself. The name definition of pin 1 of switch K1 is connected to 0_TPA+, pin 2 of K1 is connected to the 0_TPA+ signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPA+ signal is associated with its TPA+ inside the physical layer port 0 interface of the 1394B bus node; the name definition of pin 4 of switch K1 is connected to 0_TPA-, pin 5 of K1 is connected to the 0_TPA- signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPA- signal is associated with its TPA- inside the physical layer port 0 interface of the 1394B bus node. The name definition of pin 1 of switch K2 is connected to 0_TPB+, pin 2 of K2 is connected to the 0_TPB+ signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPB+ signal is associated with its TPB+ inside the physical layer port 0 interface of the 1394B bus node; the name definition of pin 4 of switch K2 is connected to 0_TPB-, pin 5 of K2 is connected to the 0_TPB- signal of the port 0 of the physical layer port 0 interface of the 1394B bus node, and the 0_TPB- signal is associated with its TPB- inside the physical layer port 0 interface of the 1394B bus node. The name definition of pin 1 of switch K3 is connected to 0_TPA+, pin 2 of K3 is connected to the 0_TPA+ signal of the port 0 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPA+ signal is associated with its TPA+ inside the physical layer port 1 interface of the 1394B bus node; the name definition of pin 4 of switch K3 is connected to 1_TPA-, pin 5 of K3 is connected to the 1_TPA- signal of the port 1 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPA- signal is associated with its TPA- inside the physical layer port 1 interface of the 1394B bus node. The name definition of pin 1 of switch K4 is connected to 1_TPB+, pin 2 of K4 is connected to the 1_TPB+ signal of the port 1 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPB+ signal is associated with its TPB+ inside the physical layer port 1 interface of the 1394B bus node; the name definition of pin 4 of switch K4 is connected to 1_TPB-, pin 5 of K4 is connected to the 1_TPB- signal of the port 1 of the physical layer port 1 interface of the 1394B bus node, and the 1_TPB- signal is associated with its TPB- inside the physical layer port 1 interface of the 1394B bus node. Pin 3 of switch K1 is connected to pin 3 of switch K4, pin 6 of switch K1 is connected to pin 6 of switch K4, pin 3 of switch K2 is connected to pin 3 of switch K3, and pin 6 of switch K2 is connected to pin 6 of switch K3.

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