A method for manufacturing a semiconductor structure, a semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; forming a gate structure on the substrate; forming an isolation layer on the sidewall of the gate structure; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure and the isolation layer; forming a via in the interlayer dielectric layer, the via exposing part of the isolation layer; cleaning the via by a cleaning solution, the etching rate of the cleaning solution to the interlayer dielectric layer being greater than the etching rate of the cleaning solution to the exposed isolation layer; and forming a metal plug in the via. The semiconductor structure manufactured based on the semiconductor structure manufacturing method can prevent the metal plug from contacting the gate structure when the metal plug is formed, thereby improving the short circuit phenomenon. In addition, since the etching rate of the cleaning solution to the isolation layer is small, the width of the via will not increase greatly, thereby preventing the formation of air gaps inside the metal when the metal plug is formed in the via, thereby improving the conductivity of the metal plug.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In related technologies, during the manufacturing process of semiconductor devices, metal interconnect structures are typically used to achieve current conduction, thereby realizing the specific functions of the semiconductor device. Generally, after creating the via, a metal plug is fabricated within the corresponding via, such as using metal embedding technology to form a metal plug. During the formation of the via, the etching process can create deposits within the via. Therefore, after etching out the via, it is necessary to clean these deposits. However, the cleaning solution is corrosive, and the cleaning process may cause the via to enlarge. Depositing a metal plug on an enlarged via could lead to contact between the metal plug and the gate, resulting in leakage and reduced yield. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure to at least solve the above-mentioned problems.

[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] Provide substrate;

[0007] A gate structure is formed on the substrate;

[0008] An isolation layer is formed on the sidewall of the gate structure;

[0009] An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covering the gate structure and the isolation layer;

[0010] A via is formed within the interlayer dielectric layer, and the via exposes a portion of the isolation layer;

[0011] The through-hole is cleaned with a cleaning solution, wherein the corrosion rate of the cleaning solution on the interlayer dielectric layer is greater than the corrosion rate of the cleaning solution on the exposed isolation layer;

[0012] A metal plug is formed inside the through hole.

[0013] According to some embodiments of this disclosure, the step of forming the isolation layer includes:

[0014] A first isolation layer is formed on the sidewall of the gate structure;

[0015] A second isolation layer is formed on the sidewall of the first isolation layer;

[0016] A third isolation layer is formed on the sidewall of the second isolation layer;

[0017] Wherein, the thickness of the first isolation layer is greater than the thickness of the second isolation layer, and the thickness of the third isolation layer is greater than the thickness of the first isolation layer.

[0018] According to some embodiments of this disclosure, the material of the third isolation layer is the same as that of the first isolation layer, and the material of the second isolation layer is different from that of the first isolation layer.

[0019] According to some embodiments of this disclosure, after forming the first isolation layer, the method further includes:

[0020] A patterned photoresist layer is formed on the substrate, the patterned photoresist layer exposing the first isolation layer;

[0021] The first isolation layer is ion-doped so that the doping concentration at the bottom of the first isolation layer is greater than the doping concentration at the top of the first isolation layer.

[0022] According to some embodiments of this disclosure, the thickness of the top of the third isolation layer is less than the thickness of the bottom of the third isolation layer.

[0023] According to some embodiments of this disclosure, after forming the third isolation layer, the method further includes:

[0024] A patterned photoresist layer is formed on the substrate, the patterned photoresist layer exposing the third isolation layer;

[0025] The third isolation layer is ion-doped so that the doping concentration at the top of the third isolation layer is greater than the doping concentration at the bottom of the third isolation layer.

[0026] According to some embodiments of this disclosure, the doping concentration in the first isolation layer is less than the doping concentration in the third isolation layer.

[0027] According to some embodiments of this disclosure, the doped ions in the first isolation layer and the third isolation layer are the same.

[0028] According to some embodiments of this disclosure, the via is formed by a dry etching process, and the via exposes the third isolation layer.

[0029] According to some embodiments of this disclosure, the material of the third isolation layer is different from the material of the interlayer dielectric layer, and the density of the third isolation layer is greater than the density of the interlayer dielectric layer.

[0030] A second aspect of this disclosure provides a semiconductor structure, comprising:

[0031] Substrate;

[0032] A gate structure is located on the substrate;

[0033] An isolation layer is located on the sidewall of the gate structure;

[0034] Interlayer dielectric layer, located on the substrate;

[0035] A metal plug is located on the substrate and between the isolation layer and the interlayer dielectric layer;

[0036] The density of the isolation layer is greater than that of the interlayer dielectric layer.

[0037] According to some embodiments of this disclosure, the isolation layer includes:

[0038] The first isolation layer is located on the sidewall of the gate structure;

[0039] The second isolation layer is located on the side wall of the first isolation layer;

[0040] The third isolation layer is located on the side wall of the second isolation layer;

[0041] The material of the third isolation layer is the same as that of the first isolation layer, the material of the first isolation layer is different from that of the second isolation layer, and the material of the second isolation layer is the same as that of the interlayer dielectric layer.

[0042] According to some embodiments of this disclosure, the thickness of the first isolation layer is greater than the thickness of the second isolation layer, and the thickness of the first isolation layer is less than the thickness of the third isolation layer.

[0043] According to some embodiments of this disclosure, the thickness of the bottom of the third isolation layer is greater than the thickness of the top of the third isolation layer, and the doping concentration of the top of the third isolation layer is greater than the doping concentration of the bottom of the third isolation layer.

[0044] According to some embodiments of this disclosure, the thickness of the bottom of the first isolation layer is greater than the thickness of the top of the first isolation layer, and the doping concentration of the bottom of the first isolation layer is greater than the doping concentration of the top of the first isolation layer.

[0045] Beneficial Effects: The semiconductor structure fabrication method provided in this disclosure involves forming vias in an interlayer dielectric layer through an etching process. Based on an isolation layer disposed outside the gate structure, when cleaning the vias to remove deposits generated during etching, the corrosion rate of the cleaning solution on the isolation layer is low, thus not reducing the width of the isolation layer. In other words, a large preset distance can be maintained between the vias and the gate structure. Therefore, when forming the metal plug, the metal plug will not contact the gate structure, thereby improving short-circuit phenomena. Furthermore, because the corrosion rate of the cleaning solution on the isolation layer is low, the width of the vias will not increase significantly. Thus, when forming the metal plug within the via, air gaps will not form inside the metal, thereby improving the conductivity of the metal plug.

[0046] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0048] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0049] Figure 2 This is a flowchart illustrating the formation of an isolation layer according to an exemplary embodiment;

[0050] Figure 3 This is a flowchart illustrating the doping process of a first isolation layer according to an exemplary embodiment;

[0051] Figure 4 This is a flowchart illustrating the doping process of a third isolation layer according to an exemplary embodiment;

[0052] Figure 5 This is a schematic diagram of a substrate and gate structure in a semiconductor structure according to an exemplary embodiment;

[0053] Figure 6 This is a schematic diagram of a semiconductor structure in which an initial first silicon nitride layer is formed, according to an exemplary embodiment.

[0054] Figure 7 This is a schematic diagram of a semiconductor structure in which a first silicon nitride layer is formed, according to an exemplary embodiment.

[0055] Figure 8 This is a schematic diagram of a semiconductor structure in which an initial first oxide layer is formed, according to an exemplary embodiment.

[0056] Figure 9 This is a schematic diagram of a semiconductor structure in which a first oxide layer is formed, according to an exemplary embodiment.

[0057] Figure 10 This is a schematic diagram of a semiconductor structure in which an initial second silicon nitride layer is formed, according to an exemplary embodiment.

[0058] Figure 11 This is a schematic diagram of a semiconductor structure in which an isolation layer is formed, according to an exemplary embodiment.

[0059] Figure 12 This is a schematic diagram of a semiconductor structure in which an isolation layer is formed, according to another exemplary embodiment;

[0060] Figure 13 This is a schematic diagram of a semiconductor structure forming an interlayer dielectric layer according to an exemplary embodiment;

[0061] Figure 14 This is a schematic diagram illustrating the formation of a through-hole in a semiconductor structure according to an exemplary embodiment;

[0062] Figure 15 This is a schematic diagram illustrating a semiconductor structure forming a metal plug according to an exemplary embodiment.

[0063] Figure label:

[0064] 101, Substrate; 201, Gate oxide layer; 202, Gate metal; 300, Isolation layer; 301, First silicon nitride layer; 301', Initial first silicon nitride layer; 302, First oxide layer; 302', Initial first oxide layer; 303, Second silicon nitride layer; 303', Initial second silicon nitride layer; 401, Interlayer dielectric layer; A, Through-hole; 601, Third silicon nitride layer; 701, Metal plug. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0066] In related technologies, during the manufacturing process of semiconductor devices, metal interconnect structures, such as metal plugs, are typically used to enable the conduction of current within the device. During the formation of the plug vias, etching can create deposits within the vias. Therefore, after etching, these deposits need to be cleaned. However, the cleaning solution is corrosive, and this process can potentially enlarge the plug vias. Depositing metal plugs on these enlarged vias could lead to contact between the metal plug and the gate, causing leakage and reducing the yield of the semiconductor device.

[0067] To overcome the above problems, this disclosure provides a method for fabricating a semiconductor structure. Through-holes are formed in the interlayer dielectric layer through an etching process. Since deposits are generated during etching, the through-holes need to be cleaned. Simultaneously, because the cleaning solution has a low corrosion rate on the isolation layer, the width of the isolation layer is not reduced. This means the distance between the through-hole and the gate is relatively large. Therefore, when forming the metal plug, the metal plug will not contact the gate, thereby improving short-circuit performance. Furthermore, because the cleaning solution has a low corrosion rate on the isolation layer, the width of the through-hole will not increase significantly. Therefore, when forming the metal plug within the through-hole, air gaps will not form inside the metal, thereby improving the conductivity of the metal plug. The method for fabricating the semiconductor structure in this disclosure will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0068] An exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment. The fabrication method includes:

[0069] Step S101, providing substrate 101;

[0070] Step S102: A gate structure is formed on the substrate 101;

[0071] Step S103: An isolation layer 300 is formed on the sidewall of the gate structure;

[0072] Step S104: An interlayer dielectric layer 401 is formed on the substrate 101, and the interlayer dielectric layer 401 covers the gate structure and the isolation layer 300.

[0073] Step S105: A via A is formed in the interlayer dielectric layer 401, and via A exposes part of the isolation layer 300;

[0074] Step S106: The through hole A is cleaned with a cleaning solution, wherein the corrosion rate of the cleaning solution on the interlayer dielectric layer 401 is greater than the corrosion rate of the cleaning solution on the exposed isolation layer 300.

[0075] Step S107: A metal plug 701 is formed in the through hole A.

[0076] In this exemplary embodiment, the semiconductor structure fabrication method involves forming a gate structure on a substrate 101, then using an isolation layer 300 formed on the surface of the gate structure as a protective layer. The isolation layer 300 covers the surface of the gate structure, providing isolation and protection while partially exposing the doped regions. Next, an interlayer dielectric layer 401 is formed on the substrate 101, covering the gate structure and the isolation layer 300. Finally, a via A is formed, and the via A is cleaned with a cleaning solution, resulting in a metal plug 701 inside the via A. It should be noted that, since the via A needs to be cleaned with a cleaning solution when forming the via A for fabricating the metal plug 701, to reduce the corrosion of the via A near the gate structure by the cleaning solution, the materials of the isolation layer 300 and the interlayer dielectric layer 401 formed within the semiconductor structure in this exemplary embodiment meet the corresponding cleaning conditions, ensuring that the corrosion rate of the interlayer dielectric layer 401 by the cleaning solution is greater than the corrosion rate of the isolation layer 300.

[0077] For example, in order to meet the requirements of the corresponding cleaning conditions, the materials of the selected isolation layer 300 and the interlayer dielectric layer 401 satisfy the following condition: the density of the isolation layer 300 is greater than the density of the interlayer dielectric layer 401.

[0078] Based on the isolation layer 300 formed by the semiconductor structure in this exemplary embodiment, during the cleaning process of the via A using the cleaning solution, the corrosion rate of the isolation layer 300 by the cleaning solution is lower than the corrosion rate of the interlayer dielectric layer 401 by the cleaning solution. This reduces the corrosion of the via A near the gate structure by the cleaning solution, reduces the left and right offset of the via A, and thus avoids short circuits between the gate structure and the metal plug 701 formed in the via A, thereby improving the yield of the semiconductor device.

[0079] refer to Figure 5 , Figure 11 , Figure 12 and Figure 15 This is a schematic diagram of a semiconductor structure fabricated based on the semiconductor fabrication method in this exemplary embodiment.

[0080] like Figure 5 As shown, Figure 5This is a schematic diagram of a substrate and gate structure in a semiconductor structure according to an exemplary embodiment. The semiconductor structure includes a substrate 101, a gate structure is formed on the upper surface of the substrate 101, and doped regions are formed in the substrate 101 located on both sides of the gate structure.

[0081] In this exemplary embodiment, the substrate 101 of the semiconductor structure can be a multilayer structure with corresponding functional regions fabricated in the previous process, or a substrate of any other semiconductor structure, such as a silicon substrate, a SiC substrate, etc. The gate structure includes a gate oxide layer 201 and a gate metal 202 located on the gate oxide layer 201. The material of the gate oxide layer 201 can be silicon oxide, or it can be a high-k dielectric material, such as hafnium oxide, zirconium oxide, etc. The material of the gate metal 202 can be polysilicon or a conductive material such as a metal. After the gate oxide layer 201 and the gate metal 202 are sequentially formed on the surface of the substrate 101, the gate metal 202 and the gate oxide layer 201 are etched to form the gate structure.

[0082] like Figure 11 As shown, Figure 11 This is a schematic diagram illustrating a semiconductor structure forming an isolation layer according to an exemplary embodiment. The semiconductor structure further includes an isolation layer 300. The isolation layer 300 is located on the sidewall of the gate structure, and by forming the isolation layer 300 on the sidewall of the gate structure, isolation protection is provided for the gate structure. The isolation layer 300 is also located on the top of the gate structure. Exemplarily, the material of the isolation layer 300 includes at least one of the following: silicon nitride, aluminum nitride, etc.

[0083] like Figure 12 As shown, in some embodiments, the isolation layer 300 may also be located only on the sidewall of the gate structure, that is, the portion of the isolation layer 300 located on the gate structure is removed, thereby reducing the thickness of the semiconductor structure.

[0084] like Figure 13 As shown, Figure 13 This is a schematic diagram illustrating a semiconductor structure forming an interlayer dielectric layer according to an exemplary embodiment. The semiconductor structure further includes an interlayer dielectric layer 401. The interlayer dielectric layer 401 is located on a substrate 101 and can cover the gate structure and the isolation layer 300. The interlayer dielectric layer 401, formed by deposition, achieves interlayer isolation of the semiconductor structure. Exemplarily, the material of the interlayer dielectric layer 401 includes at least one of insulating dielectric materials such as silicon dioxide, silicon oxycarbide, and silicon oxynitride.

[0085] like Figure 15 As shown, Figure 15This is a schematic diagram illustrating a semiconductor structure forming a metal plug according to an exemplary embodiment. The semiconductor structure further includes a metal plug 701. The metal plug 701 is located on a substrate 101 and between an isolation layer 300 and an interlayer dielectric layer 401; wherein the density of the isolation layer 300 is greater than the density of the interlayer dielectric layer 401.

[0086] In this exemplary embodiment, to achieve the cleaning condition that "the corrosion rate of the cleaning solution on the interlayer dielectric layer 401 is greater than the corrosion rate of the cleaning solution on the exposed isolation layer 300," when the materials of the interlayer dielectric layer 401 and the isolation layer 300 are different, a material with relatively higher density is selected as the isolation layer 300, and a material with relatively lower density is selected as the interlayer dielectric layer 401. It should be noted that if the materials of the interlayer dielectric layer 401 and the isolation layer 300 are the same, the concentration of the cleaning solution in different cleaning stages can be adjusted to clean the interlayer dielectric layer 401 and the isolation layer 300 exposed by the via A, thereby removing the deposits generated on the via A during the etching process; or, the density of the isolation layer 300 can be increased by controlling the doping of the isolation layer 300. Furthermore, it is understood that when the materials of the interlayer dielectric layer 401 and the isolation layer 300 are different, the isolation layer 300 can also be doped at a preset concentration to further increase the density of the isolation layer 300.

[0087] In some exemplary embodiments, such as Figure 2 As shown, Figure 2 This is a flowchart illustrating the formation of an isolation layer according to an exemplary embodiment. The steps of forming the isolation layer 300 include:

[0088] Step S201: A first isolation layer is formed on the sidewall of the gate structure;

[0089] Step S202: A second isolation layer is formed on the sidewall of the first isolation layer;

[0090] Step S203: A third isolation layer is formed on the sidewall of the second isolation layer.

[0091] In this exemplary embodiment, due to the high density of the isolation layer, the greater the thickness of the isolation layer 300, the greater its structural stress. The isolation layer 300 in this exemplary embodiment employs a multi-layer structure, overcoming the aforementioned problems by controlling the thickness and / or material of each layer. Exemplarily, the isolation layer 300 is designed as a three-layer structure. During the formation of the isolation layer 300, a first isolation layer is first formed on the sidewall of the gate structure; then a second isolation layer is formed on the sidewall of the first isolation layer; and finally, a third isolation layer is formed on the sidewall of the second isolation layer. Furthermore, the thicknesses of the first, second, and third isolation layers are controlled during the formation process to reduce the stress of the isolation layer 300 while achieving isolation protection for the gate structure.

[0092] like Figure 11 As shown, Figure 11 This is a schematic diagram of a semiconductor structure with an isolation layer formed according to an exemplary embodiment. The isolation layer 300 includes a first isolation layer, a second isolation layer, and a third isolation layer. The first isolation layer is located on the sidewall of the gate structure; the second isolation layer is located on the sidewall of the first isolation layer; and the third isolation layer is located on the sidewall of the second isolation layer. To prevent corrosion of the via A near the gate structure during cleaning, the isolation layer 300 needs to reach a certain thickness. However, as the overall thickness of the isolation layer 300 increases, its overall stress also increases. Therefore, the thickness of each layer in the isolation layer 300 can be designed such that "the thickness of the first isolation layer is greater than the thickness of the second isolation layer, and the thickness of the third isolation layer is greater than the thickness of the first isolation layer." That is, a first isolation layer of medium thickness is formed adjacent to the gate structure, a thinnest second isolation layer is formed as the middle layer of the isolation layer 300, and a thickest third isolation layer is formed as the outermost layer of the isolation layer 300, thereby reducing the overall stress of the isolation layer 300.

[0093] In this exemplary embodiment, since the density of the isolation layer 300 needs to be greater than that of the interlayer dielectric layer 401 to satisfy the requirement that "the corrosion rate of the cleaning solution on the interlayer dielectric layer 401 is greater than the corrosion rate of the cleaning solution on the exposed isolation layer 300", materials with higher density can be selected as the first and third isolation layers. For example, the material of the first isolation layer includes materials with higher density such as silicon nitride or aluminum nitride; the material of the third isolation layer includes materials with higher density such as silicon nitride or aluminum nitride. The density of the second isolation layer can be relatively lower, thereby reducing the overall stress of the isolation layer 300. For example, the material of the second isolation layer includes insulating dielectric materials such as silicon dioxide, silicon oxycarbide, and silicon oxynitride.

[0094] To reduce the overall stress of the isolation layer 300 and achieve isolation protection for the gate structure, exemplarily, the material of the third isolation layer is the same as that of the first isolation layer, the material of the first isolation layer is different from that of the second isolation layer, and the material of the second isolation layer is the same as that of the interlayer dielectric layer 401. That is, by using the less dense second isolation layer as an intermediate layer, the isolation layer 300 forms a sandwich structure, thereby reducing the overall stress of the isolation layer 300.

[0095] In some exemplary embodiments, to improve the density of the first isolation layer, the first isolation layer is doped after its formation. For example... Figure 3 As shown, Figure 3 This is a flowchart illustrating the doping process of a first isolation layer according to an exemplary embodiment. The method for fabricating a semiconductor structure further includes:

[0096] Step S301: A patterned photoresist layer is formed on the substrate 101, exposing the first isolation layer, such as... Figure 7 As shown;

[0097] Step S301: Ion doping is performed on the first isolation layer so that the doping concentration at the bottom of the first isolation layer is greater than the doping concentration at the top of the first isolation layer.

[0098] In this exemplary embodiment, the doping concentration at the bottom of the first isolation layer is greater than that at the top of the first isolation layer. This allows the first isolation layer and the third isolation layer to work together, thereby uniformly increasing the overall density of the isolation layer 300. The specific working method will be explained later.

[0099] Specifically, this exemplary embodiment uses silicon nitride as an example to illustrate the fabrication process of the first isolation layer in a semiconductor structure. Forming the first isolation layer on the sidewall of the gate structure includes forming a first silicon nitride layer 301, which covers the top surface and side surface of the gate structure. When forming the first silicon nitride layer 301, an initial first silicon nitride layer 301' covering the gate structure is first formed on the substrate 101, such as... Figure 6 As shown; then the initial first silicon nitride layer 301' covering the top surface of the substrate 101 is removed, leaving the initial first silicon nitride layer 301' covering the top surface of the gate structure and the initial first silicon nitride layer 301' covering the side surface of the gate structure, forming the first silicon nitride layer 301, as shown. Figure 7 As shown.

[0100] In some exemplary embodiments, the shape of the third isolation layer is etched during its formation, such that the thickness of the top of the third isolation layer is less than the thickness of the bottom of the third isolation layer. To ensure more uniform overall stress in the third isolation layer and to match the shape and density of the first isolation layer, the density of the third isolation layer is further processed after its formation. Figure 4 As shown, Figure 4 This is a flowchart illustrating the doping process of a third isolation layer according to an exemplary embodiment. The method for fabricating a semiconductor structure further includes:

[0101] In step S401, a patterned photoresist layer is formed on the substrate 101, exposing a third isolation layer, such as... Figure 11 As shown;

[0102] Step S402: Ion doping is performed on the third isolation layer so that the doping concentration at the top of the third isolation layer is greater than the doping concentration at the bottom of the third isolation layer.

[0103] In the semiconductor structure of this exemplary embodiment, considering that the third isolation layer is narrow at the top and wide at the bottom, after processing the third isolation layer based on the above-described doping method, the doping concentration at the top of the third isolation layer is high and the density is large, which can prevent or reduce the corrosion of the upper part of the third isolation layer by the cleaning solution.

[0104] Furthermore, in another alternative exemplary embodiment, a patterned photoresist layer may be formed on top of the substrate 101 and the third isolation layer, the patterned photoresist layer exposing the top of the first isolation layer and the sidewalls of the third isolation layer, such as... Figure 12 As shown, at this time, only the sidewalls of the third isolation layer and the second isolation layer are retained on the sidewall of the first isolation layer as isolation sidewalls; then, the sidewall of the third isolation layer is ion-doped so that the doping concentration at the top of the third isolation layer is greater than the doping concentration at the bottom of the third isolation layer. The isolation layer 300 formed in this exemplary embodiment can also satisfy the protection of the gate structure, while also reducing the overall thickness of the semiconductor structure.

[0105] In this exemplary embodiment described above, a patterned photoresist layer is used to expose the first and third isolation layers, and both layers are doped to reduce defects and increase their density. It should be noted that during the formation of the first and third isolation layers, etching and cleaning processes can cause the upper portions of both layers to thin, resulting in a thinner upper portion and a thicker lower portion. When cleaning the vias, to prevent prolonged corrosion of the top of the third isolation layer by the cleaning solution, a higher doping concentration is applied to the top of the third isolation layer, resulting in higher density at the top and thus mitigating the susceptibility of the isolation layer to corrosion.

[0106] When doping the third isolation layer, the doping concentration at the top of the third isolation layer is made greater than the doping concentration at the bottom of the third isolation layer, or in other words, the doping concentration within the third isolation layer gradually decreases from top to bottom. In this case, to achieve a better overall density of the isolation layer through cooperation between the first isolation layer and the corresponding third isolation layer, the density of the upper part of the first isolation layer can be made less than the density of the lower part of the first isolation layer. Therefore, when doping the first isolation layer, the doping concentration needs to be controlled so that the doping concentration at the top of the first isolation layer is less than the doping concentration at the bottom of the first isolation layer, or in other words, the doping concentration within the first isolation layer gradually increases from top to bottom.

[0107] Furthermore, in some alternative embodiments, since both the first and third isolation layers are narrower at the top and wider at the bottom, to prevent the top of the third isolation layer from being completely etched away and exposing the first isolation layer, thus preventing further etching of the first isolation layer and affecting the gate structure, the doping concentration at the top of the first isolation layer can be increased. This prevents the upper part of the gate structure from being exposed, effectively improving leakage current between the gate and the metal plug. Of course, in other alternative embodiments, the doping concentrations of the first and third isolation layers can be made to be consistent, thereby improving leakage current.

[0108] In some exemplary embodiments, considering that the third isolation layer, as the outermost layer of isolation layer 300, is adjacent to the interlayer dielectric layer 401, and that part of the sidewall of the third isolation layer will be exposed when fabricating via A, the doping concentration of the third isolation layer can be increased to improve the overall density of the outer side of isolation layer 300 in order to avoid affecting the gate structure. Therefore, in this exemplary embodiment, the doping concentration of the third isolation layer in the semiconductor structure is greater than the doping concentration within the first isolation layer. It should be noted that the doping concentration of the third isolation layer being greater than the doping concentration within the first isolation layer can be understood as the overall doping concentration of the third isolation layer being greater than the overall doping concentration of the first isolation layer.

[0109] It should be noted that there are many types of dopant ions that can improve the density of the first and third isolation layers. To save on doping costs and processes, the same type of dopant ions can be used when doping the first and third isolation layers; that is, the dopant ions in the first and third isolation layers are the same. The type of dopant ions can be selected according to actual needs, and these dopant ions include boron (B) and arsenic (A). S )wait.

[0110] Furthermore, this exemplary embodiment describes the fabrication process of the second and third isolation layers of a semiconductor structure, using silicon nitride as an example where the second isolation layer is an oxide layer and the third isolation layer is made of silicon nitride.

[0111] First, a first oxide layer 302 is formed on the sidewall of the first isolation layer as a second isolation layer, wherein the first oxide layer 302 covers the top surface and the side surface of the first isolation layer; specifically, an initial first oxide layer 302' covering the first isolation layer is formed on the substrate 101; the initial first oxide layer 302' covering the top surface of the substrate 101 is removed, such as... Figure 8 As shown; retaining the initial first oxide layer 302' covering the side surface of the first insulating layer and the initial first oxide layer 302' covering the top surface of the first insulating layer, forming the first oxide layer 302, as shown. Figure 9 As shown.

[0112] Then, a second silicon nitride layer 303 is formed as a third isolation layer, wherein the second silicon nitride layer 303 covers the top surface and the side surface of the first oxide layer 302. Specifically, an initial second silicon nitride layer 303' covering the first oxide layer 302 is formed on the substrate 101, as follows: Figure 10 As shown; the initial second silicon nitride layer 303' covering the top surface of the substrate 101 is removed, while the initial second silicon nitride layer 303' covering the side surface of the first oxide layer 302 and the initial second silicon nitride layer 303' covering the top surface of the first oxide layer 302 are retained, forming the second silicon nitride layer 303, as shown. Figure 11 As shown.

[0113] In this exemplary embodiment, the second isolation layer is made of oxide material, and the third isolation layer is made of silicon nitride material. Furthermore, this exemplary embodiment also provides selectable ranges for the thickness of the first oxide layer 302 and the thickness of the second silicon nitride layer 303: the thickness of the first oxide layer 302 is 1 nm to 3 nm; and the thickness of the second silicon nitride layer 303 is 14 nm to 18 nm.

[0114] In some exemplary embodiments, the via A is formed within the interlayer dielectric layer 401 using a dry etching process. Since the outermost layer of the isolation layer 300 is a third isolation layer, the via exposes a portion of the third isolation layer. Then, the via is cleaned with a cleaning solution to form a cleaned via A, as shown below. Figure 14 As shown, because the corrosion rate of the cleaning solution on the interlayer dielectric layer 401 is greater than the corrosion rate of the cleaning solution on the exposed isolation layer 300, the inner wall surface of the via A will not shift towards the side closer to the gate structure; finally, a metal plug 701 is formed in the via A. Figure 15 As shown, the metal plug 701 is located on the substrate 101 and between the isolation layer and the interlayer dielectric layer 401; wherein the density of the isolation layer 300 is greater than the density of the interlayer dielectric layer 401.

[0115] Understandably, since the density of the isolation layer 300 is required to be greater than that of the interlayer dielectric layer 401, and the third isolation layer in the isolation layer 300 is adjacent to the interlayer dielectric layer 401 as the outermost layer, the material of the third isolation layer only needs to meet the following conditions: the material of the third isolation layer is different from that of the interlayer dielectric layer 401, and the density of the third isolation layer is greater than that of the interlayer dielectric layer 401. Using a third isolation layer with greater density as the outermost layer also achieves isolation protection for the gate structure, preventing the metal plug 701 from directly forming a short circuit with the gate structure, thus improving the yield.

[0116] In some exemplary embodiments, the metal grown within the through-hole A includes a conductive material such as tungsten. When tungsten is selected as the metal plug 701, forming the metal plug 701 within the through-hole A includes growing tungsten within the through-hole A after it has been treated with a cleaning solution using a metal growth process.

[0117] In some exemplary embodiments, the semiconductor structure further includes a third silicon nitride layer 601 formed on the top surface of the second oxide layer. Specifically, the second oxide layer is first formed, covering the substrate 101, the side surfaces of the third isolation layer, and the top surface of the third isolation layer; finally, the third silicon nitride layer 601 is formed, covering the second oxide layer, for isolation from other layers.

[0118] In this disclosure, to avoid excessive corrosion of via A during the cleaning solution treatment, which could expose the gate structure and cause a short circuit between the metal plug 701 and the gate structure, the isolation layer 300 is optimized. During the optimization of the isolation layer 300, it was considered that a thicker isolation layer would result in higher overall stress and a harder material, affecting the overall performance of the semiconductor device. Therefore, the isolation layer 300 is layered, with the second isolation layer serving as a transition layer between the first and third isolation layers, reducing the overall stress of the isolation layer. Furthermore, because the outermost third isolation layer has higher hardness, after via A is formed, the subsequent cleaning process consumes very little of the third isolation layer, thus protecting via A from excessive corrosion by the cleaning solution and allowing it to form a straighter profile, which is beneficial for the fabrication of the metal plug 701. It should be noted that the effect of the cleaning solution on the interlayer dielectric layer is not shown in the figure; the cleaning solution can be a DHF solution.

[0119] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0120] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0121] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0122] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0123] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0124] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The manufacturing method comprises: providing a substrate; forming a gate structure on the substrate; forming an isolation layer on the sidewall of the gate structure; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure and the isolation layer; forming a via in the interlayer dielectric layer, the via exposing part of the isolation layer; cleaning the via by a cleaning solution, the cleaning solution having a corrosion rate on the interlayer dielectric layer greater than a corrosion rate on the exposed isolation layer; forming a metal plug in the via; wherein the step of forming the isolation layer comprises: forming a first isolation layer on the sidewall of the gate structure; forming a second isolation layer on the sidewall of the first isolation layer; forming a third isolation layer on the sidewall of the second isolation layer; wherein the thickness of the first isolation layer is greater than the thickness of the second isolation layer, and the thickness of the third isolation layer is greater than the thickness of the first isolation layer.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The material of the third isolation layer is the same as the material of the first isolation layer, and the material of the second isolation layer is different from the material of the first isolation layer.

3. The method of fabricating a semiconductor structure of claim 1, wherein, After forming the first isolation layer, further comprising: forming a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the first isolation layer; ion-doping the first isolation layer so that the doping concentration at the bottom of the first isolation layer is greater than the doping concentration at the top of the first isolation layer.

4. The method of fabricating a semiconductor structure of claim 3, wherein, The thickness of the top of the third isolation layer is less than the thickness of the bottom of the third isolation layer.

5. The method of fabricating a semiconductor structure of claim 4, wherein, After forming the third isolation layer, further comprising: forming a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the third isolation layer; ion-doping the third isolation layer so that the doping concentration at the top of the third isolation layer is greater than the doping concentration at the bottom of the third isolation layer.

6. The method of fabricating a semiconductor structure of claim 5, wherein, The doping concentration in the first isolation layer is less than the doping concentration of the third isolation layer.

7. The method of fabricating a semiconductor structure of claim 6, wherein, The doping ions in the first isolation layer and the third isolation layer are the same.

8. The method of fabricating a semiconductor structure of claim 1, wherein, The via is formed by a dry etching process, and the via exposes the third isolation layer.

9. The method of fabricating a semiconductor structure of claim 8, wherein, The material of the third isolation layer is different from the material of the interlayer dielectric layer, and the density of the third isolation layer is greater than the density of the interlayer dielectric layer.

10. A semiconductor structure, characterized by comprises: a substrate; a gate structure on the substrate; an isolation layer on the sidewall of the gate structure; an interlayer dielectric layer on the substrate; a metal plug on the substrate and between the isolation layer and the interlayer dielectric layer; wherein the density of the isolation layer is greater than the density of the interlayer dielectric layer; wherein the isolation layer comprises: a first isolation layer on the sidewall of the gate structure; a second isolation layer on the sidewall of the first isolation layer; a third isolation layer on the sidewall of the second isolation layer; wherein the material of the third isolation layer is the same as the material of the first isolation layer, the material of the first isolation layer is different from the material of the second isolation layer, and the material of the second isolation layer is the same as the material of the interlayer dielectric layer.

11. The semiconductor structure of claim 10, wherein, The first isolation layer has a thickness greater than a thickness of the second isolation layer, and the first isolation layer has a thickness less than a thickness of the third isolation layer.

12. The semiconductor structure of claim 11, wherein, The third isolation layer has a thickness at a bottom of the third isolation layer greater than a thickness at a top of the third isolation layer, and the third isolation layer has a doping concentration at the bottom of the third isolation layer greater than a doping concentration at the top of the third isolation layer.

13. The semiconductor structure of claim 11, wherein, The first isolation layer has a thickness at a bottom of the first isolation layer greater than a thickness at a top of the first isolation layer, and the first isolation layer has a doping concentration at the bottom of the first isolation layer greater than a doping concentration at the top of the first isolation layer.

Images