Semiconductor devices and electronic devices

Abstract

The present application provides a semiconductor device and an electronic device, which includes an insulating substrate and a thin film transistor layer arranged on the insulating substrate, the thin film transistor layer including a first active layer, an insulating layer and a second active layer arranged on the insulating substrate, the insulating layer being arranged between the first active layer and the second active layer and covering the first active layer; wherein, the present application forms a through hole located on the first active layer by arranging the insulating layer, and the thin film transistor layer also includes a third active layer at least partially located on the sidewall of the through hole, one side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, and reducing the power consumption; and further reducing the area occupied by the semiconductor device, thereby improving the integration of the semiconductor device, which is conducive to the development of high PII and high refresh rate products and the realization of some IC functions.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and an electronic device. Background Art

[0002] At present, flat-panel display devices such as liquid crystal display (LCD) panels and organic light-emitting diode (OLED) mobile terminals are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc. due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream display devices.

[0003] In the prior art, it is known that integrating integrated circuits (ICs), such as pixels, drivers, multiplexers, controls, and logic, onto a system on glass (SOG) substrate can improve the integration level of semiconductor devices and reduce dependence on IC chips. However, achieving SOG requires improving the integration level, maximum operating frequency, and current density of existing thin-film transistors (TFTs). Since the on-state electrical performance of a TFT is related to the portion of the active layer between the source and drain electrodes (i.e., the channel length of the active layer), achieving the aforementioned effects requires a shorter channel length and a smaller size for the TFT. However, conventional TFTs are typically planar. When fabricating an "I"-shaped active layer on a substrate using existing exposure equipment, the minimum size of the mask pattern is generally greater than 2 μm. In the prior art, achieving a short channel for the TFT is difficult. Therefore, how to reduce the channel length of the TFT and the area occupied by the TFT in the entire display panel while ensuring normal operation of the TFT device is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor device and an electronic device to alleviate the deficiencies in the related art.

[0005] To achieve the above functions, the technical solutions provided in the embodiments of the present application are as follows:

[0006] An embodiment of the present application provides a semiconductor device, including:

[0007] Insulation substrate;

[0008] a thin film transistor layer disposed on the insulating substrate, the thin film transistor layer comprising a first active layer, an insulating layer, and a second active layer stacked on the insulating substrate, the insulating layer being disposed between the first active layer and the second active layer and covering the first active layer;

[0009] The insulating layer is formed with a through hole located on the first active layer, and the thin film transistor layer also includes a third active layer at least partially located on the side wall of the through hole, one side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer.

[0010] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer further includes a first metal layer located within the insulating layer, the first metal layer is insulated from the first active layer, and the first metal layer is located on at least one side of the through hole.

[0011] In the semiconductor device provided in the embodiment of the present application, the first metal layer is disposed around the third active layer on the sidewall of the through hole.

[0012] In the semiconductor device provided in an embodiment of the present application, the first active layer includes a first conductor portion doped with ions, the second active layer includes a second conductor portion doped with ions, and the orthographic projection of the first conductor portion on the insulating substrate overlaps with at least a portion of the orthographic projection of the second conductor portion on the insulating substrate; wherein one side of the third active layer is connected to the first conductor portion, and the other side of the third active layer is connected to the second conductor portion.

[0013] In the semiconductor device provided in the embodiment of the present application, the doping ion concentration of the second conductor portion is lower than the doping ion concentration of the first conductor portion.

[0014] In the semiconductor device provided in an embodiment of the present application, the thin film transistor layer includes a second metal layer located on a side of the second active layer away from the insulating layer, the second metal layer including a first electrode connected to the first conductor portion, and a second electrode connected to the second conductor portion;

[0015] The first conductor portion includes a first conductor sub-portion connected to the third active layer and a second conductor sub-portion connected to the first electrode, and the orthographic projection of the second conductor sub-portion on the insulating substrate does not overlap with the orthographic projection of the second conductor portion on the insulating substrate.

[0016] In the semiconductor device provided in an embodiment of the present application, the second conductor portion includes a third conductor sub-portion connected to the third active layer, and a fourth conductor sub-portion connected to the second electrode, wherein the doping ion concentration of the first conductor sub-portion is less than the doping ion concentration of the second conductor sub-portion, and the doping ion concentration of the third conductor sub-portion is less than the doping ion concentration of the fourth conductor sub-portion.

[0017] In the semiconductor device provided in the embodiment of the present application, the first conductor sub-section is connected to one side of the third active layer, and the third conductor sub-section is connected to the other side of the third active layer.

[0018] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer includes a channel located between the first active layer and the second active layer, and the length of the channel and the depth of the through hole satisfy the following relationship:

[0019]

[0020] Wherein, L represents the length of the channel, H represents the depth of the through hole, and α represents the angle between the third active layer on the sidewall of the through hole and the bottom of the through hole.

[0021] In the semiconductor device provided in the embodiment of the present application, the angle α between the third active layer on the sidewall of the through hole and the bottom of the through hole is greater than 90 degrees and less than or equal to 120 degrees.

[0022] In the semiconductor device provided in the embodiment of the present application, in a direction perpendicular to the insulating substrate, the length of the channel is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

[0023] In the semiconductor device provided in an embodiment of the present application, the third active layer includes a first active sub-section and a second active sub-section connected to each other, the first active sub-section is located on a side of the insulating layer away from the insulating base, the first active sub-section is connected to the second active layer, and the second active sub-section is connected to the first active layer through the side wall of the through hole.

[0024] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer further includes a barrier layer located between the insulating layer and the second active layer, and at least a portion of the barrier layer is located in the through hole.

[0025] In the semiconductor device provided in the embodiment of the present application, a side of the barrier layer close to the second active layer is flush with a side of the insulating layer close to the second active layer.

[0026] In the semiconductor device provided in the embodiment of the present application, the third active layer is located on the sidewall and bottom of the through hole, and extends to a side of the insulating layer away from the insulating base.

[0027] In the semiconductor device provided in an embodiment of the present application, the insulating layer includes a first insulating layer and a second insulating layer provided on the insulating substrate, the first insulating layer is located on and covers the first active layer, and the second active layer covers the first active layer;

[0028] The first insulating layer is formed with a first through hole located on the first active layer, and the second insulating layer is formed with a second through hole located on the first active layer and connected to the first through hole, and the angle between the side wall of the second through hole and the first active layer is equal to the angle between the side wall of the first through hole and the first active layer.

[0029] An embodiment of the present application provides an electronic device, which includes any of the semiconductor devices described above.

[0030] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a semiconductor device and an electronic device, the semiconductor device including an insulating substrate and a thin film transistor layer arranged on the insulating substrate, the thin film transistor layer including a first active layer, an insulating layer and a second active layer arranged on the insulating substrate, the insulating layer being arranged between the first active layer and the second active layer and covering the first active layer; wherein, the embodiment of the present application forms a through hole located on the first active layer by arranging the insulating layer, the thin film transistor layer also includes a third active layer at least partially located on the sidewall of the through hole, one side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, and reducing the power consumption; and further reducing the area occupied by the semiconductor device, thereby improving the integration of the semiconductor device, which is conducive to the development of high PII, high refresh rate products and the realization of some IC functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a top cross-sectional view of a conventional thin film transistor;

[0033] Figure 2for Figure 1 Schematic diagram of the cross-sectional structure along the AA′ direction;

[0034] Figure 3 A top cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0035] Figure 4 for Figure 3 Schematic diagram of the first cross-sectional structure along the AA′ direction;

[0036] Figure 5 for Figure 4 Enlarged view of point B in the middle;

[0037] Figure 6 for Figure 3 Schematic diagram of the first cross-sectional structure along the AA′ direction;

[0038] Figure 7 for Figure 6 Enlarged view of point B in the middle;

[0039] Figure 8 for Figure 3 Schematic diagram of the third cross-sectional structure along the AA′ direction;

[0040] Figure 9 for Figure 8 Enlarged view of point B in the middle;

[0041] Figure 10 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0042] Figures 11A to 11G for Figure 10 Structural process flow chart for semiconductor device manufacturing. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0044] The embodiments of the present application provide a semiconductor device and an electronic device. These are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0045] See also Figures 3 to 11G , embodiments of the present application provide a semiconductor device and an electronic device, the semiconductor device comprising:

[0046] Insulating substrate 10;

[0047] a thin film transistor layer 40 disposed on the insulating substrate 10, the thin film transistor layer 40 including a first active layer 41, an insulating layer 44, and a second active layer 42 stacked on the insulating substrate 10, the insulating layer 44 being disposed between the first active layer 41 and the second active layer 42 and covering the first active layer 41;

[0048] In which, the insulating layer 44 is formed with a through hole 44C located on the first active layer 41, and the thin film transistor layer 40 also includes a third active layer 43 located at least partially on the side wall 44C1 of the through hole 44C, one side of the third active layer 43 is connected to the first active layer 41, and the other side of the third active layer 43 is connected to the second active layer 42.

[0049] Please combine Figure 1 and Figure 2 ;in, Figure 1 is a top cross-sectional view of a conventional thin film transistor; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the AA′ direction.

[0050] The existing thin film transistor includes an insulating substrate 10, and a light-shielding layer 20, a first buffer layer 30, an active layer 410, a gate insulating layer 44, a gate 45A, an interlayer insulating layer 46, a source 47A, a drain 47B, a flat layer 50, a common electrode 61, a passivation layer 70 and a pixel electrode 62 stacked in sequence on the insulating substrate 10; it should be noted that this embodiment does not specifically limit the type of existing thin film transistors. This embodiment only takes the existing display panel including a top-gate thin film transistor as an example to illustrate the technical solution of this application.

[0051] It is understandable that with the continuous development of the display panel industry, consumers have put forward higher and higher requirements for display panels with narrow borders, high aperture ratios, high brightness, high resolution and other parameters. In order to achieve the above effects, it is necessary to improve the integration, maximum operating frequency and current density of existing thin film transistors (TFTs). Since the electrical performance of the thin film transistor when it is turned on is related to the part of the active layer corresponding to the source and the drain (that is, the channel length of the active layer 410), it is necessary to make the thin film transistor have a shorter channel length and a smaller volume; however, in the traditional thin film transistor manufacturing process, the thin film transistor is usually planar, and when the "I" type active layer is produced on an insulating substrate by existing exposure equipment, the minimum size of its mask pattern is generally greater than 2μm. Therefore, in the existing technology, it is difficult to achieve short channel of the thin film transistor.

[0052] In the embodiment of the present application, a through hole 44C is formed on the first active layer 41 by setting the insulating layer 44, and the thin film transistor layer 40 also includes a third active layer 43 at least partially located on the side wall 44C1 of the through hole 44C, one side of the third active layer 43 is connected to the first active layer 41, and the other side of the third active layer 43 is connected to the second active layer 42, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, and reducing power consumption; and further reducing the area occupied by the semiconductor device, improving the integration of the semiconductor device, which is conducive to the development of high PII and high refresh rate products; at the same time, since the semiconductor device provided by this embodiment has the characteristics of small size and high integration, it can also realize IC data storage, voltage conversion and other functions.

[0053] The technical solution of this application is now described in conjunction with specific embodiments.

[0054] In one embodiment, please combine Figure 3 、 Figure 4 and Figure 5 ;in, Figure 3 A top cross-sectional view of a semiconductor device provided in an embodiment of the present application; Figure 4 for Figure 3 Schematic diagram of the first cross-sectional structure along the AA′ direction; Figure 5 for Figure 4 Enlarged view of point B in the middle.

[0055] In this embodiment, the semiconductor device includes an insulating substrate 10 and a thin film transistor layer 40 disposed on the insulating substrate 10. The insulating substrate 10 may include a rigid substrate or a flexible substrate. This embodiment does not impose any specific restrictions on the material of the insulating substrate 10.

[0056] The thin film transistor layer 40 includes a first active layer 41, an insulating layer 44 and a second active layer 42 stacked on the insulating substrate 10, wherein the insulating layer 44 is arranged between the first active layer 41 and the second active layer 42 and covers the first active layer 41; wherein the insulating layer 44 is formed with a through hole 44C located on the first active layer 41, and the thin film transistor layer 40 also includes a third active layer 43 at least partially located on the side wall 44C1 of the through hole 44C, one side of the third active layer 43 is connected to the first active layer 41, and the other side of the third active layer 43 is connected to the second active layer 42.

[0057] Specifically, the thin film transistor layer 40 includes at least one thin film transistor (not marked in the figure), and the thin film transistor includes the first active layer 41, the third active layer 43 and the second active layer 42 stacked on the insulating substrate 10; further, the first active layer 41 is a first conductor portion 41 doped with ions, the second active layer 42 is a second conductor portion 42 doped with ions, and the third active layer 43 includes an active segment 43A located on the side wall 44C1 of the through hole 44C, the orthographic projection of the first conductor portion 41 on the insulating substrate 10 at least overlaps with a portion of the orthographic projection of the second conductor portion 42 on the insulating substrate 10, one side of the active segment 43A is connected to the first conductor portion 41, and the other side of the active segment 43A is connected to the second conductor portion 42.

[0058] It can be understood that, in this embodiment, the first active layer 41, the insulating layer 44, and the second active layer 42 are stacked on the insulating substrate 10, the insulating layer 44 is arranged between the first active layer 41 and the second active layer 42 and covers the first active layer 41, the insulating layer 44 is formed with a through hole 44C located on the first active layer 41, and the thin film transistor layer 40 further includes a third active layer 43 at least partially located on the sidewall 44C1 of the through hole 44C. One side of the third active layer 43 is connected to the first active layer 41, and the other side of the third active layer 43 is connected to the second active layer 42, wherein the first active layer 41 is a first conductor portion 41 doped with ions, and the second active layer 42 is a second conductor portion 42 doped with ions. The third active layer 43 includes an active segment 43A located on the sidewall 44C1 of the through hole 44C, that is, in this embodiment, the channel P of the thin film transistor is located on the sidewall 44C1 of the through hole 44C.

[0059] Specifically, in this embodiment, the channel P is located between the first active layer 41 and the second active layer 42 , and the length of the channel P and the depth of the through hole 44C satisfy the following relationship:

[0060]

[0061] Wherein, L represents the length of the channel P, H represents the depth of the through hole 44C, and α represents the angle between the sidewall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C.

[0062] Furthermore, in a direction perpendicular to the insulating substrate 10, the cross-section of the side wall 44C1 of the through hole 44C is linear, and the angle α between the side wall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C is greater than 90 degrees and less than or equal to 120 degrees. Preferably, the angle α is preferably 95 degrees, 100 degrees, 110 degrees or 120 degrees; the depth of the through hole 44C is greater than or equal to 0.3 microns and less than or equal to 1 micron, wherein the depth of the through hole 44C is preferably 0.03 microns, 0.5 microns or 1 micron; in a direction perpendicular to the insulating substrate 10, the length of the channel P is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

[0063] It can be understood that in this embodiment, the channel P length of the thin film transistor can be determined by the depth of the through hole 44C. Therefore, compared with traditional thin film transistors that are limited by exposure equipment during the manufacturing process and whose channel P length is usually greater than 2 microns, this embodiment arranges the active section 43A on the side wall 44C1 of the through hole 44C, wherein the depth of the through hole 44C is greater than or equal to 0.3 microns and less than or equal to 1 micron, thereby reducing the channel P length, realizing the short channel P of the thin film transistor, and further reducing the area of ​​the thin film transistor, which is conducive to the manufacture of micro thin film transistors.

[0064] It should be noted that, since the channel P of the thin film transistor is located on the sidewall 44C1 of the through hole 44C, compared with traditional thin film transistors that are limited by exposure equipment during the manufacturing process and whose channel length is generally greater than 2 microns, this embodiment disposes the active section 43A on the sidewall 44C1 of the through hole 44C. Therefore, the length of the channel P can be controlled by controlling the depth of the through hole 44C and the angle α between the sidewall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C. That is, the length of the channel P can be controlled independently of the exposure equipment, thereby achieving a short channel of the thin film transistor; and further reducing the area of ​​the thin film transistor, which is conducive to the manufacture of micro thin film transistors. In addition, since the width of the channel P is determined by the width of the orthographic projection of the third active layer 43 on the insulating substrate 10, under the condition that the width of the channel P is constant, shortening the length of the channel P can make the thin film transistor have a larger aspect ratio, thereby having a larger on-state current and reducing the power consumption of the thin film transistor.

[0065] It should be noted that, in this embodiment, the semiconductor device also includes a first buffer layer 30 and a light-shielding layer 20 located between the insulating substrate 10 and the insulating layer 44, the first buffer layer 30 covers the light-shielding layer 20, and the orthographic projection of the light-shielding layer 20 on the insulating substrate 10 at least covers the orthographic projection of the third active layer 43 on the insulating substrate 10; wherein, the light-shielding layer 20 can block light directed to the third active layer 43, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the third active layer 43, thereby maintaining the stability of the thin film transistor during operation.

[0066] In this embodiment, the thin film transistor layer 40 also includes a first metal layer 45 located in the insulating layer 44, the first metal layer 45 is insulated from the first active layer 41, and the first metal layer 45 is located on at least one side of the through hole 44C; preferably, the first metal layer 45 includes but is not limited to a gate 45A, the gate 45A is insulated from the first active layer 41, and the gate 45A is located on at least one side of the through hole 44C; further, the gate 45A has an orthographic projection on the side wall 44C1 of the third active layer 43 covering the active segment 43A, so that the gate 45A can adjust the channel P current of the thin film transistor.

[0067] Specifically, the first metal layer 45 is formed with an opening 45B located on the first active layer 41, and the opening 45B is arranged corresponding to the through hole 44C. The aperture of the opening 45B is larger than the aperture of the through hole 44C, so that the first metal layer 45 is arranged around the third active layer 43 on the side wall 44C1 of the through hole 44C, that is, the gate 45A is arranged around the third active layer 43 on the side wall 44C1 of the through hole 44C, and the shape of the orthographic projection of the gate 45A on the insulating substrate 10 is annular. The orthographic projection of the gate 45A on the insulating substrate 10 overlaps with the four sides of the orthographic projection of the active segment 43A on the insulating substrate 10, that is, a ring-shaped channel P region is formed on the active segment 43A, thereby controlling the width of the channel P region and further adjusting the channel P current of the thin film transistor.

[0068] It should be noted that, in this embodiment, the insulating layer 44 includes a first insulating layer 44 and a second insulating layer 44 provided on the insulating substrate 10, the first insulating layer 44 is located on the first active layer 41 and covers the first active layer 41, the second active layer 42 covers the first metal layer 45, preferably, the first insulating layer 44 is a second buffer layer 44, the second insulating layer 44 is a gate insulating layer 44; wherein, the first insulating layer 44 is formed with a first through hole 44C2 located on the first active layer 41, and the second insulating layer 44 is formed with a through hole 44C2 located on the first active layer 41 and connected to the first active layer 41. The first through hole 44C2 is connected to the second through hole 44C3, and the angle between the side wall 44C1 of the second through hole 44C3 and the first active layer 41 is equal to the angle between the side wall 44C1 of the first through hole 44C2 and the first active layer 41, that is, the through hole 44C includes the first through hole 44C2 and the second through hole 44C3 that are connected to each other. It can be understood that in this embodiment, the insulating layer 44 is provided to include the first insulating layer 44 and the second insulating layer 44 provided on the insulating substrate 10, so as to facilitate the control of the depth of the through hole 44C, and further facilitate the control of the length of the channel P.

[0069] In the present application, the material of the first active layer 41, the material of the second active layer 42 and the material of the third active layer 43 include but are not limited to amorphous silicon, polycrystalline silicon, or oxide semiconductor materials. Preferably, the first conductor part 41 and the second conductor part 42 are both made of silicide and polycrystalline silicon doped with n-type impurities at a high concentration, and the doping ion concentration of the second conductor part 42 is less than the doping ion concentration of the first conductor part 41.

[0070] It can be understood that, in this embodiment, the second conductor portion 42 with a lower dopant ion concentration is formed on the active segment 43A, so that the dopant ions in the second conductor portion 42 are not easily diffused into the active segment 43A, which is beneficial to improving the short channel effect in the thin film transistor structure, thereby optimizing the performance of the thin film transistor.

[0071] It can be understood that the first conductor portion 41 and the second conductor portion 42 can both be made of silicide and polysilicon doped with n-type impurities at a high concentration. This is only for illustration. For example, in another embodiment, the first conductor portion 41 and the second conductor portion 42 are both N-type heavily doped amorphous silicon layers. Therefore, when manufacturing the thin film transistor, no additional ion implantation is required, thereby avoiding the risk of plasma gas diffusing from the second conductor portion 42 into the active section 43A when the second conductor portion 42 is made of silicide and polysilicon doped with n-type impurities at a high concentration.

[0072] Furthermore, the thin film transistor layer 40 also includes a blocking layer 48 located between the insulating layer 44 and the second active layer 42, and at least a portion of the blocking layer 48 is located in the through hole 44C, thereby preventing the plasma gas from diffusing toward the active segment 43A when the second conductor portion 42 is formed on the third active layer 43, so as to maintain the operating stability of the thin film transistor.

[0073] It should be noted that, in this embodiment, the first metal layer 45 is located in the insulating layer 44 and has a certain thickness. Therefore, a step is formed at the position of the first metal layer 45 in the insulating layer 44. At the same time, since the third active layer 43 is located on the side wall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C, a step difference is formed at the position of the through hole 44C.

[0074] Continuing from the above, in this embodiment, the side of the blocking layer 48 close to the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42. Specifically, the blocking layer 48 includes a first blocking portion 48A located on the side of the insulating layer 44 away from the insulating base 10, and a second blocking portion 48B located in the through hole 44C. The side of the first blocking portion 48A close to the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42, thereby improving the problem of unevenness of the upper surface of the insulating layer 44 at the position of the first metal layer 45 due to the thickness of the first metal layer 45. The side of the second blocking portion 48B close to the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42, thereby avoiding the risk of the second conductor portion 42 breaking at the step position when the second conductor portion 42 is formed on the third active layer 43.

[0075] In this embodiment, the thin film transistor layer 40 includes a second metal layer 47 located on a side of the second active layer 42 away from the insulating layer 44. The second metal layer 47 includes a first electrode connected to the first conductor portion 41 and a second electrode connected to the second conductor portion 42. The first electrode includes but is not limited to one of a source electrode 47A and a drain electrode 47B, and the second electrode includes but is not limited to the other of the source electrode 47A and the drain electrode 47B. In this embodiment, the technical solution of the present application is illustrated by taking the first electrode as the drain electrode 47B and the second electrode as the source electrode 47A as an example.

[0076] The semiconductor device includes an interlayer insulating layer 46 located between the second active layer 42 and the second metal layer 47, a first via hole 46A passing through the interlayer insulating layer 46 and located on the second conductor portion 42, and a second via hole 46B passing through the interlayer insulating layer 46, the barrier layer 48, the second insulating layer 44 and the first insulating layer 44 and located on the first conductor portion 41, wherein the first via hole 46A passes through the interlayer insulating layer 46, the second via hole 46B passes through the interlayer insulating layer 46, the barrier layer 48, the second insulating layer 44 and the first insulating layer 44, and the source 47A passes through the The first via 46A is connected to the second conductor portion 42, and the drain 47B is connected to the second conductor portion 42 through the second via 46B; specifically, the first conductor portion 41 includes a first conductor sub-portion 41A1 connected to the third active layer 43, and a second conductor sub-portion 41A2 connected to the first electrode, the orthographic projection of the first conductor sub-portion 41A1 on the insulating substrate 10 at least overlaps with a portion of the orthographic projection of the second conductor portion 42 on the insulating substrate 10, and the orthographic projection of the second conductor sub-portion 41A2 on the insulating substrate 10 does not overlap with the orthographic projection of the second conductor portion 42 on the insulating substrate 10.

[0077] As mentioned above, it can be understood that in this embodiment, along the direction from the source 47A to the drain 47B, the length of the first conductor portion 41 is greater than the length of the second conductor portion 42, thereby facilitating the connection between the drain 47B and the first conductor portion 41. Compared with the existing thin film transistor, this embodiment increases the distance between the source 47A and the drain 47B, avoiding contact short circuit between the source 47A and the drain 47B, which is beneficial to improving the production yield of the product.

[0078] In another embodiment, please combine light 3, Figure 6 and Figure 7 ;in, Figure 6 for Figure 3 Schematic diagram of the first cross-sectional structure along the AA′ direction; Figure 7 for Figure 6 Enlarged view of point B in the middle.

[0079] In this embodiment, the structure of the display panel is similar to / identical to the structure of the semiconductor device provided in the above embodiment. For details, please refer to the description of the semiconductor device in the above embodiment, which will not be repeated here. The only difference between the two is:

[0080] In this embodiment, the third active layer 43 is located on the sidewall 44C1 and the bottom 44C4 of the through hole 44C, and extends to the side of the insulating layer 44 away from the insulating substrate 10. Specifically, the third active layer 43 includes a first active sub-portion 43A1 and a second active sub-portion 43A2 connected to each other. The first active sub-portion 43A1 is located on the side of the insulating layer 44 away from the insulating substrate 10. The first active sub-portion 43A1 is connected to the second active layer 42. The second active sub-portion 43A2 passes through the through hole 44C. The side wall 44C1 of 4C is connected to the first active layer 41, wherein the first active sub-section 43A1 is connected to the second conductor section 42, the second active sub-section 43A2 is connected to the first conductor section 41, and the orthographic projection of the first conductor section 41 on the insulating substrate 10 covers the orthographic projection of the second active sub-section 43A2 on the insulating substrate 10, and the orthographic projection of the second conductor section 42 on the insulating substrate 10 covers the orthographic projection of the first active sub-section 43A1 on the insulating substrate 10.

[0081] It can be immediately seen that, in this embodiment, by setting the orthographic projection of the second conductor portion 42 on the insulating substrate 10 to cover the orthographic projection of the first active sub-portion 43A1 on the insulating substrate 10, the contact area between the second conductor portion 42 and the third active layer 43 is increased, thereby improving the stability of signal transmission.

[0082] In another embodiment, please combine light 3, Figure 8 ;in, Figure 8 for Figure 3 Schematic diagram of the third cross-sectional structure along the AA′ direction; Figure 9 for Figure 8 Enlarged view of point B in the middle.

[0083] In this embodiment, the structure of the display panel is similar to / identical to the structure of the semiconductor device provided in the above embodiment. For details, please refer to the description of the semiconductor device in the above embodiment, which will not be repeated here. The only difference between the two is:

[0084] In this embodiment, the second conductor portion 42 includes a third conductor sub-portion 42A1 connected to the third active layer 43, and a fourth conductor sub-portion 42A2 connected to the second electrode, wherein the doping ion concentration of the first conductor sub-portion 41A1 is lower than the doping ion concentration of the second conductor sub-portion 41A2, and the doping ion concentration of the third conductor sub-portion 42A1 is lower than the doping ion concentration of the fourth conductor sub-portion 42A2.

[0085] Specifically, in this embodiment, the first conductor sub-section 41A1 is connected to one side of the third active layer 43, and the third conductor sub-section 42A1 is connected to the other side of the third active layer 43; it can be understood that this embodiment prevents the plasma gas in the first conductor section 41 and the second conductor section 42 from diffusing toward the active section 43A by setting the first conductor sub-section 41A1 with a smaller doping ion concentration to be connected to one side of the third active layer 43, and the third conductor sub-section 42A1 with a smaller doping ion concentration to be connected to the other side of the third active layer 43, so as to achieve the effect of maintaining the working stability of the thin film transistor.

[0086] The present application also provides a method for manufacturing a semiconductor device. Figure 6 、 Figure 7 、 Figure 10 、 Figures 11A to 11G ;in, Figure 10 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application; Figures 11A to 11G for Figure 10 Structural process flow chart for semiconductor device manufacturing.

[0087] In this embodiment, the method for manufacturing the vertical structure semiconductor device includes the following steps:

[0088] Step S100: providing an insulating substrate 10.

[0089] Among them, when the insulating substrate 10 is a rigid substrate, the material can be metal or glass; when the insulating substrate 10 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide resin, and polyamide resin.

[0090] Step S200: forming a thin film transistor layer 40 on the insulating substrate 10, the thin film transistor layer 40 including a first active layer 41, an insulating layer 44 and a second active layer 42 stacked on the insulating substrate 10, the insulating layer 44 being arranged between the first active layer 41 and the second active layer 42 and covering the first active layer 41; wherein the insulating layer 44 is formed with a through hole 44C located on the first active layer 41, the thin film transistor layer 40 also includes a third active layer 43 at least partially located on a sidewall 44C1 of the through hole 44C, one side of the third active layer 43 is connected to the first active layer 41, and the other side of the third active layer 43 is connected to the second active layer 42.

[0091] Specifically, in this embodiment, before step S200, the method for manufacturing a semiconductor device further includes the following steps:

[0092] Step S110: forming a light shielding layer 20 and a first buffer layer 30 on the insulating substrate 10 in sequence. Figure 11A As shown; the material of the light shielding layer 20 includes but is not limited to metal materials, and the metal materials include but are not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the material of the first buffer layer 30 includes but is not limited to a single layer of silicon nitride (Si3N4), a single layer of silicon dioxide (SiO2), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above film layers.

[0093] It should be noted that, in this embodiment, the first active layer 41 includes a first conductor portion 41 doped with ions, the second active layer 42 includes a second conductor portion 42 doped with ions, and the third active layer 43 includes an active segment 43A located on the sidewall 44C1 of the through hole 44C. The orthographic projection of the first conductor portion 41 on the insulating substrate 10 overlaps with at least a portion of the orthographic projection of the second conductor portion 42 on the insulating substrate 10. One side of the active segment 43A is connected to the first conductor portion 41, and the other side of the active segment 43A is connected to the second conductor portion 42.

[0094] Specifically, in this embodiment, step S200 includes the following steps:

[0095] Step S201: forming a first amorphous silicon layer on the buffer layer, and performing crystallization treatment on the first amorphous silicon layer to form a first polycrystalline silicon thin film; specifically, depositing a layer of amorphous silicon material (a-si) on the buffer layer to form the first amorphous silicon layer, and performing excimer laser annealing (ELA) treatment on the first amorphous silicon layer to form the first polycrystalline silicon thin film.

[0096] Step S202: patterning the first polysilicon film to form a first polysilicon pattern. Specifically, using a mask, a positive photoresist, and a yellow light and etching process to pattern the first polysilicon film, thereby forming the first polysilicon pattern on the buffer layer.

[0097] Step S203: ion implantation is performed on the first polysilicon pattern to form the first conductor portion 41. Figure 11B As shown; wherein, the ions doped into the first polysilicon pattern are boron ions or phosphorus ions.

[0098] Step S204: forming a first insulating layer 44 on the first conductor portion 41, wherein the second insulating layer 44 covers the first conductor portion 41, and the materials of the first insulating layer 44 include but are not limited to single-layer silicon nitride (Si3N4), single-layer silicon dioxide (SiO2), single-layer silicon oxynitride (SiON), and single-layer silicon nitride oxide (SiON). x ), or a double-layer structure of the above film layers.

[0099] Step S205: A gate 45A is formed on a side of the second buffer layer 44 away from the first buffer layer 30, wherein the thickness of the gate 45A is greater than or equal to 0.05 microns and less than or equal to 0.2 microns, and the material of the gate 45A is a metal material, and the metal material includes but is not limited to at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W).

[0100] Specifically, the step S205 includes: forming a first metal layer 45 on a side of the second buffer layer 44 away from the first buffer layer 30, patterning the first metal layer 45 to form the gate 45A, etching an opening 45B located above the first conductor portion 41 on the gate 45A, and the opening 45B passes through the gate 45A. Figure 11C shown.

[0101] Step S206: forming a second insulating layer 44 on the side of the gate 45A away from the second buffer layer 44, wherein the second insulating layer 44 covers the gate 45A, thereby blocking water and oxygen and insulating the gate 45A. The materials of the second insulating layer 44 include but are not limited to single-layer silicon nitride (Si3N4), single-layer silicon dioxide (SiO2), single-layer silicon oxynitride (SiON), and single-layer silicon nitride oxide (SiON). x ), or a double-layer structure of the above film layers.

[0102] Step S207: Through a mask process, the through hole 44C located on the first conductor portion 41 is opened on the second insulating layer 44 and the first insulating layer 44, and the through hole 44C is corresponding to the opening 45B. The aperture of the through hole 44C is smaller than the aperture of the opening 45B, so that the gate 45A is arranged around the third active layer 43 on the side wall 44C1 of the through hole 44C, wherein the through hole 44C includes a first through hole 44C2 passing through the first insulating layer 44, and a second through hole 44C3 passing through the second insulating layer 44, and the angle between the side wall 44C1 of the second through hole 44C3 and the first active layer 41 is equal to the angle between the side wall 44C1 of the first through hole 44C2 and the first active layer 41, as shown in FIG. Figure 11D shown.

[0103] Step S208 : forming a third active layer 43 on a side of the second insulating layer 44 away from the first insulating layer 44 , wherein at least a portion of the third active layer 43 is located on the sidewall 44C1 of the through hole 44C.

[0104] Specifically, the third active layer 43 is located on the sidewall 44C1 and the bottom 44C4 of the through hole 44C, and extends to the side of the insulating layer 44 away from the insulating base 10; wherein the third active layer 43 includes a first active sub-portion 43A1 and a second active sub-portion 43A2 connected to each other, the first active sub-portion 43A1 is located on the side of the insulating layer 44 away from the insulating base 10, the second active sub-portion 43A2 passes through the sidewall 44C1 of the through hole 44C and is connected to the first conductor portion 41, and the orthographic projection of the first conductor portion 41 on the insulating base 10 covers the orthographic projection of the second active sub-portion 43A2 on the insulating base 10, as shown in FIG. Figure 11E shown.

[0105] Step S209: forming a barrier layer 48 on a side of the second insulating layer 44 away from the first insulating layer 44, at least a portion of the barrier layer 48 is located in the through hole 44C; specifically, the barrier layer 48 includes a first barrier portion 48A located on a side of the insulating layer 44 away from the insulating substrate 10, and a second barrier portion 48B located in the through hole 44C, a side of the first barrier portion 48A close to the second active layer 42 is flush with a side of the insulating layer 44 close to the second active layer 42, and a side of the second barrier portion 48B close to the second active layer 42 is flush with a side of the insulating layer 44 close to the second active layer 42. Preferably, the material of the barrier layer 48 is silicon oxide (SiO X ),like Figure 11F shown.

[0106] Step S210: forming a second amorphous silicon layer on a side of the third active layer 43 away from the first conductor portion 41, and performing crystallization treatment on the second amorphous silicon layer to form a second polycrystalline silicon thin film; specifically, depositing a layer of amorphous silicon material (a-si) on the third active layer 43 to form the second amorphous silicon layer, and performing excimer laser annealing (ELA) treatment on the second amorphous silicon layer to form the second polycrystalline silicon thin film.

[0107] Step S211 : patterning the third polysilicon film to form a second polysilicon pattern. Specifically, the third polysilicon film is patterned using a mask, positive photoresist, yellow light, and etching processes to form the second polysilicon pattern on the third active layer 43 .

[0108] Step S212: Ion implantation is performed on the second polysilicon pattern to form the second conductor portion 42, wherein the first active sub-portion 43A1 is connected to the second active layer 42, and the orthographic projection of the second conductor portion 42 on the insulating substrate 10 covers the orthographic projection of the first active sub-portion 43A1 on the insulating substrate 10.

[0109] Specifically, the first conductor portion 41 includes a first conductor sub-portion 41A1 connected to the third active layer 43, and a second conductor sub-portion 41A2 connected to the first conductor sub-portion 41A1, the orthographic projection of the first conductor sub-portion 41A1 on the insulating substrate 10 at least overlaps with a portion of the orthographic projection of the second conductor portion 42 on the insulating substrate 10, and the orthographic projection of the second conductor sub-portion 41A2 on the insulating substrate 10 does not overlap with the orthographic projection of the second conductor portion 42 on the insulating substrate 10. Figure 11G shown.

[0110] Step S213: forming an interlayer insulating layer 46 on a side of the barrier layer 48 away from the second insulating layer 44, wherein the interlayer insulating layer 46 covers the barrier layer 48, the second conductor portion 42 and the second gate 45A.

[0111] Step S214: Through a mask process, a first via 46A is opened on the interlayer insulating layer 46, and a second via 46B is opened on the interlayer insulating layer 46, the barrier layer 48, the second insulating layer 44 and the first insulating layer 44, wherein the first via 46A passes through the interlayer insulating layer 46 and is located on the second conductor portion 42, and the second via 46B passes through the interlayer insulating layer 46, the barrier layer 48, the second insulating layer 44 and the first insulating layer 44 and is located on the second conductor sub-portion 41A2.

[0112] Step S215: forming a source electrode 47A and a drain electrode 47B on the side of the interlayer insulating layer 46 away from the barrier layer 48, wherein the source electrode 47A is connected to the second conductor portion 42 through the first via hole 46A, and the drain electrode 47B is connected to the second conductor portion 42 through the second via hole 46B. Figure 6 and Figure 7 shown.

[0113] This embodiment provides an electronic device, which includes the semiconductor device described in any one of the above embodiments.

[0114] It can be understood that the semiconductor device has been described in detail in the above embodiments and will not be repeated here.

[0115] In specific applications, the electronic device can be a display screen of a smartphone, tablet computer, laptop computer, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV or digital camera, and can even be used on electronic devices with flexible display screens.

[0116] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0117] The above is a detailed introduction to a semiconductor device and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: Insulation substrate; a thin film transistor layer disposed on the insulating substrate, the thin film transistor layer comprising a first active layer, an insulating layer, and a second active layer stacked on the insulating substrate, the insulating layer being disposed between the first active layer and the second active layer and covering the first active layer; The insulating layer is formed with a through hole located on the first active layer, and the thin film transistor layer also includes a third active layer at least partially located on the side wall of the through hole, one side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer. The thin film transistor layer also includes a blocking layer located between the insulating layer and the second active layer, and at least a portion of the blocking layer is located in the through hole.

2. The semiconductor device according to claim 1, wherein The thin film transistor layer further includes a first metal layer located in the insulating layer, the first metal layer is insulated from the first active layer, and the first metal layer is located at least on one side of the through hole.

3. The semiconductor device according to claim 2, wherein: The first metal layer is disposed around the third active layer on the sidewall of the through hole.

4. The semiconductor device according to claim 1, wherein The first active layer includes a first conductor portion doped with ions, the second active layer includes a second conductor portion doped with ions, and the orthographic projection of the first conductor portion on the insulating substrate at least partially overlaps with the orthographic projection of the second conductor portion on the insulating substrate; wherein one side of the third active layer is connected to the first conductor portion, and the other side of the third active layer is connected to the second conductor portion.

5. The semiconductor device according to claim 4, wherein The doping ion concentration of the second conductor portion is lower than the doping ion concentration of the first conductor portion.

6. The semiconductor device according to claim 4, wherein The thin film transistor layer includes a second metal layer located on a side of the second active layer away from the insulating layer, the second metal layer includes a first electrode connected to the first conductor portion, and a second electrode connected to the second conductor portion; The first conductor portion includes a first conductor sub-portion connected to the third active layer and a second conductor sub-portion connected to the first electrode, and the orthographic projection of the second conductor sub-portion on the insulating substrate does not overlap with the orthographic projection of the second conductor portion on the insulating substrate.

7. The semiconductor device according to claim 6, wherein: The second conductor portion includes a third conductor sub-portion connected to the third active layer, and a fourth conductor sub-portion connected to the second electrode, wherein the doping ion concentration of the first conductor sub-portion is less than the doping ion concentration of the second conductor sub-portion, and the doping ion concentration of the third conductor sub-portion is less than the doping ion concentration of the fourth conductor sub-portion.

8. The semiconductor device according to claim 7, wherein: The first conductor sub-section is connected to one side of the third active layer, and the third conductor sub-section is connected to the other side of the third active layer.

9. The semiconductor device according to claim 1, wherein The thin film transistor layer includes a channel located between the first active layer and the second active layer, and the length of the channel and the depth of the through hole satisfy the following relationship: Wherein, L represents the length of the channel, H represents the depth of the through hole, and α represents the angle between the third active layer on the sidewall of the through hole and the bottom of the through hole.

10. The semiconductor device according to claim 9, wherein An included angle α between the third active layer on the sidewall of the through hole and the bottom of the through hole is greater than 90 degrees and less than or equal to 120 degrees.

11. The semiconductor device according to claim 9, wherein In a direction perpendicular to the insulating substrate, a length of the channel is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

12. The semiconductor device according to claim 1, wherein The third active layer includes a first active sub-section and a second active sub-section connected to each other, the first active sub-section is located on a side of the insulating layer away from the insulating substrate, the first active sub-section is connected to the second active layer, and the second active sub-section is connected to the first active layer through the side wall of the through hole.

13. The semiconductor device according to claim 1, wherein A side of the barrier layer close to the second active layer is flush with a side of the insulating layer close to the second active layer.

14. The semiconductor device according to claim 1, wherein The third active layer is located on the sidewall and bottom of the through hole and extends to a side of the insulating layer away from the insulating base.

15. The semiconductor device according to claim 1, wherein The insulating layer includes a first insulating layer and a second insulating layer provided on the insulating substrate, the first insulating layer is located on and covers the first active layer, and the second active layer covers the first active layer; The first insulating layer is formed with a first through hole located on the first active layer, and the second insulating layer is formed with a second through hole located on the first active layer and connected to the first through hole, and the angle between the side wall of the second through hole and the first active layer is equal to the angle between the side wall of the first through hole and the first active layer.

16. An electronic device, characterized in that: The electronic device comprises the semiconductor device according to any one of claims 1 to 15.

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