A reverse protection circuit and load switch

Abstract

The application provides a reverse protection circuit and a load switch, and relates to the technical field of reverse protection circuits.The reverse protection circuit comprises a reverse voltage detection and selection circuit, a power tube P4 and a power tube shutdown circuit.The power tube P4 is used for outputting power from a voltage input end VIN to a voltage output end VOUT.The reverse voltage detection and selection circuit is used for comparing the voltage of the voltage input end VIN and the voltage of the voltage output end VOUT, and adjusting the switch of the power tube shutdown circuit to be turned off when the difference between the voltage of the voltage output end VOUT and the voltage of the voltage input end VIN is greater than a reverse voltage detection threshold value.The reverse protection can be completed by setting only one power tube, and the integrated cost of the reverse protection circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of reverse protection circuits, and in particular to a reverse protection circuit and a load switch. Background Art

[0002] Reverse protection circuits are crucial components of load switches. For example, they prevent current from flowing from the voltage output terminal (VOUT) to the voltage input terminal (VIN), thereby preventing damage to the power transistor. Existing reverse protection circuits include the following types: The first type uses diodes. Diodes are low-cost, easy to integrate, and suitable for low-current applications. However, high-current applications require a small voltage drop between the input and output terminals of the load switch, and the large forward voltage of diodes reduces power supply efficiency. The second type uses two power transistors connected back-to-back. While this reverse protection circuit reduces the voltage drop between the voltage input terminal (VIN) and the voltage output terminal (VOUT) compared to diodes, the two power transistors occupy a larger area, increasing integration costs. The third type uses reverse voltage detection. This circuit uses the PMOS transistor's turn-on voltage (VTH_P) as the reverse voltage detection threshold. The power transistor is shut down when the voltage difference between the voltage output terminal (VOUT) and the voltage input terminal (VIN) exceeds |VTH_P|. However, in this reverse protection circuit, the reverse voltage detection threshold uses a relatively large turn-on voltage VTH_P, while the power tube's on-resistance is very small. As a result, the reverse current is already relatively large when the power tube turns off the load switch, which can easily burn out the power tube. Therefore, there is an urgent need for a reverse protection circuit that is easy to integrate and can promptly shut down the power tube. Summary of the Invention

[0003] The purpose of the present invention is to provide a reverse protection circuit and a load switch. The reverse protection circuit is applied to the load switch, and only one power tube is provided to complete the reverse protection, thereby reducing the integration cost of the reverse protection circuit.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A reverse protection circuit includes: a reverse voltage detection circuit, a power tube P4 and a power tube shutdown circuit;

[0006] The drain of the power tube P4 and the first port of the reverse voltage detection circuit are both connected to the voltage input terminal VIN;

[0007] The source of the power tube P4 and the second port of the reverse voltage detection circuit are both connected to the voltage output terminal VOUT;

[0008] The gate of the power tube P4 is connected to the first port of the power tube shutdown circuit;

[0009] The back gate of the power tube P4 is connected to the third port of the reverse voltage detection circuit and the second port of the power tube shutdown circuit respectively;

[0010] The fourth port of the reverse voltage detection circuit is connected to the third port of the power tube shutdown circuit;

[0011] The fifth port of the reverse voltage detection circuit is used to control the opening and closing state of the switch S in the power tube shutdown circuit;

[0012] The fourth port of the power tube shutdown circuit is connected to the output end of the driving circuit;

[0013] The power transistor P4 is used to output power from the voltage input terminal VIN to the voltage output terminal VOUT;

[0014] The reverse voltage detection circuit is used to compare the voltage of the voltage input terminal VIN and the voltage of the voltage output terminal VOUT, and when the difference between the voltage of the voltage output terminal VOUT and the voltage of the voltage input terminal VIN is greater than the reverse voltage detection threshold, adjust the switch of the power tube shutdown circuit to disconnect.

[0015] Optionally, the power tube shutdown circuit further includes: a PMOS tube P3;

[0016] The connection point formed by connecting the drain of the PMOS tube P3 and the first end of the switch S is the first port of the power tube shutdown circuit;

[0017] The source of the PMOS tube P3 is the second port of the power tube shutdown circuit;

[0018] The gate of the PMOS tube P3 is the third port of the power tube shutdown circuit;

[0019] The second end of the switch S is the fourth port of the power tube shutdown circuit.

[0020] Optionally, the reverse voltage detection circuit includes: a reverse voltage detection circuit and a back gate potential selection circuit of a power tube;

[0021] The connection point obtained by connecting the positive input terminal of the reverse voltage detection circuit and the first port of the back gate potential selection circuit of the power tube is the first port of the reverse voltage detection circuit;

[0022] The connection point obtained by connecting the negative input terminal of the reverse voltage detection circuit and the second port of the back gate potential selection circuit of the power tube is the second port of the reverse voltage detection circuit;

[0023] The connection point obtained by connecting the forward output terminal of the reverse voltage detection circuit and the third port of the back gate potential selection circuit of the power tube is the fourth port of the reverse voltage detection circuit;

[0024] The connection point formed by connecting the reverse output terminal of the reverse voltage detection circuit and the fourth port of the back gate potential selection circuit of the power tube is the fifth port of the reverse voltage detection circuit;

[0025] The fifth port of the back gate potential selection circuit of the power tube is the third port of the reverse voltage selection circuit;

[0026] The reverse voltage detection circuit is used to compare the voltage at the voltage input terminal VIN and the voltage at the voltage output terminal VOUT;

[0027] The back-gate potential selection circuit of the power tube is used to select the largest voltage between the voltage at the voltage input terminal VIN and the voltage at the voltage output terminal VOUT as the back-gate voltage of the power tube P4.

[0028] Optionally, the back gate potential selection circuit of the power tube includes: a PMOS tube P1 and a PMOS tube P2;

[0029] The drain of the PMOS tube P1 is the first port of the back gate potential selection circuit of the power tube;

[0030] A connection point formed by connecting the source of the PMOS transistor P1 and the source of the PMOS transistor P2 is the fifth port of the back gate potential selection circuit of the power transistor;

[0031] The gate of the PMOS tube P1 is the fourth port of the back gate potential selection circuit of the power tube;

[0032] The drain of the PMOS tube P2 is the second port of the back gate potential selection circuit of the power tube;

[0033] The gate of the PMOS tube P2 is the third port of the back gate potential selection circuit of the power tube.

[0034] Optionally, the reverse voltage detection circuit includes: a PMOS transistor P5, a PMOS transistor P6, a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, a PMOS transistor P10, a PMOS transistor P11, a PMOS transistor P12, a PMOS transistor P13, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, an NMOS transistor N6, an NMOS transistor N7, an NMOS transistor N8, an NMOS transistor N9, and a bias current unit;

[0035] The connection point formed by connecting the source of the PMOS transistor P5 and the source of the PMOS transistor P6 is the negative input terminal of the reverse voltage detection circuit;

[0036] The back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13, and the source of the PMOS transistor P13 are all connected to the back gate of the power transistor P4;

[0037] The connection point formed by connecting the source of the PMOS transistor P7, the source of the PMOS transistor P8, the source of the PMOS transistor P9, the back gate of the PMOS transistor P9, the source of the PMOS transistor P10, and the back gate of the PMOS transistor P10 is the positive input terminal of the reverse voltage detection circuit;

[0038] The gate of the PMOS transistor P5, the gate of the PMOS transistor P6, the drain of the PMOS transistor P6, the gate of the PMOS transistor P7, the drain of the PMOS transistor P7 and the gate of the PMOS transistor P8 are connected to one end of the bias current unit;

[0039] The other end of the bias current unit, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, the source of the NMOS transistor N5, the source of the NMOS transistor N6, the source of the NMOS transistor N7, the source of the NMOS transistor N8, the source of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded;

[0040] The drain of the PMOS transistor P5, the drain of the NMOS transistor N1, the gate of the NMOS transistor N1, the gate of the NMOS transistor N2, the drain of the NMOS transistor N3 and the gate of the NMOS transistor N6 are connected;

[0041] The drain of the PMOS transistor P8, the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, the gate of the NMOS transistor N4, the drain of the NMOS transistor N4 and the gate of the NMOS transistor N5 are connected;

[0042] The drain of the PMOS transistor P9, the gate of the PMOS transistor P9, the gate of the PMOS transistor P10 and the drain of the NMOS transistor N5 are connected;

[0043] The drain of the PMOS transistor P10, the drain of the NMOS transistor N6, the gate of the PMOS transistor P11, and the gate of the NMOS transistor N7 are connected;

[0044] The drain of the PMOS transistor P11, the drain of the NMOS transistor N7, the gate of the PMOS transistor P12, and the gate of the NMOS transistor N8 are connected;

[0045] The connection point formed by connecting the drain of the PMOS transistor P12, the drain of the NMOS transistor N8, the gate of the PMOS transistor P13, and the gate of the NMOS transistor N9 is the positive output end of the reverse voltage detection circuit;

[0046] A connection point formed by connecting the drain of the PMOS transistor P13 and the drain of the NMOS transistor N9 is a reverse output end of the reverse voltage detection circuit.

[0047] Optionally, the ratio of the width to length of the PMOS transistor P5 to the width to length of the PMOS transistor P6 is 1:1;

[0048] The ratio of the width to length of the PMOS transistor P7 to the width to length of the PMOS transistor P8 is 1:1;

[0049] The ratio of the width to length of the PMOS transistor P9 to the width to length of the PMOS transistor P10 is 1:6;

[0050] The ratio of the width to length of the NMOS transistor N1 to the width to length of the NMOS transistor N2 is 1:1;

[0051] The ratio of the width to length of the NMOS transistor N3 to the width to length of the NMOS transistor N4 is 1:1;

[0052] The ratio of the width to length of the NMOS transistor N5 to the width to length of the NMOS transistor N6 is 1:6.

[0053] A load switch is provided, wherein the load switch applies the reverse protection circuit.

[0054] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0055] The present invention provides a reverse protection circuit and a load switch, comprising: a reverse voltage detection circuit, a power tube P4 and a power tube shutdown circuit; only one power tube is provided to complete reverse protection, thereby reducing the integration cost of the reverse protection circuit.

[0056] In addition, in a reverse protection circuit provided by the invention, the width-to-length ratio of the PMOS tube in the reverse voltage detection circuit within the reverse voltage detection circuit can be adjusted to adjust the reverse voltage detection threshold, thereby avoiding the situation in the prior art where the turn-on voltage VTH_P of the PMOS tube is used as the reverse voltage detection threshold, where the reverse current is already too large when the power tube turns off the load switch, and the excessively large reverse current can easily burn the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 This is a reverse protection circuit diagram in Example 1 of the present invention;

[0059] Figure 2 This is a reverse voltage detection circuit diagram in Example 1 of the present invention;

[0060] Figure 3 Graph showing changes of VOUT and VIN over time in Example 1 of the present invention;

[0061] Figure 4 Graph showing the change of the REV_L signal over time in Example 1 of the present invention;

[0062] Figure 5 Graph showing the change of the REV_H signal over time in Example 1 of the present invention;

[0063] Figure 6 is a graph showing the change of the SUB signal over time in Example 1 of the present invention;

[0064] Figure 7 Graph showing the change of the GATE signal over time in Example 1 of the present invention;

[0065] Figure 8 is a curve diagram showing the reverse current IREVERSE changing with time in Example 1 of the present invention;

[0066] Figure 9 This is a circuit layout diagram of the PMOS tube of the back gate potential selection circuit of the power tube in Example 1 of the present invention. DETAILED DESCRIPTION

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0068] The purpose of the present invention is to provide a reverse protection circuit and a load switch. The reverse protection circuit is applied to the load switch, and only one power tube is provided to complete the reverse protection, thereby reducing the integration cost of the reverse protection circuit.

[0069] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] Example 1

[0071] like Figure 1 As shown, this embodiment provides a reverse protection circuit, including: a reverse voltage detection circuit, a power tube P4 and a power tube shutdown circuit; the drain of the power tube P4 and the first port of the reverse voltage detection circuit are both connected to the voltage input terminal VIN; the source of the power tube P4 and the second port of the reverse voltage detection circuit are both connected to the voltage output terminal VOUT; the gate of the power tube P4 is connected to the first port of the power tube shutdown circuit; the back gate of the power tube P4 is respectively connected to the third port of the reverse voltage detection circuit and the second port of the power tube shutdown circuit; the fourth port of the reverse voltage detection circuit is connected to the power tube shutdown circuit. The third port of the power tube shutdown circuit is connected; the fifth port of the reverse voltage detection circuit is used to control the opening and closing state of the switch S in the power tube shutdown circuit; the fourth port of the power tube shutdown circuit is connected to the output end of the drive circuit; the power tube P4 is used to output power from the voltage input terminal VIN to the voltage output terminal VOUT; the reverse voltage detection circuit is used to compare the voltage of the voltage input terminal VIN with the voltage of the voltage output terminal VOUT, and when the difference between the voltage of the voltage output terminal VOUT and the voltage of the voltage input terminal VIN is greater than the reverse voltage detection threshold, adjust the switch S of the power tube shutdown circuit to be disconnected.

[0072] Specifically, the reverse voltage detection circuit's reverse terminal REV_L controls the opening and closing of switch S. Switch S controls the connection between the output DRV of drive circuit I2 and the gate GATE of power transistor P4. The reverse voltage detection circuit (RCP) is a comparator I1 that compares the VIN signal with the VOUT signal and outputs logic control signals REV_L and REV_H. The power transistor's back-gate potential selection circuit turns on power transistor P1 and turns off power transistor P2 when the logic control signals REV_L are low and REV_H are high. The back-gate potential SUB of power transistor P4 is set to VIN, i.e., the highest potential is selected. Conversely, the circuit turns off power transistor P1 and turns on power transistor P2, setting the back-gate potential SUB of power transistor P4 to the potential of the voltage output terminal VOUT, i.e., the highest potential is selected. Power transistor P4 is a high-power PMOS transistor responsible for outputting power from the voltage input terminal VIN to the voltage output terminal VOUT. When the voltage at the voltage output terminal VOUT is higher than the voltage at the voltage input terminal VIN by a reverse voltage detection threshold, the PMOS tube P3 pulls up the gate GATE potential of the power tube P4, and at the same time, the switch S disconnects the output DRV of the drive circuit I2 from the gate GATE of the power tube P4.

[0073] The power tube shutdown circuit further includes: a PMOS tube P3; a connection point formed by connecting the drain of the PMOS tube P3 and the first end of the switch S is a first port of the power tube shutdown circuit; a source of the PMOS tube P3 is a second port of the power tube shutdown circuit; a gate of the PMOS tube P3 is a third port of the power tube shutdown circuit; and a second end of the switch S is a fourth port of the power tube shutdown circuit.

[0074] Specifically, the reverse voltage detection circuit includes: a reverse voltage detection circuit and a back-gate potential selection circuit for a power tube; the connection point obtained by connecting the positive input terminal of the reverse voltage detection circuit with the first port of the back-gate potential selection circuit for the power tube is the first port of the reverse voltage detection circuit; the connection point obtained by connecting the negative input terminal of the reverse voltage detection circuit with the second port of the back-gate potential selection circuit for the power tube is the second port of the reverse voltage detection circuit; the connection point obtained by connecting the positive output terminal of the reverse voltage detection circuit with the third port of the back-gate potential selection circuit for the power tube is the fourth port of the reverse voltage detection circuit; the connection point obtained by connecting the reverse output terminal of the reverse voltage detection circuit with the fourth port of the back-gate potential selection circuit for the power tube is the fifth port of the reverse voltage detection circuit; the fifth port of the back-gate potential selection circuit for the power tube is the third port of the reverse voltage detection circuit; the reverse voltage detection circuit is used to compare the voltage of the voltage input terminal VIN and the voltage of the voltage output terminal VOUT; the back-gate potential selection circuit for the power tube is used to select the largest voltage between the voltage of the voltage input terminal VIN and the voltage of the voltage output terminal VOUT as the back-gate voltage of the power tube P4.

[0075] Specifically, the back-gate potential selection circuit of the power tube includes: a PMOS tube P1 and a PMOS tube P2; the drain of the PMOS tube P1 serves as the first port of the back-gate potential selection circuit of the power tube; the connection point obtained by connecting the source of the PMOS tube P1 and the source of the PMOS tube P2 serves as the fifth port of the back-gate potential selection circuit of the power tube; the gate of the PMOS tube P1 serves as the fourth port of the back-gate potential selection circuit of the power tube; the drain of the PMOS tube P2 serves as the second port of the back-gate potential selection circuit of the power tube; and the gate of the PMOS tube P2 serves as the third port of the back-gate potential selection circuit of the power tube.

[0076] like Figure 2 The reverse voltage detection circuit includes: a PMOS transistor P5, a PMOS transistor P6, a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, a PMOS transistor P10, a PMOS transistor P11, a PMOS transistor P12, a PMOS transistor P13, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, an NMOS transistor N6, an NMOS transistor N7, an NMOS transistor N8, an NMOS transistor N9 and a bias current unit.

[0077] The connection point formed by connecting the source of the PMOS transistor P5 and the source of the PMOS transistor P6 is the negative input terminal of the reverse voltage detection circuit.

[0078] The back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13, and the source of the PMOS transistor P13 are all connected to the back gate of the power transistor P4.

[0079] The connection point obtained by connecting the source of the PMOS transistor P7, the source of the PMOS transistor P8, the source of the PMOS transistor P9, the back gate of the PMOS transistor P9, the source of the PMOS transistor P10 and the back gate of the PMOS transistor P10 is the positive input terminal of the reverse voltage detection circuit.

[0080] The gate of the PMOS transistor P5 , the gate of the PMOS transistor P6 , the drain of the PMOS transistor P6 , the gate of the PMOS transistor P7 , the drain of the PMOS transistor P7 , and the gate of the PMOS transistor P8 are connected to one end of the bias current unit.

[0081] The other end of the bias current unit, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, the source of the NMOS transistor N5, the source of the NMOS transistor N6, the source of the NMOS transistor N7, the source of the NMOS transistor N8, the source of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded.

[0082] The drain of the PMOS transistor P5 , the drain of the NMOS transistor N1 , the gate of the NMOS transistor N1 , the gate of the NMOS transistor N2 , the drain of the NMOS transistor N3 , and the gate of the NMOS transistor N6 are connected.

[0083] The drain of the PMOS transistor P8, the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, the gate of the NMOS transistor N4, the drain of the NMOS transistor N4 and the gate of the NMOS transistor N5 are connected.

[0084] The drain of the PMOS transistor P9 , the gate of the PMOS transistor P9 , the gate of the PMOS transistor P10 , and the drain of the NMOS transistor N5 are connected.

[0085] The drain of the PMOS transistor P10 , the drain of the NMOS transistor N6 , the gate of the PMOS transistor P11 , and the gate of the NMOS transistor N7 are connected.

[0086] The drain of the PMOS transistor P11, the drain of the NMOS transistor N7, the gate of the PMOS transistor P12, and the gate of the NMOS transistor N8 are connected.

[0087] A connection point formed by connecting the drain of the PMOS transistor P12, the drain of the NMOS transistor N8, the gate of the PMOS transistor P13, and the gate of the NMOS transistor N9 is a positive output terminal of the reverse voltage detection circuit.

[0088] A connection point formed by connecting the drain of the PMOS transistor P13 and the drain of the NMOS transistor N9 is a reverse output terminal of the reverse voltage detection circuit.

[0089] Specifically, the ratio of the width to length ratio of the PMOS transistor P5 to the width to length ratio of the PMOS transistor P6 is 1:1; the ratio of the width to length ratio of the PMOS transistor P7 to the width to length ratio of the PMOS transistor P8 is 1:1; the ratio of the width to length ratio of the PMOS transistor P9 to the width to length ratio of the PMOS transistor P10 is 1:6; the ratio of the width to length ratio of the NMOS transistor N1 to the width to length ratio of the NMOS transistor N2 is 1:1; the ratio of the width to length ratio of the NMOS transistor N3 to the width to length ratio of the NMOS transistor N4 is 1:1; and the ratio of the width to length ratio of the NMOS transistor N5 to the width to length ratio of the NMOS transistor N6 is 1:6.

[0090] In this embodiment, PMOS transistors P5 and PMOS transistors P6 form a current mirror unit with an M ratio of 1:1. PMOS transistors P7 and PMOS transistors form a current mirror unit with an M ratio of 1:1. NMOS transistors N1, NMOS transistors N2, and NMOS transistors N6 form a current mirror unit with an M ratio of 1:1:6. NMOS transistors N4, NMOS transistors N3, and NMOS transistors N5 form a current mirror unit with an M (number of devices) ratio of 1:1:1. PMOS transistors P9 and PMOS transistors P10 form a current mirror unit with an M ratio of 1:6. PMOS transistors P11 and NMOS transistors N7 form an inverter unit. PMOS transistors P12 and NMOS transistors N8 form an inverter unit. PMOS transistors P13 and NMOS transistors N9 form an inverter unit. IBIAS is a bias current unit.

[0091] The working curves of each node in the reverse protection circuit in this embodiment are as follows: Figure 3-8 As shown, Figure 3-Figure 8 , the initial state of the signal at the voltage output terminal VOUT is not higher than the signal at the voltage input terminal VIN, and the circuit is in a normal working state without reverse protection. At this time, the logic control signal REV_L signal is L, the logic control signal REV_H signal is H, the back gate potential SUB signal selects the voltage input terminal VIN signal, the gate GATE signal is L, and there is no reverse current I REVERSE Then the voltage input VIN remains unchanged, and the voltage signal at the voltage output terminal VOUT gradually increases. As the voltage signal at the voltage output terminal VOUT increases, the reverse current I REVERSE When the voltage output terminal VOUT voltage signal rises to VOUT-VIN>VRCP, the logic control signal REV_L signal is H, the logic control signal REV_H signal is L, the back gate potential SUB signal selects VOUT, the gate GATE signal is H, and the reverse current I REVERSE Close, the circuit enters the reverse protection state.

[0092] The reverse voltage detection threshold is defined as V RCP ,according to Figure 2We can get:

[0093] V RCP =V GS_P6 -V GS_P7 (1)

[0094] Among them, V GS_P6 Represents the gate-source voltage of PMOS tube P6; V GS_P7 Indicates the gate-source voltage of PMOS tube P7.

[0095] If PMOS transistors P6 and PMOS transistors P7 operate in the saturation region and the channel length modulation effect is ignored, according to formula (1), we can obtain:

[0096]

[0097] In formula (2), μ P is the surface mobility of the P-channel device (cm 2 / V·s), C OX is the gate oxide capacitance per unit area (F / cm 2 ). I DS_P6 Indicates the source-drain current of PMOS tube P6; I DS_P7 Represents the source-drain current of PMOS tube P7; V TH_P6 Indicates the turn-on threshold voltage of PMOS tube P6; V TH_P7 Indicates the turn-on threshold voltage of the PMOS tube P7.

[0098] I BIAS =I DS_P6 +I DS_P7 (3)

[0099] The condition for the reverse voltage detection circuit (RCP) output REV_L or REV_H level to reverse is I DS_P6 =I DS_P7 ,Right now

[0100] V TH_P6 ≈V TH_P7 (4)

[0101] Then, formula (2) can be converted to:

[0102]

[0103] According to formula (5), the desired reverse voltage detection threshold V can be obtained by adjusting the current of the bias current unit, the width-to-length ratio of the PMOS tube P6, or the width-to-length ratio of the PMOS tube P7. RCP .

[0104] The reverse voltage detection circuit (RCP) of the present invention is not only simple in structure but also small in device size. It is also easy to achieve good device matching in layout design. The resulting reverse voltage detection threshold (VRCP) can also be designed to be very small. In addition, the back gate potential selection circuit of the power tube is also very simple, requiring only two PMOS tubes. Through the outputs REV_L and REV_H of the reverse voltage detection circuit (RCP), the PMOS tube P1 and the PMOS tube P2 can control the back gate selection of the power tube to have the highest potential. If VOUT-VIN>V RCP , then SUB selects VOUT; otherwise, SUB selects VIN. In the layout design, if Figure 4 , P1 and P2 in the back gate potential selection circuit of the power tube are respectively placed on both sides of the power tube P4 to form a symmetrical structure.

[0105] Example 2

[0106] This embodiment provides a load switch, and the load switch applies a reverse protection circuit as described in Example 1.

[0107] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from the other embodiments. Similar or identical parts between the various embodiments can be referred to in conjunction with each other. At the same time, those skilled in the art will appreciate that variations in the specific implementation and scope of application are possible based on the principles of the present invention. In summary, this specification should not be construed as limiting the present invention.

Claims

1. A reverse protection circuit, characterized in that: include: Reverse voltage detection circuit, power tube P4 and power tube shutdown circuit; The drain of the power tube P4 and the first port of the reverse voltage detection circuit are both connected to the voltage input terminal VIN; The source of the power tube P4 and the second port of the reverse voltage detection circuit are both connected to the voltage output terminal VOUT; The gate of the power tube P4 is connected to the first port of the power tube shutdown circuit; The back gate of the power tube P4 is connected to the third port of the reverse voltage detection circuit and the second port of the power tube shutdown circuit respectively; The fourth port of the reverse voltage detection circuit is connected to the third port of the power tube shutdown circuit; The fifth port of the reverse voltage detection circuit is used to control the opening and closing state of the switch S in the power tube shutdown circuit; The fourth port of the power tube shutdown circuit is connected to the output end of the driving circuit; The power transistor P4 is used to output power from the voltage input terminal VIN to the voltage output terminal VOUT; The reverse voltage detection circuit is used to compare the voltage of the voltage input terminal VIN with the voltage of the voltage output terminal VOUT, and when the difference between the voltage of the voltage output terminal VOUT and the voltage of the voltage input terminal VIN is greater than the reverse voltage detection threshold, adjust the switch of the power tube shutdown circuit to be disconnected; The power tube shutdown circuit further includes: PMOS tube P3; The connection point formed by connecting the drain of the PMOS tube P3 and the first end of the switch S is the first port of the power tube shutdown circuit; The source of the PMOS tube P3 is the second port of the power tube shutdown circuit; The gate of the PMOS tube P3 is the third port of the power tube shutdown circuit; The second end of the switch S is the fourth port of the power tube shutdown circuit; The reverse voltage detection circuit includes: a reverse voltage detection circuit and a back gate potential selection circuit of the power tube; The connection point obtained by connecting the forward output terminal of the reverse voltage detection circuit and the third port of the back gate potential selection circuit of the power tube is the fourth port of the reverse voltage detection circuit; The reverse voltage detection circuit is used to compare the voltage at the voltage input terminal VIN and the voltage at the voltage output terminal VOUT; The back-gate potential selection circuit of the power tube is used to select the largest voltage between the voltage at the voltage input terminal VIN and the voltage at the voltage output terminal VOUT as the back-gate voltage of the power tube P4.

2. A reverse protection circuit according to claim 1, characterized in that: The connection point obtained by connecting the positive input terminal of the reverse voltage detection circuit and the first port of the back gate potential selection circuit of the power tube is the first port of the reverse voltage detection circuit; The connection point obtained by connecting the negative input terminal of the reverse voltage detection circuit and the second port of the back gate potential selection circuit of the power tube is the second port of the reverse voltage detection circuit; The connection point formed by connecting the reverse output terminal of the reverse voltage detection circuit and the fourth port of the back gate potential selection circuit of the power tube is the fifth port of the reverse voltage detection circuit; The fifth port of the back gate potential selection circuit of the power tube is the third port of the reverse voltage selection circuit.

3. The reverse protection circuit according to claim 2, characterized in that: The back gate potential selection circuit of the power tube includes: PMOS tube P1 and PMOS tube P2; The drain of the PMOS tube P1 is the first port of the back gate potential selection circuit of the power tube; A connection point formed by connecting the source of the PMOS transistor P1 and the source of the PMOS transistor P2 is the fifth port of the back gate potential selection circuit of the power transistor; The gate of the PMOS tube P1 is the fourth port of the back gate potential selection circuit of the power tube; The drain of the PMOS tube P2 is the second port of the back gate potential selection circuit of the power tube; The gate of the PMOS tube P2 is the third port of the back gate potential selection circuit of the power tube.

4. The reverse protection circuit according to claim 1, characterized in that: The reverse voltage detection circuit comprises: PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, PMOS transistor P9, PMOS transistor P10, PMOS transistor P11, PMOS transistor P12, PMOS transistor P13, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9 and a bias current unit; The connection point formed by connecting the source of the PMOS transistor P5 and the source of the PMOS transistor P6 is the negative input terminal of the reverse voltage detection circuit; The back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13, and the source of the PMOS transistor P13 are all connected to the back gate of the power transistor P4; The connection point formed by connecting the source of the PMOS transistor P7, the source of the PMOS transistor P8, the source of the PMOS transistor P9, the back gate of the PMOS transistor P9, the source of the PMOS transistor P10, and the back gate of the PMOS transistor P10 is the positive input terminal of the reverse voltage detection circuit; The gate of the PMOS transistor P5, the gate of the PMOS transistor P6, the drain of the PMOS transistor P6, the gate of the PMOS transistor P7, the drain of the PMOS transistor P7 and the gate of the PMOS transistor P8 are connected to one end of the bias current unit; The other end of the bias current unit, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, the source of the NMOS transistor N5, the source of the NMOS transistor N6, the source of the NMOS transistor N7, the source of the NMOS transistor N8, the source of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded; The drain of the PMOS transistor P5, the drain of the NMOS transistor N1, the gate of the NMOS transistor N1, the gate of the NMOS transistor N2, the drain of the NMOS transistor N3 and the gate of the NMOS transistor N6 are connected; The drain of the PMOS transistor P8, the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, the gate of the NMOS transistor N4, the drain of the NMOS transistor N4 and the gate of the NMOS transistor N5 are connected; The drain of the PMOS transistor P9, the gate of the PMOS transistor P9, the gate of the PMOS transistor P10 and the drain of the NMOS transistor N5 are connected; The drain of the PMOS transistor P10, the drain of the NMOS transistor N6, the gate of the PMOS transistor P11, and the gate of the NMOS transistor N7 are connected; The drain of the PMOS transistor P11, the drain of the NMOS transistor N7, the gate of the PMOS transistor P12, and the gate of the NMOS transistor N8 are connected; The connection point formed by connecting the drain of the PMOS transistor P12, the drain of the NMOS transistor N8, the gate of the PMOS transistor P13, and the gate of the NMOS transistor N9 is the positive output end of the reverse voltage detection circuit; A connection point formed by connecting the drain of the PMOS transistor P13 and the drain of the NMOS transistor N9 is a reverse output end of the reverse voltage detection circuit.

5. The reverse protection circuit according to claim 4, characterized in that: The ratio of the width to length of the PMOS transistor P5 to the width to length of the PMOS transistor P6 is 1:1; The ratio of the width to length of the PMOS transistor P7 to the width to length of the PMOS transistor P8 is 1:1; The ratio of the width to length of the PMOS transistor P9 to the width to length of the PMOS transistor P10 is 1:6; The ratio of the width to length of the NMOS transistor N1 to the width to length of the NMOS transistor N2 is 1:1; The ratio of the width to length of the NMOS transistor N3 to the width to length of the NMOS transistor N4 is 1:1; The ratio of the width to length of the NMOS transistor N5 to the width to length of the NMOS transistor N6 is 1:

6.

6. A load switch, characterized in that: The load switch applies a reverse protection circuit as described in any one of claims 1 to 5.

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