A multi-stage down-conversion frequency synthesis device and method

Abstract

The present invention discloses a multi-stage down-conversion frequency synthesis device and method, belonging to the field of frequency synthesis. The present invention simplifies the circuit and reduces debugging difficulty, making debugging easier. A VCO phase-locked loop also generates a fixed tuned local oscillator frequency using the multi-stage down-conversion method. The appropriate VCO fixed tuned local oscillator point can be flexibly selected based on different YTO frequency bands, effectively avoiding various intermodulation spurs. By mixing the YTO and VCO, the near-end phase noise curve of the YTO loop is brought close to the phase noise curve of the VCO loop, achieving a low phase noise level. Both the YTO loop and the VCO loop achieve low phase noise levels through the multi-stage down-conversion method, further flexibly suppressing intermodulation spurs.

Description

Technical Field

[0001] The present invention belongs to the technical field of frequency synthesis, and in particular relates to a multi-stage down-conversion frequency synthesis device and method. Background Art

[0002] Frequency synthesis technology, simply put, generates a target frequency through linear operations in the frequency domain using one or more reference signal sources. The circuit that implements frequency synthesis is called a frequency synthesizer, and frequency synthesizers are a crucial component of modern electronic systems. Frequency synthesizers typically employ the following technologies: 1. Direct digital signal processing (DDS); 2. Phase-locked loop (PLL); 3. DDS+PLL. DDS typically exhibits poor spurious performance in frequency synthesized signals and is generally not used directly. The basic theory of phase-locked loops (PLLs) was proposed in the 1930s and has since matured and been applied to electronic systems.

[0003] Existing technical solutions for wideband YTO frequency synthesis are also based on PLL technology. For 4-10 GHz wideband YTO frequency synthesis, the existing technical solution is as follows: a VCO phase-locked loop is introduced to perform down-mixing on the YTO. A first-stage down-mixing process generates a phase-locked frequency. A VCO (1 GHz to 2.5 GHz) is selected and subjected to two-stage frequency doubling. The 2 GHz to 5 GHz frequency obtained after the first frequency doubling is bandpass filtered through a switch-based frequency division process. The 4 GHz to 10 GHz frequency obtained after the second frequency doubling is again bandpass filtered through a switch-based frequency division process. The YTO loop's phase-locked reference is obtained using a fractional divider. The VCO loop's phase-locked reference is derived from an external high-purity reference signal obtained by integer frequency division. The VCO's two-stage frequency doubling output is mixed with an external high-purity 4.8 GHz reference or a multiplied 9.6 GHz signal. This first-stage mixing output is then sampled at 100 MHz, a harmonic mixing method, to obtain the VCO loop's phase-locked input signal. This technical method is relatively complex, and the corresponding circuit structure is also complex, making debugging difficult. Since the VCO loop adopts a harmonic mixing method, the phase noise of the VCO loop cannot be optimized.

[0004] There are two main frequency synthesis methods for locking a wideband YIG tuned oscillator (YTO). One involves dividing the YTO to obtain a phase-locked frequency, integrating it with a reference frequency to lock the YTO. The other involves mixing a wideband VCO with the YTO to obtain a phase-locked frequency, which is then integrated with the reference frequency to lock the YTO. The first method relies heavily on the wideband YTO for phase noise, which generally results in poor phase noise performance and fails to achieve low phase noise levels. The second method generally struggles to find a suitable wideband VCO for the wideband YTO. Existing methods involve multiple frequency multiplication of a suitable wideband VCO, which is then mixed with the wideband YTO to obtain the phase-locked frequency. However, this method requires multiple filtering steps, requiring a large space for filtering, shielding, and other processing. Furthermore, the circuit is complex and debugging is challenging.

[0005] Existing wideband YTO frequency synthesis technology generally adopts a one-stage down-conversion scheme, which obtains the phase-locked frequency by mixing with multiple frequency multiplication of the VCO phase-locked loop. The VCO multiple frequency multiplication path requires a lot of filtering and shielding processing on the path, which occupies a large amount of printed circuit board space, makes the circuit complex, is difficult to debug, and is costly. Summary of the Invention

[0006] In view of the above technical problems existing in the prior art, the present invention proposes a multi-stage down-conversion frequency synthesis device and method, which has a reasonable design, overcomes the shortcomings of the prior art, and has good effects.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A multi-stage down-conversion frequency synthesis device includes a YTO ring;

[0009] The YTO loop includes a 4.8 GHz reference signal, a first power divider, a fractional frequency divider, a binary frequency divider, a first mixer, a first single-pole double-throw switch, a first phase detector, a first integrator circuit, a voltage-to-current conversion circuit, a VCO loop, a YTO drive circuit, a YTO, a second mixer, and a second single-pole double-throw switch;

[0010] A 4.8 GHz reference signal, one end of the first power divider, a fractional frequency divider, a first phase detector, a first integrator circuit, a voltage-to-current conversion circuit, a YTO, a second mixer, and a second single-pole double-throw switch are sequentially connected through lines; the other end of the first power divider, a two-frequency divider, a first mixer, a first single-pole double-throw switch, and a first phase detector are sequentially connected through lines; a YTO drive circuit is connected to the YTO through a line; a VCO loop is connected to the second mixer through a line; and the second single-pole double-throw switch is respectively connected to the first single-pole double-throw switch and the first mixer through lines;

[0011] A 4.8 GHz reference signal, having a frequency of 4.8 GHz, comes from outside the module and is configured to be output to the first power divider;

[0012] A first power divider is configured to achieve balanced distribution of 4.8 GHz signal power, with one path serving as an input to the fractional frequency divider and the other path serving as an input to the binary frequency divider;

[0013] The fractional frequency divider is configured to generate the reference signal f for the phase detector of the YTO loop with a frequency of 25MHz to 75MHz. PDREF ;

[0014] A divider-by-two frequency divider is configured to generate a fixed local oscillator at 2.4 GHz for secondary down-mixing;

[0015] The first mixer is configured as the second stage mixer for the YTO loop, and the output is the phase detection frequency f of the YTO loop. PD ;

[0016] The first single-pole double-throw switch is configured to select a path according to the frequency band of the YTO ring; if f YTO If the frequency is less than or equal to 7.6GHz, the second SPDT switch path is selected; otherwise, the first mixer path is selected.

[0017] A first phase detector is configured to perform frequency and phase detection on a reference signal and an input signal, and output the result to an integration circuit;

[0018] A first integrating circuit is configured to integrate the output signal of the first phase detector to obtain an error voltage, and has a low-pass filtering function to filter out high-frequency and noise components in the error signal;

[0019] A voltage-to-current conversion circuit is configured to convert the error voltage signal into a current signal to drive the YTO;

[0020] The VCO loop is configured to output a fixed down-converted local oscillator of 4 to 8 GHz;

[0021] The YTO driving circuit is configured to drive the YTO to work;

[0022] YTO is a YIG (Yttrium Iron Garnet) tuned oscillator;

[0023] The second mixer is configured to mix the signal output by the YTO with the signal output by the VCO loop to obtain a first-level mixing output |f YTO -f VCO ∣;

[0024] The second single-pole double-throw switch is configured to select a path according to the frequency band of the YTO ring; if fYTO If the frequency is less than or equal to 7.6 GHz, the first SPDT switch path is selected; otherwise, the first mixer path is selected.

[0025] Preferably, the VCO loop includes a 100 MHz reference signal, a 4.8 GHz reference signal, a second power divider, a third mixer, a second phase detector, a second integrator circuit, a filter, a frequency doubler, a VCO drive circuit, a VCO, a fourth mixer, and a wideband prescaler;

[0026] A 100 MHz reference signal is connected to the second phase detector via a line; a 4.8 GHz reference signal, one end of the second power divider, and a third mixer are sequentially connected via a line; the third mixer, the second phase detector, the second integrator circuit, the VCO, the fourth mixer, and the filter form a loop and are connected via a line; a VCO drive circuit is connected to the VCO via a line; the other end of the second power divider, the frequency doubler, the wideband prescaler, and the fourth mixer are connected via a line;

[0027] A 100 MHz reference signal, with a frequency of 100 MHz, comes from outside the module and is configured to be output to the second phase detector;

[0028] A 4.8 GHz reference signal, having a frequency of 4.8 GHz, comes from outside the module and is configured to be output to the second power divider;

[0029] A second power divider is configured to achieve balanced distribution of 4.8 GHz signal power, with one channel serving as an input to the third mixer and the other channel serving as an input to the frequency doubler;

[0030] a third mixer configured to perform secondary mixing of the VCO loop, obtain a phase detection frequency of the VCO loop, and output the frequency to the second phase detector;

[0031] A second phase detector is configured to perform frequency and phase detection on the reference signal and the input signal, and output the result to the second integration circuit;

[0032] a second integrating circuit configured to integrate the output of the second phase detector to obtain an error voltage, and having a low-pass filtering function to filter out high-frequency and noise components in the error signal;

[0033] The filter is configured to perform low-pass filtering on the first-stage mixer output of the VCO loop to filter out noise components;

[0034] The frequency doubler is configured to double the frequency of the 4.8 GHz signal to obtain a frequency of 9.6 GHz, and output the frequency to the wide-band prescaler.

[0035] A VCO driving circuit is configured to drive the VCO to operate;

[0036] VCO, voltage-controlled oscillator;

[0037] A fourth mixer performs a first-stage mixing operation on the signal output by the VCO and the signal output by the wide-band prescaler to obtain a frequency of 4.7 GHz or 4.9 GHz;

[0038] A wideband prescaler is configured to output a fixed down-converted local oscillator for the VCO loop.

[0039] In addition, the present invention also provides a multi-stage down-conversion frequency synthesis method, which uses the multi-stage down-conversion frequency synthesis device as described above and specifically includes the following steps:

[0040] Step 1: Set up an external high-purity frequency source to provide frequencies of 4.8 GHz and 100 MHz;

[0041] Step 2: If f YTO ≤7.6GHz, the frequency after the YTO and VCO ring are mixed by the second mixer is obtained through the second single-pole double-throw switch and the first single-pole double-throw switch to obtain the phase detection frequency, and output to the first phase detector; if f YTO >7.6GHz, the frequency after the YTO and VCO loop are mixed by the second mixer passes through the second single-pole double-throw switch, and the frequency obtained by mixing with the 4.8GHz reference signal through the first power divider and the output 2.4GHz of the two-way frequency divider is obtained by the first single-pole double-throw switch to obtain the phase detection frequency, which is output to the first phase detector;

[0042] Step 3: The YTO loop phase reference frequency is generated by the 4.8 GHz reference signal after passing through the first power divider and then through the fractional frequency divider;

[0043] Step 4: The YTO ring is locked by the YTO driving circuit and the first phase detector output, which is then outputted through the first integration circuit and then to the voltage-current conversion circuit output;

[0044] Step 5: Select the VCO loop fixed tuning local oscillator point according to the YTO frequency;

[0045] Step 6: The 4.8 GHz reference signal is passed through the second power divider, the frequency doubler, and the wideband prescaler to generate the first-stage mixing output frequency of the VCO loop;

[0046] Step 7: The VCO and the first-stage mixer output frequency are mixed through the fourth mixer. The output passes through a filter and the 4.8 GHz reference signal. The output of the second power divider is mixed through the third mixer to obtain a 100 MHz phase-locked frequency. The frequency is then integrated with the reference 100 MHz phase-locked frequency.

[0047] Step 8: The VCO driving circuit and the second phase-comparison integrator jointly control the locking of the VCO loop through the output of the second integration circuit.

[0048] Preferably, the frequency range of the YTO is 4 to 10 GHz, and the frequency range of the VCO is 4 to 8 GHz.

[0049] Preferably, the frequency band of the YTO output frequency is: f YTO ≤7.6GHz or f YTO >7.6GHz.

[0050] The beneficial technical effects brought about by the present invention are:

[0051] The present invention simplifies the circuit and reduces the difficulty of debugging through a multi-stage down-conversion method, making debugging easier. The VCO phase-locked loop also generates a fixed tuned local oscillator frequency through a multi-stage down-conversion method. The appropriate VCO fixed tuned local oscillator point can be flexibly selected according to different YTO frequency bands, effectively avoiding various intermodulation spurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is the principle diagram of the YTO ring of the present invention;

[0053] Figure 2 This is the principle diagram of the VCO ring of the present invention;

[0054] Among them, 1-4.8GHz reference signal; 2-first power divider; 3-fractional divider; 4-divider; 5-first mixer; 6-first single-pole double-throw switch; 7-first phase detector; 8-first integration circuit; 9-voltage-to-current conversion circuit; 10-VCO loop; 11-YTO drive circuit; 12-YTO; 13-second mixer; 14-second single-pole double-throw switch; 15-100MHz reference signal; 16-second power divider; 17-third mixer; 18-second phase detector; 19-second integration circuit; 20-filter; 21-doubler; 22-VCO drive circuit; 23-VCO; ​​24-fourth mixer; 25-wideband predivider. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0056] The present invention mainly targets wide-band YTO and proposes a low-phase-noise frequency synthesis method based on multi-stage down-conversion. By mixing the YTO and VCO, the proximal phase noise curve of the YTO loop is made close to the phase noise curve of the VCO loop, achieving a low phase noise level. Both the YTO loop and the VCO loop achieve a low phase noise level through the multi-stage down-conversion method, and can flexibly suppress intermodulation spurs.

[0057] Example 1:

[0058] A multi-stage down-conversion frequency synthesis device, including a YTO ring; the principle is as follows Figure 1 As shown,

[0059] The YTO loop includes a 4.8 GHz reference signal 1, a first power divider 2, a fractional frequency divider 3, a binary frequency divider 4, a first mixer 5, a first single-pole double-throw switch 6, a first phase detector 7, a first integration circuit 8, a voltage-current conversion circuit 9, a VCO loop 10, a YTO drive circuit 11, a YTO 12, a second mixer 13, and a second single-pole double-throw switch 14;

[0060] A 4.8 GHz reference signal 1, one end of the first power divider 2, a fractional frequency divider 3, a first phase detector 7, a first integrator circuit 8, a voltage-to-current conversion circuit 9, a YTO 12, a second mixer 13, and a second single-pole double-throw switch 14 are connected in sequence through lines; the other end of the first power divider 2, the two-frequency divider 4, the first mixer 5, the first single-pole double-throw switch 6, and the first phase detector 7 are connected in sequence through lines; the YTO drive circuit 11 is connected to the YTO 12 through a line; the VCO loop 10 is connected to the second mixer 13 through a line; and the second single-pole double-throw switch 14 is respectively connected to the first single-pole double-throw switch 6 and the first mixer 5 through lines;

[0061] A 4.8 GHz reference signal 1 having a frequency of 4.8 GHz, coming from outside the module, and configured to be output to the first power divider 2;

[0062] The first power divider 2 is configured to achieve balanced distribution of 4.8 GHz signal power, with one path serving as the input of the fractional frequency divider 3 and the other path serving as the input of the binary frequency divider 4;

[0063] The fractional frequency divider 3 is configured to generate a reference signal f for the phase detector of the YTO loop of 25MHz to 75MHz. PDREF ;

[0064] A two-way frequency divider 4 is configured to generate a fixed local oscillator at 2.4 GHz for secondary down-mixing;

[0065] The first mixer 5 is configured as the second stage mixer for the YTO loop, and the output is the phase detection frequency f of the YTO loop. PD ;

[0066] The first single-pole double-throw switch 6 is configured to select a path according to the frequency band of the YTO ring; if f YTO If the frequency is less than or equal to 7.6GHz, the second SPDT switch path is selected; otherwise, the first mixer path is selected.

[0067] A first phase detector 7 is configured to perform frequency and phase detection on a reference signal and an input signal, and output the result to an integration circuit;

[0068] The first integrator circuit 8 is configured to integrate the output signal of the first phase detector 7 to obtain an error voltage, and has a low-pass filtering function to filter out high-frequency and noise components in the error signal;

[0069] The voltage-to-current conversion circuit 9 is configured to convert the error voltage signal into a current signal to drive the YTO;

[0070] The VCO loop 10 is configured to output a fixed down-converted local oscillator of 4 to 8 GHz;

[0071] The YTO driving circuit 11 is configured to drive the YTO to operate;

[0072] YTO12, a YIG (Yttrium Iron Garnet) tuned oscillator;

[0073] The second mixer 13 is configured to mix the signal output by the YTO 12 with the signal output by the VCO loop 10 to obtain a first-level mixing output |f YTO -f VCO ∣;

[0074] The second single-pole double-throw switch 14 is configured to select a path according to the frequency band of the YTO ring; if f YTO If the frequency is less than or equal to 7.6 GHz, the first SPDT switch path is selected; otherwise, the first mixer path is selected.

[0075] Example 2:

[0076] The VCO loop principle in the YTO loop is as follows Figure 2 As shown, the VCO loop includes a 100 MHz reference signal 15, a 4.8 GHz reference signal 1, a second power divider 16, a third mixer 17, a second phase detector 18, a second integrator circuit 19, a filter 20, a frequency doubler 21, a VCO driving circuit 22, a VCO 23, a fourth mixer 24 and a wideband prescaler 25;

[0077] The 100 MHz reference signal 15 is connected to the second phase detector 18 via a line; the 4.8 GHz reference signal 1, one end of the second power divider 16, and the third mixer 17 are connected in sequence via a line; the third mixer 17, the second phase detector 18, the second integrator circuit 19, the VCO 23, the fourth mixer 24, and the filter 20 form a loop and are connected via a line; the VCO drive circuit 22 is connected to the VCO 23 via a line; the other end of the second power divider 16, the frequency doubler 21, the wideband prescaler 25, and the fourth mixer 24 are connected via a line;

[0078] A 100 MHz reference signal 15 , having a frequency of 100 MHz, comes from outside the module and is configured to be output to the second phase detector;

[0079] 4.8 GHz reference signal 1, with a frequency of 4.8 GHz, comes from outside the module and is configured to be output to the second power divider;

[0080] The second power divider 16 is configured to achieve balanced distribution of 4.8 GHz signal power, with one path being the input of the third mixer 17 and the other path being the input of the frequency doubler 21;

[0081] The third mixer 17 is configured to perform secondary mixing of the VCO loop to obtain the phase detection frequency of the VCO loop and output it to the second phase detector 18;

[0082] The second phase detector 18 is configured to detect the frequency and phase of the reference signal and the input signal, and output the detected frequency and phase to the second integration circuit 19;

[0083] The second integrator circuit 19 is configured to integrate the output of the second phase detector 18 to obtain an error voltage, and has a low-pass filtering function to filter out high-frequency and noise components in the error signal;

[0084] The filter 20 is configured to perform low-pass filtering on the first-stage mixer output of the VCO loop to filter out noise components;

[0085] The frequency doubler 21 is configured to double the frequency of the 4.8 GHz signal to 9.6 GHz, and output the signal to the wide-band prescaler.

[0086] The VCO driving circuit 22 is configured to drive the VCO to operate;

[0087] VCO 23, voltage controlled oscillator;

[0088] The fourth mixer 24 performs a first-stage mixing on the signal output by the VCO 23 and the signal output by the wide-band prescaler 25 to obtain 4.7 GHz or 4.9 GHz;

[0089] The wideband prescaler 25 is configured to output a fixed down-conversion local oscillator of the VCO loop.

[0090] Example 3:

[0091] Based on the above embodiments, the present invention further provides a multi-stage down-conversion frequency synthesis method, wherein:

[0092] The frequency synthesis equation is:

[0093] f YTO =f VCO±4.8GHz / NF, (YTO output frequency f YTO ≤7.6GHz);

[0094] f YTO =2.4GHz+f VCO ±4.8GHz / NF, (YTO output frequency f YTO >7.6GHz);

[0095] f VCO =4.8GHz±f PRE ±100MHz;

[0096] In the above formula, f YTO is the YTO output signal, which can be any frequency between 4 and 10 GHz; f VCO is the VCO output signal, according to f YTO The frequency can be selected from a limited fixed frequency range of 4 to 8 GHz; NF is the frequency division ratio of the fractional divider; f PRE is the output signal of the wideband prescaler, according to f VCO The frequency may be selected from a limited fixed frequency range of 75 MHz to 3000 MHz.

[0097] The specific steps include:

[0098] Step 1: Set up an external high-purity frequency source to provide frequencies of 4.8 GHz and 100 MHz;

[0099] Step 2: If f YTO ≤7.6GHz, the frequency after the YTO and VCO ring are mixed by the second mixer is obtained through the second single-pole double-throw switch and the first single-pole double-throw switch to obtain the phase detection frequency, and output to the first phase detector; if f YTO >7.6GHz, the frequency after the YTO and VCO loop are mixed by the second mixer passes through the second single-pole double-throw switch, and the frequency obtained by mixing with the 4.8GHz reference signal through the first power divider and the output 2.4GHz of the two-way frequency divider is obtained by the first single-pole double-throw switch to obtain the phase detection frequency, which is output to the first phase detector;

[0100] Step 3: The YTO loop phase reference frequency is generated by the 4.8 GHz reference signal passing through the first power divider and then the fractional frequency divider;

[0101] Step 4: The YTO ring is locked by the YTO driving circuit and the first phase detector output, which is then outputted through the first integration circuit and then to the voltage-current conversion circuit output;

[0102] Step 5: Select the VCO loop fixed tuning local oscillator point according to the YTO frequency;

[0103] Step 6: The 4.8 GHz reference signal is passed through the second power divider, the frequency doubler, and the wideband prescaler to generate the first-stage mixing output frequency of the VCO loop;

[0104] Step 7: The VCO and the first-stage mixer output frequency are mixed through the fourth mixer. The output passes through a filter and the 4.8 GHz reference signal. The output of the second power divider is mixed through the third mixer to obtain a 100 MHz phase-locked frequency. The frequency is then integrated with the reference 100 MHz phase-locked frequency.

[0105] Step 8: The VCO driving circuit and the second phase-comparison integrator jointly control the locking of the VCO loop through the output of the second integration circuit.

[0106] The frequency range of YTO is 4~10GHz, and the frequency range of VCO is 4~8GHz.

[0107] The frequency band of YTO output frequency is: f YTO ≤7.6GHz or f YTO >7.6GHz.

[0108] Assume that a frequency synthesis signal f is required YTO For 4050MHz signal, you can set f VCO is 4100MHz, NF is 96.0, f PRE It is 600MHz.

[0109] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A multi-stage down-conversion frequency synthesis device, characterized in that: Includes YTO rings; The YTO loop includes a 4.8 GHz reference signal, a first power divider, a fractional frequency divider, a binary frequency divider, a first mixer, a first single-pole double-throw switch, a first phase detector, a first integrator circuit, a voltage-to-current conversion circuit, a VCO loop, a YTO drive circuit, a YTO, a second mixer, and a second single-pole double-throw switch; A 4.8 GHz reference signal, one end of the first power divider, a fractional frequency divider, a first phase detector, a first integrator circuit, a voltage-to-current conversion circuit, a YTO, a second mixer, and a second single-pole double-throw switch are sequentially connected through lines; the other end of the first power divider, a two-frequency divider, a first mixer, a first single-pole double-throw switch, and a first phase detector are sequentially connected through lines; a YTO drive circuit is connected to the YTO through a line; a VCO loop is connected to the second mixer through a line; and the second single-pole double-throw switch is respectively connected to the first single-pole double-throw switch and the first mixer through lines; A 4.8 GHz reference signal, having a frequency of 4.8 GHz, comes from outside the module and is configured to be output to the first power divider; A first power divider is configured to achieve balanced distribution of 4.8 GHz signal power, with one path serving as an input to the fractional frequency divider and the other path serving as an input to the binary frequency divider; The fractional frequency divider is configured to generate the reference signal f for the phase detector of the YTO loop with a frequency of 25MHz to 75MHz. PDREF ; A divider-by-two frequency divider is configured to generate a 2.4 GHz frequency as a fixed local oscillator for the second stage down-mixing; The first mixer is configured as the second stage mixer for the YTO loop, and the output is the phase detection frequency f of the YTO loop. PD ; The first single-pole double-throw switch is configured to select a path according to the frequency band of the YTO ring; if f YTO If the frequency is less than or equal to 7.6GHz, the second SPDT switch path is selected; otherwise, the first mixer path is selected. A first phase detector is configured to perform frequency and phase detection on a reference signal and an input signal, and output the result to an integration circuit; A first integrating circuit is configured to integrate the output signal of the first phase detector to obtain an error voltage, and has a low-pass filtering function to filter out high-frequency and noise components in the error signal; A voltage-to-current conversion circuit is configured to convert the error voltage signal into a current signal to drive the YTO; The VCO loop is configured to output a fixed down-converted local oscillator of 4 to 8 GHz; The YTO driving circuit is configured to drive the YTO to work; YTO, YIG tuned oscillator; The second mixer is configured to mix the signal output by the YTO with the signal output by the VCO loop to obtain a first-level mixing output |f YTO -f VCO ∣; The second single-pole double-throw switch is configured to select a path according to the frequency band of the YTO ring; if f YTO If the frequency is less than or equal to 7.6 GHz, the first SPDT switch path is selected; otherwise, the first mixer path is selected.

2. The multi-stage down-conversion frequency synthesis device according to claim 1, wherein: The VCO loop includes a 100 MHz reference signal, a 4.8 GHz reference signal, a second power divider, a third mixer, a second phase detector, a second integrator circuit, a filter, a frequency doubler, a VCO drive circuit, a VCO, a fourth mixer, and a wideband prescaler; A 100 MHz reference signal is connected to the second phase detector via a line; a 4.8 GHz reference signal, one end of the second power divider, and a third mixer are sequentially connected via a line; the third mixer, the second phase detector, the second integrator circuit, the VCO, the fourth mixer, and the filter form a loop and are connected via a line; a VCO drive circuit is connected to the VCO via a line; the other end of the second power divider, the frequency doubler, the wideband prescaler, and the fourth mixer are connected via a line; A 100 MHz reference signal, with a frequency of 100 MHz, comes from outside the module and is configured to be output to the second phase detector; A 4.8 GHz reference signal, having a frequency of 4.8 GHz, comes from outside the module and is configured to be output to the second power divider; A second power divider is configured to achieve balanced distribution of 4.8 GHz signal power, with one channel serving as an input to the third mixer and the other channel serving as an input to the frequency doubler; a third mixer configured to perform secondary mixing of the VCO loop, obtain a phase detection frequency of the VCO loop, and output the frequency to the second phase detector; A second phase detector is configured to perform frequency and phase detection on the reference signal and the input signal, and output the result to the second integration circuit; a second integrating circuit configured to integrate the output of the second phase detector to obtain an error voltage, and having a low-pass filtering function to filter out high-frequency and noise components in the error signal; The filter is configured to perform low-pass filtering on the first-stage mixer output of the VCO loop to filter out noise components; A frequency doubler is configured to double the frequency of a 4.8 GHz signal to obtain a frequency of 9.6 GHz, and output the frequency to a wide-band prescaler; A VCO driving circuit is configured to drive the VCO to operate; VCO, voltage-controlled oscillator; A fourth mixer performs a first-stage mixing operation on the signal output by the VCO and the signal output by the wide-band prescaler to obtain a frequency of 4.7 GHz or 4.9 GHz; A wideband prescaler is configured to output a fixed down-converted local oscillator for the VCO loop.

3. A multi-stage down-conversion frequency synthesis method, characterized in that: The multi-stage down-conversion frequency synthesis device according to claim 2 specifically comprises the following steps: Step 1: Set up an external high-purity frequency source to provide frequencies of 4.8 GHz and 100 MHz; Step 2: Based on the frequency band of the YTO output frequency, determine whether it can be mixed with the 2.4 GHz frequency generated by the divider to obtain the phase detection frequency; the details are as follows: If f YTO ≤7.6GHz, the signal output by the YTO and the signal output by the VCO loop are mixed by the second mixer, and the mixed frequency is obtained by the second single-pole double-throw switch and the first single-pole double-throw switch to obtain the phase detection frequency, which is output to the first phase detector; If f YTO >7.6GHz, the signal output by the YTO and the signal output by the VCO loop are mixed by the second mixer, and the mixed frequency is mixed by the second single-pole double-throw switch with the output frequency 2.4GHz of the 4.8GHz reference signal after passing through the first power divider and the divider, and then mixed by the first mixer. The mixed frequency is obtained by the first single-pole double-throw switch to obtain the phase detection frequency and output to the first phase detector; Step 3: Get the YTO loop phase reference frequency; The 4.8GHz reference signal passes through the first power divider and the fractional frequency divider to obtain the phase reference frequency of the YTO loop; Step 4: Select the fixed tuning point of the VCO loop according to the frequency of the YTO; Step 5: The 4.8 GHz reference signal passes through the second power divider, doubler, and wideband prescaler to obtain the first-stage mixing output frequency of the VCO loop; Step 6: The VCO and the output frequency of the first mixer are mixed by the fourth mixer. The mixed frequency passes through a filter and the signal output by the second power divider with the 4.8 GHz reference signal and enters the third mixer for mixing. The mixing obtains a 100 MHz phase-locked frequency, which enters the second phase detector with the 100 MHz reference signal. The second phase detector performs frequency and phase detection on the 100 MHz reference signal and the 100 MHz phase-locked frequency, and outputs the result to the second integrator circuit. Step 7: The VCO driving circuit and the second phase-comparison circuit jointly control the locking of the VCO loop through the output of the second integration circuit.

4. The multi-stage down-conversion frequency synthesis method according to claim 3, wherein: The frequency range of YTO is 4~10GHz, and the frequency range of VCO is 4~8GHz.

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