Ka-band frequency source based on phase-locked loop structure
By using a Ka-band frequency source based on a phase-locked loop (PLL) structure, combined with a PLL module and a frequency multiplication module, low phase noise, wide bandwidth, and high stability of the frequency source are achieved. This solves the problem that existing single-feature frequency sources cannot meet user needs, and improves the communication quality and stability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU XUSITE TECH CO LTD
- Filing Date
- 2025-04-10
- Publication Date
- 2026-05-05
AI Technical Summary
Existing frequency sources typically only possess one of the characteristics of high stability, low phase noise, or wide bandwidth, and cannot simultaneously achieve low phase noise, wide bandwidth, and high stability, resulting in a poor user experience.
A Ka-band frequency source based on a phase-locked loop (PLL) structure is adopted, including a main controller, a crystal oscillator module, a PLL module, and a frequency multiplier module. The low-pass and high-pass filters of the PLL module are used for harmonic suppression, and frequency processing is performed through a fixed-frequency attenuator and a power amplifier. The frequency band is widened by combining a frequency multiplier chip, thereby achieving low phase noise, wide bandwidth, and high stability of the frequency signal.
It achieves low phase noise, wide bandwidth and high stability of frequency source, and the output frequency has low phase noise, wide bandwidth and high stability, making it suitable for radar and communication systems.
Smart Images
Figure CN224205078U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of frequency source technology, specifically to a Ka-band frequency source based on a phase-locked loop structure. Background Technology
[0002] Traditionally, the 30GHz-300GHz range has been defined as the millimeter wave band, but a more popular view now considers 24GHz-300GHz as the millimeter wave band. Within the millimeter wave band, there are four atmospheric "windows" with relatively low transmission attenuation, with center frequencies around 35, 94, 140, and 220GHz. Long-distance terrestrial relay communication and satellite-to-terrestrial communication utilize this low propagation loss characteristic within these windows. Millimeter wave frequency sources are the core components of radar and communication systems, and their performance directly determines the system's communication quality. The phase noise of the frequency source determines the quality and performance of the system's signal phase noise, while its stability plays a decisive role in the overall stability of the microwave system. Its applicable bandwidth determines the application scenarios and scope of the frequency source. Currently, existing frequency sources often only possess one of the characteristics such as high stability, low phase noise, or wide bandwidth, resulting in a poor user experience. Utility Model Content
[0003] This invention provides a Ka-band frequency source based on a phase-locked loop structure, which can achieve low phase noise, wide bandwidth and high stability.
[0004] This utility model is achieved through the following technical solution:
[0005] This utility model provides a Ka-band frequency source based on a phase-locked loop (PLL) structure, comprising: a main controller, a crystal oscillator module, a PLL module, and a frequency multiplication processing module. The PLL module is connected to the main controller, the crystal oscillator module, and the frequency multiplication processing module. The PLL module includes a power supply module, a PLL main chip, a loop filter module, and a lock-in status indicator module. The PLL main chip is connected to the power supply module, the loop filter module, the lock-in status indicator module, and the main controller. The frequency multiplication processing module includes a low-pass filter, a high-pass filter, a fixed-frequency attenuator, a power amplifier, a frequency multiplier chip, and a band-pass filter connected in sequence. The input terminal of the low-pass filter is connected to the output terminal of a voltage-controlled oscillator (VCO).
[0006] Furthermore, the phase-locked loop main chip includes a frequency and phase detector, a voltage-controlled oscillator (VCO), and an N-divider. The frequency and phase detector, the loop filter module, and the VCO are connected in sequence, and the N-divider is connected to both the frequency and phase detector and the VCO.
[0007] Furthermore, the phase-locked loop main chip also includes a data register, which is connected to the main controller.
[0008] Furthermore, the power supply module adopts an LT1962 power supply circuit, which includes an LT1962 chip. The eighth and fifth pins of the LT1962 chip are connected to one end of the first capacitor, one end of the second capacitor, and one end of the third capacitor, respectively, and then connected to the input power supply. The other end of the first capacitor is connected to the other ends of the second and third capacitors and then grounded. The third pin of the LT1962 chip is connected to the first pin through a fourth capacitor and then connected to one end of the first resistor, one end of the fifth capacitor, one end of the sixth capacitor, one end of the seventh capacitor, and one end of the third resistor, respectively. The second pin of the LT1962 chip is connected to the other end of the first resistor and one end of the second resistor, respectively. The fourth pin of the LT1962 chip is connected to the other end of the second resistor and then grounded. The other end of the fifth capacitor is connected to the other ends of the sixth and seventh capacitors and then grounded. The other end of the third resistor is the power output terminal.
[0009] Furthermore, the main controller uses the CY7C68013 chip.
[0010] Furthermore, the main chip of the phase-locked loop is the ADF5355 chip.
[0011] Furthermore, the locking indicator module uses a digital locking status indicator, and the MUXOUT pin of the ADF5355 chip is connected to a light-emitting diode.
[0012] Furthermore, the crystal oscillator module employs a 100MHz temperature-controlled crystal oscillator.
[0013] Furthermore, the frequency multiplication processing module uses the HMC578 chip.
[0014] Furthermore, the loop filter module employs a passive third-order filter.
[0015] Compared with the prior art, this utility model has the following advantages and beneficial effects:
[0016] This invention provides a Ka-band frequency source based on a phase-locked loop (PLL) structure. The PLL module's output frequency is set to 0.054 GHz - 14 GHz. The frequency output from the PLL module is input to a frequency multiplier module for processing. The low-pass and high-pass filters in the frequency multiplier module further suppress harmonics in the PLL output frequency. The processed frequency is then attenuated and amplified by a fixed-frequency attenuator and a power amplifier, reaching the input power range of the frequency multiplier chip. The frequency multiplier chip widens the bandwidth of the amplified frequency signal, resulting in an output frequency with advantages such as low phase noise, wide bandwidth, and high stability. Attached Figure Description
[0017] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention and form part of this application, do not constitute a limitation thereof. In the drawings:
[0018] Figure 1 A structural block diagram of a Ka-band frequency source based on a phase-locked loop structure is provided for an embodiment of this utility model;
[0019] Figure 2 This is a circuit diagram of the power supply module in an embodiment of the present invention;
[0020] Figure 3 This is a circuit diagram of the minimum system built based on the CY7C68013 chip in this embodiment of the present invention. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this utility model are only used to explain this utility model and are not intended to limit this utility model.
[0022] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.
[0023] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the description of the invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0024] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0025] like Figure 1 As shown in the first embodiment of this utility model, a Ka-band frequency source based on a phase-locked loop (PLL) structure is provided, comprising: a main controller, a crystal oscillator module, a PLL module, and a frequency multiplier module. The PLL module is connected to the main controller, the crystal oscillator module, and the frequency multiplier module. The PLL module includes a power supply module, a PLL main chip, a loop filter module, and a lock-in status indicator module. The PLL main chip is connected to the power supply module, the loop filter module, the lock-in status indicator module, and the main controller. The frequency multiplier module includes a low-pass filter, a high-pass filter, a fixed-frequency attenuator, a power amplifier, a frequency multiplier chip, and a band-pass filter connected in sequence. The input terminal of the low-pass filter is connected to the output terminal of the voltage-controlled oscillator (VCO). The main controller sends control commands to the PLL module, enabling the PLL module to stably lock and correctly output the target frequency. The low-pass and high-pass filters in the frequency multiplier module further suppress harmonics at the frequency output by the PLL module. The processed frequency is attenuated and amplified by the fixed-frequency attenuator and the power amplifier, amplified to the input power range of the frequency multiplier chip. The frequency multiplier chip widens the bandwidth of the amplified frequency signal, so that the output frequency meets the goals of low phase noise, wide bandwidth, and high stability.
[0026] In this embodiment, the phase-locked loop (PLL) main chip includes a phase-frequency detector, a voltage-controlled oscillator (VCO), and an N-divider. The phase-frequency detector, loop filter module, and VCO are connected sequentially, and the N-divider is connected to both the phase-frequency detector and the VCO. The PLL main chip also includes a data register connected to the main controller. The type of the PLL module is determined by the number of poles in the open-loop gain located at the origin; that is, the type of PLL is equal to the number of integrators in the loop. The order of the PLL is determined by the zeros of the characteristic equation or the denominator of the closed-loop transfer function. The order of the loop is determined by the loop filter module and the VCO. The VCO contains one integrator, one pole of the transfer function is determined by the VCO, and the other poles are located in the loop filter. The loop filter is a key factor in determining the order of the PLL. The loop filter is connected to the output of the phase detector, and its main function is to filter out noise and suppress high-frequency components in the error voltage to ensure loop stability. A voltage-controlled oscillator (VCO) generates a target frequency from an input voltage, acting as a voltage-to-frequency converter. The frequency range a VCO can generate is its most critical parameter, but a wider range often comes at the cost of reduced phase noise. The operating principle of a VCO is to obtain the target frequency through voltage tuning. VCOs employ feedback oscillators. A frequency divider divides the frequency at a specific point by a division factor to reduce the frequency. The frequency divider in the phase-locked loop (PLL) main chip is a feedback divider, located between the VCO's feedback signal and the phase-frequency detector, ensuring that the VCO's output frequency is consistent with or close to the reference frequency for frequency comparison by the phase-frequency detector. The loop filter module uses a passive third-order filter.
[0027] The phase-locked loop (PLL) main chip uses the ADF5355 chip. The ADF5355 chip integrates the basic PLL structure, including a voltage-controlled oscillator (VCO), a frequency and phase detector with a charge pump, and a frequency divider. It also integrates registers, latches, and multiplexers. This chip can perform fractional-N and integer-N frequency division. The frequency and phase detector has a maximum phase detection frequency of 125MHz, and the reference frequency can be input up to 600MHz, offering flexible base frequency settings. The VCO gain is 15MHz / V. Furthermore, the chip has 13 internal data registers, each consisting of 32 bits of binary code. These data registers work together to ensure the normal operation of the PLL.
[0028] like Figure 2As shown, the power supply module uses an LT1962 power supply circuit, which provides a stable 3.3V power supply to other modules. The LT1962 power supply circuit includes an LT1962 chip. Pins 8 and 5 of the LT1962 chip are connected to one end of the first capacitor, one end of the second capacitor, and one end of the third capacitor, respectively, and then connected to the input power supply. The other end of the first capacitor is connected to the other ends of the second and third capacitors and then grounded. A transient voltage suppressor diode (TVS) is connected to the input power supply. When the input voltage rises abnormally, the TVS diode quickly conducts, clamping the voltage within a safe range and protecting the subsequent circuitry from surge impacts. The first, second, and third capacitors form a filter network. The first and third capacitors perform high-frequency filtering to suppress high-frequency noise, while the second capacitor is used for low-frequency filtering to stabilize the input power supply. The third pin of the LT1962 chip is connected to the first pin via a fourth capacitor, and then connected to one end of the first resistor, one end of the fifth capacitor, one end of the sixth capacitor, one end of the seventh capacitor, and one end of the third resistor. The second pin of the LT1962 chip is connected to the other end of the first resistor and one end of the second resistor. The fourth pin of the LT1962 chip is connected to the other end of the second resistor and then grounded. The other end of the fifth capacitor is connected to the other ends of the sixth and seventh capacitors and then grounded. The other end of the third resistor is the 3.3V power output terminal. The fifth, sixth, and seventh capacitors further filter out high-frequency and low-frequency noise in the output voltage, ensuring a clean 3.3V power supply. The first and second resistors form a voltage divider network. The third resistor is a current sampling resistor used to output a stable 3.3V power supply to power other modules. The power module achieves a stable 5.5V to 3.3V conversion through TVS protection, multi-stage filtering, and linear voltage regulation, and has anti-interference and overvoltage protection capabilities to ensure the reliability of the power supply.
[0029] In this embodiment, the master controller uses the CY7C68013 chip. The CY7C68013 chip, acting as the master controller, sends timing commands to the phase-locked loop (PLL) master chip ADF5355. The minimum system built based on the CY7C68013 chip is as follows: Figure 3 As shown, the clock system uses a 24MHz crystal oscillator; the communication interface with the computer uses a mini-USB (Universal Serial Bus) interface, and the power supply also uses this interface; the communication interface with the ADF5355 phase-locked loop main chip is a pin connector, which is completed by pins 40, 41, and 42, respectively, corresponding to the phase-locked loop enable LE, clock CLK, and data DATA.
[0030] To maintain a low phase noise level for the frequency source, a 100MHz cryogenic crystal oscillator is used in the crystal module, serving as the reference frequency for the frequency and phase detector. This crystal oscillator exhibits a phase noise level better than -168dBc / Hz@10kHz and clutter suppression greater than 75dBc. Internal compensation for the crystal's frequency-temperature characteristics ensures good frequency stability over a wide temperature range.
[0031] The frequency multiplier module uses the HMC578 chip, an active broadband frequency multiplier based on GaAs pHEMT technology. It can double frequencies from 11.5GHz to 16.5GHz, outputting signals from 23GHz to 33GHz. Powered by 5V DC, it features low input power consumption and high power output. Furthermore, it exhibits excellent system noise performance, with a phase noise of -132dBc / Hz@100kHz, meeting the low phase noise requirements of the frequency source.
[0032] The lock indication module uses a digital lock status indicator, with the MUXOUT pin of the ADF5355 chip connected to an LED. The MUXOUT pin of the main chip ADF5355 is a multiplexed output pin that can indicate the lock status. In this embodiment, a digital lock status indicator is used; when the loop is locked, the LED connected to the MUXOUT pin is lit to indicate the lock.
[0033] This invention provides a Ka-band frequency source based on a phase-locked loop (PLL) structure. The PLL module has an output frequency of 0.054 GHz to 14 GHz, a frequency step of 1.2 MHz, and a phase noise of -132.84 dBc / Hz@1 MHz at 1.8 GHz and -120.72 dBc / Hz@1 MHz at 12 GHz. The frequency output from the PLL module is input to a frequency multiplier module for processing. The low-pass and high-pass filters in the frequency multiplier module further suppress harmonics. The processed frequency is attenuated and amplified by a fixed-frequency attenuator and a power amplifier, reaching the input power range of the frequency multiplier chip. The frequency multiplier chip widens the bandwidth of the amplified frequency signal, achieving a stable frequency output of 24 GHz to 28 GHz with a frequency stability of 0.6 ppm, a frequency step of 2.4 MHz, and an output power of over 0 dBm. The spurious suppression is better than -50dBc, and the phase noise at 27GHz is -113.90dBc / Hz@1MHz. Therefore, the Ka-band frequency source based on a phase-locked loop structure provided by this invention has the advantages of low phase noise, wide bandwidth, and high stability.
[0034] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above description is only a specific embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.
Claims
1. A Ka-band frequency source based on a phase-locked loop structure, comprising: The system comprises a main controller, a crystal oscillator module, a phase-locked loop (PLL) module, and a frequency multiplier module. The PLL module is connected to the main controller, the crystal oscillator module, and the frequency multiplier module, respectively. The PLL module includes a power supply module, a PLL main chip, a loop filter module, and a lock-in status indicator module. The PLL main chip is connected to the power supply module, the loop filter module, the lock-in status indicator module, and the main controller, respectively. The frequency multiplier module includes a low-pass filter, a high-pass filter, a fixed-frequency attenuator, a power amplifier, a frequency multiplier chip, and a band-pass filter connected in sequence. The input terminal of the low-pass filter is connected to the output terminal of the voltage-controlled oscillator (VCO).
2. The Ka-band frequency source based on a phase-locked loop structure according to claim 1, characterized in that, The phase-locked loop main chip includes a frequency and phase detector, a voltage-controlled oscillator (VCO), and an N-divider. The frequency and phase detector, the loop filter module, and the VCO are connected in sequence, and the N-divider is connected to both the frequency and phase detector and the VCO.
3. The Ka-band frequency source based on a phase-locked loop structure according to claim 2, characterized in that, The phase-locked loop main chip also includes a data register, which is connected to the main controller.
4. The Ka-band frequency source based on a phase-locked loop structure according to claim 1, characterized in that, The power module uses an LT1962 power supply circuit, which includes an LT1962 chip. The eighth and fifth pins of the LT1962 chip are connected to one end of a first capacitor, one end of a second capacitor, and one end of a third capacitor, respectively, and then connected to the input power supply. The other end of the first capacitor is connected to the other ends of the second and third capacitors and then grounded. The third pin of the LT1962 chip is connected to the first pin via a fourth capacitor and then connected to one end of a first resistor, one end of a fifth capacitor, one end of a sixth capacitor, one end of a seventh capacitor, and one end of the third resistor, respectively. The second pin of the LT1962 chip is connected to the other ends of the first and second resistors, respectively. The fourth pin of the LT1962 chip is connected to the other end of the second resistor and then grounded. The other end of the fifth capacitor is connected to the other ends of the sixth and seventh capacitors and then grounded. The other end of the third resistor is the power output terminal.
5. The Ka-band frequency source based on a phase-locked loop structure according to claim 1, characterized in that, The main controller uses the CY7C68013 chip.
6. The Ka-band frequency source based on a phase-locked loop structure according to claim 1, characterized in that, The main chip of the phase-locked loop is the ADF5355 chip.
7. The Ka-band frequency source based on a phase-locked loop structure according to claim 6, characterized in that, The lock status indication module uses digital lock status indication, and the MUXOUT pin of the ADF5355 chip is connected to a light-emitting diode.
8. The Ka-band frequency source based on a phase-locked loop structure according to claim 6, characterized in that, The crystal oscillator module uses a 100MHz temperature-controlled crystal oscillator.
9. The Ka-band frequency source based on a phase-locked loop structure according to any one of claims 1-8, characterized in that, The frequency multiplication processing module uses the HMC578 chip.
10. The Ka-band frequency source based on a phase-locked loop structure according to claim 9, characterized in that, The loop filter module uses a passive third-order filter.