ADS-B IN signal code element recognition and extraction method, medium and device based on FPGA under low signal-to-noise ratio

Abstract

The present invention provides a method, medium and device for identifying and extracting ADS-B IN signal code elements under low signal-to-noise ratio based on FPGA, the method comprising: performing autocorrelation operation on input signal; generating standard pulse with pulse width of N microseconds; performing header detection after cross-correlation operation on the signal after autocorrelation operation and standard pulse; after determining the header, finding the first code element position according to pulse timing, using shift register to store N microseconds before and after the first code element; calculating the amplitude value of N microseconds before the first code element; calculating the amplitude value of N microseconds after the first code element; sampling according to an enable signal with pulse width of 2N microseconds, when the enable signal is valid, comparing the amplitude values ​​of N microseconds before and after the first code element, and outputting code words according to the comparison result; determining the number of sampling times, and completing data locking. The present invention can realize S mode 1090ES code element extraction under low signal-to-noise ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of ADS-B IN signal symbol recognition and extraction, and in particular to an ADS-B IN signal symbol recognition and extraction method, medium and device under low signal-to-noise ratio based on FPGA. Background Art

[0002] With the rapid development of the civil aviation industry, in order to meet the requirements of the next generation aviation management system, the Automatic Dependent Air Traffic Control-Broadcast (ADS-B) technology came into being. This technology is a replacement and extension of air traffic control surveillance radar and is a new generation of surveillance technology promoted by the International Civil Aviation Organization (ICAO). Compared with traditional secondary radar, ADS-B technology has the advantages of low ground station construction cost, wide surveillance range, fast information update rate, and global seamless coverage. Therefore, ADS-B technology has become one of the effective methods for handling global aviation control.

[0003] The airborne equipment informs the ground of its real-time position, status and other information by broadcasting. The ground station calculates the information based on the received message, forms the corresponding track, and monitors the aircraft. The S mode 1090ES broadcast by the airborne equipment adopts pulse position coding modulation, and its specific format is as follows: Figure 1 As shown. Its baseband signal consists of an 8us preamble formed by 4 fixed pulses and a 112us data block consisting of 112 bits of data. The 8us preamble adopts amplitude (AM) modulation, while the 112us data block adopts pulse position modulation (PPM) modulation. Each data in the 112us data block is called a code element, that is, each code element has a width of 1us, and each code element consists of two 0.5us code chips before and after. According to the definition of PPM modulation, if the previous code chip of each code element is 0 and the next code chip is 1, then the code element represents the information of 0; conversely, if the previous code chip of each code element is 1 and the next code chip is 0, then the code element represents the information of 1.

[0004] Due to the different distances between the aircraft and the 1090ES receiver, and the influence of electromagnetic wave attenuation, the signal strength and signal-to-noise ratio received by the 1090ES receiver will vary greatly. Under high signal-to-noise ratio conditions, conventional methods can be used to extract signal symbols, thereby decoding the signal; if under low signal-to-noise ratio conditions, conventional S-mode 1090ES symbol extraction methods are easily affected by noise, resulting in an increase in false alarm rates. Correct extraction of symbol information under low signal-to-noise ratios is crucial to ensuring effective monitoring of the ADS-B system.

[0005] Currently, the widely used S-mode 1090ES decoding technology is the baseline multi-point decision method recommended by ICAO. The specific principle of this method is as follows: Figure 2 shown.

[0006] This method uses the -6dB level below the reference voltage as the threshold level, and the ±3dB level of the reference voltage as the threshold level, and performs weighted counting on the sampling points within and outside the ±3dB window range. Since the middle point is relatively stable, the points in the middle range are not counted. Therefore, when using the weighted algorithm, a larger weight is used for the middle point; and the weights for the sampling points close to the pulse transition section of the code element are slightly lower, because their credibility is lower than that of the sampling points in the middle part of the code element. The specific algorithm is as follows:

[0007] A1: The sum of the weighted count values ​​of the points within the ±3dB window in the first 0.5μs;

[0008] A2: The sum of the weighted count values ​​of the points within the ±3dB window in the last 0.5μs;

[0009] B1: the sum of weighted count values ​​of points below the threshold in the first 0.5 μs;

[0010] B2: the sum of weighted count values ​​of points below the threshold in the last 0.5 μs;

[0011] S1 = A1 - A2 + B2 - B1;

[0012] S2 = A2 - A1 + B1 - B2;

[0013] Among them, S1 is the score of the code element being rated as "1"; S2 is the score of the code element being rated as "0";

[0014] Then compare the values ​​of S1 and S2, and the larger score determines the bit value corresponding to the codeword. If they are equal, the bit of the codeword is 0.

[0015] Through the above introduction to the principle of the traditional baseline multi-point decision method, we can know that the traditional method of extracting code elements uses the reference voltage -6dB level as the threshold level. Therefore, when the signal-to-noise ratio is low, many interference points will be generated, causing the B1 and B2 in the above parameters to increase, causing scoring errors and code element misjudgment; in addition, when the signal is small or the signal-to-noise ratio is low, the ±3dB condition will also produce more interference points, causing the A1 and A2 in the above parameters to increase, causing scoring errors and code element misinterpretation. At the same time, the restrictions of the two parameters will also lose some sensitivity indicators. Summary of the invention

[0016] The present invention aims to provide a method, medium and device for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA, so as to solve the problems existing in the above-mentioned existing S mode 1090ES symbol extraction method.

[0017] The present invention provides a method for identifying and extracting ADS-B IN signal code elements under low signal-to-noise ratio based on FPGA, comprising the following steps:

[0018] Step 1: Perform autocorrelation operation on the input signal;

[0019] Step 2: Generate a standard pulse with a pulse width of N microseconds;

[0020] Step 3: Perform cross-correlation operation on the signal after the autocorrelation operation in step 1 and the standard pulse generated in step 2;

[0021] Step 4: Perform header detection on the signal after the cross-correlation operation in step 3;

[0022] Step 5: After determining the header in step 4, find the first code element position according to the pulse timing, and use the shift register to store N microseconds before and after the first code element;

[0023] Step 6: Calculate the amplitude value N microseconds before the first codeword, recorded as sum_pre; calculate the amplitude value N microseconds after the first codeword, recorded as sum_later;

[0024] Step 7: Sampling is performed according to an enable signal with a pulse width of 2N microseconds. When the enable signal is valid, sum_pre and sum_later are compared, and a codeword is output according to the comparison result.

[0025] Step 8: According to the DF value, determine the number of sampling times and complete data locking.

[0026] In some embodiments, the circuit for implementing the autocorrelation operation in step 1 includes: a delay circuit, a detector and an integrator;

[0027] The input ends of the delay circuit and the detector are both used for inputting signals;

[0028] The output end of the delay circuit is connected to a detector;

[0029] The output end of the detector is connected to the input end of the integrator;

[0030] The output terminal of the integrator is used for outputting a signal.

[0031] Furthermore, in step 7, the method of outputting a codeword according to the comparison result includes:

[0032] If sum_pre≥sum_later, output codeword 1;

[0033] If sum_pre<sum_later, the code word 0 is output.

[0034] In some embodiments, N=0.5.

[0035] The present invention also provides a computer terminal storage medium storing computer terminal executable instructions, wherein the computer terminal executable instructions are used to execute the above-mentioned ADS-B IN signal code element recognition and extraction method under low signal-to-noise ratio based on FPGA.

[0036] The present invention also provides a computing device, comprising:

[0037] At least one processor; and a memory in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned ADS-B IN signal symbol recognition and extraction method under low signal-to-noise ratio based on FPGA.

[0038] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0039] 1. The present invention utilizes autocorrelation algorithm and cross-correlation algorithm to improve the signal-to-noise ratio of input signals in a low signal-to-noise ratio environment.

[0040] 2. The present invention realizes the extraction of code element signals by comparing the amplitude strength before and after the code element, without the restriction conditions of traditional ±3dB parameters and 6dB parameters, thereby improving the decoding sensitivity of ADS-B IN signals in low signal-to-noise ratio environments.

[0041] 3. The present invention can be implemented through software, which is convenient for transplantation and debugging between different platforms and reduces production and maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 This is a schematic diagram of the 1090ES pulse position encoding format.

[0044] Figure 2 Schematic diagram of the baseline multi-point decision method.

[0045] Figure 3 The present invention is a flowchart of a method for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA in an embodiment of the present invention.

[0046] Figure 4Schematic diagram of the circuit structure for implementing the autocorrelation algorithm in an embodiment of the present invention.

[0047] Figure 5 4 is a signal waveform diagram before autocorrelation operation processing in an embodiment of the present invention.

[0048] Figure 6 4 is a signal waveform diagram after autocorrelation operation processing in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Example

[0052] like Figure 3 As shown, this embodiment proposes a method for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA, comprising the following steps:

[0053] Step 1: Perform autocorrelation operation on the input signal; Figure 4 As shown, the circuit for implementing the autocorrelation operation includes: a delay circuit, a detector and an integrator;

[0054] The input ends of the delay circuit and the detector are both used for inputting signals;

[0055] The output end of the delay circuit is connected to a detector;

[0056] The output end of the detector is connected to the input end of the integrator;

[0057] The output terminal of the integrator is used for outputting a signal.

[0058] The signal before autocorrelation operation is as follows Figure 5 As shown, the signal before autocorrelation operation is as follows Figure 6 shown.

[0059] Step 2: Generate a standard pulse with a pulse width of 0.5us;

[0060] Step 3: Perform cross-correlation operation on the signal after the autocorrelation operation in step 1 and the standard pulse generated in step 2;

[0061] Step 4: Perform header detection on the signal after the cross-correlation operation in step 3;

[0062] Step 5: After determining the header in step 4, find the first code element position according to the pulse timing, and use the shift register to store 0.5us before and after the first code element;

[0063] Step 6: Calculate the amplitude value 0.5us before the first code element, recorded as sum_pre; calculate the amplitude value 0.5us after the first code element, recorded as sum_later;

[0064] Step 7: Sampling is performed according to the 1us enable signal. When the enable signal is valid, sum_pre and sum_later are compared, and the codeword is output according to the comparison result:

[0065] If sum_pre≥sum_later, output codeword 1;

[0066] If sum_pre<sum_later, the code word 0 is output.

[0067] Step 8: According to the DF value, determine the number of sampling times and complete data locking.

[0068] Therefore, the ADS-B IN signal symbol recognition and extraction method based on FPGA under low signal-to-noise ratio implemented by the present invention is simple, effective, and easy to implement. It can realize S-mode 1090ES symbol extraction under low signal-to-noise ratio and ensure the indicators and performance requirements of the ADS-B receiving system. Compared with the traditional S-mode 1090ES symbol extraction method, the present invention has the following beneficial effects:

[0069] 1. The present invention utilizes autocorrelation algorithm and cross-correlation algorithm to improve the signal-to-noise ratio of input signals in a low signal-to-noise ratio environment.

[0070] 2. The present invention realizes the extraction of code element signals by comparing the amplitude strength before and after the code element, without the restriction conditions of traditional ±3dB parameters and 6dB parameters, thereby improving the decoding sensitivity of ADS-B IN signals in low signal-to-noise ratio environments.

[0071] 3. The present invention can be implemented through software, which is convenient for transplantation and debugging between different platforms and reduces production and maintenance costs.

[0072] In addition, in some embodiments, a computer terminal storage medium is provided, which stores computer terminal executable instructions, and the computer terminal executable instructions are used to execute the ADS-B IN signal code element recognition and extraction method under low signal-to-noise ratio based on FPGA as described in the above embodiments. Examples of computer storage media include magnetic storage media (e.g., floppy disks, hard disks, etc.), optical recording media (e.g., CD-ROMs, DVDs, etc.) or memories, such as memory cards, ROMs, or RAMs. Computer storage media can also be distributed on network-connected computer systems, such as application stores.

[0073] In addition, in some embodiments, a computing device is proposed, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the ADS-B IN signal symbol identification and extraction method under low signal-to-noise ratio based on FPGA as described in the above embodiments. Examples of computing devices include PCs, tablet computers, smart phones, or PDAs.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA, characterized in that: The steps include: Step 1: Perform autocorrelation operation on the input signal; Step 2: Generate a standard pulse with a pulse width of N microseconds; Step 3: Perform cross-correlation operation on the signal after the autocorrelation operation in step 1 and the standard pulse generated in step 2; Step 4: Perform header detection on the signal after the cross-correlation operation in step 3; Step 5: After determining the header in step 4, find the first code element position according to the pulse timing, and use the shift register to store N microseconds before and after the first code element; Step 6: Calculate the amplitude value N microseconds before the first codeword, recorded as sum_pre; calculate the amplitude value N microseconds after the first codeword, recorded as sum_later; Step 7: Sampling is performed according to an enable signal with a pulse width of 2N microseconds. When the enable signal is valid, sum_pre and sum_later are compared, and a codeword is output according to the comparison result. Step 8: According to the DF value, determine the sampling times and complete data locking; The circuit for implementing the autocorrelation operation in step 1 includes: a delay circuit, a detector and an integrator; The input ends of the delay circuit and the detector are both used for inputting signals; The output end of the delay circuit is connected to a detector; The output end of the detector is connected to the input end of the integrator; The output terminal of the integrator is used for outputting a signal.

2. The method for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA according to claim 1 is characterized in that: In step 7, the method of outputting a codeword according to the comparison result includes: If sum_pre≥sum_later, output codeword 1; If sum_pre<sum_later, the code word 0 is output.

3. The method for identifying and extracting ADS-B IN signal symbols under low signal-to-noise ratio based on FPGA according to claim 1, characterized in that: N＝0.5。 4. A computer terminal storage medium storing computer terminal executable instructions, characterized in that: The computer terminal executable instructions are used to execute the ADS-B IN signal symbol recognition and extraction method under low signal-to-noise ratio based on FPGA as described in any one of claims 1 to 3.

5. A computing device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the ADS-B IN signal symbol recognition and extraction method under low signal-to-noise ratio based on FPGA as described in any one of claims 1 to 3.

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