A chip sorting path optimization method and optimization system

Abstract

The present invention provides a chip sorting path optimization method and optimization system, the optimization method comprising: obtaining the performance parameters of the chip on the wafer; determining the position of the bin of chips of the same specification through cluster analysis, and determining the order of each bin according to the set sorting rules; sorting the clusters for a single classification bin and determining the order of each cluster; sequentially selecting clusters to be sorted, sorting the selected clusters, and calculating the optimal path for a single cluster and at least three adjacent rows of chips; completing the sorting of the entire cluster block, and then calculating the optimal path for the next cluster, thereby completing the calculation of the entire bin sorting path. The technical solution of the present invention is adopted, by first clustering and separating, then sorting the clustered areas as a whole, and then performing path optimization calculation for each cluster area, while meeting the requirements of efficiency and optimal sorting path.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip detection, and in particular relates to a chip sorting path optimization method and optimization system. Background Art

[0002] Chip sorting is the process of transferring chips of the same specification (bin category) from different wafers to another wafer. In the LED chip industry, binning is performed based on the dominant wavelength and optical power of the emitted light. Chips with the same optical or electrical parameters are typically grouped together in a group called a bin. Because incoming wafers often contain several different chip specifications, the distribution of these chips on the wafer often appears as small islands, with the various specifications nested within each other. During the chip sorting process, chips of various specifications are sorted sequentially according to predefined rules. As chip sizes decrease and their number increases, sorting efficiency becomes a key metric for distinguishing sorting equipment. In addition to being dependent on the structural characteristics of the equipment itself, the choice of chip picking path also influences the overall sorting efficiency. The length of the total path affects the equipment's movement efficiency. Numerous methods exist to calculate the optimal path. However, since the number of chips to be sorted within a cluster can exceed 20,000, classic optimization methods, such as GA algorithms, are no longer able to meet both efficiency and path optimization requirements. Summary of the Invention

[0003] In response to the above technical problems, the present invention discloses a chip sorting path optimization method and optimization system, which improves the efficiency of sorting and takes into account both efficiency and path optimization.

[0004] To this end, the technical solution adopted in the present invention is:

[0005] A chip sorting path optimization method, comprising:

[0006] Obtain performance parameters of chips on wafers;

[0007] Through cluster analysis, the position of the bins of chips of the same specification is determined, and the order of each bin is determined according to the set sorting rules;

[0008] For a single classification bin, sort the clusters and determine the order of each cluster;

[0009] Select the clusters that need to be sorted in turn, sort the selected clusters, and calculate the optimal path for at least three adjacent rows of chips for each cluster;

[0010] After the sorting of the entire cluster block is completed, the optimal path of the next cluster is calculated, thereby completing the calculation of the entire bin sorting path.

[0011] By adopting the technical solution of the present invention, advanced clustering is performed and then path optimization is performed respectively, thereby improving the sorting efficiency.

[0012] Furthermore, during the chip sorting process, the information of the incoming wafer is stored in a map file. Based on the information in the map file, the classification information (bin type) of the chip is parsed out, and then the location of the bin is determined through cluster analysis. According to the sorting rules, the order of the entire bin is determined; then, for a single bin type, a path optimization algorithm is used, combined with the results of cluster analysis, to obtain the optimal sorting path for use by subsequent equipment, which can improve sorting efficiency.

[0013] As a further improvement of the present invention, the calculation of the optimal path includes:

[0014] Select the current chip and determine whether there is a chip at the next position in the forward direction. If so, add this chip position to the path and use this chip as the current chip, repeating the above steps. If there is no chip at the next position in the forward direction, determine whether the position in the same column of the next row is empty. If it is not empty, add the chip position in the next row to the path, set the forward direction to the next row, and mark the previous row as the waiting row. When searching in the next row, it is necessary to synchronously access whether the chip in the previous row exists. If so, prioritize the previous row as the starting point of the current path to take over the forward direction.

[0015] As a further improvement of the present invention, a connected domain analysis method is used to perform cluster analysis.

[0016] As a further improvement of the present invention, the connected domain analysis method includes: recording the white units around an image unit with the same mark, so that two adjacent image units may use different marks; that is, marking the black and white grayscale data of the image processing with 0 or 1 to indicate whether a chip exists at the current position (for example, 1 represents a chip of the same specification, and 0 represents no chip); after the marking is completed, these marks are aggregated, and all graphics in the same connected area are aggregated to form an area similar to an image spot, each area is classified and marked to determine the category of the chip, and then the chips with the same category of marks are clustered according to the area.

[0017] Connected component labeling (CCL) is a commonly used image blob analysis method and a broadly defined image clustering method. Existing algorithms are primarily used in image analysis, suffer from long computational time, and cannot output the pixel units that make up the image blob. Furthermore, they are not applicable to non-image applications. This technical solution innovatively applies image processing operations to the analysis of chip map information. In addition to location and test data information, chip sorting map information also includes chip classification information, which is discretely distributed throughout the map area. The goal of chip sorting is to separate chips of the same classification. To efficiently select chips of the same type, this discrete information must first be clustered. Using image analysis methods, images composed of multiple discrete regions, or several discrete regions within a class image, are clustered, achieving better clustering results. In particular, for chip sorting equipment, cluster analysis of chip map files is required, providing a foundation for optimizing sorting paths.

[0018] The present invention also discloses a chip sorting path optimization system, which is characterized by comprising:

[0019] Chip performance parameter acquisition module, used to obtain the performance parameters of the chip on the wafer;

[0020] The cluster analysis module determines the location of bins of chips of the same specification through cluster analysis, and determines the order of each bin according to the set sorting rules;

[0021] The sorting module sorts the clusters for a single classification bin and determines the order of each cluster;

[0022] The optimal path calculation module selects clusters to be sorted in turn, sorts the selected clusters, and calculates the optimal path for a single cluster and at least three adjacent rows of chips.

[0023] As a further improvement of the present invention, the calculation method of the optimal path calculation module is as follows: select the current chip, determine whether there is a chip at the next position in the forward direction, and if so, add this chip position to the path, and use this chip as the current chip, and repeat the above steps; if there is no chip at the next position in the forward direction, determine whether the position in the same column of the next row is empty; if it is not empty, add the chip position of the next row to the path, set the forward direction to the next row, and mark the previous row as a waiting row; when searching in the next row, it is necessary to synchronously access whether the chip in the previous row exists. If so, the previous row is prioritized as the starting point of the current path, thereby taking over the forward movement.

[0024] As a further improvement of the present invention, the cluster analysis module adopts a connected domain analysis method to perform cluster analysis, including:

[0025] The white cells around an image unit are recorded with the same marker, so that two adjacent image units may use different markers; that is, the black and white grayscale data of the image processing are marked with 0 or 1 to indicate whether there is a chip at the current position (for example, 1 represents a chip of the same specification, and 0 represents no chip); after the marking is completed, these markers are aggregated, and all graphics in the same connected area are aggregated to form an area similar to an image spot. Each area is classified and marked with the category of the chip, and then the chips with the same category of markers are clustered according to the area.

[0026] The present invention also discloses a device comprising a connected processor and memory, wherein the processor is used to execute a computer program stored in the memory to perform the chip sorting path optimization method as described above.

[0027] The present invention also discloses a computer-readable storage medium, which includes a computer program. When the computer program is run on a computer, the method for optimizing the chip sorting path as described above is executed.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] First, the technical solution of this invention achieves excellent clustering capabilities by clustering multiple discrete regions within an image or a class of images, a common requirement. Furthermore, for chip sorting equipment, cluster analysis of chip map files is required, providing a foundation for optimizing sorting paths.

[0030] Second, the cluster segmentation of the present invention is based on the principle of the connected domain analysis algorithm. The basic data structure is modified, and the algorithm is extended to non-image fields. The black and white grayscale data of image processing is replaced with 0 and 1, indicating whether there is a chip at the current position, to optimize the memory structure. To address the problem of low computational efficiency in the reference code, an efficient data model structure and set type are used to check the inclusion relationship through the set, reducing the algorithm calculation time by 30% overall. At the same time, the algorithm implementation structure is modified to connect some areas that were originally disconnected but very close together as needed, and all the regional units that make up the spots are output. Then, for the areas that have been clustered and segmented, the overall sorting is first carried out, and then the path optimization calculation is performed for each cluster area, meeting the requirements of efficiency and optimal sorting path. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 14 is a flow chart of a cluster analysis process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The preferred embodiments of the present invention are described in further detail below.

[0033] A chip sorting path optimization method. During the chip sorting process, the information of the incoming wafer is stored in a map file. Based on the information in the map file, the chip classification information (bin type) is parsed. Then, the bin position is determined through cluster analysis. According to the sorting rules, the order of the entire bin is determined. Then, for each bin type, a path optimization algorithm is used, combined with the results of cluster analysis, to obtain the optimal sorting path for use in subsequent sorting equipment.

[0034] After obtaining a single classification bin, calculate the optimal sorting path according to the device's operating rules as follows:

[0035] 1. Sort the clusters. A cluster is a chip area with a number between 100,000 and 100,000. By setting a starting point, the start and end points of the cluster are sorted according to the closest distance to the previous end point, thereby determining the order of clusters.

[0036] 2. Select the clusters that need to be sorted one by one and perform path optimization for each cluster.

[0037] 3. Sort the selected clusters. The principle of sorting is to select paths for three adjacent rows of chips at the same time.

[0038] 4. First, select the current chip and determine whether there is a chip at the next position in the forward direction. If so, add this chip position to the path and use this chip as the current chip; repeat this step.

[0039] 5. If there is no chip at the next position in the forward direction, determine whether the position in the same column of the next row is empty; if it is not empty, add the chip position in the next row to the path, set the forward direction to the next row, and mark the previous row as the waiting row.

[0040] 6. When searching in the next row, it is necessary to synchronously check whether the chip in the previous row exists. If so, the previous row is prioritized as the starting point of the current path, and the next step is taken.

[0041] 7. Finally, the sorting of the entire cluster block is completed.

[0042] 8. After completing the cluster block sorting, the next cluster optimal path is calculated to complete the calculation of the entire bin sorting path.

[0043] In the above steps, clustering adopts the connected domain analysis method. In the process of implementing the connected domain analysis method, it is first necessary to record the white cells around an image unit with the same mark, that is, the black and white grayscale data of the image processing is marked with 0 or 1 to indicate whether there is a chip at the current position (for example, 1 represents a chip with the same specifications, and 0 represents no chip); after the marking is completed, these marks are aggregated to aggregate all the graphics in the same connected area to form an area similar to an image spot. In the chip map file, each physical location will have a classification mark to mark the category of each chip. The chips of the same category are very scattered, and the chips with the same category mark need to be clustered according to the region. For example Figure 1 As shown, the specific operations include:

[0044] 1. Create a 2D array of byte type. The size of the array should be larger than the range of the data to be processed in the future, and initialize all values of the array to 0.

[0045] 2. Import location information from a known chip map file in CSV format.

[0046] 3. Compare the 2D arrays and set the relative position value to 1.

[0047] 4. Traverse the entire 2D array from top to bottom and from left to right.

[0048] 5. If the current value is 0, return to step 4.

[0049] 6. If the current array value is 1, search for the 8-connected area around this position. If there is an existing marker in the connected area, set the current position to the existing marker and save all connected markers to the C# collection class.

[0050] 7. Return to step 4 until all locations have been traversed and marked.

[0051] 8. Re-traverse all the data.

[0052] 9. Save all the positions marked in the same set into a set of point positions.

[0053] 10. Take the set of all point positions as the output result.

[0054] The above steps better cluster several discrete regions within an image or image class composed of multiple discrete regions. Using an improved connected domain analysis method, this innovatively applies image processing operations to the cluster analysis of chip map information, optimizing the algorithm's computational process and improving the efficiency of cluster analysis. By optimizing the label storage method used in the connected domain analysis implementation, leveraging the existing data structures of the C# language and combining it with the requirements for processing chip map files, the cluster analysis algorithm significantly improves algorithm efficiency and can be used to address classification problems within chip map files. Finally, a simple chip path optimization algorithm was designed that meets the trade-off between timeliness and optimality of path calculation, making it suitable for on-site manufacturing needs.

[0055] The embodiment of the present invention further discloses a chip sorting path optimization system using the above chip sorting path optimization method, which includes:

[0056] Chip performance parameter acquisition module, used to obtain the performance parameters of the chip on the wafer;

[0057] The cluster analysis module determines the location of bins of chips of the same specification through cluster analysis, and determines the order of each bin according to the set sorting rules;

[0058] The sorting module sorts the clusters for a single classification bin and determines the order of each cluster;

[0059] The optimal path calculation module selects clusters to be sorted in turn, sorts the selected clusters, and calculates the optimal path for a single cluster and at least three adjacent rows of chips.

[0060] Furthermore, the calculation method of the optimal path calculation module is: select the current chip, determine whether there is a chip at the next position in the forward direction, and if so, add this chip position to the path, and use this chip as the current chip, and repeat the above steps; if there is no chip at the next position in the forward direction, determine whether the position in the same column of the next row is empty; if it is not empty, add the chip position of the next row to the path, set the forward direction to the next row, and mark the previous row as the waiting row; when searching in the next row, it is necessary to synchronously access whether the chip in the previous row exists. If so, the previous row is prioritized as the starting point of the current path, thereby taking over the forward movement.

[0061] The cluster analysis module uses a connected domain analysis method to perform cluster analysis, including:

[0062] The white cells around an image unit are recorded with the same marker, so that two adjacent image units may use different markers; that is, the black and white grayscale data of the image processing are marked with 0 or 1 to indicate whether there is a chip at the current position (for example, 1 represents a chip of the same specification, and 0 represents no chip); after the marking is completed, these markers are aggregated, and all graphics in the same connected area are aggregated to form an area similar to an image spot. Each area is classified and marked with the category of the chip, and then the chips with the same category of markers are clustered according to the area.

[0063] An embodiment of the present invention further discloses a device comprising a connected processor and memory, wherein the processor is configured to execute a computer program stored in the memory to perform the above-mentioned chip sorting path optimization method.

[0064] An embodiment of the present invention further discloses a computer-readable storage medium, which includes a computer program. When the computer program is run on a computer, it is used to execute the chip sorting path optimization method as described above. The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be deemed to fall within the scope of protection of the present invention.

Claims

1. A chip sorting path optimization method, characterized in that: It includes: Obtain performance parameters of chips on wafers; Through cluster analysis, the position of the bins of chips of the same specification is determined, and the order of each bin is determined according to the set sorting rules; For a single classification bin, sort the clusters and determine the order of each cluster; Select the clusters that need to be sorted in turn, sort the selected clusters, and calculate the optimal path for at least three adjacent rows of chips for each cluster; After sorting the entire cluster block, the optimal path for the next cluster is calculated, thus completing the calculation of the entire bin sorting path. Cluster analysis was performed using the connected domain analysis method; The connected domain analysis method includes: marking the black and white grayscale data of the image processing with 0 or 1 to indicate whether a chip exists at the current position; after the marking is completed, the marks are aggregated, and all graphics in the same connected region are aggregated to form an area similar to an image spot, each area is classified and marked as a chip category, and then chips with the same category are clustered according to the region; The calculation of the optimal path includes: selecting the current chip, judging whether there is a chip at the next position in the forward direction, and if so, adding this chip position to the path, and using this chip as the current chip, and repeating the above steps; if there is no chip at the next position in the forward direction, judging whether the position in the same column of the next row is empty; if it is not empty, adding the chip position of the next row to the path, setting the forward direction to the next row, and marking the previous row as a waiting row; when searching the next row, it is necessary to synchronously access whether the chip in the previous row exists, and if so, giving priority to using the previous row as the starting point of the current path, thereby taking over the forward movement.

2. A chip sorting path optimization system, characterized in that: It includes: Chip performance parameter acquisition module, used to obtain the performance parameters of the chip on the wafer; The cluster analysis module determines the location of bins of chips of the same specification through cluster analysis, and determines the order of each bin according to the set sorting rules; The sorting module sorts the clusters for a single classification bin and determines the order of each cluster; The optimal path calculation module selects the clusters to be sorted in turn, sorts the selected clusters, and calculates the optimal path for each cluster and at least three adjacent rows of chips at the same time; The cluster analysis module uses a connected domain analysis method to perform cluster analysis, including: marking the black and white grayscale data of the image processing with 0 or 1 to indicate whether a chip exists at the current position; After the marking is completed, the marks are aggregated, and all the graphics in the same connected area are aggregated to form an area similar to an image spot. Each area is classified and marked with the category of the chip, and then the chips with the same category of marks are clustered according to the area; The calculation method of the optimal path calculation module is as follows: select the current chip, determine whether there is a chip at the next position in the forward direction, and if so, add this chip position to the path, and use this chip as the current chip, and repeat the above steps; if there is no chip at the next position in the forward direction, determine whether the position in the same column of the next row is empty; if it is not empty, add the chip position of the next row to the path, set the forward direction to the next row, and mark the previous row as a waiting row; when searching the next row, it is necessary to synchronously access whether the chip in the previous row exists, and if so, prioritize the previous row as the starting point of the current path, so as to take over the forward movement.

3. A preferred device for a chip sorting path, comprising a connected processor and memory, characterized in that: The processor is configured to execute the computer program stored in the memory to perform the chip sorting path optimization method according to claim 1 .

4. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a computer program, and when the computer program is run on a computer, the method for optimizing the chip sorting path according to claim 1 is executed.

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