Semiconductor structure, method of forming a semiconductor structure, and memory

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a semiconductor structure, a forming method of the semiconductor structure and a memory, the semiconductor structure comprises: a substrate; a first conductive layer, part of the first conductive layer is located in the substrate, and the rest of the first conductive layer protrudes above the substrate; a barrier layer, the barrier layer is located on the substrate, and at least located on the sidewall of the first conductive layer protruding from the substrate; a dielectric layer, the dielectric layer is located on the barrier layer; a second conductive layer, the second conductive layer penetrates the dielectric layer and the barrier layer, the second conductive layer is in contact with the barrier layer sidewall, and the second conductive layer is in contact with at least part of the upper surface of the first conductive layer, so that the performance of the semiconductor structure can be improved at least.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a semiconductor structure, a method for forming a semiconductor structure, and a memory. Background Technology

[0002] With the rapid development of integrated circuit technology, the density of devices in integrated circuits is increasing, the feature size of semiconductor devices is constantly decreasing, and the electrode area of ​​semiconductor structures is also constantly decreasing. During the manufacturing process, metal interconnect structures are fabricated on the electrodes for lead wire or testing purposes. The introduction of metal interconnect structures can not only increase device integration and improve device operating speed, but also reduce chip costs and simplify device fabrication processes.

[0003] Barrier layers play a crucial role in metal interconnect structures, directly affecting device performance. During the fabrication of metal interconnect structures, after multiple processing steps, the contact surfaces of different conductive layers become uneven. In existing technologies, the contact area between the barrier layer and different conductive layers is small, resulting in poor adhesion between the barrier layer and the conductive layer. This may lead to the separation of different conductive layers in subsequent fabrication processes, affecting the performance of the semiconductor structure.

[0004] Improving the contact effect between different conductive layers in a metal interconnect structure has become a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a semiconductor structure, a method for forming a semiconductor structure, and a memory, which at least helps to solve the problem of poor contact between different conductive layers in a semiconductor structure.

[0006] According to some embodiments of this application, one aspect of this application provides a semiconductor structure, including: a substrate; a first conductive layer, a portion of which is located within the substrate, and the remaining portion of which protrudes above the substrate; a barrier layer, which is located on the substrate and at least located on the sidewall of the first conductive layer protruding from the substrate; a dielectric layer, which is located on the barrier layer; and a second conductive layer, which penetrates the dielectric layer and the barrier layer, and is in contact with the sidewall of the barrier layer and at least a portion of the upper surface of the first conductive layer.

[0007] In addition, the barrier layer includes a first barrier layer and a second barrier layer stacked in sequence, and the materials of the first barrier layer and the second barrier layer are different; the second barrier layer, the first barrier layer and the first conductive layer form a hole; the second conductive layer also fills the hole.

[0008] In addition, in the direction perpendicular to the upper surface of the first conductive layer, the thickness of the first barrier layer is less than the thickness of the second barrier layer.

[0009] In addition, in the direction perpendicular to the upper surface of the first conductive layer, the thickness ratio of the first barrier layer to the second barrier layer is 1:3 to 1:4.

[0010] In addition, in the direction perpendicular to the upper surface of the first conductive layer, the thickness of the first barrier layer is 5 nanometers to 10 nanometers, and the thickness of the second barrier layer is 15 nanometers to 40 nanometers.

[0011] In addition, the material of the first barrier layer includes silicon oxynitride or silicon fluoride; the material of the second barrier layer includes silicon nitride or silicon carbonitride.

[0012] In addition, the second conductive layer is in contact with the entire upper surface of the first conductive layer.

[0013] In addition, in the direction perpendicular to the upper surface of the substrate, the thickness ratio of the first conductive layer protruding from the substrate to the thickness of the first conductive layer located within the substrate is 1:1 to 1:2.

[0014] Additionally, it includes a stop layer located on the upper surface of the substrate and between the substrate and the barrier layer.

[0015] According to some embodiments of this application, another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first conductive layer, a portion of which is located within the substrate and the remaining portion of which protrudes above the substrate; forming a barrier layer, the barrier layer being located on the substrate and at least located on the sidewalls of the first conductive layer protruding from the substrate; forming a dielectric layer, the dielectric layer covering the surface of the barrier layer; and forming a second conductive layer, the second conductive layer penetrating the dielectric layer and the barrier layer, the second conductive layer contacting the sidewalls of the barrier layer and at least a portion of the upper surface of the first conductive layer.

[0016] Additionally, the step of forming the first conductive layer includes: forming a sacrificial layer on the substrate; patterning the sacrificial layer and the substrate, forming a first trench in the sacrificial layer and the substrate; forming the first conductive layer filling the first trench; and removing the sacrificial layer.

[0017] In addition, before forming the sacrificial layer, the process includes: forming a stop layer on the upper surface of the substrate; and in the process step of removing the sacrificial layer, removing the sacrificial layer until the stop layer is exposed.

[0018] Additionally, the step of forming the barrier layer, the dielectric layer, and the second conductive layer includes: forming an initial barrier layer that covers the exposed surface of the first conductive layer and is located on the substrate; forming an initial dielectric layer that covers the upper surface of the initial barrier layer; patterning the initial dielectric layer and the initial barrier layer until at least a portion of the surface of the first conductive layer is exposed, forming a second trench, with the remaining initial dielectric layer serving as the dielectric layer and the remaining initial barrier layer serving as the barrier layer; and forming a second conductive layer that fills the second trench.

[0019] In addition, the barrier layer includes a first barrier layer and a second barrier layer stacked in sequence, and the materials of the first barrier layer and the second barrier layer are different; after forming the second trench, the process further includes: wet etching the first barrier layer exposed by the second trench so that the second barrier layer, the first conductive layer and the remaining first barrier layer form a hole; in the process step of forming the second conductive layer, the second conductive layer also fills the hole.

[0020] In addition, the wet etching process has a higher etching selectivity for the first barrier layer than for the second barrier layer.

[0021] In addition, the etching solution used in the wet etching process includes an aqueous solution of hydrofluoric acid.

[0022] According to some embodiments of this application, in another aspect, this application also provides a memory including the semiconductor structure described in any of the above.

[0023] The technical solution provided in this application has at least the following advantages:

[0024] The semiconductor structure provided in this application embodiment has a barrier layer that contacts not only the sidewall of the first conductive layer protruding from the substrate, but also the sidewall of the second conductive layer. This ensures that the same barrier layer has contact with different conductive layers, which is beneficial for fixing the positions of different conductive layers using the barrier layer. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to stress, thus preventing gaps from forming. At the same time, the contact between the sidewalls of the barrier layer and the conductive layer increases the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer on the conductive layer. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a semiconductor structure;

[0027] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0029] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure provided in another embodiment of this application.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100, 200, 300 - Substrate; 101, 201, 301 - Electrode; 102, 202, 302 - First conductive layer; 203, 303 - Stop layer; 104, 204, 304 - Barrier layer; 105, 205, 305 - Dielectric layer; 106, 206, 306 - Second conductive layer; 214, 314 - First barrier layer; 224, 324 - Second barrier layer; 307 - Sacrificial layer; 308 - First trench; 315 - Initial dielectric layer; 344 - Initial first barrier layer; 354 ​​- Initial second barrier layer; 309 - Second trench; 310 - Hole. Detailed Implementation

[0032] As is known from the background art, the contact effect between different conductive layers in a semiconductor structure is poor.

[0033] Figure 1 This is a schematic diagram of a semiconductor structure.

[0034] The following section provides a specific explanation using a semiconductor structure as an example. (Refer to...) Figure 1A semiconductor structure includes: a substrate 100 having an electrode 101 therein; a first conductive layer 102 located within the substrate 100 and in contact with the electrode 101; a barrier layer 104 located on the substrate 100 and on the top surface of the first conductive layer 102 exposed on the substrate 100; a dielectric layer 105 located on the barrier layer 104; and a second conductive layer 106 penetrating the dielectric layer 105 and the barrier layer 104, the second conductive layer 106 in contact with the sidewall of the barrier layer 104 and a portion of the upper surface of the first conductive layer 102.

[0035] It can be seen that the barrier layer 104 is only located on part of the upper surface of the first conductive layer 102, and the contact area between the barrier layer 104 and the first conductive layer 102 is small, resulting in poor adhesion and fixation between the first conductive layer 102 and the barrier layer 104. At the same time, since the bottom surfaces of the barrier layer 104 and the second conductive layer 106 are on the same horizontal plane, in subsequent manufacturing processes, when the process stress causes the position of the second conductive layer 106 to change, the direction of position change of the barrier layer 104 under this process stress is the same as the direction of position change of the second conductive layer 106, and it cannot play the role of fixing the second conductive layer 106.

[0036] This application provides a semiconductor structure in which the barrier layer contacts not only the sidewall of the first conductive layer protruding from the substrate, but also the sidewall of the second conductive layer. This ensures that the same barrier layer and different conductive layers are in contact, which is beneficial for fixing the positions of different conductive layers using the barrier layer. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to stress, thus preventing gaps from forming. At the same time, the contact between the sidewalls of the barrier layer and the conductive layer increases the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer on the conductive layer.

[0037] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0038] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0039] refer to Figure 2The semiconductor structure includes: a substrate 200; a first conductive layer 202, a portion of which is located within the substrate 200, and the remainder of which protrudes above the substrate 200; a barrier layer 204, which is located on the substrate 200 and at least on the sidewall of the first conductive layer 202 protruding from the substrate 200; a dielectric layer 205, which is located on the barrier layer 204; and a second conductive layer 206, which penetrates the dielectric layer 205 and the barrier layer 204, and is in contact with the sidewall of the barrier layer 204 and at least a portion of the upper surface of the first conductive layer 202.

[0040] In this process, the barrier layer 204 not only contacts the sidewall of the first conductive layer 202 protruding from the substrate 200, but also contacts the sidewall of the second conductive layer 206. This ensures that the same barrier layer 204 has contact with different conductive layers, which is beneficial for fixing the positions of different conductive layers using the barrier layer 204. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to process stress, thus creating gaps and affecting the performance of the semiconductor structure. At the same time, the contact between the barrier layer 204 and the sidewall of the conductive layer increases the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 204 on the conductive layer.

[0041] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0042] The substrate 200 is made of an insulating material to isolate the conductive layer from other conductive structures. In some embodiments, the substrate 200 is made of silicon dioxide. In other embodiments, the substrate 200 may also be made of silicon nitride or silicon carbide.

[0043] In some embodiments, a metal interconnect structure is formed on the semiconductor substrate to be processed, on which source electrodes, drain electrodes and gate electrodes have already been formed. Therefore, the substrate 200 may also have an electrode 201, which is an electrical connection structure led out from the semiconductor substrate. The specific material can be a metal material such as tungsten or silver.

[0044] The width of the upper surface of electrode 201 is greater than the width of the lower surface. The surface of electrode 201 that contacts the first conductive layer 202 is the upper surface. The larger the width of the upper surface, the larger the contact area. The larger the contact area, the lower the contact resistance, which can effectively improve the conductivity efficiency of the semiconductor structure.

[0045] The surface of electrode 201 may have a protective layer (not shown in the figure). The material of the protective layer may be titanium nitride, which can effectively prevent ions in electrode 201 from diffusing outward and causing adverse effects.

[0046] In some embodiments, the first conductive layer 202 is made of copper, which has a low resistivity. This improves the conductivity of the semiconductor structure while reducing its production cost. In other embodiments, the first conductive layer may be made of aluminum or cobalt.

[0047] In some embodiments, the first conductive layer 202 can be formed directly using a copper sputtering process. In other embodiments, the first conductive layer can also be formed using a chemical vapor deposition process.

[0048] In some embodiments, a portion of the first conductive layer 202 is located within the substrate 200, while the remaining portion of the first conductive layer 202 protrudes above the substrate 200. This is because the subsequently formed barrier layer 204 needs to contact a portion of the sidewall of the first conductive layer 202, so the substrate 200 needs to expose a portion of the first conductive layer 202.

[0049] Specifically, in the direction perpendicular to the upper surface of the substrate 200, the thickness ratio of the first conductive layer 202 protruding from the substrate 200 to the thickness of the first conductive layer 202 located within the substrate 200 is 1:1 to 1:2.

[0050] Since part of the first conductive layer 202 is located within the substrate 200, the substrate 200 also has a fixing effect on the first conductive layer 202. The thickness ratio of the first conductive layer 202 protruding from the substrate 200 to the first conductive layer 202 located within the substrate 200 is maintained within the above range. While ensuring the fixing effect of the substrate 200 on the first conductive layer 202, sufficient contact area is reserved for the barrier layer 204.

[0051] The first conductive layer 202 not only contacts the upper surface of the electrode 201, but also contacts part of the sidewall of the electrode 201. The contact area is large, so the contact resistance between the first conductive layer 202 and the electrode 201 is low, which further improves the conductivity of the semiconductor structure.

[0052] The surface of the first conductive layer 202 may also have a protective layer (not shown in the figure) to prevent ions in the first conductive layer 202 from diffusing outward. The material of the protective layer on the surface of the first conductive layer 202 may be tantalum metal or tantalum nitride.

[0053] In some embodiments, a stop layer 203 is also included, which is located on the upper surface of the substrate 200 and between the substrate 200 and the barrier layer 204.

[0054] The material of the stop layer 203 can be silicon nitride or silicon carbonitride. Since, when forming the first conductive layer 202, in order to make part of the first conductive layer 202 located above the substrate 200, it is necessary to remove part of the substrate 200 after forming the first conductive layer 202. The stop layer 203 can serve as an etching stop layer for the process of removing part of the substrate 200, effectively preventing over-etching.

[0055] In some embodiments, the barrier layer 204 is not only located on the sidewall of the first conductive layer 202 protruding above the substrate 200, but also in contact with a portion of the upper surface of the first conductive layer 202. The large contact area between the barrier layer 204 and the first conductive layer 202 is beneficial for improving the adhesion and fixation effect of the barrier layer 204 on the first conductive layer 202. Furthermore, since there is more than one contact surface between the barrier layer 204 and the first conductive layer 202, when the first conductive layer 202 is subjected to process stress in a certain direction, even if the barrier layer 204 in contact with one side of the first conductive layer 202 cannot exert an adhesion effect, the barrier layer 204 in contact with other sides of the first conductive layer 202 will still exert an adhesion effect, ensuring that the barrier layer 204 and the first conductive layer 202 have a good adhesion effect in most cases.

[0056] In some embodiments, the barrier layer 204 can be a two-layer structure, including a first barrier layer 214 and a second barrier layer 224 stacked sequentially, with the first barrier layer 214 and the second barrier layer 224 made of different materials; the second barrier layer 224, the first barrier layer 214, and the first conductive layer 202 form a hole; the second conductive layer 206 also fills the hole. In other embodiments, the barrier layer can also be a single-layer structure.

[0057] Since the second barrier layer 224, the first barrier layer 214, and the first conductive layer 202 form a hole, the upper surface of the first conductive layer 202 exposes a large area for contact with the second conductive layer 206. This is beneficial for increasing the contact area between the first conductive layer 202 and the second conductive layer 206, reducing contact resistance, and further improving the conductivity of the entire semiconductor structure. Because of the hole, the first barrier layer 214 and the second barrier layer 224 form a snap-fit-like structure that holds the second conductive layer 206, which fills the hole, in place. In subsequent manufacturing processes, regardless of the direction of process stress the second conductive layer 206 is subjected to, the first barrier layer 214 and the second barrier layer 224 will fix the second conductive layer 206 in place, ensuring that the second conductive layer 206 will not detach from the surface of the first conductive layer 202.

[0058] In some embodiments, the thickness of the first barrier layer 214 is less than the thickness of the second barrier layer 224 in a direction perpendicular to the upper surface of the first conductive layer 202.

[0059] When etching the first barrier layer 214 to form a hole, over-etching is prone to occur, resulting in fewer barrier layers 204 on the upper surface of the first conductive layer 202. Therefore, the second barrier layer 224 has a larger thickness, which helps to ensure that even if the first barrier layer 214 is over-etched, the upper surface of the first conductive layer 202 still has a large area of ​​barrier layer 204. The first barrier layer 214 has a smaller thickness, which helps to control the etching effect when forming a hole.

[0060] In some embodiments, the thickness ratio of the first barrier layer 214 and the second barrier layer 224 is 1:3 to 1:4 in the direction perpendicular to the upper surface of the first conductive layer 202.

[0061] Specifically, in the direction perpendicular to the upper surface of the first conductive layer 202, the thickness of the first barrier layer 214 is 5 nanometers to 10 nanometers, specifically 6 nanometers, 7 nanometers or 8 nanometers; the thickness of the second barrier layer 224 is 15 nanometers to 40 nanometers, specifically 20 nanometers, 25 nanometers or 30 nanometers.

[0062] Within this range, the first barrier layer 214 ensures adhesion while not being too thick, which would make it difficult to control the etching effect when forming holes; the second barrier layer 224 is not too thin, which would cause poor adhesion of the entire barrier layer 204 when the first barrier layer 214 is over-etched.

[0063] In some embodiments, the material of the first barrier layer 214 includes silicon oxynitride or silicon fluoride; the material of the second barrier layer 224 includes silicon nitride or silicon carbonitride. Under the same wet etching process, the etching selectivity of the first barrier layer 214 is greater than that of the second barrier layer 224. This is beneficial because etching the first barrier layer 214 to form a hole will not have an excessive impact on the second barrier layer 224.

[0064] In some embodiments, the material of the dielectric layer 205 may be the same as the material of the substrate 200 to prevent different second conductive layers 206 from making electrical contact. Specifically, the material of the dielectric layer 205 may be silicon dioxide, silicon nitride, or silicon carbide.

[0065] In some embodiments, the width of the second conductive layer 206 located in the region near the second barrier layer 224 is smaller than the width of the top surface of the second conductive layer 206; this configuration ensures that the barrier layer 204 on the upper surface of the first conductive layer 202 has a large area, while increasing the area of ​​the exposed top surface of the second conductive layer 206 used for subsequent detection or lead wires.

[0066] In some embodiments, the second conductive layer 206 may be made of tungsten. In other embodiments, the second conductive layer may also be made of a metal with high conductivity, such as silver or cobalt.

[0067] The surface of the second conductive layer 206 may have a protective layer (not shown in the figure). The material of the protective layer may be titanium nitride, which can effectively prevent ions in the second conductive layer 206 from diffusing outward and causing adverse effects.

[0068] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application.

[0069] refer to Figure 3 In other embodiments, the second conductive layer 206 is in contact with the entire upper surface of the first conductive layer 202.

[0070] When removing the first barrier layer 214 on the top surface of the first conductive layer 202, all the first barrier layers 214 located on the upper surface of the first conductive layer 202 are removed, exposing the entire upper surface of the first conductive layer 202. This is beneficial for the first conductive layer 202 and the second conductive layer 206 to have the largest contact area and reduce contact resistance.

[0071] In some embodiments, the barrier layer 204 contacts not only the sidewall of the first conductive layer 202 protruding from the substrate 200, but also the sidewall of the second conductive layer 206. This ensures that the same barrier layer 204 has contact with different conductive layers, which is beneficial for fixing the positions of different conductive layers using the barrier layer 204. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to process stress, thus creating gaps and affecting the performance of the semiconductor structure. At the same time, the contact between the barrier layer 204 and the sidewall of the conductive layer increases the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 204 on the conductive layer.

[0072] Accordingly, another embodiment of this application also provides a method for forming a semiconductor structure. The semiconductor structure formed by the method of this other embodiment is the same as the semiconductor structure provided in the foregoing embodiments. The method for forming a semiconductor structure according to another embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0073] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure provided in another embodiment of this application.

[0074] refer to Figure 4 Provides a 300 base.

[0075] The substrate 300 is made of an insulating material to isolate the conductive layer from other conductive structures. In some embodiments, the substrate 300 is made of silicon dioxide. In other embodiments, the substrate 300 may also be made of silicon nitride or silicon carbide.

[0076] In some embodiments, a metal interconnect structure is formed on the semiconductor substrate to be processed, on which source electrodes, drain electrodes and gate electrodes have already been formed. Therefore, the substrate 300 may also have an electrode 301, which is an electrical connection structure led out from the semiconductor substrate. The specific material can be a metal material such as tungsten or silver.

[0077] The width of the upper surface of electrode 301 is greater than the width of the lower surface. The surface of electrode 301 that contacts the subsequently formed first conductive layer is the upper surface. The larger the width of the upper surface, the larger the contact area. The larger the contact area, the lower the contact resistance, which can effectively improve the conductivity efficiency of the semiconductor structure.

[0078] refer to Figures 5-7 A first conductive layer 302 is formed, with a portion of the first conductive layer 302 located within the substrate 300 and the remaining portion of the first conductive layer 302 protruding above the substrate 300.

[0079] Specifically, refer to Figure 5 A stop layer 303 is formed on the upper surface of the substrate 300.

[0080] In some embodiments, an atomic layer deposition process is used to form a stop layer 303. The material of the stop layer 303 can be silicon nitride or silicon carbonitride. Since a sacrificial layer needs to be removed after the first conductive layer is formed in order to ensure that part of the first conductive layer is located above the substrate 300, the stop layer 303 can serve as an etching stop layer for the sacrificial layer removal process, effectively preventing over-etching.

[0081] A sacrificial layer 307 is formed on the substrate 300, specifically the sacrificial layer 307 located on the upper surface of the stop layer 303.

[0082] In some embodiments, a sacrificial layer 307 is formed using a chemical vapor deposition process. The material of the sacrificial layer 307 is the same as that of the substrate 300. Since the materials of the substrate 300 and the sacrificial layer 307 are the same, the etching rates of the sacrificial layer 307 and the substrate 300 can be kept consistent, which is more conducive to the implementation of the process.

[0083] refer to Figure 6 The patterned sacrificial layer 307 and substrate 300 are used to form a first trench 308 within the sacrificial layer 307 and substrate 300.

[0084] In some embodiments, a wet etching process is used to remove part of the sacrificial layer 307, part of the stop layer 303, and part of the substrate 300, forming a first trench 308 for subsequent formation of the first conductive layer.

[0085] refer to Figure 7 Forming a filling of the first trench 308 (reference) Figure 6 The first conductive layer 302; removal of the sacrificial layer 307 (reference) Figure 6 Until the stop layer 303 is exposed.

[0086] In some embodiments, a first conductive layer 302 is formed using a chemical vapor deposition process; a sacrificial layer 307 is removed using a wet etching process, and a stop layer 303 serves as an etching stop layer.

[0087] In some embodiments, the first conductive layer 302 is made of copper, which has a low resistivity. This improves the conductivity of the semiconductor structure while reducing its production cost. In other embodiments, the first conductive layer may be made of aluminum or cobalt.

[0088] In some embodiments, a portion of the first conductive layer 302 is located within the substrate 300, while the remaining portion of the first conductive layer 302 protrudes above the substrate 300. This is because the subsequently formed barrier layer 304 needs to contact a portion of the sidewall of the first conductive layer 302, so the substrate 300 needs to expose a portion of the first conductive layer 302.

[0089] The first conductive layer 302 not only contacts the upper surface of the electrode 301, but also contacts part of the sidewall of the electrode 301. The contact area is large, so the contact resistance between the first conductive layer 302 and the electrode 301 is low, which further improves the conductivity of the semiconductor structure.

[0090] refer to Figures 8-11 A barrier layer 304 is formed on the substrate 300 and at least on the sidewall of the first conductive layer 302 protruding from the substrate 300; a dielectric layer 305 is formed, covering the surface of the barrier layer 304; a second conductive layer 306 is formed, penetrating the dielectric layer 305 and the barrier layer 304, the second conductive layer 306 is in contact with the sidewall of the barrier layer 304, and the second conductive layer 306 is in contact with at least a portion of the upper surface of the first conductive layer 303.

[0091] Since the barrier layer 304 is in contact not only with the sidewall of the first conductive layer 302 protruding from the substrate 300, but also with the sidewall of the second conductive layer 306, there is contact between the same barrier layer 304 and different conductive layers. This is beneficial for fixing the positions of different conductive layers using the barrier layer 304. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to process stress, thus creating gaps and affecting the performance of the semiconductor structure. At the same time, the contact between the barrier layer 304 and the sidewall of the conductive layer helps to increase the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 304 on the conductive layer.

[0092] Specifically, refer to Figure 8An initial barrier layer 334 is formed, which covers the exposed surface of the first conductive layer 302 and is located on the substrate 300; an initial dielectric layer 315 is formed, which covers the upper surface of the initial barrier layer 334.

[0093] In some embodiments, the initial barrier layer 304 includes an initial first barrier layer 344 and an initial second barrier layer 354. The initial first barrier layer 344 is first formed on the substrate 300 and on the surface of the first conductive layer 302 protruding from the substrate 300 using an atomic deposition process. Then, the initial second barrier layer 354 is formed on the surface of the initial first barrier layer 344 using an atomic deposition process. Finally, the initial dielectric layer 315 is formed using a chemical vapor deposition process.

[0094] In some embodiments, the materials of the initial first barrier layer 344 and the initial second barrier layer 354 are different. The initial first barrier layer 344 is made of silicon oxynitride or silicon fluoride; the initial second barrier layer 354 is made of silicon nitride or silicon carbonitride. Under the same wet etching process, the etching selectivity of the initial first barrier layer 344 is greater than that of the initial second barrier layer 354. This is beneficial because it prevents the second barrier layer from being excessively affected when the first barrier layer is etched to form a hole.

[0095] In some embodiments, the material of the initial dielectric layer 315 can be the same as the material of the substrate 300, which can prevent electrical contact between different second conductive layers formed subsequently. Specifically, the material of the initial dielectric layer 315 can be silicon dioxide, silicon nitride, or silicon carbide.

[0096] refer to Figure 9 The initial dielectric layer 315 and the initial barrier layer 334 are patterned until at least a portion of the surface of the first conductive layer 302 is exposed, forming a second trench 309, with the remaining initial dielectric layer 315 serving as dielectric layer 305 and the remaining initial barrier layer 334 serving as barrier layer 304.

[0097] The barrier layer 304 includes a first barrier layer 314 and a second barrier layer 324 stacked sequentially, and the first barrier layer 314 and the second barrier layer 324 are made of different materials.

[0098] In some embodiments, the thickness of the first barrier layer 314 is less than the thickness of the second barrier layer 324 in a direction perpendicular to the upper surface of the first conductive layer 302.

[0099] When the first barrier layer 314 is etched to form a hole, over-etching is likely to occur, resulting in fewer barrier layers 304 on the upper surface of the first conductive layer 302. Therefore, the second barrier layer 324 has a larger thickness, which helps to ensure that even if the first barrier layer 314 is over-etched, the upper surface of the first conductive layer 302 still has a large area of ​​barrier layer 304. The first barrier layer 314 has a smaller thickness, which helps to control the etching effect when forming a hole.

[0100] In some embodiments, the thickness ratio of the first barrier layer 314 to the second barrier layer 324 is 1:3 to 1:4 in the direction perpendicular to the upper surface of the first conductive layer 302.

[0101] Specifically, in the direction perpendicular to the upper surface of the first conductive layer 302, the thickness of the first barrier layer 314 is 5 nanometers to 10 nanometers, specifically 6 nanometers, 7 nanometers or 8 nanometers; the thickness of the second barrier layer 324 is 15 nanometers to 40 nanometers, specifically 20 nanometers, 25 nanometers or 30 nanometers.

[0102] Within this range, the first barrier layer 314 ensures adhesion while not being too thick, which would make it difficult to control the etching effect when forming holes; the second barrier layer 324 is not too thin, which would cause poor adhesion of the entire barrier layer 304 when the first barrier layer 314 is over-etched.

[0103] refer to Figure 10 After forming the second trench 309, the method further includes: wet etching the first barrier layer 314 exposed in the second trench 309 so that the second barrier layer 324, the first conductive layer 302 and the remaining first barrier layer 314 form a hole 310.

[0104] Since the second barrier layer 324, the first barrier layer 314, and the first conductive layer 302 form a hole 310, the upper surface of the first conductive layer 302 exposes a large area for contact with the second conductive layer 306. This is beneficial for increasing the contact area between the first conductive layer 302 and the second conductive layer 306, reducing contact resistance, and further improving the conductivity of the entire semiconductor structure. Because of the hole 310, the first barrier layer 314 and the second barrier layer 324 form a snap-fit-like structure that holds the second conductive layer 306, which fills the hole 310, in place. In subsequent manufacturing processes, regardless of the direction of process stress the second conductive layer 306 is subjected to, the first barrier layer 314 and the second barrier layer 324 will fix the second conductive layer 306 in place, ensuring that the second conductive layer 306 will not detach from the surface of the first conductive layer 302.

[0105] In some embodiments, the wet etching process has a higher etching selectivity for the first barrier layer 314 than for the second barrier layer 324. Therefore, the second barrier layer 324 is not affected during this wet etching process.

[0106] In some embodiments, the etching solution used in the wet etching process includes an aqueous solution of hydrofluoric acid. The mass ratio of hydrofluoric acid to water is 1:50 to 1:100, specifically 1:60, 1:70, or 1:80.

[0107] refer to Figure 11 Forming a filling of the second trench 309 (reference) Figure 10 The second conductive layer 306 further fills the holes 310 (see reference). Figure 10 ).

[0108] In some embodiments, the width of the second conductive layer 306 located in the region near the second barrier layer 324 is smaller than the width of the top surface of the second conductive layer 306; this configuration ensures that the barrier layer 304 on the upper surface of the first conductive layer 302 has a large area, while increasing the area of ​​the exposed top surface of the second conductive layer 306 used for subsequent detection or lead wires.

[0109] In some embodiments, the second conductive layer 306 is formed using a chemical vapor deposition process, and the material of the second conductive layer 306 can be tungsten. In other embodiments, the material of the second conductive layer can also be a metal with high conductivity, such as silver or cobalt.

[0110] In some embodiments, since the formed barrier layer 304 contacts not only the sidewall of the first conductive layer 302 protruding from the substrate 300, but also the sidewall of the second conductive layer 306, there is contact between the same barrier layer 304 and different conductive layers. This is beneficial for fixing the positions of different conductive layers using the barrier layer 304. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to process stress, thus creating gaps and affecting the performance of the semiconductor structure. At the same time, the contact between the barrier layer 304 and the sidewall of the conductive layer helps to increase the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 304 on the conductive layer.

[0111] Another embodiment of this application also provides a memory, including: the semiconductor structure provided in the above embodiments.

[0112] In some embodiments, the memory includes a barrier layer in a semiconductor structure that contacts not only the sidewall of a first conductive layer protruding from the substrate but also the sidewall of a second conductive layer. This ensures contact between the same barrier layer and different conductive layers, which is beneficial for fixing the positions of different conductive layers using the barrier layer. In subsequent processes, the positional relationship between different conductive layers is less likely to change due to process stress, thus creating gaps and affecting the performance of the semiconductor structure. At the same time, the contact between the sidewalls of the barrier layer and the conductive layer increases the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer on the conductive layer.

[0113] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device, comprising: a substrate; a first conductive layer, part of which is located in the substrate, and the rest of which protrudes above the substrate; a barrier layer located on the substrate and at least on the sidewall of the first conductive layer protruding from the substrate; a dielectric layer located on the barrier layer; a second conductive layer penetrating the dielectric layer and the barrier layer, the second conductive layer being in contact with the sidewall of the barrier layer and the entire upper surface of the first conductive layer.

2. The semiconductor structure of claim 1, wherein, The barrier layer comprises a first barrier layer and a second barrier layer stacked in sequence, and the material of the first barrier layer is different from that of the second barrier layer; The second barrier layer, the first barrier layer and the first conductive layer form a hole; The second conductive layer also fills the hole.

3. The semiconductor structure of claim 2, wherein, In the direction perpendicular to the upper surface of the first conductive layer, the thickness of the first barrier layer is less than that of the second barrier layer.

4. The semiconductor structure of claim 3, wherein, In the direction perpendicular to the upper surface of the first conductive layer, the thickness ratio of the first barrier layer to the second barrier layer is 1:3-1:

4.

5. The semiconductor structure of claim 3, wherein, In the direction perpendicular to the upper surface of the first conductive layer, the thickness of the first barrier layer is 5-10 nm, and the thickness of the second barrier layer is 15-40 nm.

6. The semiconductor structure of claim 2, wherein, The material of the first barrier layer comprises silicon oxynitride or silicon nitride fluoride; and the material of the second barrier layer comprises silicon nitride or silicon carbon nitride.

7. The semiconductor structure of claim 1, wherein, In the direction perpendicular to the upper surface of the substrate, the thickness ratio of the first conductive layer protruding from the substrate to the first conductive layer located in the substrate is 1:1-1:

2.

8. The semiconductor structure of claim 1, wherein, Further comprising: a stop layer located on the upper surface of the substrate and between the substrate and the barrier layer.

9. A method of forming a semiconductor structure, comprising: The application also relates to a manufacturing method of the semiconductor device, comprising: providing a substrate; forming a first conductive layer, part of which is located in the substrate, and the rest of which protrudes above the substrate; forming a barrier layer located on the substrate and at least on the sidewall of the first conductive layer protruding from the substrate; forming a dielectric layer covering the surface of the barrier layer; forming a second conductive layer penetrating the dielectric layer and the barrier layer, the second conductive layer being in contact with the sidewall of the barrier layer and the entire upper surface of the first conductive layer.

10. The method of forming a semiconductor structure of claim 9, wherein, The step of forming the first conductive layer comprises: forming a sacrificial layer on the substrate; patterning the sacrificial layer and the substrate to form a first groove in the sacrificial layer and the substrate; forming the first conductive layer filling the first groove; removing the sacrificial layer.

11. The method of forming a semiconductor structure of claim 10, wherein, Before forming the sacrificial layer, the method further comprises: forming a stop layer on the upper surface of the substrate; In the process step of removing the sacrificial layer, the sacrificial layer is removed until the stop layer is exposed.

12. The method of forming a semiconductor structure of claim 9, wherein, The steps of forming the barrier layer, the dielectric layer and the second conductive layer comprise: forming an initial barrier layer covering the exposed surface of the first conductive layer and located on the substrate; forming an initial dielectric layer covering an upper surface of the initial barrier layer; patterning the initial dielectric layer and the initial barrier layer until at least part of the surface of the first conductive layer is exposed, forming a second trench, and the remaining initial dielectric layer as the dielectric layer and the remaining initial barrier layer as the barrier layer; forming the second conductive layer filling the second trench.

13. The method of forming a semiconductor structure of claim 12, wherein, the barrier layer comprises a first barrier layer and a second barrier layer stacked in sequence, and the material of the first barrier layer and the material of the second barrier layer are different; after forming the second trench, further comprising: wet etching the first barrier layer exposed by the second trench, so that the second barrier layer, the first conductive layer and the remaining first barrier layer enclose a hole; in the process step of forming the second conductive layer, the second conductive layer also fills the hole.

14. The method of forming a semiconductor structure of claim 13, wherein, the etching selectivity of the wet etching process to the first barrier layer is greater than the etching selectivity to the second barrier layer.

15. The method of forming a semiconductor structure of claim 14, wherein, the etching solution selected by the wet etching process comprises hydrofluoric acid aqueous solution.

16. A memory, comprising: comprising: the semiconductor structure according to any one of claims 1-8.

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