A Micro-LED chip and a manufacturing method thereof

Abstract

The present invention discloses a Micro-LED chip and a manufacturing method thereof. The manufacturing method of the Micro-LED chip includes: providing a stacked structure, the stacked structure including a substrate, a first nitride layer, a multi-quantum well layer, and a second nitride layer stacked from bottom to top; using a first dry etching process to remove a part of the second nitride layer and a part of the multi-quantum well layer on the stacked structure, exposing the first nitride layer, and forming an etching channel and a plurality of mesa surfaces; using a second dry etching process to repair the damage to the quantum wells on the sidewalls of the etching channel, and the etching power of the second dry etching process is less than the etching power of the first dry etching process; forming a second electrode on the upper surface of the mesa surface, the second electrode being electrically connected to the second nitride layer, and forming a first electrode at the bottom of the etching channel, the first electrode being electrically connected to the first nitride layer. By repairing the damaged quantum wells, the adverse effects caused by the size effect of the Micro-LED are reduced, and thus the quantum efficiency of the Micro-LED is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a Micro-LED chip and a manufacturing method thereof. Background Art

[0002] By thinning, miniaturizing, and matrixing the LED structure, the Micro-LED chip reduces the pixel pitch from the millimeter level of traditional LED advertising screens to the micron level. It is a solid self-luminous display technology highly integrated on a single chip. The Micro-LED chip does not require a backlight and has advantages over the current mainstream LCD and OLED display technologies in terms of power consumption, brightness, color saturation, service life, and response speed. Moreover, its structure is simple, and a single pixel can be achieved with only RGB three-color lamp beads. However, the unit size of the Micro-LED chip generally requires to be below 50μm. As the size of a single die continues to shrink, the accompanying size effect will intensify. The reduction in chip size will decrease the light absorption area and increase the ratio of the chip sidewall / chip surface area, thereby reducing the light absorption efficiency and increasing the dark current. Therefore, sidewall recombination is reduced. During the chip manufacturing process, the quantum wells at the sidewall edges will be damaged, and the size effect further exacerbates this. With the continuous advancement of Micro-LED full-color displays, these problems have become pain points and difficulties in technological progress. To solve these technical problems, we need to propose an effective method to improve these defects. Summary of the Invention

[0003] The purpose of the present invention is to provide a Micro-LED chip and a manufacturing method thereof, which can repair the damaged quantum wells, reduce the adverse effects brought by the size effect of the Micro-LED chip, and thereby improve the internal quantum efficiency and external quantum efficiency of the Micro-LED chip while maintaining a high manufacturing efficiency.

[0004] The purpose of the present invention is achieved by the following technical solutions:

[0005] A manufacturing method of a Micro-LED chip includes:

[0006] Providing a stacked structure, the stacked structure includes a substrate, a first nitride layer, a multi-quantum well layer, and a second nitride layer stacked in sequence from bottom to top, wherein the first nitride layer is an N-type nitride layer, and the second nitride layer is a P-type nitride layer; or the first nitride layer is a P-type nitride layer, and the second nitride layer is an N-type nitride layer;

[0007] Using a first dry etching process to remove a part of the second nitride layer and a part of the multi-quantum well layer on the stacked structure, exposing the first nitride layer, and forming an etching channel and a plurality of mesa surfaces;

[0008] Using a second dry etching process to repair quantum well damage on the sidewalls of the etched trench, the etching power of the second dry etching process being less than the etching power of the first dry etching process;

[0009] A second electrode is formed on the upper surface of the mesa, the second electrode being electrically connected to the second nitride layer; and a first electrode is formed at the bottom of the etched trench, the first electrode being electrically connected to the first nitride layer.

[0010] Preferably, in the first dry etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 280-520 sccm, the Cl2 gas flow rate is 12-28 sccm, and the etching power is 200-300 W;

[0011] In the second dry etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 70-130 sccm, the Cl2 gas flow rate is 3-7 sccm, and the etching power is 17-23W.

[0012] Preferably, removing a portion of the second nitride layer and a portion of the multi-quantum well layer on the stacked structure by a first dry etching process includes:

[0013] First, a patterned first mask layer is formed on the upper surface of the stacked structure, and a first dry etching process is used to remove a portion of the second nitride layer and a portion of the multi-quantum well layer on the stacked structure to form an etched channel and a plurality of mesas, and then the first mask layer is removed;

[0014] A second dry etching process is used to repair quantum well damage on the sidewalls of the etched trench, comprising:

[0015] First, a thermal expansion layer is formed on the upper surface of the mesa after the first mask layer is removed, and then a patterned second mask layer is formed on the thermal expansion layer and at the bottom of the etching channel. The stacked structure is heated to cause the portion of the second mask layer on the mesa near the edge of the etching channel to warp upward. A second dry etching process is used to repair the quantum well damage on the sidewall of the etching channel, and then the thermal expansion layer and the second mask layer are removed.

[0016] Preferably, the manufacturing method also includes: after forming the second electrode and the first electrode, forming a first passivation layer, the first passivation layer covering the upper surface of the table not covered by the second electrode, the partial surface of the second electrode, the side walls of the etching channel, the bottom of the etching channel not covered by the first electrode, the first nitride layer, and the partial surface of the first electrode.

[0017] Preferably, the first passivation layer includes a first insulating layer and a first protective layer stacked in sequence. The first protective layer covers a part of the first insulating layer. The first insulating layer is a silicon nitride layer or a silicon oxide layer, and the first protective layer includes a Cr layer, an Al layer, and an Au layer stacked in sequence;

[0018] The thermal expansion layer is a Ni layer.

[0019] Preferably, a first dry etching process is used to remove a part of the second nitride layer and a part of the multiple quantum well layer on the stacked structure, including:

[0020] First, a patterned second passivation layer and a patterned first mask layer are sequentially formed on the upper surface of the stacked structure. The first mask layer corresponds to the position of the second passivation layer and covers the second passivation layer. The second passivation layer includes a thermal expansion layer. A first dry etching process is used to remove a part of the second nitride layer and a part of the multiple quantum well layer on the stacked structure, forming an etching channel and a plurality of mesa;

[0021] A second dry etching process is used to repair the quantum well damage on the sidewall of the etching channel, including:

[0022] First, a patterned second mask layer is formed at the bottom of the etching channel, and then the stacked structure is heated to make a part of the first mask layer near the edge of the etching channel on the mesa warp upward. A second dry etching process is used to repair the quantum well damage on the sidewall of the etching channel, and then the second mask layer is removed.

[0023] Preferably, the manufacturing method further includes: after forming the second electrode and the first electrode, forming a third passivation layer, and the third passivation layer covers the sidewall of the etching channel, the first nitride layer on the bottom of the etching channel not covered by the first electrode, and a part of the surface of the first electrode.

[0024] Preferably, the second passivation layer includes a second insulating layer and a second protective layer stacked in sequence. The second protective layer covers a part of the second insulating layer. The second insulating layer is a silicon nitride layer or a silicon oxide layer, and the second protective layer includes a Cr layer, an Al layer, a Ni layer, and an Au layer stacked in sequence. The thermal expansion layer is the Ni layer;

[0025] The third passivation layer includes a third insulating layer and a third protective layer stacked in sequence. The third protective layer covers a part of the third insulating layer. The third insulating layer is a silicon nitride layer or a silicon oxide layer, and the third protective layer includes a Cr layer, an Al layer, and an Au layer stacked in sequence.

[0026] Preferably, the temperature for heating the stacked structure is 352 - 362 °C.

[0027] Preferably, after repairing the damage of the quantum well on the sidewall of the etching channel by using a second dry etching process, the etching channel forms a trapezoidal groove structure that is narrow at the top and wide at the bottom.

[0028] Preferably, the stacked structure further includes: a buffer layer and a current spreading layer, the buffer layer is located between the substrate and the first nitride layer, and the current spreading layer is located on the second nitride layer;

[0029] The first dry etching process further includes removing a part of the current spreading layer on the stacked structure.

[0030] A Micro-LED chip is obtained by the manufacturing method described in any one of the above.

[0031] Compared with the prior art, the beneficial effects of the present invention at least include:

[0032] The etching power of the second dry etching process is less than that of the first dry etching process. The first dry etching process ensures the etching efficiency, and the second dry etching process repairs the damage of the quantum well on the sidewall of the etching channel, which can reduce the adverse effects brought by the size effect of the Micro-LED, thereby improving the internal quantum efficiency and external quantum efficiency of the Micro-LED. Description of the Drawings

[0033] Figure 1 is a flowchart of the preparation method of the Micro-LED chip according to the embodiment of the present invention.

[0034] Figures 2a to 2e is a schematic cross-sectional structure diagram of the Micro-LED chip in Embodiment 1 of the present invention in steps.

[0035] Figure 3 is a schematic diagram of the thermal expansion layer in the embodiment of the present invention causing the mask layer to warp.

[0036] Figure 4 is a schematic diagram of Ga and N in the multi-quantum well layer in the embodiment of the present invention breaking to form dangling bonds.

[0037] Figure 5 is a schematic cross-sectional structure diagram of the Micro-LED chip in Embodiment 2 of the present invention.

[0038] Figure 6 is a schematic diagram of the linear expansion coefficient curve of nickel in the embodiment of the present invention.

[0039] In the figure: 100, a stacked structure; 101, a substrate; 102, a buffer layer; 103, a first nitride layer; 104, a multi-quantum well layer; 105, a second nitride layer; 106, an etching channel; 107, a current spreading layer; 108, a first electrode; 109, a second electrode; 110, a first passivation layer; 111, a first insulating layer; 112, a first protective layer; 120, a second passivation layer; 121, a second insulating layer; 122, a second protective layer; 130, a third passivation layer; 131, a third insulating layer; 132, a third protective layer; 140, a nano-rough layer; 150, a thermal expansion layer; 160, a second mask layer. Detailed implementation manners

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted.

[0041] The words expressing positions and directions described in the present invention are illustrative with reference to the drawings, but can be changed as needed, and all such changes are included in the protection scope of the present invention.

[0042] Example 1

[0043] Referring to Figure 1 and Figures 2a-2e , the method for preparing a Micro-LED chip provided by the present invention includes the following steps S101-S104.

[0044] Step S101: Provide a stacked structure 100.

[0045] As Figure 2aAs shown, the stacked structure 100 includes a substrate 101, a first nitride layer 103, a multiple quantum well layer 104, and a second nitride layer 105 stacked from bottom to top. The stacked structure 100 can be used to form multiple Micro-LED chip units. The stacked structure 100 can be directly purchased or prepared by using existing technologies, which will not be elaborated here. As a specific embodiment, the substrate 101 can be made of materials such as sapphire, silicon, gallium nitride, or silicon carbide. In this embodiment, the substrate 101 is preferably sapphire. The first nitride layer 103 is located on the substrate 101, the multiple quantum well layer 104 is located on the first nitride layer 103, and the second nitride layer 105 is located on the multiple quantum well layer 104. The multiple quantum well layer 104 is preferably made of a gallium nitride-based material and is used for carrier recombination and light emission. When the first nitride layer 103 is an N-type nitride layer, the second nitride layer 105 is a P-type nitride layer; when the first nitride layer 103 is a P-type nitride layer, the second nitride layer 105 is an N-type nitride layer. In this embodiment, the first nitride layer 103 is an N-type nitride layer, preferably an N-type gallium nitride layer, and the second nitride layer 105 is a P-type nitride layer, preferably a P-type gallium nitride layer.

[0046] Step S102: Use a first dry etching process to remove part of the second nitride layer 105 and part of the multiple quantum well layer 104 on the stacked structure 100, expose the first nitride layer 103, and form an etching channel 106 and multiple mesa structures.

[0047] Specifically, as Figure 2bAs shown, step S102 may specifically include: forming a photoresist layer on the surface of the stacked structure 100, performing exposure and development on the photoresist layer to form a patterned first mask layer (not shown), and the photoresist may be a positive photoresist or a negative photoresist; using a first dry etching process to etch the stacked structure 100, removing a part of the second nitride layer 105 and a part of the multiple quantum well layer 104 on the stacked structure 100, exposing the first nitride layer 103, and forming an etching channel 106 and a plurality of mesa structures; the first dry etching process may adopt a high-power etching process to improve the etching rate. As a preferred method, in the first dry etching process, the etching gases are BCl3 and Cl2, the flow rate of the BCl3 gas is 280 - 520 sccm, the flow rate of the Cl2 gas is 12 - 28 sccm, and the etching power is 200 - 300 W. As an example, the flow rate of the BCl3 gas is 300 sccm, the flow rate of the Cl2 gas is 15 sccm, and the etching power is 200 W; then, the remaining first mask layer is removed with a developer, the residual photoresist is removed by O2 plasma, and ultrasonic cleaning is performed with an ethanol solution to obtain a plurality of mesa structures. Each mesa structure includes a multiple quantum well layer 104 and a second nitride layer 105 stacked from bottom to top. Each mesa structure may correspond to a Micro-LED chip unit. The number of mesa structures may be set according to actual needs, and the size of each mesa structure and the spacing between adjacent mesa structures may also be set according to actual needs.

[0048] Step S103: Use a second dry etching process to repair the damage to the quantum wells on the sidewalls of the etching channel 106, and the etching power of the second dry etching process is less than the etching power of the first dry etching process.

[0049] Specifically, as Figure 4As shown, the damaged quantum well is, for example, the formation of bonding damage due to the breakage of Ga and N in the multi-quantum well layer 104 on the sidewall of the etching channel 106 during the formation of the N region, resulting in the appearance of dangling bonds. Step S103 may specifically include: forming a photoresist layer on the surface of the stacked structure 100, exposing and developing the photoresist layer to form a patterned second mask layer 160, where the photoresist can be a positive photoresist or a negative photoresist; using a second dry etching process to etch the stacked structure 100 to remove part of the second nitride layer 105 and part of the multi-quantum well layer 104 on the stacked structure 100. Since the etching power of the second dry etching process is less than that of the first dry etching process, it can not only effectively remove the quantum well damage generated by the first dry etching process, but also will not generate secondary quantum well damage on the sidewall of the etching channel 106. In addition, the second dry etching process using low-power dry etching can stably and effectively etch a regular crystal surface morphology, overcome the defect of poor uniformity of anisotropic etching of the crystal during the wet etching process, and avoid the drastic change in the etching morphology of the micro-crystals, which affects the overall luminous efficiency of the micro-chip. As a preferred method, in the second dry etching process, the etching gases are BCl3 and Cl2, the flow rate of the BCl3 gas is 70 - 130 sccm, the flow rate of the Cl2 gas is 3 - 7 sccm, and the etching power is 17 - 23 W. As an example, the flow rate of the BCl3 gas is 100 sccm, the flow rate of the Cl2 gas is 5 sccm, and the etching power is 20 W.

[0050] The repaired Micro-LED chip can alleviate the adverse effects brought by the size effect, improve that the reduction of the chip size will reduce the light absorption area and increase the ratio of the chip sidewall / chip surface area, thereby improving the light absorption efficiency and reducing the dark current, increasing the sidewall recombination per unit area, and improving the quantum recombination efficiency.

[0051] As a preferred method, step S103 includes: first forming a thermal expansion layer 150 on the upper surface of the mesa after removing the first mask layer. The thermal expansion layer 150 can be formed by a deposition method, and the thickness of the thermal expansion layer 150 is 30 - 80 nm. The thermal expansion layer 150 can expand when heated; then forming a second mask layer 160 on the thermal expansion layer 150 and at the bottom of the etching channel 106, and the second mask layer 160 covers the thermal expansion layer 150 and the bottom of the etching channel 106; as Figure 3As shown, the stacked structure 100 is then heated to cause a portion of the second mask layer 160 on the mesa near the edge of the etching channel 106 to warp upward. After the warping, the warping height of the portion of the second mask layer 160 can gradually decrease from the edge of the etching channel 106 toward the center line of the mesa. The thermal expansion layer 150 is made of a material that is more easily expanded than the second mask layer 160 and other layers after being heated. The temperature of the heated stacked structure 100 is related to the material of the thermal expansion layer 150. After the portion of the second mask layer 160 is warped upward, a second dry etching process is then used to repair the quantum well damage on the sidewall of the etching channel 106, as shown in FIG. Figure 2c As shown, a portion of the second nitride layer 105 and a portion of the multi-quantum well layer 104 on the stacked structure 100 are removed to remove the damaged quantum wells, and, as shown in FIG. Figure 3 As shown, because the portion of the second mask layer 160 near the edge of the etched channel 106 is tilted upward, the plasma during the second dry etching process can perform tilted etching in the direction of the arrow, forming a trapezoidal groove structure with a narrow top and wide bottom in the etched channel 106, and the sidewalls of the etched channel 106 are sloped. The sloped sidewalls of the etched channel 106 can enhance the light extraction efficiency of the sidewall light reflected onto the vertical surface, effectively improving the quantum efficiency of the Micro-LED chip.

[0052] As a preferred embodiment, the thermal expansion layer 150 is a nickel layer, and the temperature of the heated stacked structure 100 is 352-362° C. Nickel is a ferromagnetic metal, such as Figure 6 As shown in the linear expansion coefficient curve of nickel, when the temperature rises to near the Curie point (Tc), a ferromagnetic-paramagnetic transition occurs. At this time, the thermal expansion coefficient will show obvious anomalies, that is, a λ-shaped expansion peak appears with the apex at Tc. The experimental value of the Curie point Tc of nickel is in the range of 352-362°C. By using a pure nickel layer as the thermal expansion layer 150 and setting the temperature of the heated stack structure 100 to 352-362°C, the thermal expansion layer 150 can be rapidly heated and expanded at this relatively low temperature, thereby causing the portion of the second mask layer 160 on the table near the edge of the etched channel 106 to warp upward. In addition, the above heating temperature is relatively low and will not affect the Micro-LED chip.

[0053] Then, the thermal expansion layer 150 is dissolved by wet etching or dry etching, and the remaining second mask layer 160 is removed by a developer. The residual glue is removed by O2 plasma, and ultrasonic cleaning is performed with an ethanol solution.

[0054] Step S104 : forming a second electrode 109 on the upper surface of the mesa, the second electrode 109 electrically connected to the second nitride layer 105 , and forming a first electrode 108 at the bottom of the etched trench 106 , the first electrode 108 electrically connected to the first nitride layer 103 .

[0055] Specifically, ifFigure 2d As shown, a second electrode 109 is formed on the second nitride layer 105 by means of electron beam evaporation, plasma sputtering, or thermal evaporation, and a first electrode 108 is formed on the first nitride layer 103 at the bottom of the etched channel 106. The second electrode 109 and the first electrode 108 are used for die bonding and wire bonding. When the first nitride layer 103 is an N-type nitride layer and the second nitride layer 105 is a P-type nitride layer, the first electrode 108 is an N-type electrode and the second electrode 109 is a P-type electrode; when the first nitride layer 103 is a P-type nitride layer and the second nitride layer 105 is an N-type nitride layer, the first electrode 108 is a P-type electrode and the second electrode 109 is an N-type electrode.

[0056] As a preferred embodiment, the second electrode 109 and the first electrode 108 include an ohmic contact layer, a reflective layer, an adhesive transition layer, and a welding layer arranged in sequence from bottom to top. The ohmic contact layer is a Cr layer with a thickness of 50 - 100 nm, and the Cr layer serves to improve the ohmic contact between the electrode and the N-type GaN layer or the P-type GaN layer. The reflective layer is an Al layer with a thickness of 50 - 100 nm. The adhesive transition layer is a Ti layer, an Ni layer, and a Pt layer arranged in sequence from bottom to top, and the thicknesses of the Ti layer, the Ni layer, and the Pt layer are each 10 - 50 nm. The adhesive transition layer ensures better adhesion of the entire electrode structure and prevents the second electrode 109 and the first electrode 108 from peeling off the stacked structure 100. The thickness of the Au layer is 1500 - 2500 nm, and the Au layer is used for welding. It should be noted that the first electrode 108 and the second electrode 109 can be formed before step S103 or after step S103.

[0057] As a preferred embodiment, after the second electrode 109 and the first electrode 108 are formed, a first passivation layer 110 is formed on the stacked structure 100. The first passivation layer 110 covers the upper surface of the mesa that is not covered by the second electrode 109, a part of the surface of the second electrode 109, the sidewalls of the etched channel 106, the first nitride layer 103 at the bottom of the etched channel 106 that is not covered by the first electrode 108, and a part of the surface of the first electrode 108.

[0058] Specifically, a first passivation layer 110 is formed on the stack structure 100. The first passivation layer 110 can be deposited by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). In this embodiment, atomic layer deposition (ALD) is preferably used for deposition. The first passivation layer 110 includes a first insulating layer 111 and a first protective layer 112 stacked in sequence. The first protective layer 112 covers a part of the first insulating layer 111. The first insulating layer 111 is a silicon nitride layer or a silicon oxide layer. The first protective layer 112 includes a Cr layer, an Al layer, and an Au layer stacked in sequence. The first insulating layer 111 separates the first protective layer 112 from the second electrode 109 and the first electrode 108, which can prevent the first protective layer 112 from connecting the second electrode 109 and the first electrode 108 to cause a short circuit. The first insulating layer 111 can also separate the first protective layer 112 from the second nitride layer 105 and the first nitride layer 103. The Cr layer of the first protective layer 112 can make the adhesion between the Al layer and the first insulating layer 111 better, preventing the first insulating layer 111 from peeling off from the first protective layer 112. The Al layer can reflect the light reflected back by the Micro-LED chip again, improving the light emitting efficiency of the Micro-LED chip. The Au layer has better coating properties and oxidation resistance, which can better protect the Micro-LED chip structure, facilitating the improvement of the reliability and thermal stability of the Micro-LED chip during use.

[0059] As a preferred method, a nano-rough layer 140 is formed on the first passivation layer 110 by laser irradiation. After surface roughening, the root mean square roughness of the surface is 15 - 20 nm. Since the refractive index of Au is usually 1.35 and the refractive index of air is 1.0, in this pair of media, Au is an optically dense medium and air is an optically sparse medium. According to Snell's law, a part of the light rays with an incident angle less than the critical angle θ can be emitted into the air, but the light rays with an incident angle greater than θ will undergo total internal reflection when incident on this interface. This results in many large-angle light rays in the light emitted from the Micro-LED chip, and these light rays cannot be emitted into the air due to total internal reflection, leading to a decrease in the light emitting efficiency of the Micro-LED chip. Surface roughening can significantly weaken the occurrence of total internal reflection, thereby improving the light emitting efficiency.

[0060] As a preferred method, as Figure 2eAs shown, the stacked structure 100 in step S101 further includes a buffer layer 102 and a current spreading layer 107. The buffer layer 102 is located between the substrate 101 and the first nitride layer 103. By providing the buffer layer 102, the lattice matching and crystal quality between the first nitride layer 103 and the substrate 101 are improved. The buffer layer 102 can be an aluminum nitride layer. The current spreading layer 107 is located on the second nitride layer 105. The current spreading layer 107 can be formed on the second nitride layer 105 by means of electron beam evaporation, plasma sputtering, or thermal evaporation. The current spreading layer 107 can be a single-layer metal layer, a multi-layer metal layer, or an ITO layer, etc. The current spreading layer 107 is preferably any one of a nickel / gold alloy, a metal mainly composed of aluminum, and ITO. As a preferred mode, the current spreading layer 107 is selected as ITO. ITO has good electrical conductivity and light transmittance, which is beneficial to the optoelectronic performance of the chip. When setting the current spreading layer 107, the second electrode 109 in step S104 is formed on the current spreading layer 107.

[0061] Finally, the stacked structure 100 is cut by laser or mechanically, and then tested and sorted to obtain Micro-LED chip units. The cutting can be carried out by known methods and will not be elaborated here.

[0062] Embodiment 2

[0063] Referring to Figure 5 , another method for preparing a Micro-LED chip provided by the present invention includes the following steps S201 - S204.

[0064] Step S201: Provide a stacked structure 100, which includes a substrate 101, a first nitride layer 103, a multi-quantum well layer 104, and a second nitride layer 105 stacked from bottom to top.

[0065] The stacked structure 100 in step S201 can be the same as or similar to the stacked structure 100 in step S101 of Embodiment 1 and will not be elaborated here.

[0066] Step S202: Use a first dry etching process to remove a part of the second nitride layer 105 and a part of the multi-quantum well layer 104 on the stacked structure 100, exposing the first nitride layer 103, and forming an etching channel 106 and a plurality of mesa.

[0067] The difference between step S202 and step S102 of embodiment 1 is that a second passivation layer 120 is formed on the stacked structure 100. The second passivation layer 120 can be deposited by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). In this embodiment, atomic layer deposition (ALD) is preferably used. The second passivation layer 120 includes a second insulating layer 121 and a second protective layer 122 stacked in sequence. The second protective layer 122 covers the second insulating layer 121. The second insulating layer 121 is a silicon nitride layer or a silicon oxide layer. The second protective layer 122 includes a Cr layer, an Al layer, a Ni layer, and an Au layer stacked in sequence. The Cr layer of the second protective layer 122 can improve the adhesion between the Al layer and the second insulating layer 121, preventing the second insulating layer 121 from peeling off from the second protective layer 122. The Ni layer serves as the thermal expansion layer 150. The Al layer can reflect the light reflected back by the Micro-LED chip again, thereby improving the luminous efficiency of the Micro-LED chip. The Au layer has better coating and oxidation resistance, which can better protect the Micro-LED chip structure, and is conducive to improving the reliability and thermal stability of the Micro-LED chip.

[0068] A patterned first mask layer (not shown) is formed on the second passivation layer 120. The first mask layer corresponds to the position of the second passivation layer 120 and covers the second passivation layer 120. A first dry etching process is used to remove part of the second nitride layer 105 and part of the multi-quantum well layer 104 on the stacked structure 100 to form an etched channel 106 and multiple mesas.

[0069] Step S203: using a second dry etching process to repair quantum well damage on the sidewall of the etched channel 106, wherein the etching power of the second dry etching process is less than the etching power of the first dry etching process.

[0070] Step S203 differs from step S103 in Example 1 in that a patterned second mask layer 160 is first formed at the bottom of the etched trench 106. The stacked structure 100 is then heated, causing the Ni layer in the second passivation layer 120 to expand upon heating, causing the portion of the first mask layer on the mesa near the edge of the etched trench 106 to warp upward. A second dry etching process is then performed to repair quantum well damage on the sidewalls of the etched trench 106. Part of the second nitride layer 105 and part of the multi-quantum well layer 104 on the stacked structure 100 are removed, removing the damaged quantum wells. The etched trench 106 is then formed into a trapezoidal groove structure that is narrow at the top and wide at the bottom, with the sidewalls of the etched trench 106 being sloped. The sloped sidewalls of the etched trench 106 enhance the light extraction efficiency of light reflected from the sidewalls into vertical surfaces, effectively improving the quantum efficiency of the Micro-LED chip.

[0071] Afterwards, a developer is used to remove the remaining first mask layer and the photoresist of the second mask layer 160. Meanwhile, the second passivation layer 120 is retained, and the residual photoresist is removed by O2 plasma and ultrasonically cleaned with an ethanol solution.

[0072] Step S204: A second electrode 109 is formed on the upper surface of the mesa. The second electrode 109 is electrically connected to the second nitride layer 105. A first electrode 108 is formed at the bottom of the etched channel 106. The first electrode 108 is electrically connected to the first nitride layer 103.

[0073] The difference between step S204 and step S104 in Embodiment 1 is that after forming the second electrode 109 and the first electrode 108, a third passivation layer 130 is formed. The third passivation layer 130 covers the sidewalls of the etched channel 106, the first nitride layer 103 on the bottom of the etched channel 106 that is not covered by the first electrode 108, and a partial surface of the first electrode 108. Specifically, the third passivation layer 130 can be deposited by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). In this embodiment, atomic layer deposition (ALD) is preferably used for deposition. The third passivation layer 130 includes a third insulating layer 131 and a third protective layer 132 stacked in sequence. The third protective layer 132 covers the third insulating layer 131. The third insulating layer 131 is a silicon nitride layer or a silicon oxide layer. The third protective layer 132 includes a Cr layer, an Al layer, and an Au layer stacked in sequence. The Cr layer of the third protective layer 132 can make the adhesion between the Al layer and the third insulating layer 131 better, preventing the third insulating layer 131 from peeling off from the third protective layer 132. The Al layer can reflect the light reflected back by the Micro-LED chip again, improving the light emission efficiency of the Micro-LED chip. The Au layer has better coating properties and oxidation resistance, which can better protect the structure of the Micro-LED chip, facilitating improving the reliability and thermal stability of the Micro-LED chip during use.

[0074] As a preferred method, the method of forming the nano-rough layer 140 on the second passivation layer 120 and the third passivation layer 130 is the same as or similar to the method of forming the nano-rough layer 140 on the third passivation layer 130 in Embodiment 1, and will not be elaborated here.

[0075] As a preferred method, the stack structure 100 in step S201 further includes a buffer layer 102 and a current spreading layer 107, which are the same as or similar to the buffer layer 102 and the current spreading layer 107 in Embodiment 1, and will not be elaborated here.

[0076] Finally, the laminated structure 100 is cut using a laser or mechanically, and the Micro-LED chip units are obtained through testing and sorting. The cutting can be performed by known methods, which will not be elaborated herein.

[0077] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and purposes of the present invention. All such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A manufacturing method of a Micro-LED chip, characterized in that, Including: Providing a stacked structure, which includes a substrate, a first nitride layer, a multi-quantum well layer, and a second nitride layer stacked in sequence from bottom to top. Among them, the first nitride layer is an N-type nitride layer, and the second nitride layer is a P-type nitride layer; or, the first nitride layer is a P-type nitride layer, and the second nitride layer is an N-type nitride layer; Forming a patterned thermal expansion layer and a patterned mask layer in sequence on the upper surface of the stacked structure; Using a first dry etching process to remove part of the second nitride layer and part of the multi-quantum well layer on the stacked structure, exposing the first nitride layer, and forming an etching channel and a plurality of mesa; Heating the stacked structure to make a part of the mask layer near the edge of the etching channel on the mesa tilt upward; Using a second dry etching process to repair the quantum well damage on the sidewall of the etching channel, and the etching power of the second dry etching process is less than the etching power of the first dry etching process; Removing the mask layer, or removing the thermal expansion layer and the patterned mask layer; Forming a second electrode on the upper surface of the mesa, the second electrode is electrically connected to the second nitride layer, and forming a first electrode at the bottom of the etching channel, the first electrode is electrically connected to the first nitride layer.

2. The manufacturing method of a Micro-LED chip according to claim 1, wherein In the first dry etching process, the etching gases are BCl3 and Cl2, the flow rate of BCl3 gas is 280 - 520 sccm, the flow rate of Cl2 gas is 12 - 28 sccm, and the etching power is 200 - 300 W; In the second dry etching process, the etching gases are BCl3 and Cl2, the flow rate of BCl3 gas is 70 - 130 sccm, the flow rate of Cl2 gas is 3 - 7 sccm, and the etching power is 17 - 23 W.

3. The manufacturing method of a Micro-LED chip according to claim 1, characterized in that, The mask layer is a second mask layer, and the method specifically includes: First forming a patterned first mask layer on the upper surface of the stacked structure, using a first dry etching process to remove part of the second nitride layer and part of the multi-quantum well layer on the stacked structure, forming an etching channel and a plurality of mesa, and then removing the first mask layer; First forming a thermal expansion layer on the upper surface of the mesa after removing the first mask layer, then forming a patterned second mask layer on the thermal expansion layer and at the bottom of the etching channel, heating the stacked structure to make a part of the second mask layer near the edge of the etching channel on the mesa tilt upward, using a second dry etching process to repair the quantum well damage on the sidewall of the etching channel, and then removing the thermal expansion layer and the second mask layer.

4. The manufacturing method of a Micro-LED chip according to claim 3, characterized in that The manufacturing method further includes: after forming the second electrode and the first electrode, forming a first passivation layer, and the first passivation layer covers the upper surface of the mesa not covered by the second electrode, part of the surface of the second electrode, the sidewall of the etching channel, the first nitride layer on the bottom of the etching channel not covered by the first electrode, and part of the surface of the first electrode.

5. The manufacturing method of a Micro-LED chip according to claim 4, wherein, The first passivation layer includes a first insulating layer and a first protective layer stacked in sequence. The first protective layer covers a part of the first insulating layer. The first insulating layer is a silicon nitride layer or a silicon oxide layer. The first protective layer includes a Cr layer, an Al layer, and an Au layer stacked in sequence; The thermal expansion layer is a Ni layer.

6. The manufacturing method of a Micro-LED chip as described in claim 1, wherein The mask layer is a first mask layer. The method specifically includes: First, a patterned second passivation layer and a patterned first mask layer are sequentially formed on the upper surface of the stacked structure. The first mask layer corresponds to the second passivation layer in position and covers the second passivation layer. The second passivation layer contains a thermal expansion layer. A first dry etching process is used to remove a part of the second nitride layer and a part of the multiple quantum well layer on the stacked structure to form an etching channel and a plurality of mesa; First, a patterned second mask layer is formed at the bottom of the etching channel, and then the stacked structure is heated to make a part of the first mask layer near the edge of the etching channel on the mesa warp upward. A second dry etching process is used to repair the quantum well damage on the sidewall of the etching channel, and then the first mask layer and the second mask layer are removed.

7. The manufacturing method of a Micro-LED chip according to claim 6, wherein The manufacturing method further includes: after forming the second electrode and the first electrode, a third passivation layer is formed. The third passivation layer covers the sidewall of the etching channel, the first nitride layer on the bottom of the etching channel not covered by the first electrode, and a part of the surface of the first electrode.

8. The manufacturing method of a Micro-LED chip according to claim 7, characterized in that, The second passivation layer includes a second insulating layer and a second protective layer stacked in sequence. The second protective layer covers a part of the second insulating layer. The second insulating layer is a silicon nitride layer or a silicon oxide layer. The second protective layer includes a Cr layer, an Al layer, a Ni layer, and an Au layer stacked in sequence. The thermal expansion layer is the Ni layer; The third passivation layer includes a third insulating layer and a third protective layer stacked in sequence. The third protective layer covers a part of the third insulating layer. The third insulating layer is a silicon nitride layer or a silicon oxide layer. The third protective layer includes a Cr layer, an Al layer, and an Au layer stacked in sequence.

9. The manufacturing method of a Micro-LED chip according to claim 5 or 8, characterized in that The temperature for heating the stacked structure is 352 - 362 °C.

10. The manufacturing method of a Micro-LED chip according to claim 3 or 6, characterized in that, After using the second dry etching process to repair the quantum well damage on the sidewall of the etching channel, the etching channel forms a trapezoidal groove structure that is narrow at the top and wide at the bottom.

11. The manufacturing method of a Micro-LED chip according to claim 1, characterized in that, The stacked structure further includes: a buffer layer and a current spreading layer. The buffer layer is located between the substrate and the first nitride layer, and the current spreading layer is located on the second nitride layer; The first dry etching process further includes removing a part of the current spreading layer on the stacked structure.

12. A Micro-LED chip, characterized in that, Obtained according to any one of claims 1 - 11.

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