Digital-to-analog conversion circuit with signal correction mechanism and digital-to-analog conversion method

Abstract

The present application provides a digital-to-analog conversion method with a signal correction mechanism, which is applied to a digital-to-analog conversion circuit including a thermometer-controlled current source generating an output analog signal according to a total current and a control circuit. The digital-to-analog conversion method includes: making the control circuit acquire current deviation values of the current source; making the control circuit sort the current deviation values to generate an opening sequence, wherein the current deviation values are divided into current deviation value groups according to the opening sequence, and the current deviation value groups are opposite in sign to each other, so as to cancel each other out when accumulated according to the opening sequence, and maintain the total absolute value of the total current deviation value not greater than half of the maximum absolute value among the current deviation values; and making the control circuit control the current source to open according to the opening sequence according to a thermometer code included in an input digital signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a digital-to-analog conversion technique, and in particular, to a digital-to-analog conversion circuit and method with a signal correction mechanism. BACKGROUND

[0002] A digital-to-analog conversion circuit is an important element for converting a signal from a digital form to an analog form. The digital-to-analog conversion circuit can multiply a corresponding conversion gain value according to different digital codes, and then generate analog signals of different sizes.

[0003] However, for a current output type digital-to-analog conversion circuit, process drift will cause non-ideal deviation of the output amplitude and shape. The deviation of the amplitude will seriously affect the system performance. SUMMARY

[0004] In view of the problems of the prior art, one object of the present application is to provide a digital-to-analog conversion circuit and method with a signal correction mechanism to improve the prior art.

[0005] The present application includes a digital-to-analog conversion circuit with a signal correction mechanism, comprising a thermometer control type current source and a control circuit. The current source generates an output analog signal according to a total current. The control circuit obtains current deviation values corresponding to the current source, and sorts the current deviation values to generate an opening sequence, wherein the current deviation values are divided into a plurality of current deviation value groups according to the opening sequence, and each two adjacent current deviation value groups are opposite in sign to each other to stagger and cancel each other when accumulated according to the opening sequence, thereby maintaining the total absolute value of the total current deviation value of the current deviation values not greater than half of the maximum absolute value among the current deviation values, and controlling the current source to open according to a plurality of thermometer codes included in an input digital signal according to the opening sequence.

[0006] The present application also includes a digital-to-analog conversion method with a signal correction mechanism, which is applied to a digital-to-analog conversion circuit including a plurality of thermometer control type current sources generating output analog signals according to a total current and a control circuit. The digital-to-analog conversion method includes: causing the control circuit to obtain a plurality of current deviation values corresponding to the current sources; causing the control circuit to sort the current deviation values to generate an opening sequence, wherein the current deviation values are divided into a plurality of current deviation value groups according to the opening sequence, and each two adjacent current deviation value groups are opposite in sign to each other to stagger and cancel each other when accumulated according to the opening sequence, thereby maintaining the total absolute value of the total current deviation value of the current deviation values not greater than half of the maximum absolute value among the current deviation values; and causing the control circuit to control the current source to open according to a plurality of thermometer codes included in an input digital signal according to the opening sequence.

[0007] The features, implementations and effects of the present application are described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of a digital-to-analog conversion device with a signal correction mechanism according to an embodiment of the present application;

[0009] Figure 2 A circuit diagram of a digital-to-analog conversion circuit according to an embodiment of the present application;

[0010] Figure 3 A flowchart of a digital-to-analog conversion method with a signal correction mechanism according to an embodiment of the present application;

[0011] Figure 4 A flowchart of a sorting procedure according to an embodiment of the present application; and

[0012] Figure 5 A flowchart of a selection procedure according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] An object of the present application is to provide a digital-to-analog conversion circuit and method with a signal correction mechanism, by performing a sorting procedure to generate an opening sequence, so that current deviation values among current sources cancel each other out when the current sources are turned on in the opening sequence, thereby achieving better linearity.

[0014] Figure 1 A block diagram of a digital-to-analog conversion device 100 with a signal correction mechanism according to an embodiment of the present application. The digital-to-analog conversion device 100 includes a digital-to-analog conversion circuit 110, an echo transmission circuit 120, a correction circuit 130, an echo cancellation circuit 140, an error calculation circuit 150, an inverted error calculation circuit 160, a correction parameter operation circuit 170, and an echo cancellation digital-to-analog conversion circuit 180.

[0015] The digital-to-analog conversion circuit 110 receives an input digital signal IS from a signal source SS to generate an output analog signal OAS. The signal source SS can be, for example, a transmission circuit (TX) in a communication system.

[0016] Figure 2 A circuit diagram of the digital-to-analog conversion circuit 110 according to an embodiment of the present application. The digital-to-analog conversion circuit 110 includes thermometer-controlled current sources CA to CO and a control circuit 200.

[0017] The input digital signal IS includes a thermometer code TC, which allows the control circuit 200 to control the operating state of each current source CA to CO to be one of a first current output state and a second current output state, to generate the output analog signal OAS according to a total current. In the first and second current output states, currents of opposite signs and equal magnitude are output, respectively.

[0018] In one embodiment, the thermometer code TC causes the control circuit 200 to control the switching circuit 210 so as to couple the current sources CA~CO to different current output paths, for example Figure 2 The solid and dashed paths are shown in one of the first and second current output states. In this embodiment, four thermometer codes are used in 16 combinations to control 15 thermometer-controlled current sources.

[0019] Operationally, as the thermometer code changes from (0000) to (1111) sequentially, the current sources CA~CO switch operation states like a thermometer, from all second current output states, to first current output states one by one according to an opening sequence, until all the current sources CA~CO are in first current output states.

[0020] In other embodiments, the digital-to-analog conversion circuit 110 can also selectively include other current sources (not shown) controlled by binary, and the input digital signal IS can include binary codes to control these current sources, so that the output analog signal OAS also includes current components of these current sources. The present application is not limited thereto.

[0021] Figure 3 A flowchart of a signal correction mechanism digital-to-analog conversion method 300 according to one embodiment of the present application is shown. The signal correction mechanism digital-to-analog conversion method 300 can be applied, for example, but not limited to Figure 2 the digital-to-analog conversion circuit 110.

[0022] In step S310, the control circuit 200 obtains the current deviation values ΔA~ΔO corresponding to the current sources CA~CO. The current deviation values ΔA~ΔO can be generated, for example, due to process offset.

[0023] In one embodiment, the current deviation values can be generated by calculating the difference between the results of transmitting the signal through the outer and inner ring paths in the digital-to-analog conversion device 100. The outer ring path transmits the output analog signal OAS through the echo transmission circuit 120 to generate the echo signal ES, and the inner ring path transmits the input digital signal IS through the correction circuit 130 and the echo cancellation circuit 140 to generate the echo cancellation signal ECS.

[0024] The error calculation circuit 150 can generate an error signal DIS according to the difference between the echo signal ES and the echo cancellation signal ECS, and perform one-dimensional inversion via the inversion error calculation circuit 160 to generate an inverted error value FD. The correction parameter operation circuit 170 can then generate an offset value according to the path delay DL of the echo cancellation circuit 140 and the inversion error calculation circuit 160, and use the inverted error value FD as the offset value. The offset value is then statistically operated to generate current deviation values ΔA~ΔO, which are fed into the control circuit 200. However, the present application is not limited thereto.

[0025] In step S320, the control circuit 200 performs a sorting procedure on the current deviation values ΔA~ΔO to generate an opening sequence. The current deviation values are divided into current deviation value groups according to the opening sequence, and the absolute values of two adjacent current deviation value groups are opposite to each other, so that they cancel each other out when accumulated according to the opening sequence, thereby maintaining the total absolute value of the total current deviation value of the current deviation values to be no more than half of the maximum absolute value among the current deviation values.

[0026] Figure 4 A flowchart of the sorting procedure 400 according to an embodiment of the present application is shown in FIG. 4. Table 1 shows the results of numerical operations performed in different rounds of the sorting procedure according to an embodiment of the present application.

[0027] Table 1

[0028]

[0029] The operation of the sorting procedure 400 will be described below in conjunction with a numerical example.

[0030] In step S410, the maximum positive value MP and the maximum negative value MN are selected from the current deviation values corresponding to the current sources that have not yet been sorted. The one with the larger absolute value is the first extreme value, and the one with the smaller absolute value is the second extreme value.

[0031] In a numerical example, the current deviation values corresponding to the current sources CA~CO are -28, -13, -5, -4, -3, -2, -1, 0, +1, +2, +3, +4, +7, +12, and +27, respectively. For the first round of the sorting procedure, the maximum positive value MP is +27 and is the second extreme value, and the maximum negative value MN is -28 and is the first extreme value.

[0032] In step S420, the intermediate absolute value MA of the first extreme value is generated.

[0033] Since the first extreme value is -28, the intermediate absolute value MA will be |-28| / 2 = 14.

[0034] In step S430, a selection procedure is performed to select at least one selected deviation value from the remaining current deviation values excluding the maximum positive value MP and the maximum negative value MN, wherein the sum of the selected deviation values is closest to the difference between the median absolute value MA and the deviation residual value INL.

[0035] Figure 5 A flowchart of the selection procedure 500 according to an embodiment of the present application is shown.

[0036] In step S510, it is determined whether one of the remaining current deviation values excluding the maximum positive value MP and the maximum negative value MN is within a deviation value range centered at a center value. The center value is preset to be a first difference between the median absolute value and the deviation residual value, and the deviation value range has maximum and minimum boundary values.

[0037] In an embodiment, the deviation value range is preset to be between +1 and -1 centered at the first difference. When the ranking procedure is initially performed, there is no deviation residual value, and the deviation residual value is 0. The first difference will be 14 - 0 = 14, the minimum boundary value of the deviation value range is 14 - 1 = 13, and the maximum boundary value is 14 + 1 = 15, and the deviation value range is represented as 13 ~ 15.

[0038] In step S520, when none of the remaining current deviation values is within the deviation value range, it is determined whether there is a remaining current deviation value greater than the maximum boundary value when the first extreme value is the maximum positive value MP, or a remaining current deviation value less than the minimum boundary value when the first extreme value is the maximum negative value MN.

[0039] In step S530, when the first extreme value is the maximum positive value MP and there is a remaining current deviation value greater than the maximum boundary value, the remaining current deviation value closest to the maximum boundary value is selected as one of the selected deviation values, and when the first extreme value is the maximum negative value MN and there is a remaining current deviation value less than the maximum boundary value, the remaining current deviation value closest to the minimum boundary value is selected as the selected deviation value.

[0040] For the first round of the ranking procedure, none of the remaining current deviation values is within the original range, and the first extreme value is the maximum negative value MN. Therefore, +12 closest to the minimum boundary value 13 will be selected as the selected deviation value.

[0041] In step S540, the minimum boundary value is subtracted from the selected deviation value to generate a modified minimum boundary value, and the maximum boundary value is subtracted from the selected deviation value to generate a modified maximum boundary value, and a modified range centered at a second difference between the center value and the selected deviation value is generated according to the modified minimum boundary value and the modified maximum boundary value as the deviation value range for re-performing the selection procedure.

[0042] For the first round of the sorting procedure, the minimum boundary value is modified to 13-12=1, the maximum boundary value is modified to 15-12=3, the second difference between the center value and the selected deviation value is 14-12=2, and the modified range is represented as 1~3.

[0043] The flow returns to step S510 to determine whether one of the remaining current deviation values is located within the new deviation value range.

[0044] In step S550, when one of the remaining current deviation values is located within the deviation value range, the one closest to the center value is selected as the selected deviation value and the selection procedure is ended.

[0045] For the first round of the sorting procedure, the current deviation value +2 is located within the adjusted deviation value range 1~3, becomes the selected deviation value, and the selection procedure is ended.

[0046] After the selection procedure is ended, the flow returns to step S440 of Figure 4 to sequentially set the current sources corresponding to the selected deviation value, the first extreme value, and the second extreme value to have an on sequence from high to low and to be lower than the on sequences of the already sorted current sources.

[0047] For the first round of the sorting procedure, the current sources CN, CJ, CA, and CO corresponding to the selected deviation value +12, +2, the first extreme value -28, and the second extreme value +27 are sequentially set to have an on sequence from high to low. Since there are no other already sorted current sources, the current sources CN, CJ, CA, and CO will have an on sequence that is high relative to other current sources.

[0048] In step S450, the current sources corresponding to the selected deviation value, the first extreme value, and the second extreme value are set as sorted.

[0049] For the first round of the sorting procedure, the current sources CN, CJ, CA, and CO are sequentially set as sorted.

[0050] In step S460, the sum of the deviation residual value, the selected deviation value, the first extreme value, and the second extreme value is set as the new deviation residual value.

[0051] For the first round of the sorting procedure, the sum of the selected deviation value +12, +2, the first extreme value -28, and the second extreme value +27, +12+2-28+27=+13, is set as the new deviation residual value.

[0052] In step S470, it is determined whether there are any current sources that have not been sorted. When there are current sources that have not been sorted, the flow returns to step S410 to continue the second round of the sorting procedure.

[0053] For the second round of the sorting procedure, step S410 selects the maximum positive value MP of +7 and the maximum negative value MN of -13 from the current bias values of the current sources CB to CI and CK to CM that have not yet been sorted. The intermediate absolute value MA generated by step S420 is |-13| / 2 = 6.5. Step S430 performs the selection procedure.

[0054] In the selection procedure, the center value is preset to be the first difference value, i.e., 6.5 - 13 = -6.5, and the bias value range is preset to be between +1 and -1 of the center value, i.e., -7.5 to -5.5. Step S510 determines whether all the current bias values except the maximum positive value MP and the maximum negative value MN are not within the bias value range centered on the center value. Step S520 determines that when the first extreme value is the maximum negative value MN, there is no current bias value smaller than the minimum boundary value.

[0055] In step S560, the minimum boundary value is subtracted by the expansion parameter to generate an expanded minimum boundary value, and the maximum boundary value is added by the expansion parameter to generate an expanded maximum boundary value, thereby generating an expanded range as the bias value range for the selection procedure.

[0056] In an embodiment, the expansion parameter is 1. Thus, for the second round of the sorting procedure, the expanded minimum boundary value is -7.5 - 1 = -8.5, and the expanded maximum boundary value is -5.5 + 1 = -4.5. The expanded range can be represented as -8.5 to -4.5.

[0057] In such a case, the flow returns to step S510 to determine whether one of the remaining current bias values is within the bias value range. In step S550, when one of the remaining current bias values is within the bias value range, the one closest to the center value is selected as the selected bias value and the selection procedure ends.

[0058] For the second round of the sorting procedure, -5 of the remaining current bias values is within the adjusted bias value range -8.5 to -4.5, becomes the selected bias value, and the selection procedure ends.

[0059] After the selection procedure ends, the flow returns to step S440 of Figure 4 to set the current sources CC, CB, and CM corresponding to the selected bias value -5, the first extreme value -13, and the second extreme value +7 to have an on sequence from high to low, and set the current sources CC, CB, and CM as sorted in step S450. Step S460 sets the sum +2 of the bias residual value +13, the selected bias value -5, the first extreme value -13, and the second extreme value +7 as a new bias residual value, and determines whether there is a current source that has not yet been sorted in step S470 to return to step S410 to continue the third round of the sorting procedure.

[0060] Similarly, for the third round of the sorting procedure, the maximum positive value MP of +4 and the second extreme value, and the maximum negative value MN of -4 and the first extreme value are generated in step S410, the intermediate absolute value MA of 2 is generated in step S420, and the selection procedure is performed in step S430. In the selection procedure, it is determined in step S510 that one of the remaining current deviation values other than the maximum positive value MP and the maximum negative value MN is in the deviation value range of -1 to +1, and the selected deviation value 0 is selected in step S550 to end the selection procedure.

[0061] After the selection procedure ends, the flow returns to Figure 4 Step S440, the current sources CH, CD, and CL corresponding to the selected deviation value 0, the first extreme value -4, and the second extreme value +4 are set to have an on sequence from high to low, the current sources CH, CD, and CL are set to be sorted in step S450, the sum +2 of the deviation residual value +2, the selected deviation value 0, the first extreme value -4, and the second extreme value +4 is made as a new deviation residual value +2 in step S460, and it is determined in step S470 that there are current sources that have not been sorted to return to step S510 to continue the fourth round of the sorting procedure.

[0062] For the fourth round of the sorting procedure, the maximum positive value MP of +3 and the second extreme value, and the maximum negative value MN of -3 and the first extreme value are generated in step S410, the intermediate absolute value MA of 1.5 is generated in step S420, and the selection procedure is performed in step S430. In the selection procedure, it is determined in step S510 that one of the remaining current deviation values other than the maximum positive value MP and the maximum negative value MN is in the deviation value range of -0.5 to +0.5, and the selected deviation value -1 is selected in step S550 to end the selection procedure.

[0063] After the selection procedure ends, the flow returns to Figure 4 Step S440, the current sources CG, CE, and CK corresponding to the selected deviation value -1, the first extreme value -3, and the second extreme value +3 are set to have an on sequence from high to low, the current sources CG, CE, and CK are set to be sorted in step S450, the sum +1 of the deviation residual value +2, the selected deviation value -1, the first extreme value -3, and the second extreme value +3 is made as a new deviation residual value +1 in step S460, and it is determined in step S470 that there are current sources that have not been sorted to return to step S510 to continue the fifth round of the sorting procedure.

[0064] For the fifth round of the sorting procedure, the maximum positive value MP of +1 and the second extreme value, and the maximum negative value MN of -2 and the first extreme value are generated in step S410, the intermediate absolute value MA of 1 is generated in step S420, and the selection procedure is performed in step S430. In an embodiment, when there are no current deviation values other than the maximum positive value MP and the maximum negative value MN, "none" is also set as a selectable object. Therefore, in the selection procedure, it is determined in step S510 that one of the remaining current deviation values other than the maximum positive value MP and the maximum negative value MN is in the deviation value range of -1 to +1, and the selected deviation value "none" that does not correspond to any current source is selected in step S550 to end the selection procedure.

[0065] After the selection procedure ends, the flow returns to Figure 4 , the current sources CF and CI corresponding to the first extreme value -2 and the second extreme value +1 are set to have a high-to-low opening order in step S440, the current sources CF and CI are set to be sorted in step S450, the sum +0 of the deviation residual value +1, the first extreme value -2, and the second extreme value +1 is made as a new deviation residual value +0 in step S460, and it is determined that there are no current sources that have not been sorted in step S470. In step S480, the sorting procedure ends.

[0066] The sorted current deviation values can be divided into multiple positive and negative current deviation value groups of (+12, +2), (-28), (+27), (-5, -13), (+7), (0), (-4), (+4), (-1, -3), (+3), (-2), and (+1) according to the positive and negative signs. Each two adjacent current deviation value groups can cancel each other when accumulated according to the opening order, and the total absolute value of the total current deviation value of the current deviation values is maintained to be not greater than half of the maximum absolute value of the current deviation values.

[0067] After the sorting procedure ends, the flow returns to Figure 3 , and the control circuit 200 is caused to control the current sources CA to CO to be turned on in the opening order according to the thermometer code included in the input digital signal IS in step S330.

[0068] In the foregoing example, the final opening order will correspond to the sorted current deviation values, and the current sources CN, CJ, CA, CO, CC, CB, CM, CH, CD, CL, CG, CE, CK, CF, and CI are sequentially turned on.

[0069] In some embodiments, the control circuit directly controls the current sources CA~CO to be turned on in the order of the physical arrangement. In such a case, with the above numerical example, the current sources CI~CO that are turned on first will continue to accumulate positive current bias values until the current sources CA~CG are turned on to offset them with negative current bias values, so that the output analog signal OAS cannot have good linearity.

[0070] On the contrary, by the above mechanism, the digital-to-analog conversion circuit and method of the present application can maintain the total absolute value of the total current bias values of the current bias values to be no more than half of the maximum absolute value of the current bias values, and have better linearity.

[0071] It should be noted that the above sorting procedure and selection procedure are only examples. In other embodiments, other sorting and selection mechanisms can be used to generate the turn-on order. The present application is not limited thereto.

[0072] In one embodiment, Figure 1 The echo cancellation digital-to-analog conversion circuit 180 included in the digital-to-analog conversion device 100 is disposed between the digital-to-analog conversion device 100 and a receiving circuit (RX) in a communication system (not shown in the figure), and generates an echo cancellation output analog signal EAS according to an input digital signal IS to offset the output analog signal OAS generated by the digital-to-analog conversion circuit 110, so as to avoid the output analog signal OAS from affecting the receiving circuit.

[0073] The echo cancellation digital-to-analog conversion circuit 180 can have the same architecture as the digital-to-analog conversion circuit 110, i.e., also includes thermometer-controlled current sources and a control circuit, so the detailed structure is not shown again. However, since the two digital-to-analog conversion circuits are independent of each other, the echo cancellation current bias values of the echo cancellation current sources in the echo cancellation digital-to-analog conversion circuit 180 will be different from those of the digital-to-analog conversion circuit 110.

[0074] In one embodiment, the control circuit of the echo cancellation digital-to-analog conversion circuit 180 can also sort and control the turn-on order of the current sources according to the same procedure as described above. In another embodiment, the control circuit of the echo cancellation digital-to-analog conversion circuit 180 can perform an echo cancellation sorting procedure to make the sorting of the current bias values of the current sources of the echo cancellation digital-to-analog conversion circuit 180 approach the sorting of the current bias values of the current sources of the digital-to-analog conversion circuit 110, so that the two have the same trend.

[0075] It should be noted that the above embodiments are only examples. In other embodiments, those skilled in the art should be able to make changes without departing from the spirit of the present application.

[0076] In summary, the digital-to-analog conversion circuit and method with signal correction mechanism can generate an opening sequence through a sorting procedure, so that the current deviation values among the current sources are offset to each other when the current sources are opened in the opening sequence, thereby achieving better linearity.

[0077] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the content explicitly or implicitly disclosed in the present application, and these changes can all fall within the scope of the patent protection of the present application. In other words, the scope of the patent protection of the present application should be defined according to the claims of the present application.

[0078] Legend of reference signs:

[0079] 100: digital-to-analog conversion device

[0080] 110: digital-to-analog conversion circuit

[0081] 120: echo transmission circuit

[0082] 130: correction circuit

[0083] 140: echo cancellation circuit

[0084] 150: error calculation circuit

[0085] 160: inverted error calculation circuit

[0086] 170: correction parameter operation circuit

[0087] 180: echo cancellation digital-to-analog conversion circuit

[0088] 200: control circuit

[0089] 210: switching circuit

[0090] 300: digital-to-analog conversion method

[0091] S310-S330: steps

[0092] 400: sorting procedure

[0093] 500: selection procedure

[0094] S410-S480: steps

[0095] S510-S560: steps

[0096] CA-CO: current sources

[0097] DL: path delay

[0098] DIS: error signal

[0099] EAS: echo cancellation output analog signal

[0100] ECS: echo cancellation signal

[0101] ES: echo signal

[0102] FD: flip error value

[0103] IS: input digital signal

[0104] OAS: output analog signal

[0105] TC: thermometer code

[0106] ΔA ~ ΔO: current deviation value

Claims

1. A digital-to-analog conversion circuit with a signal correction mechanism, comprising: a plurality of thermometer-controlled current sources generating an output analog signal according to a total current; and a control circuit obtaining a plurality of current bias values corresponding to the current sources and performing a sorting procedure on the current bias values to generate an on sequence, wherein the current bias values are divided into a plurality of current bias value groups according to the on sequence, and each two adjacent current bias value groups are opposite in sign to cancel each other out when accumulated according to the on sequence, thereby maintaining a total absolute value of a total current bias value of the current bias values not greater than half of a maximum absolute value of the current bias values, and controlling the current sources to turn on according to the on sequence based on a plurality of thermometer codes included in an input digital signal; wherein the sorting procedure comprises: selecting a maximum positive value and a maximum negative value from the current bias values corresponding to the current sources that have not been sorted, wherein the maximum positive value and the maximum negative value corresponding to a larger absolute value is a first extreme value, and the maximum positive value and the maximum negative value corresponding to a smaller absolute value is a second extreme value; generating an intermediate absolute value of the first extreme value; performing a selection procedure to select at least one selected bias value from the remaining current bias values other than the maximum positive value and the maximum negative value, wherein a sum of the selected bias value is closest to a difference between the intermediate absolute value and a bias residual value; sequentially setting the current sources corresponding to the selected bias value, the first extreme value and the second extreme value to have an on sequence from high to low, and less than the on sequence of the current sources that have been sorted; setting the current sources corresponding to the selected bias value, the first extreme value and the second extreme value as sorted; making the sum of the bias residual value, the selected bias value, the first extreme value and the second extreme value as a new bias residual value; and continuing the sorting procedure when there are current sources that have not been sorted, and ending the sorting procedure when there are no current sources that have not been sorted.

2. The digital-to-analog conversion circuit of claim 1, wherein, The selection procedure comprises: determining whether one of the remaining current bias values is within a bias value range centered on a center value, wherein the center value is preset as a first difference between the intermediate absolute value and the bias residual value, and the bias value range has a maximum boundary value and a minimum boundary value; when one of the remaining current bias values is within the bias value range, selecting the one closest to the center value as the selected bias value and ending the selection procedure; when none of the remaining current bias values is within the bias value range, when the first extreme value is the maximum positive value, selecting one of the remaining current bias values closest to the maximum boundary value as the selected bias value, and when the first extreme value is the maximum negative value, selecting one of the remaining current bias values closest to the minimum boundary value as the selected bias value; and subtracting the selected offset value from the minimum boundary value results in a modified minimum boundary value and subtracting the selected offset value from the maximum boundary value results in a modified maximum boundary value, and a modified range centered at a second difference between the center value and the selected offset value is generated as the offset value range according to the modified minimum boundary value and the modified maximum boundary value, and the selection procedure is re-performed.

3. The digital-to-analog conversion circuit of claim 2, wherein, The selection procedure further comprises: when none of the remaining current offset values is within the offset value range, and when the first extremum is the maximum positive value and none of the remaining current offset values is greater than the maximum boundary value, or when the first extremum is the maximum negative value and none of the remaining current offset values is less than the minimum boundary value, subtracting an expansion parameter from the minimum boundary value results in an expanded minimum boundary value and adding the expansion parameter to the maximum boundary value results in an expanded maximum boundary value, and an expanded range is generated as the offset value range, and the selection procedure is re-performed.

4. The digital-to-analog conversion circuit of claim 1, wherein, The digital-to-analog conversion circuit is applied in a digital-to-analog conversion device, the digital-to-analog conversion device further comprises an echo cancellation digital-to-analog conversion circuit, and the echo cancellation digital-to-analog conversion circuit comprises: a plurality of thermometer-controlled echo cancellation current sources; and an echo cancellation control circuit performing an echo cancellation ordering procedure on a plurality of echo cancellation current offset values corresponding to the echo cancellation current sources to generate an echo cancellation turn-on sequence, and controlling the echo cancellation current sources to turn on in the echo cancellation turn-on sequence according to thermometer codes included in an input digital signal, wherein the echo cancellation ordering procedure makes the ordering of the echo cancellation current offset values approach the ordering of the current offset values.

5. A digital-to-analog conversion method with a signal correction mechanism, applied in a digital-to-analog conversion circuit comprising a plurality of thermometer-controlled current sources generating an output analog signal according to a total current and a control circuit, the digital-to-analog conversion method comprising: causing the control circuit to obtain a plurality of current offset values corresponding to the current sources; causing the control circuit to perform an ordering procedure on the current offset values to generate a turn-on sequence, wherein the current offset values are divided into a plurality of current offset value groups in the turn-on sequence, and each two adjacent current offset value groups are opposite in sign to cancel each other out when accumulated in the turn-on sequence, thereby maintaining a total absolute value of a total current offset value of the current offset values not greater than half of a maximum absolute value of the current offset values; and causing the control circuit to control the current sources to turn on in the turn-on sequence according to thermometer codes included in an input digital signal; wherein the ordering procedure comprises: selecting a maximum positive value and a maximum negative value from the current offset values corresponding to the current sources that have not been ordered, wherein the maximum positive value and the maximum negative value corresponding to a larger absolute value is a first extremum, and the maximum positive value and the maximum negative value corresponding to a smaller absolute value is a second extremum; generating an intermediate absolute value of the first extremum; performing a selection procedure to select at least one selected deviation value from among the remaining current deviation values other than the maximum positive value and the maximum negative value, wherein a sum of the selected deviation values is closest to a difference between the intermediate absolute value and a residual deviation value; sequentially setting the current sources corresponding to the selected deviation values, the first extreme value and the second extreme value to have an on sequence from high to low, and less than the on sequence of the current sources that have been sequenced; sequencing the current sources corresponding to the selected deviation values, the first extreme value and the second extreme value; summing the residual deviation value, the selected deviation values, the first extreme value and the second extreme value as a new residual deviation value; and continuing the sequencing procedure when there are current sources that have not been sequenced, and ending the sequencing procedure when there are no current sources that have not been sequenced.

6. The digital-to-analog conversion method of claim 5, wherein, The selection procedure includes: determining whether one of the remaining current deviation values is within a deviation value range centered on a center value, wherein the center value is preset as a first difference between the intermediate absolute value and the residual deviation value, and the deviation value range has a maximum boundary value and a minimum boundary value; when one of the remaining current deviation values is within the deviation value range, selecting the one closest to the center value as the selected deviation value, and ending the selection procedure; when none of the remaining current deviation values is within the deviation value range, selecting, when the first extreme value is the maximum positive value, the one of the remaining current deviation values closest to the maximum boundary value as one of the selected deviation values, and selecting, when the first extreme value is the maximum negative value, the one of the remaining current deviation values closest to the minimum boundary value as the selected deviation value; and subtracting the minimum boundary value from the selected deviation value to generate a modified minimum boundary value, and subtracting the maximum boundary value from the selected deviation value to generate a modified maximum boundary value, and then performing the selection procedure again with a modified range centered on a second difference between the center value and the selected deviation value as the deviation value range according to the modified minimum boundary value and the modified maximum boundary value.

7. The digital-to-analog conversion method of claim 6, wherein, The selection procedure further includes: when none of the remaining current deviation values is within the deviation value range, and when the first extreme value is the maximum positive value and there is no remaining current deviation value greater than the maximum boundary value, or when the first extreme value is the maximum negative value and there is no remaining current deviation value less than the minimum boundary value, subtracting an expansion parameter from the minimum boundary value to generate an expanded minimum boundary value, and adding the expansion parameter to the maximum boundary value to generate an expanded maximum boundary value, and then performing the selection procedure again with an expanded range as the deviation value range.

8. The digital-to-analog conversion method of claim 5, wherein, The digital-to-analog conversion circuit is applied to a digital-to-analog conversion device, the digital-to-analog conversion device further comprises an echo cancellation digital-to-analog conversion circuit, and the echo cancellation digital-to-analog conversion circuit comprises a plurality of thermometer-controlled echo cancellation current sources and an echo cancellation control circuit, and the digital-to-analog conversion method further comprises: The echo cancellation control circuit performs an echo cancellation sorting procedure on a plurality of echo cancellation current bias values corresponding to the echo cancellation current sources to generate an echo cancellation opening sequence, and controls the echo cancellation current sources to open in the echo cancellation opening sequence according to the thermometer code included in the input digital signal, wherein the echo cancellation sorting procedure makes the sorting of the echo cancellation current bias values approach the sorting of the current bias values.

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