Image sensing device and operating method thereof

Abstract

The present application relates to an image sensing device and an operating method thereof. The image sensing device may include a pixel circuit and a drive control circuit. The pixel circuit is configured to store photoelectric charges generated by a photoelectric conversion element as image information. The drive control circuit may control the pixel circuit to adjust a signal conversion gain ratio according to the illumination of incident light at the image sensing device.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device and an operating method thereof, and more particularly, to an image sensing device and an operating method thereof capable of processing image data by adjusting a conversion gain ratio. Background Art

[0002] Image sensing devices are used in electronic devices to convert optical images into digital electrical signals. With the recent development of the automotive, medical, computer and communication industries, the demand for high-performance image sensors is increasing in various electronic devices such as smart phones, digital cameras, camcorders, personal communication systems (PSCs), game consoles, security cameras, medical micro cameras, robotics industry and infrared sensing devices.

[0003] One common type of image sensing device is a charge coupled device (CCD), which has long dominated the field of image sensors. Another common type of image sensing device is a complementary metal oxide semiconductor (CMOS) image sensing device.

[0004] CMOS image sensing devices are manufactured using CMOS manufacturing technology, so the CMOS image sensor and other signal processing circuits can be integrated into a single chip, making it possible to produce miniaturized CMOS image sensing devices and low-power image sensors at low cost. Summary of the invention

[0005] In an embodiment, an image sensing device includes: a pixel circuit, which is configured to transfer photocharges generated by a photoelectric conversion element to a floating diffusion node and store image information; and a drive control circuit, which is configured to generate a reset control signal and a transfer control signal for controlling a row operation of the pixel circuit, and generate multiple selection control signals to control a column operation of the pixel circuit, wherein the pixel circuit controls the capacitance value of the floating diffusion node based on the multiple selection control signals.

[0006] In an embodiment, a method for operating an image sensing device includes: resetting a floating diffusion node included in a pixel circuit of the image sensing device, wherein the image sensing device includes a photoelectric conversion element to detect incident light to generate photocharges that carry an image in response to the incident light, and the floating diffusion node holds the photocharges generated by the photoelectric conversion element; transferring the photocharges generated by the photoelectric conversion element to the floating diffusion node; selectively activating at least one of a plurality of selection transistors that are configured to adjust a capacitance value of the floating diffusion node; and generating an output voltage based on a voltage of the floating diffusion node adjusted according to the capacitance value of the floating diffusion node.

[0007] In an embodiment, an image sensing device includes: a photoelectric conversion element, which is configured to detect incident light to generate photocharges that carry an image in response to the incident light; a pixel circuit, which is connected to the photoelectric conversion element and includes: a floating diffusion node, which is connected to the photoelectric conversion element and is configured to receive and hold the photocharges generated by the photoelectric conversion element; and a drive transistor, which is connected to receive a signal representing the photocharges in the floating diffusion node and is configured to generate an output voltage corresponding to a voltage level of the floating diffusion node representing the photocharges in the floating diffusion node; and a drive control circuit, which is connected to the pixel circuit and is configured to generate multiple control signals to control the pixel circuit, the multiple control signals including a reset control signal for resetting the floating diffusion node and a transmission control signal for controlling the transmission of the photocharges from the photoelectric conversion element to the floating diffusion node, wherein the pixel circuit is configured to adjust the capacitance value of the floating diffusion node in response to one or more other control signals in the control signals from the drive control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example configuration of an image sensing device based on some embodiments of the disclosed technology.

[0009] Figure 2 is a block diagram illustrating some components of an image sensing device based on some embodiments of the disclosed technology.

[0010] Figure 3 is an example Figure 2 A circuit diagram of an example configuration of a pixel circuit.

[0011] Figure 4 Illustrated Figure 3 The waveforms of the first selection control signal and the second selection control signal.

[0012] Figure 5 is an example Figure 1 A plan view of an example of a pixel array.

[0013] Figure 6 is an example Figure 2 A circuit diagram of another example configuration of a pixel circuit.

[0014] Figure 7 is an example Figure 1 Flowchart of example operations of an image sensing device. DETAILED DESCRIPTION

[0015] Advantages and features of the disclosed technology and methods for achieving the advantages and features will be discussed below with reference to the accompanying drawings.

[0016] The disclosed technology may be implemented in some embodiments to provide an image sensing device capable of adjusting the capacitance of a floating diffusion node and an operating method thereof.

[0017] In some embodiments of the disclosed technology, an image sensing device can adjust a conversion gain ratio by adjusting a capacitance value of a floating diffusion node.

[0018] In some implementations, a CMOS image sensing device includes a large number of imaging pixels, each of which includes a photodiode, a reset transistor, a transfer transistor, a conversion gain transistor, a drive transistor, and a select transistor.

[0019] Figure 1 is a block diagram illustrating an example configuration of an image sensing device 100 and an image processor 1000 based on some embodiments of the disclosed technology.

[0020] Reference Figure 1 The image sensing device 100 may be configured to capture incident light carrying an image using a lens or a lens module (not illustrated). In some implementations, the image processor 1000 may control the operation of the image sensing device 100. The image processor 1000 may also be configured to process image data provided by the image sensing device 100.

[0021] The image sensing device 100 may include a pixel array 110, a correlated double sampler (CDS) 120, an analog-to-digital converter (ADC) 130, a buffer 140, a driver / controller 150, a timing generator 160, a control register 170, and a ramp signal generator 180. The pixel array 110 may include a plurality of pixels 10 arranged in rows and columns in an array. Figure 1 The image sensing device 100 is illustrated as including the above-described components by way of example, but additional components may be added and some of these components may be omitted in other implementations.

[0022] The pixel array 110 may include a plurality of pixels 10 arranged in rows and columns. Each pixel 10 may convert incident light carrying an optical image into an electrical signal representing the optical image, and transmit the electrical signal to the CDS 120. The pixel array 110 includes a photoelectric conversion element. For example, each of the plurality of pixels may include a photoelectric conversion element, so that the pixel array 110 may capture incident light and convert the captured light into an electrical signal.

[0023] In some implementations, the image sensing device 100 may use the CDS 120 to remove undesired pixel offset values ​​by sampling the pixel signal twice to remove the difference between the two samples. In one example, the CDS 120 may remove undesired pixel offset values ​​by comparing the pixel output voltages obtained before and after the light signal is incident on the pixel, so that the pixel output voltage based only on the incident light can be measured. In some implementations, the CDS 120 may sample an electrical signal representing an image captured by and received from a plurality of pixels 10 of the pixel array 110 (hereinafter, "electrical image signal"). The CDS 120 may sample the electrical image signal based on a timing control signal provided from the timing generator 160. The CDS 120 may generate an analog value corresponding to the difference between the two electrical image signals, and output the generated analog value.

[0024] ADC 130 may convert an analog signal into a digital signal. For example, ADC 130 may convert an analog CDS signal into a digital signal. Examples of ADC 130 may include a ramp comparison ADC in which an analog signal is compared with a reference signal such as a ramp signal that ramps up or down and a timer counts until the voltage of the ramp signal matches the analog signal. In some embodiments of the disclosed technology, ADC 130 may compare a voltage level corresponding to an electrical image signal with a voltage level corresponding to a ramp voltage signal provided by ramp signal generator 180. In one example, ADC 130 may convert an analog value generated by CDS 120 into a digital value by comparing the analog value generated by CDS 120 with the ramp voltage signal. The digital value may be provided to buffer 140.

[0025] Buffer 140 may hold or "latch" digital values ​​output from ADC 130 and sequentially transfer the latched digital values ​​to image processor 1000. Buffer 140 may include a plurality of latch circuits (not illustrated) for holding digital values ​​and sense amplifiers (not illustrated) for amplifying digital values.

[0026] The driver / controller 150 may selectively activate a plurality of pixels 10 of the pixel array 110 based on a timing control signal provided by the timing generator 160. For example, the driver / controller 150 may select one or more row lines LN_R among the plurality of row lines LN_R and generate various control signals for activating one or more pixels among the plurality of pixels 10. In some implementations, the various control signals may include a reset control signal, a transfer control signal, and others. The driver / controller 150 may generate a plurality of selection control signals to output image data stored in the plurality of pixels 10 through the plurality of column lines LN_C. Figures 2 to 4 Discuss reset control signals, transfer control signals, and multiple select control signals.

[0027] The timing generator 160 may generate timing control signals for controlling the CDS 120, the ADC 130, the driver / controller 150, and the ramp signal generator 180. The control register 170 may generate control signals for controlling the buffer 140, the timing generator 160, and the ramp signal generator 180. In some implementations, the image processor 1000 may control the operation of the control register 170. The ramp signal generator 180 may generate a ramp voltage signal and provide the generated ramp voltage signal to the CDS 120. In some implementations, the timing generator 160 and the control register 170 may control the operation of the ramp signal generator 180.

[0028] The image processor 1000 may include an image signal processor 1010 and a camera controller 1020 .

[0029] The image signal processor 1010 may generate a control signal for controlling the image sensing device 100, and process a digital value provided by the image sensing device 100. In some implementations, the image signal processor 1010 may receive a digital value obtained by converting a captured image and representing an image, and process the received digital value to display an image. The camera controller 1020 may control the operation of the control register 170 of the image sensing device 100 using I2C (Inter-Integrated Circuit).

[0030] Figure 2 is a block diagram illustrating some components of an image sensing device 100 according to some embodiments of the disclosed technology.

[0031] Reference Figure 2 , the image sensing device 100 may include a pixel circuit 210 and a drive control circuit 220. The pixel circuit 210 may correspond to Figure 1 The pixel 10, and the drive control circuit 220 may correspond to Figure 1 Driver / controller 150.

[0032] In some implementations, the pixel circuit 210 can be configured to convert the photoelectric conversion element (see Figure 3 ) generates photocharges that are transferred to the floating diffusion node (see Figure 3 ). Figure 3 The pixel circuit 210 is described in more detail. The pixel circuit 210 may include a circuit capable of adjusting a capacitance value of a floating diffusion node based on a plurality of selection control signals CTR_S.

[0033] The driving control circuit 220 may be configured to generate a reset control signal CTR_RX and a transmission control signal CTR_TX to control the row operation of the pixel circuit 210. The driving control circuit 220 may be configured to generate a plurality of selection control signals CTR_S to control the column operation of the pixel circuit 210. The plurality of selection control signals CTR_S may include two or more selection control signals CTR_S.

[0034] In some implementations, the drive control circuit 220 may control row operations and column operations for the pixel circuit 210. The row operation may include operations for selecting a plurality of row lines LN_R of the pixel circuit 210, as described above with reference to Figure 1 The column operation may include an operation for selecting a plurality of column lines LN_C of the pixel circuit 210, as described above with reference to Figure 1 As will be described below, the drive control circuit 220 may generate a reset control signal CTR_RX and a transmission control signal CTR_TX to control a row operation for the pixel circuit 210. The drive control circuit 220 may generate a plurality of selection control signals CTR_S to control a column operation for the pixel circuit 210.

[0035] The image sensing device 100 based on some embodiments of the disclosed technology may adjust the conversion gain of the image sensing device 100 by controlling or adjusting the capacitance value of the floating diffusion node of the pixel circuit 210 based on a plurality of selection control signals CTR_S generated by the driving control circuit 220 during a column operation.

[0036] Figure 3 is an example Figure 2 2 is a circuit diagram of an example configuration of a pixel circuit 210.

[0037] Reference Figure 3 The pixel circuit 210 may include a reset transistor RX, a transfer transistor TX, a control circuit 310 and a drive transistor DX. In some implementations, the pixel circuit 210 may further include a photoelectric conversion element PD.

[0038] The reset transistor RX can be configured to reset the floating diffusion node FD based on the reset control signal CTR_RX. The reset transistor RX can be connected between the power supply voltage terminal VDD and the floating diffusion node FD. The reset transistor RX can be turned on / off based on the reset control signal CTR_RX. In some implementations, the floating diffusion node FD is "reset" by connecting the floating diffusion node FD to the power supply voltage terminal VDD. Therefore, when the reset transistor RX is turned on, the floating diffusion node FD can be charged and "reset" by the power supply voltage terminal VDD. In this patent document, the "reset operation" includes charging the floating diffusion node FD.

[0039] The transfer transistor TX can be configured to transfer the photocharge generated by the photoelectric conversion element PD to the floating diffusion node FD based on the transfer control signal CTR_TX. The transfer transistor TX can be connected between the floating diffusion node FD and the ground voltage terminal VSS. The transfer transistor TX can be turned on or off based on the transfer control signal CTR_TX. Therefore, when the transfer transistor TX is turned on, the photocharge generated by the photoelectric conversion element PD can be transferred to the floating diffusion node FD. In this patent document, the "transfer operation" includes transferring the photocharge to the floating diffusion node FD.

[0040] The floating diffusion node FD may have a voltage level corresponding to the photocharge generated by the photoelectric conversion element PD and transmitted by the reset operation and the transfer operation. When the floating diffusion node FD is charged with photocharge, the voltage at the floating diffusion node FD increases. When the reset operation is performed, the voltage at the floating diffusion node FD decreases. Here, the voltage drop may vary according to the amount of photocharge transmitted to the floating diffusion node FD. For example, when a large amount of photocharge is transmitted, the voltage drop at the floating diffusion node FD may be smaller than when a small amount of photocharge is transmitted. That is, when a large amount of photocharge is transmitted, the voltage level of the floating diffusion node FD may be at a higher level than when a small amount of photocharge is transmitted. For example, when a small amount of photocharge is transmitted, the voltage drop at the floating diffusion node FD may be larger. That is, when a small amount of photocharge is transmitted, the voltage level of the floating diffusion node FD may be at a lower level than when a large amount of photocharge is transmitted.

[0041] As described above, the reset control signal CTR_RX and the transfer control signal CTR_TX may be generated during the row operation for the pixel circuit 210. Therefore, the row operation may include a reset operation corresponding to the reset control signal CTR_RX and a transfer operation corresponding to the transfer control signal CTR_TX. In other words, the image sensing device 100 may transfer the photocharge to the floating diffusion node FD through the reset operation and the transfer operation performed during the row operation.

[0042] The disclosed technology can be implemented in some embodiments to provide a control circuit connected between a floating diffusion node (FD) and a source follower transistor (drive transistor DX) to adjust the conversion gain of a photoelectric conversion element (e.g., a photodetector PD). In some implementations, the control circuit 310 can be configured to control or adjust the capacitance value of the floating diffusion node FD based on multiple selection control signals (e.g., CTR_S1 and CTR_S2). For example, the control circuit 310 can control or adjust the capacitance value of the floating diffusion node FD based on a first selection control signal CTR_S1 and a second selection control signal CTR_S2. Although Figure 3 The control circuit 310 is illustrated as receiving two select control signals by way of example, but in other implementations more than two select control signals may be used.

[0043] In some implementations, the control circuit 310 may include a first selection transistor SX1 and a second selection transistor SX2 corresponding to the first selection control signal CTR_S1 and the second selection control signal CTR_S2, respectively. In other implementations, the control circuit 310 may include more than two selection transistors.

[0044] The first selection transistor SX1 may be configured to adjust the capacitance value of the floating diffusion node FD to a first capacitance value based on a first selection control signal CTR_S1. In some implementations of the disclosed technology, the first selection transistor SX1 is connected between the floating diffusion node FD and the driving transistor DX. The first selection transistor SX1 may be turned on or off based on the first selection control signal CTR_S1. When the first selection transistor SX1 is turned on, the capacitance value of the floating diffusion node FD may be adjusted to a first capacitance value by activating the first selection transistor SX1 and connecting the first selection transistor SX1 to the floating diffusion node FD. When the first selection transistor SX1 is turned on and enabled, the capacitance value of the floating diffusion node FD is determined based on the capacitance of the floating diffusion node FD and the capacitance of the first selection transistor SX1 (and other selection transistors activated and connected to the floating diffusion node FD), so the voltage level of the floating diffusion node FD transmitted to the driving transistor DX may be determined based on the capacitance of the floating diffusion node FD and the capacitance of the first selection transistor SX1 (and other selection transistors activated and connected to the floating diffusion node FD).

[0045] The second selection transistor SX2 can be configured to adjust the capacitance value of the floating diffusion node FD to a second capacitance value based on a second selection control signal CTR_S2. In some implementations of the disclosed technology, the second selection transistor SX2 is connected between the floating diffusion node FD and the driving transistor DX. In an example, the first selection transistor SX1 and the second selection transistor SX2 are connected in parallel between the floating diffusion node FD and the driving transistor DX. The second selection transistor SX2 can be turned on or off based on the second selection control signal CTR_S2. When the second selection transistor SX2 is turned on, the capacitance value of the floating diffusion node FD can be adjusted to the second capacitance value by activating the second selection transistor SX2 and connecting the second selection transistor SX2 to the floating diffusion node FD. When the second selection transistor SX2 is turned on and enabled, the capacitance value of the floating diffusion node FD is determined based on the capacitance of the floating diffusion node FD and the capacitance of the second selection transistor SX2 (and other selection transistors activated and connected to the floating diffusion node FD), so the voltage level of the floating diffusion node FD transmitted to the driving transistor DX can be determined based on the capacitance of the floating diffusion node FD and the capacitance of the second selection transistor SX2 (and other selection transistors activated and connected to the floating diffusion node FD).

[0046] The first capacitance value and the second capacitance value may be different from each other. There are many factors that affect the capacitance value. For example, the channel length and width of the transistor, the thickness of the gate dielectric layer, and the impurity doping concentration of the channel region of the transistor may affect the capacitance value. Therefore, the first selection transistor SX1 may be different from the second selection transistor SX2 in at least one of the above factors, so the capacitance value of the first selection transistor SX1 and the capacitance value of the second selection transistor SX2 may be different from each other. That is, the first capacitance value adjusted from the original capacitance value of the floating diffusion node FD by activating and connecting the first selection transistor SX1 and the second capacitance value adjusted from the original capacitance value of the floating diffusion node FD by activating and connecting the second selection transistor SX2 may be different from each other.

[0047] If you will refer to Figure 4 As described in more detail, according to the drive control circuit 220 (see Figure 2), both the first selection transistor SX1 and the second selection transistor SX2 can be turned on. At this time, the capacitance value of the floating diffusion node FD is determined based on the capacitance of the floating diffusion node FD and the capacitance values ​​of the first selection transistor SX1 and the second selection transistor SX2. In this way, the capacitance value of the floating diffusion node FD can be adjusted to a third capacitance value by reflecting the capacitance values ​​of the first selection transistor SX1 and the second selection transistor SX2. As a result, depending on which of the first selection transistor SX1 and the second selection transistor SX2 is activated and whether both the first selection transistor SX1 and the second selection transistor SX2 are activated, the capacitance value of the floating diffusion node FD can be controlled to have one of the first capacitance value to the third capacitance value. In this patent document, "capacitance control operation" includes controlling the capacitance value of the floating diffusion node FD.

[0048] The driving transistor DX may be configured to generate an output voltage V_OUT corresponding to the voltage level of the floating diffusion node FD. The driving transistor DX may have a terminal connected to a power supply voltage terminal VDD and a gate terminal connected to the first selection transistor SX1 and the second selection transistor SX2. The driving transistor DX may receive the voltage of the floating diffusion node FD through the gate terminal, and the level of the voltage of the floating diffusion node FD is controlled or adjusted by at least one of the first selection transistor SX1 or the second selection transistor SX2. In some implementations, the driving transistor DX may operate as a source follower circuit or a common drain amplifier. Therefore, an increase or decrease in the voltage level of the voltage input to the gate terminal of the driving transistor DX may increase or decrease the conduction channel of the driving transistor DX, so that the output voltage V_OUT generated by the driving transistor DX increases or decreases based on the voltage input to the gate terminal of the driving transistor DX. In this patent document, "driving operation" includes activating the driving transistor DX to generate the output voltage V_OUT.

[0049] As described above, a plurality of selection control signals such as the first selection control signal CTR_S1 and the second selection control signal CTR_S2 may be operated during the column operation. Therefore, the column operation may include a capacitance control operation and a selection output operation corresponding to the first selection control signal CTR_S1 and the second selection control signal CTR_S2, and a driving operation corresponding to the driving transistor DX. In other words, the image sensing device 100 may transmit the voltage level of the floating diffusion node FD to the driving transistor DX through the capacitance control operation and the selection output operation performed during the column operation. In addition, the image sensing device 100 may generate an output voltage V_OUT through the driving operation performed during the column operation.

[0050] Figure 4 Illustrated Figure 31 and 2 . The waveforms of the first selection control signal CTR_S1 and the second selection control signal CTR_S2 are shown in FIG. Figure 4 Waveforms corresponding to the reset control signal CTR_RX, the transmission control signal CTR_TX, the first selection control signal CTR_S1, and the second selection control signal CTR_S2 are illustrated.

[0051] Reference Figure 3 and Figure 4 When the reset control signal CTR_RX is activated from a logic "low" level to a logic "high" level, the pixel circuit 210 may perform a reset operation. Then, when the transmission control signal CTR_TX is activated from a logic "high" level to a logic "low" level, the pixel circuit 210 may perform a transmission operation.

[0052] The operation state of the image sensing device 100 according to some embodiments of the disclosed technology may be divided into three operation modes depending on which one of the first selection control signal CTR_S1 and the second selection control signal CTR_S2 is activated.

[0053] In the first mode (A), only the first selection control signal CTR_S1 is activated from a logic "low" level to a logic "high" level. When the first selection control signal CTR_S1 is activated, the first selection transistor SX1 may be enabled. Therefore, by reflecting the capacitance value of the first selection transistor SX1, the capacitance value of the floating diffusion node FD is modified from its original capacitance value to the first capacitance value.

[0054] In the second mode (B), only the second selection control signal CTR_S2 is activated. When the second selection control signal CTR_S2 is activated, the second selection transistor SX2 may be enabled. Therefore, by reflecting the capacitance value of the second selection transistor SX2, the capacitance value of the floating diffusion node FD is modified from its original capacitance value to the second capacitance value.

[0055] In the third mode (C), both the first selection control signal CTR_S1 and the second selection control signal CTR_S2 are activated. When both the first selection control signal CTR_S1 and the second selection control signal CTR_S2 are activated, the first selection transistor SX1 and the second selection transistor SX2 may be enabled. Therefore, by reflecting the capacitance values ​​of the first selection transistor SX1 and the second selection transistor SX2, the capacitance value of the floating diffusion node FD is modified from its original capacitance value to a third capacitance value.

[0056] The image sensing device 100 according to some embodiments of the disclosed technology can tune the capacitance value of the floating diffusion node FD to control the conversion gain of the image sensing device 100. The capacitance value of the floating diffusion node FD can have one of a plurality of capacitance values ​​(e.g., the first capacitance value to the third capacitance value) depending on its operating state. Therefore, the image sensing device 100 can have various conversion gain ratios relative to the pixel circuit 210.

[0057] Return to reference Figure 2 During the column operation, the driving control circuit 220 may selectively activate a plurality of selection control signals CTR_S based on the driving information INF_D and the illumination information INF_P. The driving information INF_D may include a plurality of column lines LN_C (see Figure 1 ). The illumination information INF_P may include information about the illumination of the captured image. Therefore, the drive control circuit 220 may determine whether to activate multiple selection control signals CTR_S based on the drive information INF_D. In addition, the drive control circuit 220 may select one or more selection control signals to be activated among the multiple selection control signals CTR_S based on the illumination information INF_P.

[0058] In some implementations, the drive control circuit 220 may determine whether to activate multiple selection control signals CTR_S and in which mode (e.g., mode (A), (B), and (C)) to activate the multiple selection control signals CTR_S based on the drive information INF_D. The drive control circuit 220 may select one of multiple modes (e.g., mode (A), (B), or (C)) based on the illumination information INF_P. For example, when an image is captured under high illumination conditions, low illumination conditions, or medium illumination conditions, the drive control circuit 220 may select one of modes (A), (B), and (C) based on the illumination condition of the captured image. For example, the capacitance value of the floating diffusion node FD may decrease in response to the illumination information INF_P corresponding to the high illumination condition. In addition, the capacitance value of the floating diffusion node FD may increase based on the illumination information INF_P corresponding to the low illumination condition. That is, the capacitance value may be inversely proportional to the illumination information.

[0059] The image sensing device 100 according to some embodiments of the disclosed technology can control the capacitance value of the floating diffusion node FD based on the illumination conditions of the captured image. The image sensing device 100 can adjust the capacitance value of the floating diffusion node FD, thereby adopting various conversion gain ratios when converting incident light into an electrical signal.

[0060] Return to reference Figure 1In some implementations, each pixel 10 may be a unit pixel. In other implementations, each pixel 10 may be a group of unit pixels. In one example, an 8-shared pixel structure including eight unit pixels will be discussed below as an example. The disclosed technology may also be implemented in some embodiments to provide a pixel 10 having a 4-shared pixel structure including four unit pixels in each group or a 2-shared pixel structure including two unit pixels in each group. In addition, the disclosed technology may also be implemented in some embodiments to provide a pixel 10 that does not have a shared pixel structure.

[0061] Figure 5 is an example Figure 1 1 is a plan view of an example of a pixel array 110. In one example, the pixel array 110 includes eight unit pixels. In addition, the first direction D1 and the second direction D2 may indicate directions that intersect each other. For example, in an XY coordinate system, the first direction D1 may correspond to an X-axis direction, and the second direction D2 may correspond to a Y-axis direction.

[0062] like Figure 5 As shown, the pixel array 110 may include first to eighth unit pixels PX1 to PX8 arranged in rows and columns in a matrix array. The first to eighth unit pixels PX1 to PX8 may be arranged in a 2×4 matrix array. The first to fourth unit pixels PX1 to PX4 may be arranged radially around the first sub-floating diffusion node FD11 while sharing the first sub-floating diffusion node FD11. Similarly, the fifth to eighth unit pixels PX5 to PX8 may be arranged radially around the second sub-floating diffusion node FD12 while sharing the second sub-floating diffusion node FD12. The first sub-floating diffusion node FD11 and the second sub-floating diffusion node FD12 may be aligned with each other in the second direction D2. The first sub-floating diffusion node FD11 and the second sub-floating diffusion node FD12 may be electrically coupled to each other by interconnects and contact plugs (not shown) configured to couple the first sub-floating diffusion node FD11 and the second sub-floating diffusion node FD12 to each other.

[0063] Each of the first to eighth unit pixels PX1 to PX8 may include a photoelectric conversion element PD. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a PPD (pinned photodiode), or a combination thereof. For example, the photoelectric conversion element PD may be a photodiode. The photodiode may include a structure in which an N-type impurity region and a P-type impurity region are stacked in a vertical direction.

[0064] The first to eighth unit pixels PX1 to PX8 may include first to eighth transfer transistors TX1 to TX8, respectively. Photocharges generated by the photoelectric conversion element PD in response to incident light may be transferred to the first and second sub-floating diffusion nodes FD11 and FD12 through the first to eighth transfer transistors TX1 to TX8.

[0065] The first selection transistor SX1 and the second selection transistor SX2 may be disposed on one side of the first unit pixel PX1 and the second unit pixel PX2. For example, the first selection transistor SX1 may be disposed at the top of the first unit pixel PX1 in the second direction D2, and the second selection transistor SX2 may be disposed at the top of the second unit pixel PX2 in the second direction D2. For reference, the positions of the first selection transistor SX1 and the second selection transistor SX2 may vary.

[0066] The first selection transistor SX1 and the second selection transistor SX2 may share the first active region 20. The first active region 20 may have a stripe planar shape extending in the first direction D1. Although not shown in the figure, a well tap may be located adjacent to either end of the first active region 20 or both ends thereof.

[0067] The first active region 20 may include first to third junction regions 22, 24, and 26, and the first to third junction regions 22, 24, and 26 may be used as source terminals and drain terminals of the first selection transistor SX1 and the second selection transistor SX2. For example, the first junction region 22 may be used as the source terminal of the first selection transistor SX1, and the third junction region 26 may be used as the drain terminal of the second selection transistor SX2. The second junction region 24 may be used as the drain terminal of the first selection transistor SX1 and the source terminal of the second selection transistor SX2. As described above, the first selection transistor SX1 may be different from the second selection transistor SX2 in at least one of the channel length and width of the transistor, the thickness of the gate dielectric layer of the transistor, and the impurity doping concentration of the channel region of the transistor. Therefore, the first selection transistor SX1 and the second selection transistor SX2 may have different capacitance values.

[0068] In some implementations, the drive transistor DX and the reset transistor RX may be disposed between the third unit pixel PX3 and the fourth unit pixel PX4 and the fifth unit pixel PX5 and the sixth unit pixel PX6. For example, the drive transistor DX may be located between the third unit pixel PX3 and the fifth unit pixel PX5, and the reset transistor RX may be disposed between the fourth unit pixel PX4 and the sixth unit pixel PX6. For reference, the positions of the drive transistor DX and the reset transistor RX may vary.

[0069] The driving transistor DX and the reset transistor RX may share the second active region 30. The second active region 30 may have a stripe planar shape extending in the first direction D1. Although not shown in the figure, the well tap may be located adjacent to either end of the second active region 30 or both ends thereof.

[0070] The second active region 30 may include fourth to sixth junction regions 32, 34, and 36, and the fourth to sixth junction regions 32, 34, and 36 may be used as source terminals and drain terminals of the drive transistor DX and the reset transistor RX. For example, the fourth junction region 32 may be used as the drain terminal of the drive transistor DX, and the sixth junction region 36 may be used as the source terminal of the reset transistor RX. The fifth junction region 34 may be used as the source terminal of the drive transistor DX and the drain terminal of the reset transistor RX.

[0071] like Figure 5 As shown, the first and second selection transistors SX1 and SX2 may be disposed to face the driving transistor DX and the reset transistor RX based on a pixel region. The pixel region may include a region in which the first to fourth unit pixels PX1 to PX4 are disposed.

[0072] Figure 6 is an example Figure 2 2 is a circuit diagram of another example configuration of the pixel circuit 210.

[0073] Reference Figure 6 , the pixel circuit 210 may include a reset transistor RX, a transfer transistor TX, a control circuit 610 and a driving transistor DX. Figure 6 The pixel circuit 210 has Figure 3 The control circuit 610 is different from the control circuit of the pixel circuit 210. In some implementations, components other than the control circuit 610 may be the same as those described above with reference to FIG. Figure 3 The components discussed are the same or similar.

[0074] The control circuit 610 may be configured to adjust the capacitance value of the floating diffusion node FD based on a plurality of selection control signals CTR_S1 to CTR_S3. The control circuit 610 may include first to third selection transistors SX1 to SX3 corresponding to a plurality of selection control signals such as first to third selection control signals CTR_S1 to CTR_S3, respectively. Figure 6The control circuit 610 is illustrated by way of example as including three selection transistors, i.e., the first selection transistor SX1 to the third selection transistor SX3, but in other implementations the control circuit 610 may include three or more selection transistors. In addition, instead of the first selection transistor SX1 to the third selection transistor SX3 or in addition to the first selection transistor SX1 to the third selection transistor SX3, the control circuit 610 may include a variable transistor controlled in an analog type. When the control circuit 610 includes the variable transistor, the capacitance value of the floating diffusion node FD may be controlled in an analog type.

[0075] The first selection transistor SX1 may be enabled or disabled based on the first selection control signal CTR_S1. The second selection transistor SX2 may be enabled or disabled based on the second selection control signal CTR_S2. The third selection transistor SX3 may be enabled or disabled based on the third selection control signal CTR_S3.

[0076] In some implementations, Figure 3 The first selection transistor SX1 and the second selection transistor SX2 of the control circuit 310 may have different capacitance values. In some implementations, Figure 6 The first to third selection transistors SX1 to SX3 of the control circuit 610 may have different capacitance values. In some implementations, two or more selection transistors of the plurality of selection transistors have the same capacitance value and the other selection transistors have different capacitance values.

[0077] In some implementations, Figure 3 The control circuit 310 can selectively enable the first selection transistor SX1 and the second selection transistor SX2 to control the capacitance value of the floating diffusion node FD. In some implementations, Figure 6 The control circuit 610 may selectively control the number of enabled selection transistors among the first to third selection transistors SX1 to SX3 to control the capacitance value of the floating diffusion node FD.

[0078] and Figure 2Similar to the first selection control signal CTR_S1 and the second selection control signal CTR_S2, the first selection control signal CTR_S1 to the third selection control signal CTR_S3 can be activated based on the driving information INF_D and the illumination information INF_P. Here, the number of selection control signals activated based on the illumination information INF_P among the first selection control signal CTR_S1 to the third selection control signal CTR_S3 can be controlled. In other words, among the first selection transistors SX1 to the third selection transistors SX3 configured to be enabled based on the first selection control signal CTR_S1 to the third selection control signal CTR_S3, the number of selection transistors enabled based on the illumination information INF_P can vary.

[0079] More specifically, one, two, or all of the first to third selection transistors SX1 to SX3 may be enabled based on the illumination information INF_P. Depending on whether: (1) one of the first to third selection transistors SX1 to SX3 is enabled; (2) two of the first to third selection transistors SX1 to SX3 are enabled; and (3) all of the first to third selection transistors SX1 to SX3 are enabled, the capacitance value of the floating diffusion node FD may vary. Therefore, the control circuit 610 may control the capacitance value of the floating diffusion node FD based on the illumination information INF_P. The control circuit 610 may control the capacitance value of the floating diffusion node FD based on the number of enabled selection transistors among the first to third selection transistors SX1 to SX3.

[0080] Figure 7 is an example Figure 1 Flowchart of example operations of the image sensing device 100.

[0081] Reference Figures 1 to 3 and Figure 7 , the operating method of the image sensing device 100 may include: at S710, performing a reset operation and a transmission operation; at S720, performing a capacitance control operation and a selection output operation; and at S730, performing a driving operation.

[0082] First, at S710, performing a reset operation and a transmission operation may include performing a reset operation on Figure 2 The floating diffusion node FD in the pixel circuit 210 is reset. The reset operation can be performed by Figure 2 The drive control circuit 220 for generating the reset control signal CTR_RX and Figure 3 The reset operation and the transfer operation may be performed by the reset transistor RX enabled based on the reset control signal CTR_RX. In addition, at S710, performing the reset operation and the transfer operation may include transferring the photocharge generated by the photoelectric conversion element PD to the floating diffusion node FD. The transfer operation may be performed by Figure 2 The drive control circuit 220 for generating the transmission control signal CTR_TX and Figure 3 This is performed by the transmission transistor TX being enabled based on the transmission control signal CTR_TX.

[0083] At S720, performing the capacitance control operation and selecting the output operation may include controlling the capacitance value of the floating diffusion node FD. In addition, at S720, performing the capacitance control operation and selecting the output operation may include selecting and outputting the voltage level of the floating diffusion node FD (wherein the controlled capacitance value is reflected) through the corresponding path to the output terminal. Figure 3 The capacitor control operation and the selected output operation can be controlled by Figure 3 The control circuit 310 executes.

[0084] At S730, performing the driving operation may include generating an output voltage V_OUT through the driving operation based on the voltage of the floating diffusion node FD. The driving operation may be performed by Figure 3 The drive transistor DX performs

[0085] The image sensing device 100 according to some embodiments of the disclosed technology can control the capacitance value of the floating diffusion node FD. Therefore, by controlling the capacitance value, the image sensing device 100 can ensure various conversion gain ratios.

[0086] Only limited examples of implementations or embodiments of the disclosed technology are described or illustrated. Based on what is disclosed and illustrated in this patent document, variations or enhancements to the disclosed implementations or embodiments and other implementations or embodiments are possible.

[0087] CROSS-REFERENCE TO RELATED APPLICATIONS

[0088] This patent document claims priority to and the benefit of Korean Application No. 10-2021-0094944, filed on July 20, 2021, the entire contents of which are incorporated herein by reference as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a pixel circuit that transfers photocharges generated by the photoelectric conversion element to a floating diffusion node and stores image information; as well as a drive control circuit that generates a reset control signal and a transfer control signal for controlling a row operation of the pixel circuit and generates a plurality of selection control signals to control a column operation of the pixel circuit, The pixel circuit includes a driving transistor and a control circuit, wherein the driving transistor generates an output voltage corresponding to the voltage level of the floating diffusion node, and the control circuit is connected between the floating diffusion node and the driving transistor and controls the capacitance value of the floating diffusion node based on the multiple selection control signals.

2. The image sensing device according to claim 1, wherein: The row operation includes a reset operation and a transfer operation of the pixel circuit, and the column operation includes a capacitance control operation, a selection output operation, and a drive operation of the pixel circuit.

3. The image sensing device according to claim 1, wherein: During the column operation, the drive control circuit selectively activates the plurality of selection control signals based on drive information and illumination information.

4. The image sensing device according to claim 1, wherein: The pixel circuit further comprises: a reset transistor that resets the floating diffusion node based on the reset control signal; and A transfer transistor transfers the photocharge generated by the photoelectric conversion element to the floating diffusion node based on the transfer control signal.

5. The image sensing device according to claim 1, wherein: The plurality of selection control signals include a first selection control signal and a second selection control signal, and Wherein, the control circuit comprises: a first selection transistor, the first selection transistor adjusting the capacitance value to a first capacitance value based on the first selection control signal; and A second selection transistor is provided, wherein the second selection transistor adjusts the capacitance value to a second capacitance value based on the second selection control signal.

6. The image sensing device according to claim 5, wherein: The first select transistor and the second select transistor are coupled in parallel to the floating diffusion node.

7. The image sensing device according to claim 5, wherein: At least one of the channel length, channel width, gate dielectric layer thickness, and impurity doping concentration of the channel region of the first selection transistor is different from a corresponding one of the channel length, channel width, gate dielectric layer thickness, and impurity doping concentration of the channel region of the second selection transistor.

8. The image sensing device according to claim 5, wherein: The first selection transistor and the second selection transistor adjust the capacitance value to a third capacitance value different from each of the first capacitance value and the second capacitance value based on the first selection control signal and the second selection control signal.

9. The image sensing device according to claim 5, wherein: The first selection transistor and the second selection transistor are disposed to face the driving transistor and the reset transistor based on a pixel area.

10. The image sensing device according to claim 1, wherein: The control circuit includes a plurality of selection transistors that receive the plurality of selection control signals respectively. The capacitance value is adjusted based on the number of enabled selection transistors among the plurality of selection transistors.

11. A method for operating an image sensing device, the method comprising the following steps: resetting a floating diffusion node included in a pixel circuit of the image sensing device, wherein the image sensing device includes a photoelectric conversion element to detect incident light to generate photocharges carrying an image in response to the incident light, and the floating diffusion node holds the photocharges generated by the photoelectric conversion element; transferring the photocharge generated by the photoelectric conversion element to the floating diffusion node; selectively activating at least one of a plurality of selection transistors configured to adjust a capacitance value of the floating diffusion node; and An output voltage is generated based on the voltage of the floating diffusion node adjusted according to the capacitance value of the floating diffusion node.

12. The operating method according to claim 11, wherein: The step of resetting the floating diffusion node and the step of transferring the photocharge are included in a first operation of the pixel circuit associated with a row of the image sensing device, and the step of activating at least one of the plurality of selection transistors and the step of generating the output voltage are included in a second operation of the pixel circuit associated with a column of the image sensing device.

13. The operating method according to claim 11, wherein: Activation of at least one of the plurality of selection transistors is selectively performed based on illumination information.

14. The operating method according to claim 13, wherein: The capacitance value is inversely proportional to the illumination information.

15. The operating method according to claim 11, wherein: The plurality of selection transistors have different capacitance values.

16. The operating method according to claim 11, wherein: The step of activating at least one of the plurality of select transistors includes adjusting a number of enabled select transistors among the plurality of select transistors.

17. An image sensing device, comprising: a photoelectric conversion element configured to detect incident light to generate photocharges carrying an image in response to the incident light; a floating diffusion node coupled to the photoelectric conversion element and configured to receive and hold the photocharge generated by the photoelectric conversion element; a driving transistor that generates an output voltage corresponding to a voltage level of the floating diffusion node; as well as A plurality of selection transistors are connected between the floating diffusion node and the driving transistor, wherein at least one of the plurality of selection transistors is selectively activated to adjust a capacitance value of the floating diffusion node.

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