Capacitor array structure and forming method thereof

Abstract

The present invention relates to the field of integrated circuit technology, and in particular to a capacitor array structure and a method for forming the same. The method for forming the capacitor array structure includes the following steps: forming a base, the base including a substrate, a stacked structure located on the substrate, and a mask layer located on the stacked structure, the mask layer having an etching window that penetrates the mask layer in a direction perpendicular to the substrate; etching the stacked structure along the etching window to form a capacitor hole that penetrates the stacked structure in a direction perpendicular to the substrate; forming a conductive layer that fills the capacitor hole and the etching window and covers the top surface of the mask layer; removing the conductive layer and the mask layer on the top surface of the stacked structure, and the conductive layer remaining in the capacitor hole forms a lower electrode. The present invention avoids the abnormal increase in the characteristic size of the capacitor hole during the removal of the mask layer, and ensures the characteristic size of the formed lower electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a capacitor array structure and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] Due to the limitations of current process methods, the characteristic size of the capacitor holes in the formed capacitor array structure is abnormally increased, thereby affecting the electrical performance of the capacitor.

[0004] Therefore, how to avoid the abnormal enlargement of capacitor holes and improve the electrical performance of the capacitor array structure is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a capacitor array structure and a method for forming the same, which are used to solve the problem that the capacitor holes in the existing capacitor array structure are prone to abnormal increase in size, thereby improving the electrical performance of the capacitor.

[0006] In order to solve the above problems, the present invention provides a method for forming a capacitor array structure, comprising the following steps:

[0007] forming a base, the base comprising a substrate, a stacked structure located on the substrate, and a mask layer located on the stacked structure, wherein the mask layer has an etching window penetrating the mask layer in a direction perpendicular to the substrate;

[0008] Etching the stack structure along the etching window to form a capacitor hole penetrating the stack structure in a direction perpendicular to the substrate;

[0009] forming a conductive layer that fills the capacitor hole and the etching window and covers the top surface of the mask layer;

[0010] The conductive layer and the mask layer on the top surface of the stacked structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

[0011] Optionally, the specific steps of forming the substrate include:

[0012] providing a substrate;

[0013] Alternatingly depositing support layers and sacrificial layers on the surface of the substrate to form the stacked structure;

[0014] forming a mask layer on the surface of the stacked structure;

[0015] The mask layer is patterned to form an etching window in the mask layer that penetrates the mask layer along a direction perpendicular to the substrate.

[0016] Optionally, the specific steps of forming the stacking structure include:

[0017] depositing a bottom support layer on the surface of the substrate;

[0018] Depositing a first sacrificial layer on the surface of the bottom support layer;

[0019] depositing an intermediate supporting layer on the surface of the first sacrificial layer;

[0020] depositing a second sacrificial layer on the surface of the intermediate supporting layer;

[0021] A top supporting layer is deposited on the surface of the second sacrificial layer.

[0022] Optionally, the material of the support layer includes a nitride material, and the material of the sacrificial layer includes an oxide material.

[0023] Optionally, the specific step of etching the stack structure along the etching window includes:

[0024] The stacked structure is etched along the etching window using a first dry etching process.

[0025] Optionally, the specific steps of removing the conductive layer and the mask layer on the top surface of the stacked structure include:

[0026] removing the conductive layer covering the top surface of the mask layer and within the etching window to expose the mask layer;

[0027] The mask layer is removed.

[0028] Optionally, the specific step of removing the conductive layer covering the top surface of the mask layer and within the etching window includes:

[0029] A second dry etching process is used to remove the conductive layer covering the top surface of the mask layer and within the etching window.

[0030] Optionally, the specific step of removing the conductive layer covering the top surface of the mask layer and within the etching window includes:

[0031] A second dry etching process is used to remove the conductive layer covering the top surface of the mask layer and the etching window, and a portion of the mask layer is removed.

[0032] Optional, including:

[0033] The etching parameters of the second dry etching process are controlled so that the top surface of the remaining conductive layer is flush with the top surface of the stacked structure.

[0034] Optionally, the etching parameters include etching time.

[0035] Optionally, the etching selectivity ratio of the second dry etchant used in the second dry etching process to the conductive layer and the mask layer is greater than 2.

[0036] Optionally, the material of the conductive layer includes TiN, and the material of the mask layer includes polysilicon.

[0037] Optionally, the second dry etchant used in the second dry etching process includes a mixed gas of Cl 2 and BCl 3 .

[0038] Optionally, the specific steps of removing the mask layer include:

[0039] The mask layer is removed by a third dry etching process.

[0040] Optionally, the etching selectivity ratio of the third dry etchant used in the third dry etching process to the mask layer and the conductive layer is greater than 10.

[0041] Optionally, an etching selectivity ratio of the third dry etchant to the mask layer and the conductive layer is greater than an etching selectivity ratio of the second dry etchant to the conductive layer and the mask layer.

[0042] Optionally, the third dry etchant used in the third dry etching process includes a mixed gas of HBr and Cl 2 .

[0043] Optionally, after removing the mask layer, the method further includes the following steps:

[0044] The top surface of the stacked structure and the top surface of the lower electrode are cleaned.

[0045] In order to solve the above problems, the present invention further provides a capacitor array structure formed by any of the above methods for forming a capacitor array structure.

[0046] The capacitor array structure and formation method provided by the present invention, after forming a conductive layer that fills the capacitor holes and covers the top surface of the mask layer, removes the mask layer, thereby avoiding the abnormal increase of the characteristic size of the capacitor holes during the removal of the mask layer, ensuring the characteristic size of the formed lower electrode, and improving the electrical performance of the capacitor array structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] AttachmentFigure 1 is a flow chart of a method for forming a capacitor array structure in a specific embodiment of the present invention;

[0048] Attachment Figures 2A-2H 1 is a schematic cross-sectional view of the main processes in forming a capacitor array structure according to a specific embodiment of the present invention;

[0049] Attachment Figure 3 Schematic diagram of a capacitor array structure in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0050] The specific implementation of the capacitor array structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0051] This embodiment provides a method for forming a capacitor array structure. Figure 1 is a flow chart of a method for forming a capacitor array structure in a specific embodiment of the present invention, Figures 2A-2G FIG. 1 is a schematic cross-sectional view of the main process in forming a capacitor array structure according to a specific embodiment of the present invention. Figure 1 、 Figure 2A-2H As shown, the method for forming a capacitor array structure provided in this specific embodiment includes the following steps:

[0052] Step S11, forming a base, the base comprising a substrate 20, a stacked structure 22 located on the substrate 20, and a mask layer 23 located on the stacked structure 22, wherein the mask layer 23 has an etching window 231 penetrating the mask layer 23 in a direction perpendicular to the substrate 20, as shown in FIG. Figure 2B shown.

[0053] Optionally, the specific steps of forming the substrate include:

[0054] providing a substrate 20;

[0055] Alternately depositing support layers and sacrificial layers on the surface of the substrate 20 to form the stacked structure 22;

[0056] forming a mask layer 23 on the surface of the stacked structure 22;

[0057] The mask layer 23 is patterned to form an etching window 231 in the mask layer 23 that passes through the mask layer 23 in a direction perpendicular to the substrate 20 .

[0058] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This embodiment is described using a silicon substrate as an example. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 has a plurality of capacitor contacts 21 arranged in an array. The capacitor contacts 21 may be made of a conductive metal material, such as tungsten.

[0059] Optionally, the specific steps of forming the stacking structure 22 include:

[0060] Depositing a bottom support layer 221 on the surface of the substrate 20;

[0061] Depositing a first sacrificial layer 222 on the surface of the bottom support layer 221;

[0062] Depositing an intermediate supporting layer 223 on the surface of the first sacrificial layer 222;

[0063] Depositing a second sacrificial layer 224 on the surface of the intermediate supporting layer 223;

[0064] A top supporting layer 225 is deposited on the surface of the second sacrificial layer 224 .

[0065] Specifically, the bottom support layer 221, the first sacrificial layer 222, the middle support layer 223, the second sacrificial layer 224, and the top support layer 225 can be sequentially deposited on the surface of the substrate 20 in a direction perpendicular to the surface of the substrate 20 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the stacked structure 22. The above is merely an example, and those skilled in the art can select the specific number of support layers and sacrificial layers to be deposited based on actual needs, such as factors such as the height of the capacitor to be formed.

[0066] Optionally, the material of the support layer includes a nitride material, and the material of the sacrificial layer includes an oxide material.

[0067] For example, the bottom support layer 221 , the middle support layer 223 and the top support layer 225 are made of the same material, such as silicon nitride; the first sacrificial layer 222 and the second sacrificial layer 224 are also made of the same material, such as silicon dioxide.

[0068] After forming the stacked structure 22, the mask layer 23 is deposited on the top surface of the stacked structure 22 (i.e., the surface of the stacked structure 22 facing away from the substrate 20). The material of the mask layer 23 can be a hard mask material, such as polysilicon; or an organic mask material, such as carbon. Then, a patterned photoresist layer 24 is formed on the surface of the mask layer 23. The photoresist layer 24 has an opening 241 that exposes the mask layer 23, as shown in FIG. Figure 2A Then, a dry etching process may be used to etch the mask layer 23 along the opening 241 to form an etching window 231 in the mask layer 23 exposing the stacked structure (i.e., the etching window 231 penetrates the mask layer 23 along a direction perpendicular to the surface of the substrate 20), as shown. Figure 2B shown.

[0069] Step S12, etching the stacked structure 22 along the etching window 231 to form a capacitor hole 25 that penetrates the stacked structure 22 in a direction perpendicular to the substrate 20, as shown in FIG. Figure 2C shown.

[0070] Optionally, the specific steps of etching the stack structure 22 along the etching window 231 include:

[0071] The stacked structure 22 is etched along the etching window 231 using a first dry etching process.

[0072] Specifically, the stacked structure 22 can be etched vertically downward along the etched window 231 using a first dry etching process to form the capacitor hole 25 that penetrates the stacked structure 22 in a direction perpendicular to the substrate 20 and exposes the capacitor contact 21 in the substrate 20. After removing the photoresist layer 24, the following is obtained: Figure 2C The structure shown.

[0073] Step S13, forming a conductive layer 26 that fills the capacitor hole 25 and the etching window 231 and covers the top surface of the mask layer 23, as shown in FIG. Figure 2D shown.

[0074] Specifically, after forming the capacitor hole 25, in order to fully fill the capacitor hole 25 and avoid generating gaps, an atomic layer deposition process can be used to deposit a conductive material to form a conductive layer 26 that fills the capacitor hole 25 and the etched window 231 and covers the top surface of the mask layer 23. The material of the conductive layer 26 can be, but is not limited to, TiN.

[0075] In this specific embodiment, after forming the capacitor hole 25, the mask layer 23 is not removed, but the capacitor hole 25 is first filled, thereby avoiding the problem of abnormal increase in the characteristic size of the capacitor hole 25 caused by subsequent processes, such as the process of removing the mask layer 23.

[0076] Step S14, removing the conductive layer 26 and the mask layer 23 on the top surface of the stacked structure 22, and the conductive layer 26 remaining in the capacitor hole 25 forms a lower electrode 27, as shown in FIG. Figure 2F shown.

[0077] Optionally, the specific steps of removing the conductive layer 26 and the mask layer 23 on the top surface of the stacked structure 22 include:

[0078] The conductive layer 26 covering the top surface of the mask layer 23 and the etching window 231 is removed to expose the mask layer 23. Figure 2E As shown;

[0079] The mask layer 23 is removed.

[0080] In order to facilitate the impact on the conductive layer 26 filled in the capacitor hole 25 during the process of removing the mask layer 23, this specific embodiment adopts a step-by-step removal method, first removing the conductive layer 26 covering the top surface of the mask layer 23 and the etching window 231, and then removing the mask layer 23.

[0081] Optionally, the specific steps of removing the conductive layer 26 covering the top surface of the mask layer 23 and within the etching window 231 include:

[0082] A second dry etching process is used to remove the conductive layer 26 covering the top surface of the mask layer 23 and the etching window 231 .

[0083] Optionally, the specific steps of removing the conductive layer 26 covering the top surface of the mask layer 23 and within the etching window 231 include:

[0084] A second dry etching process is used to remove the conductive layer 26 covering the top surface of the mask layer 23 and the etching window 231 , and to remove a portion of the mask layer 23 .

[0085] Optionally, the method for forming the semiconductor structure includes:

[0086] The etching parameters of the second dry etching process are controlled so that the top surface of the remaining conductive layer 26 is flush with the top surface of the stacked structure 22 .

[0087] Optionally, the etching parameters include etching time.

[0088] Specifically, the second dry etchant used in the second dry etching process can be selected so that the etching rate of the second dry etchant on the conductive layer 26 is greater than the etching rate of the second dry etchant on the mask layer 23, and the specific values ​​of the etching rate of the second dry etchant on the conductive layer 26 and the specific values ​​of the etching rate of the second dry etchant on the mask layer 23 are predetermined. During the etching process, the amount of the conductive layer 26 etched away can be precisely controlled by controlling the etching time, so that the top surface of the remaining conductive layer 26 is flush with the top surface of the stacked structure 22, thereby avoiding damage to the conductive layer 26 inside the capacitor hole 25 and ensuring the integrity of the morphology of the lower electrode 27 formed subsequently.

[0089] Those skilled in the art can also control other etching parameters to make the top surface of the remaining conductive layer 26 flush with the top surface of the stacked structure 22, such as adjusting the type of the second dry etchant and / or the flow rate of the second dry etchant, which is not limited in this specific embodiment.

[0090] Optionally, the etching selectivity ratio of the second dry etchant used in the second dry etching process to the conductive layer 26 and the mask layer 23 is greater than 2, for example, may be 3, 5, 8, 10 or 20.

[0091] Optionally, the material of the conductive layer 26 includes TiN, and the material of the mask layer 23 includes polysilicon.

[0092] Optionally, the second dry etchant used in the second dry etching process includes a mixed gas of Cl 2 and BCl 3 .

[0093] Specifically, when the material of the conductive layer 26 includes TiN and the material of the mask layer 23 includes polysilicon, selecting a mixed gas including Cl2 and BCl3 as the second dry etchant can effectively improve the etching selectivity between the conductive layer 26 and the mask layer 23, thereby being able to fully remove the top surface of the mask layer 23 and the conductive layer 26 within the etching window 231.

[0094] Optionally, the specific steps of removing the mask layer 23 include:

[0095] The mask layer 23 is removed by a third dry etching process.

[0096] Optionally, the etching selectivity ratio of the third dry etchant used in the third dry etching process to the mask layer 23 and the conductive layer 26 is greater than 10, for example, may be 15, 20, 30, 50 or 100.

[0097] Optionally, the etching selectivity of the third dry etchant to the mask layer 23 and the conductive layer 26 is greater than the etching selectivity of the second dry etchant to the conductive layer 26 and the mask layer 23 .

[0098] Optionally, the third dry etchant used in the third dry etching process includes a mixed gas of HBr and Cl 2 .

[0099] Specifically, in order to avoid damaging the lower electrode 27 during the removal of the remaining mask layer 23, it is necessary to control the etching selectivity of the third dry etchant to the mask layer 23 and the conductive layer 26 to be greater than the etching selectivity of the second dry etchant to the conductive layer 26 and the mask layer 23. For example, when the conductive layer 26 is made of TiN and the mask layer 23 is made of polysilicon, a mixed gas including HBr and Cl2 is selected as the third dry etchant to fully remove the mask layer 23 while not damaging the lower electrode 27 in the capacitor hole 25.

[0100] Optionally, after removing the mask layer 23, the following steps are further included:

[0101] The top surface of the stacked structure 22 and the top surface of the lower electrode 27 are cleaned.

[0102] Specifically, in order to avoid the influence of the polymer produced during the etching of the mask layer 23 or the residual third dry etchant on subsequent processes, such as the influence on the subsequent deposition of the dielectric layer and the upper electrode, after etching the mask layer 23, deionized water can be used to clean the top surface of the stacked structure 22 and the top surface of the lower electrode 27 to remove residual impurities.

[0103] Afterwards, a dry etching process may be used to remove part of the top support layer 225 to expose the second sacrificial layer 224; then, a wet etching process may be used to remove all of the second sacrificial layer 224; then, a part of the intermediate support layer 223 may be etched away to expose the first sacrificial layer 222; after the wet etching process is used to remove all of the first sacrificial layer 222, the following is obtained. Figure 2G Next, a dielectric layer 28 is deposited on the surface of the lower electrode 27, the surface of the remaining top support layer 225, the surface of the remaining middle support layer 223, and the surface of the bottom support layer 221, and an upper electrode 29 is deposited on the surface of the dielectric layer 28. Then, a conductive filling layer 30 is formed to cover the surface of the upper electrode 29 and fill the recess in the upper electrode 29, forming a structure as shown in FIG. Figure 2HThe columnar capacitor shown in FIG. The dielectric layer 28 may be made of an oxide material with a high dielectric constant. The upper electrode 29 may be made of the same material as the lower electrode 27, such as TiN. The conductive filling layer 30 may be made of polysilicon.

[0104] Furthermore, this specific embodiment also provides a capacitor array structure, which is formed by any of the above-mentioned methods for forming a capacitor array structure. Figure 3 Schematic diagram of a capacitor array structure in a specific embodiment of the present invention.

[0105] The capacitor array structure and formation method provided in this specific embodiment are such that, after forming a conductive layer that fills the capacitor holes and covers the top surface of the mask layer, the mask layer is removed, thereby avoiding an abnormal increase in the characteristic size of the capacitor holes during the removal of the mask layer, ensuring the characteristic size of the formed lower electrode, and improving the electrical performance of the capacitor array structure.

[0106] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a capacitor array structure, characterized in that: The steps include: forming a base, the base comprising a substrate, a stacked structure located on the substrate, and a mask layer located on the stacked structure, wherein the mask layer has an etching window penetrating the mask layer in a direction perpendicular to the substrate; Etching the stack structure along the etching window to form a capacitor hole penetrating the stack structure in a direction perpendicular to the substrate; forming a conductive layer that fills the capacitor hole and the etching window and covers the top surface of the mask layer; Using a second dry etching process to remove the conductive layer covering the top surface of the mask layer and within the etching window to expose the mask layer; The mask layer is removed; the conductive layer remaining in the capacitor hole forms a lower electrode; The etching parameters of the second dry etching process are controlled so that the top surface of the remaining conductive layer is flush with the top surface of the stacked structure.

2. The method for forming a capacitor array structure according to claim 1, wherein: The specific steps of forming the substrate include: providing a substrate; Alternatingly depositing support layers and sacrificial layers on the surface of the substrate to form the stacked structure; forming a mask layer on the surface of the stacked structure; The mask layer is patterned to form an etching window in the mask layer that penetrates the mask layer along a direction perpendicular to the substrate.

3. The method for forming a capacitor array structure according to claim 2, wherein: The specific steps of forming the stacking structure include: depositing a bottom support layer on the surface of the substrate; Depositing a first sacrificial layer on the surface of the bottom support layer; depositing an intermediate supporting layer on the surface of the first sacrificial layer; depositing a second sacrificial layer on the surface of the intermediate supporting layer; A top supporting layer is deposited on the surface of the second sacrificial layer.

4. The method for forming a capacitor array structure according to claim 2, wherein: The material of the support layer includes a nitride material, and the material of the sacrificial layer includes an oxide material.

5. The method for forming a capacitor array structure according to claim 1, wherein: The specific steps of etching the stacked structure along the etching window include: The stacked structure is etched along the etching window using a first dry etching process.

6. The method for forming a capacitor array structure according to claim 1, wherein: A second dry etching process is used to remove the conductive layer covering the top surface of the mask layer and the etching window, and a portion of the mask layer is removed.

7. The method for forming a capacitor array structure according to claim 1, wherein: The etching parameters include etching time.

8. The method for forming a capacitor array structure according to claim 1 or 6, wherein: The etching selectivity ratio of the second dry etchant used in the second dry etching process to the conductive layer and the mask layer is greater than 2.

9. The method for forming a capacitor array structure according to claim 1 or 6, wherein: The conductive layer is made of TiN, and the mask layer is made of polysilicon.

10. The method for forming a capacitor array structure according to claim 1 or 6, wherein: The second dry etchant used in the second dry etching process includes a mixed gas of Cl 2 and BCl 3 .

11. The method for forming a capacitor array structure according to claim 10, wherein: The specific steps of removing the mask layer include: The mask layer is removed by a third dry etching process.

12. The method for forming a capacitor array structure according to claim 11, wherein: The etching selectivity ratio of the third dry etchant used in the third dry etching process to the mask layer and the conductive layer is greater than 10.

13. The method for forming a capacitor array structure according to claim 12, wherein: An etching selectivity ratio of the third dry etchant to the mask layer and the conductive layer is greater than an etching selectivity ratio of the second dry etchant to the conductive layer and the mask layer.

14. The method for forming a capacitor array structure according to claim 12, wherein: The third dry etchant used in the third dry etching process includes a mixed gas of HBr and Cl 2 .

15. The method for forming a capacitor array structure according to claim 1, wherein: After removing the mask layer, the method further includes the following steps: The top surface of the stacked structure and the top surface of the lower electrode are cleaned.

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