A wire break detection circuit for isolation capacitor interconnection binding wires used in digital isolators

Abstract

The present invention provides an isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator, comprising: an isolator circuit; it comprises a transmitter and a receiver, the isolation capacitor at the output end of the transmitter is connected to the isolation capacitor at the input end of the receiver through a first binding line and a second binding line respectively; the transmitter comprises a Schmitt trigger, a modulator, a transmission driver A, a transmission driver B, a logic AND gate A and a logic AND gate B; the receiver comprises a first switch tube, a second switch tube, an amplifier and demodulator and a driver; and also comprises an interface and test circuit, the input end of which is connected to a clock signal CLK and a data signal DATA, and the output end is respectively connected to the input end of the logic AND gate A and the logic AND gate B, and the gates of the first switch tube and the second switch tube. The present invention can test the problem of disconnection of the isolation capacitor interconnection binding line on a single side during mass production testing to screen out defective products with such problems and avoid uncertain consequences.

Description

Technical Field

[0001] The invention relates to the technical field of digital isolator chips, and in particular to an isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator. Background Art

[0002] Among the existing digital isolator chips, most use capacitor isolation. Figure 1 As shown in the figure, a unidirectional channel is used as an example. A digital isolator channel usually contains two bare cores, bare core 1 is the transmitter, and bare core 2 is the receiver. The isolation capacitor is integrated on bare core 1 and bare core 2. The two isolation capacitors are connected in series through binding wires inside the capacitor isolator chip (such as C1_P and C2_P in series, C1_N and C2_N in series). In order to provide signal reliability and anti-interference ability, differential transmission is usually used for signal transmission (such as C1_P and C1_N form a differential transmitter, and C2_P and C2_N form a differential receiver). After the input signal IN is modulated by the TX driver, it is transmitted to C2_P and C2_N through C1_P and C1_N, and then amplified and demodulated by RX and output from OUT.

[0003] However, in the current solution, if a single wire of the interconnection binding wire of the isolation capacitor is broken, mass production testing cannot effectively screen out defective products. Figure 2 As shown, the transmitter 10 includes an input Schmitt trigger 101, an ON / OFF-KEY modulation 102, a high frequency oscillator 103, and a transmission driver module 104. The input signal is shaped by the Schmitt trigger 101, modulated into an OOK signal by the ON / OFF-KEY modulation 102, and driven to two differential isolation capacitors by the transmission driver module 104. The receiver 20 includes an amplifier and demodulator 105 and a driver 106; the weak signal received from the isolation capacitor is amplified and demodulated by the amplifier and demodulator 105, the signal is restored, and then driven by the driver 106 and output. L1 and L2 are the interconnecting binding wires of the isolation capacitors of the two isolator bare cores. Due to the inevitable possibility of wire breakage in the packaging manufacturing process, if L1 and L2 are broken at the same time, the signal cannot be transmitted normally, and the conventional mass production final test can screen it out; if one of the binding wires L1 and L2 is broken, it means that the amplitude of the input signal is halved. Since the receiving side has a higher gain, the signal may still be demodulated normally. In this way, the ordinary mass production final test method cannot screen out this type of defective products, resulting in certain risks on the client side. Summary of the invention

[0004] In view of this, an embodiment of the present application provides an isolation capacitor interconnect binding line break detection circuit for a digital isolator, which can perform special tests on the isolation capacitor interconnect binding line break problem on a single side during mass production testing to screen out defective products with such problems and avoid uncertain consequences.

[0005] The embodiment of the present application provides the following technical solution: an isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator, comprising: an isolator circuit, an interface and a test circuit;

[0006] The isolator circuit includes a transmitter and a receiver, and an isolation capacitor at an output end of the transmitter and an isolation capacitor at an input end of the receiver are connected via a first binding wire and a second binding wire, respectively;

[0007] The transmitter includes a Schmitt trigger, a modulator, a transmission driver A, a transmission driver B, and a logic AND gate A and a logic AND gate B; an input signal is connected to the input of the Schmitt trigger, an output of the Schmitt trigger is connected to the input of the modulator, an output of the modulator is connected to the first input terminals of the logic AND gate A and the logic AND gate B respectively, output terminals of the logic AND gate A and the logic AND gate B are connected to the input terminals of the transmission driver A and the transmission driver B respectively, and output terminals of the transmission driver A and the transmission driver B are connected to the isolation capacitors at the output terminals of the transmitter respectively;

[0008] The receiver includes a first switch tube, a second switch tube, an amplifier and demodulator, and a driver, wherein the drains of the first switch tube and the second switch tube are respectively connected to the isolation capacitor at the input end of the receiver, the sources are respectively connected to the two input ends of the amplifier and demodulator, and the output end of the amplifier and demodulator is connected to the driver;

[0009] The input end of the interface and test circuit is connected to the clock signal CLK and the data signal DATA, and the output end of the interface and test circuit is respectively connected to the second input end of the logic AND gate A and the logic AND gate B, and the gate of the first switch tube and the second switch tube;

[0010] When the circuit is in normal working mode, all outputs of the interface and the test circuit are signal 1;

[0011] When the circuit is in test mode, when testing is performed on the transmitter side, the two output ends of the interface and the test circuit on the receiver side both output signal 1 by default, and the two output ends of the interface and the test circuit on the transmitter side respectively output signal 1 and signal 0 alternately twice, and the single-ended channels corresponding to the two differential binding lines are respectively selected, and the test is performed from the non-default value of the TX input isolator, and the disconnection of the first binding line and the second binding line is judged according to whether the output of the receiver is normal; when testing is performed on the receiver side, the two output ends of the interface and the test circuit on the transmitter side both output signal 1 by default, and the two output ends of the interface and the test circuit on the receiver side respectively output signal 1 and signal 0 alternately twice, and the single-ended channels corresponding to the two differential binding lines are respectively selected, and the test is performed from the non-default value of the TX input isolator, and the disconnection of the first binding line and the second binding line is judged according to whether the output of the receiver is normal.

[0012] According to an embodiment, the transmitter further comprises a high frequency oscillator connected to an input terminal of the modulator.

[0013] According to an embodiment, the receiver further includes a first resistor and a second resistor, wherein the first resistor and the second resistor are respectively connected to two input terminals of the amplifier and demodulator.

[0014] According to an embodiment, the first switch tube and the second switch tube are any one of an NMOS tube, a PMOS tube, and a transmission gate.

[0015] According to an embodiment, when the circuit is in the test mode, communication is performed in a manner including IIC or SPI.

[0016] Compared with the prior art, the detection circuit of the embodiment of the present invention enters the test mode in the final test of mass production, and can control the signal transmission of each binding line path on the transmitting side and the receiving side respectively, perform signal transmission test, and determine the defective products with broken wires. The defective chip has poor reliability and poor anti-interference ability, which may bring potential uncertain risks. The present invention performs testability design of the circuit at the design end, and can easily screen out defective products during the final test of mass production, which greatly improves the test screening efficiency, improves the reliability of the terminal product, and reduces the risk of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the structure of a single-channel capacitive digital isolator;

[0019] Figure 2 It is the circuit schematic diagram of a single-channel capacitive digital isolator;

[0020] Figure 3 It is a schematic diagram of the structure of a disconnection detection circuit for an isolation capacitor interconnection binding line according to an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of an isolation interface chip that is sealed together with other bare cores according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments, and the technical scheme of the present invention will be clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] An embodiment of the present invention provides an isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator, comprising: an isolator circuit, an interface and a test circuit;

[0025] The isolator circuit includes a transmitter and a receiver, and an isolation capacitor at an output end of the transmitter and an isolation capacitor at an input end of the receiver are connected via a first binding wire and a second binding wire, respectively;

[0026] The transmitter includes a Schmitt trigger, a modulator, a high-frequency oscillator, a transmission driver A, a transmission driver B, and also includes a logic AND gate A and a logic AND gate B; an input signal is connected to the input of the Schmitt trigger, the output of the Schmitt trigger and the high-frequency oscillator are both connected to the input of the modulator, the output of the modulator is respectively connected to the first input terminals of the logic AND gate A and the logic AND gate B, the output terminals of the logic AND gate A and the logic AND gate B are respectively connected to the input terminals of the transmission driver A and the transmission driver B, and the output terminals of the transmission driver A and the transmission driver B are respectively connected to the isolation capacitors at the output terminals of the transmitter;

[0027] The receiver includes a first switch tube, a second switch tube, an amplifier and demodulator and a driver, a first resistor and a second resistor, the drains of the first switch tube and the second switch tube are respectively connected to the isolation capacitor at the input end of the receiver, and the sources are respectively connected to the two input ends of the amplifier and demodulator, the first resistor and the second resistor are respectively connected to the two input ends of the amplifier and demodulator, and the output end of the amplifier and demodulator is connected to the driver;

[0028] The input end of the interface and test circuit is connected to the clock signal CLK and the data signal DATA, and the output end of the interface and test circuit is respectively connected to the second input end of the logic AND gate A and the logic AND gate B, and the gate of the first switch tube and the second switch tube;

[0029] When the circuit is in normal working mode, all outputs of the interface and the test circuit are signal 1;

[0030] When the circuit is in test mode, when testing on the transmitter side, the two output ends of the interface and the test circuit on the receiver side both output signal 1 by default, and the two output ends of the interface and the test circuit on the transmitter side output signal 1 and signal 0 alternately twice, respectively, and the single-ended channels corresponding to the two differential binding lines are selected respectively, and the test is performed from the non-default value of the TX input isolator. According to whether the output of the receiver is normal, the disconnection of the first binding line and the second binding line is judged; when testing on the receiver side, the two output ends of the interface and the test circuit on the transmitter side both output signal 1 by default, and the two output ends of the interface and the test circuit on the receiver side output signal 1 and signal 0 alternately twice, respectively, and the single-ended channels corresponding to the two differential binding lines are selected respectively, and the test is performed from the non-default value of the TX input isolator. According to whether the output of the receiver is normal, the disconnection of the first binding line and the second binding line is judged. If there is only TX or RX on one side, it is only necessary to control TX or RX separately to perform disconnection detection of the interconnection binding line of the isolation capacitor on the single side.

[0031] The present invention provides a circuit that can screen out the defective chip during mass production final test. In specific implementation, it can be applied to a variety of connection structures and has stronger versatility. A specific isolator circuit diagram including the test circuit is shown in FIG. Figure 3 As shown, the figure takes two digital isolator channels, one positive and one negative, as an example. The capacitive digital isolator comprises two bare cores 100, each bare core comprises a transmitter 110, a receiver 120, and a test circuit 108.

[0032] The transmitter 110 includes a Schmitt trigger 101, an ON / OFF-KEY modulator 102, a high-frequency oscillator 103, a transmitting driver 104A and a transmitting driver 104B, and a logic AND gate 107A and a logic AND gate 107B. The input signal VIN is connected to the input of the Schmitt trigger 101, the output of the Schmitt trigger 101 is connected to the input of the modulator 102, the output of the high-frequency oscillator 103 is connected to another input of the modulator 102, the output of the modulator 102 is connected to the input ends of two logic AND gates, respectively, the other input of the logic AND gate 107A and the logic AND gate 107B is connected to the output of the test and interface circuit 108, the outputs of the logic AND gate 107A and the logic AND gate 107B are connected to the inputs of two TX drivers, respectively, the transmitting driver 104A and the transmitting driver 104B, and the outputs of the transmitting driver 104A and the transmitting driver 104B are connected to the input ends of two isolation capacitors.

[0033] The receiver 120 includes a first switch tube, a second switch tube, a first resistor R1, a first resistor R2, an amplifier and demodulator 105, a driver 106 and other circuits. The first switch tube and the second switch tube of this embodiment are both NMOS tubes. The input signal comes from an isolation capacitor, and the isolation capacitor input differential signal is connected to the drain end of the NMOS tube M1 and the NMOS tube M2 respectively. The source end of the NMOS tube M1 and the NMOS tube M2 are respectively connected to the two input ends of the amplifier and demodulator 105, and the gate of the NMOS tube M1 and the NMOS tube M2 are respectively connected to the test and interface circuit 108; the first resistor R1 and the first resistor R2 are respectively connected to the two input ends of the amplifier and demodulator 105. The output of the amplifier and demodulator 105 is connected to the input end of the driver 106, and the output of the driver 106 is connected to VOUT.

[0034] The test and interface circuit 108 is connected to the interface pins DATA and CLK.

[0035] The two bare cores 100 are connected via four package binding interconnect wires L1, L2, L3, and L4.

[0036] like Figure 3As shown, the input signal VIN is shaped by the Schmitt trigger 101, and the high-frequency oscillator 103 provides a high-frequency carrier signal. The input signal and the high-frequency carrier signal are modulated into OOK signals in the modulator 102, and then logically ANDed with the test signal through the logic AND gate 107A and the logic AND gate 107B, and driven to two differential isolation capacitors by the transmitting driver 104A and the transmitting driver 104B respectively. When the isolation capacitor interconnection binding lines L1 and L2 are not broken, the differential signal is transmitted to the input end of RX, and the amplifier and demodulator 105 amplifies and demodulates the input signal, and outputs it to the driver 106 to drive the external load. Under normal working conditions, output port A=B=1, logic AND gate 107A and logic AND gate 107B pass the input signal directly, and the test circuit does not affect normal working; when testing, output port A and output port B can be configured to control the TX transmission signal; under normal working conditions, output port C=D=1, NMOS tube M1 and NMOS tube M2 are always on, and there is no effect on signal transmission. When entering the test mode, the output port C and D signals will be controlled by the test circuit to control RX.

[0037] During the final test of mass production, it is necessary to enter the test mode. Usually, IIC or SPI can be used for communication to control the internal circuit. It can be multiplexed with pins such as EN or NC, where CLK is the clock signal and DATA is the data signal. The TX transmitter can be tested by gating, and the RX receiver can be tested by gating. Taking the bare core on the left as an example, after the test control signal enters the test and interface circuit 108, the connectivity of the two TX paths is tested respectively. Considering that it is easier to test and screen if both binding lines are broken or normal, the main consideration is the case where one of the binding lines is broken. When the output port A=1, B=0, the transmit driver 104A outputs a normal drive signal, and the transmit driver 104B has no signal output. If L1 happens to be broken, there is no signal input to the two differential inputs of RX, which means that the chip is defective; if L1 is normal and L2 is broken, RX outputs normally. Continue polling, output port A = 0, B = 1, transmit driver 104A has no output, transmit driver 104B outputs normally, if L1 is disconnected, RX demodulates normally; if L2 is disconnected, RX has no output, and defective products can be accurately screened out. By controlling the output port C and D signals, the receiver 120 can be detected for disconnection. Considering the case where one of L3 and L4 is disconnected, if L3 is disconnected and L4 is normal, when the output port C = 1, D = 0, the TX signal on the right cannot be transmitted to RX normally, RX has no output, and defective products can be screened out; if L3 is normal and L4 is disconnected, when C = 0, D = 1, the TX signal on the right cannot be transmitted to RX normally, RX has no output, and defective products can also be screened out.

[0038] Figure 3The example of two channels, one positive and one negative, is given. The present invention can also be applied to other channel configurations, such as all the channels on the left are transmitters, or all are receivers. It can also be applied to other sealing situations. In another embodiment, Figure 4 As shown, two isolator bare cores are sealed together with another other functional bare core 200 (such as RS485 or CAN) to form an isolated CAN or an isolated RS485. Only the control test of the digital isolator bare core on the far left can detect the interconnection breakage of TX and RX, which is efficient and easy to screen out defective products.

[0039] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A disconnection detection circuit for an isolation capacitor interconnection binding line of a digital isolator, characterized in that: include: Isolator circuits, interfaces and test circuits; The isolator circuit includes a transmitter and a receiver, and an isolation capacitor at an output end of the transmitter and an isolation capacitor at an input end of the receiver are connected via a first binding wire and a second binding wire, respectively; The transmitter includes a Schmitt trigger, a modulator, a transmission driver A, a transmission driver B, and a logic AND gate A and a logic AND gate B; an input signal is connected to the input of the Schmitt trigger, an output of the Schmitt trigger is connected to the input of the modulator, an output of the modulator is connected to the first input terminals of the logic AND gate A and the logic AND gate B respectively, output terminals of the logic AND gate A and the logic AND gate B are connected to the input terminals of the transmission driver A and the transmission driver B respectively, and output terminals of the transmission driver A and the transmission driver B are connected to the isolation capacitors at the output terminals of the transmitter respectively; The receiver includes a first switch tube, a second switch tube, an amplifier and demodulator, and a driver, wherein the drains of the first switch tube and the second switch tube are respectively connected to the isolation capacitor at the input end of the receiver, the sources are respectively connected to the two input ends of the amplifier and demodulator, and the output end of the amplifier and demodulator is connected to the driver; The input end of the interface and test circuit is connected to the clock signal CLK and the data signal DATA, and the output end of the interface and test circuit is respectively connected to the second input end of the logic AND gate A and the logic AND gate B, and the gate of the first switch tube and the second switch tube; When the circuit is in normal working mode, all outputs of the interface and the test circuit are signal 1; When the circuit is in test mode, when testing is performed on the transmitter side, the interface on the receiver side and the two output ends of the test circuit both output signal 1 by default, and the interface on the transmitter side and the two output ends of the test circuit respectively output signal 1 and signal 0 twice alternately, and the single-ended channels corresponding to the two differential binding lines are respectively selected, and the test is performed from the non-default value of the TX input isolator, and the disconnection of the first binding line and the second binding line is judged according to whether the output of the receiver is normal; When testing on the receiver side, the two output ends of the interface and the test circuit on the transmitter side both output signal 1 by default, and the two output ends of the interface and the test circuit on the receiver side output signal 1 and signal 0 alternately twice, respectively, and the single-ended channels corresponding to the two differential binding lines are selected respectively. The test is performed from the non-default value of the TX input isolator, and the disconnection status of the first binding line and the second binding line is judged based on whether the output of the receiver is normal.

2. The isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator according to claim 1, characterized in that: The transmitter further comprises a high frequency oscillator connected to an input of the modulator.

3. The isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator according to claim 1, characterized in that: The receiver further includes a first resistor and a second resistor, wherein the first resistor and the second resistor are respectively connected to two input terminals of the amplifier and demodulator.

4. The isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator according to claim 1, characterized in that: The first switch tube and the second switch tube are any one of an NMOS tube, a PMOS tube, and a transmission gate.

5. The isolation capacitor interconnection binding line disconnection detection circuit for a digital isolator according to claim 1, characterized in that: When the circuit is in test mode, communication is performed using methods including IIC or SPI.

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