Signal processing device and method for digital pendulum inclinometer

Abstract

The embodiment of this specification provides a signal processing device and method for a digital pendulum inclinometer, wherein the device includes: a sensor circuit, an ARM circuit and a logic gate circuit; the sensor circuit converts phase data into an analog sine wave through a digital-to-analog converter, performs signal modulation, and then sends the modulated signal to the ARM circuit; the ARM circuit receives the modulated signal, performs analog-to-digital conversion on the modulated signal, and then performs noise reduction processing through a singular value decomposition algorithm; the logic gate circuit is connected to the ARM circuit, and is used to demodulate the noise-reduced signal, sample the demodulated signal, and then output it. The present invention replaces most of the analog circuits with digital circuits, avoids some internal circuit noise, and improves the signal-to-noise ratio through a noise reduction algorithm. The present invention also changes the previous multi-device discrete signal processing method into an integrated integrated processing method, which can reduce hardware costs, improve stability, and facilitate transportation, operation and maintenance.

Description

Technical Field

[0001] This document relates to the field of signal processing technology, and in particular to a signal processing device and method for a digital pendulum inclinometer. Background Art

[0002] In order to observe solid tides and earthquakes, it is necessary to obtain continuous information on the state of topographic deformation. A pendulum inclinometer is a widely used instrument for observing topographic deformation. Usually, when its sensor senses changes in the ground surface, it converts the ground motion signal into a digital signal through signal demodulation and type conversion.

[0003] Usually the signal processing of the pendulum inclinometer is divided into two parts: demodulation and acquisition. The two processes of signal processing are completed by two parts of circuits, namely analog circuits and digital circuits, which are usually two separate groups of circuits, two devices, and some peripheral devices. In order to extract weak signals from background noise, the method usually adopted is to amplify the signal and filter it, then demodulate it, and finally convert it into a digital signal.

[0004] The existing instrument signal processing method is mainly based on analog circuits, especially before the signal type conversion, it is completely analog circuit processing. The characteristics of full analog circuits are simple circuit structure, low cost, obvious delay and internal circuit noise. The reason for using full analog methods in the past is that the inclinometer data does not require a high sampling rate and the control of hardware costs. However, in order to design observation equipment with higher reliability and stability, and to obtain higher quality observation data, the delay and noise problems must be fundamentally solved, and the signal processing scheme of the pendulum inclinometer must be redesigned.

[0005] Specific issues that need to be addressed:

[0006] 1. Signal delay issues, including phase lag caused by amplifiers and capacitors;

[0007] 2. Noise problems, including internal circuit noise and noise introduced by lines and interfaces;

[0008] 3. The components are scattered, the lines are complicated, and the sensors, data collectors and other equipment are separately packaged, which is inconvenient for transportation and maintenance, and adds additional interference. Summary of the invention

[0009] The purpose of this method is to propose a signal processing device and method with high digitization and integration, combining transducer and data acquisition. Because most analog circuits are replaced by digital circuits, the internal noise and delay of the circuit can be reduced, and the interference from the external environment of the device can be reduced to a great extent. In addition, the signal processing circuit adopts an integrated, monolithic integrated design, which can make the instrument smaller and eliminate redundant lines, interfaces, etc., which not only reduces transportation costs but also reduces the difficulty of operation.

[0010] The embodiment of the present invention provides a signal processing device for a digital pendulum inclinometer, characterized by comprising: a sensor circuit, an ARM circuit and a logic gate circuit;

[0011] The sensor circuit is connected to the logic gate circuit and the ARM circuit, converts the phase data into an analog sine wave through a digital-to-analog converter, performs signal modulation, and then sends the modulated signal to the ARM circuit;

[0012] The ARM circuit receives the adjustment signal sent by the sensor circuit, converts the modulated signal into digital form, and performs noise reduction processing using a singular value decomposition algorithm;

[0013] The logic gate circuit is connected to the ARM circuit and is used for demodulating the noise-reduced signal, sampling the demodulated signal and then outputting it.

[0014] An embodiment of the present invention provides a signal processing method for a digital pendulum inclinometer, comprising:

[0015] After the sensor circuit converts the signal type, it uses the AXI bus to save the data to the DDR3 memory. Then the ARM circuit performs noise reduction processing on the data in the memory. The noise reduction processing uses the singular value decomposition algorithm to separate the useful signal and the noise signal, and remove the noise signal.

[0016] The logic gate circuit reads the noise-reduced data in the memory and saves it in the BRAM. The data in the BRAM is kept refreshed in real time and the signal is demodulated.

[0017] The demodulated signal is downsampled and then output.

[0018] By adopting the embodiment of the present invention, a new design of the pendulum inclinometer signal processing circuit is carried out. The control and operation design based on the embedded chip has a high degree of digitization and circuit integration, which greatly reduces noise and delay, and can significantly enhance the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 A schematic diagram of a signal processing device of a digital pendulum inclinometer according to an embodiment of the present invention;

[0021] Figure 2 This is a flow chart of a signal processing method of a digital pendulum inclinometer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0023] Device Embodiment

[0024] The embodiment of the present invention provides a signal processing device for a digital pendulum inclinometer. Figure 1 is a schematic diagram of a signal processing device for a digital pendulum inclinometer according to an embodiment of the present invention. Figure 1 As shown, the signal processing device of the digital pendulum inclinometer according to the embodiment of the present invention specifically includes:

[0025] Sensor circuit 10, ARM circuit 20 and logic gate circuit 30;

[0026] The sensor circuit 10 is connected to the logic gate circuit 30 and the ARM circuit 20, converts the phase data into an analog sine wave through a digital-to-analog converter, performs signal modulation, and then sends the modulated signal to the ARM circuit 20;

[0027] The ARM circuit 20 receives the modulated signal sent by the sensor circuit 10, converts the modulated signal from analog to digital and then performs noise reduction processing using a singular value decomposition algorithm;

[0028] The logic gate circuit 30 is connected to the ARM circuit 20 and is used to demodulate the noise-reduced signal, perform sampling processing on the demodulated signal and then output it.

[0029] The sensor circuit 10 specifically includes: an inverter 12, two digital-to-analog converters 11, and a capacitor 13;

[0030] The inverter 12 is connected in series with one of the digital-to-analog converters 11 and then connected in parallel with the other analog-to-digital converter 11, and the phase data is passed through the two digital-to-analog converters to form two sinusoidal waves with opposite phases and equal amplitudes;

[0031] The capacitor 13 is composed of three parallel capacitor plates. Two sinusoidal waves with opposite phases and equal amplitudes are added to the parallel capacitor plates on both sides. The signal drawn from the middle plate is a modulated wave modulated by the baseband signal and sent to the ARM circuit 20.

[0032] The ARM circuit 20 specifically includes: an analog-to-digital converter 21 and a singular value decomposition processor 26;

[0033] The analog-to-digital converter 21 is used to convert the modulated wave into a digital signal;

[0034] The singular value decomposition processor 26 is used to separate the useful signal and the noise signal of the digital signal, and extract the noise signal to obtain a modulated signal containing only terrain deformation information. The singular value decomposition processor 26 specifically includes: cache 22, DDR323, floating point operator 25 and clock circuit 24;

[0035] Cache 22, used to temporarily store data involved in the calculation;

[0036] DDR323, used to store data sent by the analog-to-digital converter;

[0037] A floating point operator 25, used for performing operations on the data involved in the noise reduction process;

[0038] The SVD clock circuit 24 is used to control the data in the DDR3 to be refreshed in real time.

[0039] The logic gate circuit 30 specifically includes: a BRAM circuit 31, a demodulation circuit, a filtering and downsampling circuit 36, a logic operation circuit and a read-only memory 40;

[0040] The BRAM circuit 31 is used to receive and temporarily store the data sent by the ARM circuit; the BRAM circuit specifically includes: an AXI protocol communication control circuit 32 and a block memory circuit 33; the AXI protocol communication control circuit is used to provide AXI communication protocol support for communication between various circuits; the block memory circuit is used to store the data sent by the ARM circuit.

[0041] The demodulation circuit demodulates the modulated signal obtained after noise reduction, and then uses a low-pass filter to remove high-frequency signals at a rate of 35%;

[0042] The filtering and downsampling circuit 36 ​​samples the signal after low-pass filtering using a cascaded integrator comb filter to reduce the sampling rate and the amount of data;

[0043] The logic operation circuit specifically includes: an adder 39, a multiplier 38 and a subtractor 37, which is used to provide multiplication operations for the demodulation circuit and to provide addition and subtraction operations for the filtering and down-sampling circuit.

[0044] The read-only memory 40 is used for storing the phase data.

[0045] The logic gate circuit further includes: a clock circuit 34, which is used to provide clock pulses for the signal processing device of the entire digital pendulum inclinometer.

[0046] The embodiment of the present invention adopts a direct digital frequency synthesizer (DDS) to generate a sine wave by using a phase accumulator to address the amplitude. The frequency control input causes the phase accumulator to start accumulating, and the phase data and the amplitude have a one-to-one correspondence in the read-only memory (ROM) address. These amplitude data are stored in the accumulator. Figure 1 The DAC in the digital circuit converts it into a continuous analog voltage signal, which is then filtered to obtain a sinusoidal waveform of a specific frequency. This periodic waveform synthesized by digital circuit control is a signal with programmable frequency and amplitude.

[0047] In order to convert the tilt of the pendulum, i.e., the capacitor 13, into a voltage, it is necessary to modulate and demodulate the signal generated by the differential capacitor to extract the signal waveform of the target frequency band. Two sinusoidal waves with opposite phases and equal amplitudes are added to the pendulum capacitor plates. At this time, the signal drawn from the middle plate is a modulated wave modulated by the baseband signal. The modulated wave is converted into a digital signal by ADC and then filtered and denoised by SVD. The matrix representing the signal is subjected to SVD, and only the first k larger singular values ​​are retained, thereby retaining the main information of the image. This operation will greatly reduce the memory requirements for image storage. This can also be used for image denoising, because small singular values ​​generally correspond to noise.

[0048] The digital signal data obtained after noise reduction is multiplied by the carrier data in the read-only memory through a multiplier, and then a low-pass filter is used. This process is the demodulation process of the signal, which is mathematically expressed as the signal is multiplied by the carrier again, and then the high-frequency signal is filtered out by a low-pass filter. The entire modulation and demodulation process is mathematically expressed as: original signal * carrier * carrier → low-pass filter = 1 / 4 times the original signal. Therefore, the high-frequency part can be removed by using a low-pass filter, and then a multiplier or an adder is added to multiply it by four times to restore the baseband signal.

[0049] The signal after low-pass filtering is sampled using a cascaded integrator comb filter to reduce the amount of data. After sampling, the position of each frequency component on the spectrum will change. In order to avoid frequency aliasing caused by sampling, a cascaded integrator comb (CIC) filter is used to implement the sampling work. Its implementation in the circuit only requires adders, subtractors, delay circuits, etc., and the hardware cost is low and easy to implement.

[0050] This method has made a new design for the signal processing circuit of the pendulum inclinometer. It is based on the control and operation design of the embedded chip, with a high degree of digitization and circuit integration, which greatly reduces noise and delay, and can significantly enhance the stability and reliability of the system. Compared with the prior art, the technical route proposed by the present invention has a high degree of digitization and extremely fast data processing speed. Using digital circuits to replace most analog circuits can avoid some internal noise in the circuit. The analog circuit interferes with the signal due to the voltage fluctuation in the circuit, while the digital circuit digitizes the signal to avoid the influence of such interference on the signal. In addition, the introduction of the noise reduction algorithm can further improve the signal-to-noise ratio and improve the data quality. The instruction set processor and the logic gate circuit are used for signal processing to realize the parallel operation of the digital signal, and the processing speed is fast. The previous analog circuit connects the various parts of the signal processing in series, which inevitably accumulates the delays generated by each part, and the use of parallel computing can reduce the superposition delay. At the same time, the previous multi-device discrete signal processing method is changed to an integrated integrated processing method, which can reduce hardware costs, improve stability, and facilitate transportation, operation and maintenance.

[0051] By adopting the embodiments of the present invention, the following beneficial effects are achieved:

[0052] Signal processing is based on digital circuits. Different from the previous full analog circuits built on amplifiers, this method uses digital circuits built on FPGAs for signal processing. Except for the sensor circuit and signal conversion circuit, all other circuits are digital circuits.

[0053] Integrated design of sensor transduction, data acquisition and data processing. Different from the previous separate structure of sensor circuit and data acquisition circuit, this method uses the circuit structure design of each functional circuit integrated and single board integrated.

[0054] Singular value decomposition algorithm noise reduction. A new digital noise reduction function is added, which uses the singular value decomposition algorithm to pre-process the signal and improve the signal-to-noise ratio.

[0055] Fully digital demodulation. Different from the previous analog circuits such as phase-locked amplifier circuits, this method uses digital detection and digital demodulation.

[0056] Digital filtering. Unlike the previous amplifier circuit filtering, digital filtering is used. The filtering coefficients and filtering delay of digital filtering are completely controllable, and different types of filters can be realized at low cost. The sampling operation of cascaded integrator comb filter can realize smooth sampling operation and the calculation is simple and easy to implement.

[0057] Parameters such as filtering parameters and sampling frequency can be changed on-site through programming, and the modification of observation mode is very flexible.

[0058] Method Embodiment

[0059] An embodiment of the present invention provides a signal processing method for a digital pendulum inclinometer, comprising:

[0060] After the sensor circuit converts the signal type, the data is saved to the DDR3 memory using the AXI bus, and then the ARM circuit performs noise reduction processing on the data in the memory, wherein the noise reduction processing realizes the separation of useful signals and noise signals through the singular value decomposition algorithm, and removes the noise signal;

[0061] The logic gate circuit reads the noise-reduced data in the memory and saves it in the BRAM. The data in the BRAM is kept refreshed in real time and the signal is demodulated.

[0062] The demodulated signal is downsampled and then output.

[0063] like Figure 2 is a flow chart of a signal processing method for a digital pendulum inclinometer according to an embodiment of the present invention. Figure 2 It can be seen that after the sensor signal is converted into a signal type, the data is saved in the DDR3 memory using the AXI bus, and then the ARM core performs noise reduction processing on the data in the memory. The noise reduction process uses the singular value decomposition algorithm (SVD) to separate the useful signal from the noise signal and remove the noise signal. The data after noise reduction processing is saved in the memory, and the data storage address before and after processing is different, and the data is kept in a real-time refresh state.

[0064] The logic gate circuit core reads the noise-reduced data in the memory and saves it in the BRAM. Like the above memory, the data in the BRAM is kept refreshed in real time. Then the logic gate circuit is used to demodulate the signal. In order to increase the signal processing speed, the signal is calculated in parallel using pipeline and other methods. The ability to perform parallel calculations on data at the hardware level is a major feature of the logic gate circuit.

[0065] The demodulated signal is downsampled and then output. The downsampling / decimation process uses a cascaded integrator comb filter (CIC) for sampling. This process includes two low-pass filtering and two samplings. The low-pass filtering also uses a logic gate circuit digital filter.

[0066] The design of this signal processing method is completed by digital circuits except for the signal type conversion part, including analog-to-digital conversion and digital-to-analog conversion, which are completed by analog circuits. The digital circuit includes a programmable logic gate circuit, namely FPGA, and a processor circuit, namely ARM. The signal noise reduction function is completed by the processor circuit, and the process includes operations such as matrix addition and multiplication, as well as memory reading and writing. The control of the signal type converter, the implementation of the read-only memory, the multiplier, the filter, etc. are all completed by the logic circuit.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal processing device for a digital pendulum inclinometer, characterized in that: include: Sensor circuit, ARM circuit and logic gate circuit; The sensor circuit is connected to the logic gate circuit and the ARM circuit, converts the phase data into an analog sine wave through a digital-to-analog converter, performs signal modulation, and then sends the modulated signal to the ARM circuit; An ARM circuit receives a modulation signal sent by the sensor circuit, performs analog-to-digital conversion on the modulation signal, and then performs noise reduction processing using a singular value decomposition algorithm; The logic gate circuit is connected to the ARM circuit and is used for demodulating the noise-reduced signal, sampling the demodulated signal and then outputting it.

2. The device according to claim 1, characterized in that The sensor circuit specifically includes: an inverter, two digital-to-analog converters, and a capacitor; The inverter is connected in series with one of the digital-to-analog converters and then connected in parallel with the other digital-to-analog converter, and the phase data is passed through the two digital-to-analog converters to form two sinusoidal waves with opposite phases and equal amplitudes; The capacitor is composed of three parallel capacitor plates. The two sinusoidal waves with opposite phases and equal amplitudes are added to the parallel capacitor plates on both sides. The signal drawn from the middle plate is a modulated wave modulated by the baseband signal and sent to the ARM circuit.

3. The device according to claim 2, characterized in that The ARM circuit specifically includes: an analog-to-digital converter and a singular value decomposition processor; The analog-to-digital converter is used to convert the modulated wave into a digital signal; The singular value decomposition processor is used to separate the useful signal and the noise signal of the digital signal, and extract the noise signal to obtain a modulated signal containing only terrain deformation information.

4. The device according to claim 1, characterized in that The logic gate circuit specifically includes: a BRAM circuit, a demodulation circuit, a filtering and downsampling circuit, a logic operation circuit and a read-only memory; A BRAM circuit, used for receiving and temporarily storing data sent by the ARM circuit; The demodulation circuit demodulates the modulated signal obtained after noise reduction, and then uses a low-pass filter to remove high-frequency signals; The filtering and downsampling circuit samples the signal after low-pass filtering using a cascaded integral comb filter to reduce the sampling rate and the amount of data; A logic operation circuit, used for providing operation support for the demodulation circuit and the filtering and down-sampling circuit; A read-only memory is used to store the phase data.

5. The device according to claim 4, characterized in that The logic operation circuit specifically includes: an adder, a multiplier and a subtractor, which are used to provide multiplication operations for the demodulation circuit and provide addition and subtraction operations for the filtering and down-sampling circuit.

6. The device according to claim 4, characterized in that The filtering and downsampling circuit adopts a method of two low-pass filtering and two samplings when performing sampling.

7. The device according to claim 4, characterized in that The BRAM circuit specifically includes: an AXI protocol communication control circuit and a block memory circuit; AXI protocol communication control circuit, used to provide AXI communication protocol support for communication between various circuits; The block memory circuit is used to store the data sent by the ARM circuit.

8. The device according to claim 7, characterized in that The logic gate circuit further comprises: a clock circuit, which is used to provide clock pulses for the signal processing device of the entire digital pendulum inclinometer.

9. The device according to claim 3, characterized in that The singular value decomposition processor specifically includes: cache, DDR3, floating point operator and SVD clock circuit; The cache is used to temporarily store the data involved in the calculation; The DDR3 is used to store data sent by the analog-to-digital converter; The floating point operator is used to perform operations on the data involved in the noise reduction process; The SVD clock circuit is used to control the data in the DDR3 to be refreshed in real time.

10. A signal processing method for a digital pendulum inclinometer, characterized in that: A signal processing device based on a digital pendulum inclinometer according to any one of claims 1 to 9, comprising: After the sensor circuit converts the signal type, it uses the AXI bus to save the data to the DDR3 memory, and then the ARM circuit performs noise reduction processing on the data in the memory, wherein the noise reduction processing separates the useful signal and the noise signal through the singular value decomposition algorithm and removes the noise signal; The logic gate circuit reads the noise-reduced data in the memory and saves it in the BRAM. The data in the BRAM is kept refreshed in real time and the signal is demodulated. The demodulated signal is downsampled and then output.

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