Firmware data loading method, system, device and storage medium

Abstract

The present application discloses a firmware data loading method, system, device and storage medium, which are applied to the field of system-on-chip design technology, including: after the SoC system is powered on, receiving each read instruction sent by the SoC system; when receiving any one read instruction, determining whether the data content specified by the read instruction is cached; if so, feeding back the data content specified by the read instruction in the cache to the SoC system; otherwise, reading the data content in parallel based on N blocks of firmware data memories, arranging the read data and placing it in the cache, and feeding back the data content specified by the read instruction in the cache to the SoC system; wherein each of the N blocks of firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2. Applying the solution of the present application can improve the firmware data reading speed and ensure the reliability of the SoC system.

Description

Technical Field

[0001] The present invention relates to the technical field of system-on-chip design, and in particular to a firmware data loading method, system, device and storage medium. Background Art

[0002] Firmware is the lowest-level software responsible for system operations, typically recording the most basic parameters and operating procedures of each module in a SoC (System on Chip). Firmware data is typically stored in rewritable, non-volatile storage such as Flash. When the SoC system is powered on, the processor core reads the firmware from Flash to perform operations such as hardware initialization and program execution. Therefore, the organization and access method of firmware data affect the stability and startup speed of the SoC system's firmware.

[0003] The speed at which firmware data is read is limited by the data bit width and interface frequency of the Flash chip. The interface frequency of a Flash chip is generally only tens of MHz and, due to chip performance limitations, cannot be increased during system design. Therefore, one current approach is to use multiple Flash chips to splice together and expand the data bit width, thereby increasing the firmware data read speed. The data bit width of a single Flash chip can generally range from 1 bit to 4 bits, while two Flash chips can expand the data bit width to 8 bits. Some designs even splice more Flash chips to achieve a larger bit width. When writing data, the firmware data is split and written to multiple Flash chips according to the data bit width. Another current approach is to store the same firmware data on each Flash chip, achieving redundant backup of the firmware data. This way, if one Flash chip reads the firmware incorrectly, causing the SoC system to fail to boot properly, it can be switched to another Flash chip for re-reading, thus ensuring the reliability of the SoC system.

[0004] In the aforementioned multi-Flash chip splicing solution, since the firmware data is split and stored across multiple Flash chips, each Flash chip must be read in parallel. However, this organization increases the probability of firmware data errors. If a data problem or interface problem occurs in any of the parallel Flash chips, the entire firmware data will be damaged and cannot be correctly read into the SoC system for normal operation.

[0005] In the above-mentioned multi-Flash chip redundant backup solution, each Flash chip stores the same firmware data. When reading, the complete firmware data is read from one Flash chip, so the reading speed is low.

[0006] In summary, how to effectively improve the reading speed of firmware data and ensure the reliability of the SoC system is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0007] The purpose of the present invention is to provide a firmware data loading method, system, device and storage medium to effectively improve the reading speed of firmware data and ensure the reliability of the SoC system.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] A firmware data loading method, comprising:

[0010] After the SoC system is powered on, receiving various read instructions sent by the SoC system;

[0011] Upon receiving any one read instruction, determining whether the data content specified by the read instruction is cached;

[0012] If yes, feeding back the data content specified by the read instruction in the cache to the SoC system;

[0013] If not, the data content is read in parallel based on the N firmware data memories, the read data is sorted and placed in a cache, and the data content specified by the read instruction in the cache is fed back to the SoC system;

[0014] Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2.

[0015] Preferably, the parallel reading of the data content based on N firmware data memories includes:

[0016] Determine the shard size;

[0017] Dividing the address interval in the read instruction based on the slice size to obtain divided sub-address intervals;

[0018] According to a rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories; wherein M represents the number of divided sub-address intervals;

[0019] Based on the divided sub-address intervals and N firmware data storage devices, the data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0020] Preferably, N=2. Accordingly, according to the rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories, including:

[0021] According to the rule of interleaving the first firmware data memory and the second firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories.

[0022] Preferably, it also includes:

[0023] After the data content specified by the read instruction is read, if no new read instruction is received, data of K slices in size are read from each of the N firmware data memories in a parallel reading manner to obtain data of size N*K;

[0024] Wherein, K is a positive integer, data of size N*K constitutes target data with continuous addresses, and the first address of the target data is the last address of the address range in the read instruction+1.

[0025] Preferably, it also includes:

[0026] receiving an instruction sent by the SoC system indicating a firmware data memory failure;

[0027] Accordingly, the parallel reading of the data content based on the N firmware data memories includes:

[0028] The data content is read in parallel based on each non-faulty firmware data memory among the N firmware data memories.

[0029] Preferably, the parallel reading of the data content based on N firmware data memories includes:

[0030] Determine the shard size;

[0031] Dividing the address interval in the read instruction based on the slice size to obtain divided sub-address intervals;

[0032] According to each allocation sub-address intervals, and sequentially allocated from the first firmware data memory to the Nth firmware data memory, dividing the M sub-address intervals into corresponding firmware data memories; wherein M represents the number of the divided sub-address intervals;

[0033] Based on the divided sub-address intervals and N firmware data storage devices, the data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0034] Preferably, in the process of parallel reading of the data content, before determining that the memory initialization of the SoC system is completed, the slice size used is a set first slice size, and after determining that the memory initialization of the SoC system is completed, the slice size used is a set second slice size;

[0035] The first fragment size is smaller than the second fragment size.

[0036] A firmware data loading system, comprising:

[0037] An instruction reading module, configured to receive various read instructions sent by the SoC system after the SoC system is powered on;

[0038] A judgment module, configured to, upon receiving any one read instruction, determine whether the data content specified by the read instruction is cached;

[0039] If yes, triggering a first feedback module to feed back the data content specified by the read instruction in the cache to the SoC system;

[0040] If not, triggering a second feedback module for reading the data content in parallel based on the N firmware data memories, arranging the read data and placing it in a cache, and feeding back the data content specified by the read instruction in the cache to the SoC system;

[0041] Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2.

[0042] A firmware data loading device, comprising:

[0043] Memory for storing computer programs;

[0044] A processor is used to execute the computer program to implement the steps of the firmware data loading method as described above.

[0045] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the firmware data loading method described above.

[0046] By applying the technical solution provided in the embodiment of the present invention, after the SoC system is powered on, it is possible to receive various read instructions sent by the SoC system, and then feed back the corresponding data content to the SoC system according to each received read instruction. Therefore, the solution of the present application can effectively realize the reading of firmware data.

[0047] Specifically, when any one read instruction is received, it can be determined whether the data content specified by the read instruction is cached, that is, if the data content specified by the read instruction is cached, the data content specified by the read instruction in the cache can be directly fed back to the SoC system without reading from the firmware data memory, which effectively improves the reading speed of the firmware data. If the data content specified by the read instruction is not cached, in the solution of the present application, N blocks of firmware data memory are set up, N is a positive integer not less than 2, and the data content is read in parallel based on the N blocks of firmware data memory, thereby making the reading speed of the firmware data higher. After the parallel reading, the read data can be sorted and placed in the cache, and then the data content specified by the read instruction in the cache can be fed back to the SoC system. In addition, in the solution of the present application, each of the N blocks of firmware data memory stores complete SoC system startup firmware data, realizing redundant backup of the SoC system startup firmware data, which is beneficial to ensuring the reliability of the SoC system.

[0048] In summary, the solution of the present application can effectively improve the reading speed of firmware data and ensure the reliability of the SoC system. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 This is a flowchart of an implementation method of firmware data loading in the present invention;

[0051] Figure 2 A schematic diagram of parallel reading of data content in a specific embodiment of the present invention;

[0052] Figure 3A schematic diagram of parallel reading of data content in another specific embodiment of the present invention;

[0053] Figure 4 This is a structural diagram of a firmware data loading system in the present invention;

[0054] Figure 5 The figure is a structural diagram of a firmware data loading device in the present invention. DETAILED DESCRIPTION

[0055] The core of the present invention is to provide a firmware data loading method, which can effectively improve the reading speed of firmware data and ensure the reliability of the SoC system.

[0056] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0057] Please refer to Figure 1 , Figure 1 This is a flowchart of an implementation method of a firmware data loading method in the present invention. The firmware data loading method may include the following steps:

[0058] Step S101: After the SoC system is powered on, various read instructions sent by the SoC system are received.

[0059] Specifically, in practical applications, the solution of the present application can be implemented using a device such as an FPGA (Field Programmable Gate Array), where the FPGA is in communication with N firmware data memories and the SoC system. Alternatively, when designing the SoC system, the functionality of the present application can be integrated into the chip of the SoC system in the form of functional modules.

[0060] After the SoC system is powered on, it initializes its parameters and begins reading the SoC system startup firmware data, hereinafter referred to as firmware data. To read the complete firmware data, the SoC system needs to issue read instructions multiple times. Each time a read instruction is issued, the SoC system reads a continuous segment of data. In other words, the received read instructions determine the data content that needs to be read and fed back to the SoC system.

[0061] Step S102: When any one read instruction is received, determine whether the data content specified by the read instruction is cached; if yes, execute step S103; if not, execute step S104.

[0062] After receiving any one read instruction, it can be determined whether the data content specified by the read instruction is cached according to the address range carried in the read instruction.

[0063] The address range carried in the read instruction can be in the form of the first address + the last address, or in the form of the first address + the data length. It can be seen that the data content specified by the read instruction can be determined through the address range carried in the read instruction, that is, in the firmware data memory, the data content pointed to by the address range is the data content specified by the read instruction received this time.

[0064] Of course, in other specific situations, the address range can be set to other forms as needed, as long as it can effectively reflect the data content specified by the read instruction, and it does not affect the implementation of the present invention.

[0065] Step S103: Feedback the data content specified by the read instruction in the cache to the SoC system.

[0066] If the cache contains the data content specified by the read instruction, there is no need to read the data content from the firmware data memory. The data content specified by the read instruction in the cache can be directly fed back to the SoC system to effectively ensure the fast startup of the SoC system.

[0067] It should be noted that when determining whether the cache contains the data content specified by the read instruction, the judgment is usually made based on the address, that is, for any data fragment in the cache, the address of the data fragment will be recorded, so that when executing step S102, the address range carried in the read instruction can be used to determine whether the cache stores the data content of the address range.

[0068] Step S104: Reading data content in parallel based on the N firmware data memories, sorting the read data and placing it in a cache, and feeding back the data content specified by the read instruction in the cache to the SoC system;

[0069] Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2.

[0070] If the data content specified by the read instruction is not cached, the data content needs to be read from the firmware data memory. During reading, the present application performs parallel reading of the data content based on N firmware data memories to effectively improve the data reading speed.

[0071] After parallel reading, the read data can be sorted and placed in the cache, and then the data content specified by the read instruction in the cache is fed back to the SoC system.

[0072] Moreover, in the solution of the present application, each of the N firmware data memories stores complete SoC system startup firmware data, where N is a positive integer not less than 2. That is to say, the complete SoC system startup firmware data is redundantly stored in the N firmware data memories, thereby effectively ensuring the reliability of the SoC system startup.

[0073] Furthermore, it should be noted that in some cases, a portion of the data content specified by the read instruction may be stored in the cache. In this case, when executing step S104, it is possible to select only the portion of data not stored in the cache to be read from the firmware data memory. After the read is complete, the portion of data stored in the cache is combined with the portion of data stored in the cache to form the data content specified by the read instruction. Of course, it is also possible to select directly to read the entire data content specified by the read instruction from the N firmware data memories, without affecting the implementation of the present invention.

[0074] When data content is read in parallel based on N firmware data memories, there may be various specific implementations. For example, in one specific implementation of the present invention, the parallel reading of data content based on N firmware data memories described in step S104 may specifically include:

[0075] Determine the shard size;

[0076] Based on the slice size, the address interval in the read instruction is divided to obtain each divided sub-address interval;

[0077] According to a rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories; wherein M represents the number of divided sub-address intervals;

[0078] Based on the divided sub-address intervals and N firmware data storage devices, data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0079] In this embodiment, please refer to Figure 2 , taking N=3 as an example. First, the slice size can be determined. For example, in a specific case, the slice size is a fixed value. The slice size represents the size of data read in a single read when reading data from the firmware data memory.

[0080] After determining the slice size, the address range in the read instruction can be divided based on the slice size to obtain the divided sub-address ranges. Figure 2 In the embodiment, the data content pointed to by the address interval in the read instruction is P1-P9. After dividing the address interval in the read instruction, 9 sub-address intervals are obtained. The data content corresponding to each of the 9 sub-address intervals is Figure 2 P1-P9 in.

[0081] After obtaining the divided sub-address intervals, in this implementation, the M sub-address intervals are divided into corresponding firmware data memories according to the rule of allocating one sub-address interval each time and cyclically allocating from the 1st firmware data memory to the Nth firmware data memory.

[0082] That is to say, first the first sub-address interval is allocated to the first firmware data memory, then the second sub-address interval is allocated to the second firmware data memory, and the third sub-address interval is allocated to the third firmware data memory. Since it is a cyclic allocation, the fourth sub-address interval is allocated to the first firmware data memory, the fifth sub-address interval is allocated to the second firmware data memory, and so on, until all 9 sub-address intervals are allocated.

[0083] The M sub-address intervals are divided into corresponding firmware data memories in order to determine from which firmware data memory the data in the corresponding sub-address interval should be read.

[0084] After the corresponding relationship is assigned, the data content can be read in parallel based on the divided sub-address intervals and N blocks of firmware data memory. And from the above allocation method, it can be seen that the purpose is to read the data content specified by any sub-address interval from the firmware data memory corresponding to the sub-address interval. For example, for the first sub-address interval, its corresponding firmware data memory is the first firmware data memory, that is, Figure 2Therefore, the data content P1 specified by the first sub-address interval is read from Flash1. Correspondingly, the data content P2 specified by the second sub-address interval is read from Flash2, and the data content P3 specified by the third sub-address interval is read from Flash3. It can be understood that the data contents P1, P2, and P3 are read in parallel, that is, the data contents P1, P2, and P3 are read into the cache almost at the same time.

[0085] exist Figure 2 In the implementation method, after the data content is read in parallel based on the three firmware data memories, the read data can be sorted, that is, sorted into the order of P1-P9, and then placed in the cache, so that the data content P1-P9 specified by the read instruction in the cache can be fed back to the SoC system.

[0086] Figure 2 The three firmware data memories are all Flash chips, which is also the solution commonly used in practical applications. That is, Flash chips with SPI interfaces are usually used to store firmware data. Of course, in other specific occasions, other types of firmware data memories can be used to store firmware data, which does not affect the implementation of the present invention.

[0087] Furthermore, in a specific embodiment of the present invention, N=2. Accordingly, according to the rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories, including:

[0088] According to the rule of interleaving the first firmware data memory and the second firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories.

[0089] In this implementation, N is set to 2, which is also a more commonly used implementation in practical applications. The design of two firmware data storage devices is not too costly, and can also effectively achieve firmware data redundancy and ensure the speed of data reading.

[0090] Since N=2, the M sub-address intervals are divided into corresponding firmware data memories according to the rule of interleaving the first firmware data memory and the second firmware data memory.

[0091] See Figure 3 , also take the data content pointed to by the address interval in the read instruction as P1-P9 as an example, and after dividing the address interval in the read instruction, 9 sub-address intervals are obtained. The data content corresponding to each of these 9 sub-address intervals is Figure 3Since there are only two firmware data memories, the cyclic allocation rule is to perform interleaved allocation in the two firmware data memories, that is, the first sub-address interval is allocated to Figure 3 Flash1, so that the subsequent reading of the data content P1 corresponding to the first sub-address interval is performed from Flash1, and the second sub-address interval is allocated to Figure 3 The third sub-address interval is allocated to Flash2. Figure 3 The 4th sub-address range of Flash1 is allocated to Figure 3 Flash2, and so on.

[0092] Furthermore, in a specific embodiment of the present invention, it may also include:

[0093] After reading the data content specified by the read instruction, if no new read instruction is received, K slices of data are read from each of the N firmware data memories in a parallel reading manner to obtain N*K size data;

[0094] Wherein, K is a positive integer, data of size N*K constitutes target data with continuous addresses, and the first address of the target data is the last address of the address range in the read instruction + 1.

[0095] After the data content specified by the read instruction is read, when no new read instruction is received, it is considered that a certain amount of data can continue to be read into the cache, thereby further improving the overall SoC system startup speed.

[0096] In this embodiment, K slices of data are read from each of the N firmware data memories in parallel, resulting in a total of N*K data. The N*K data has consecutive addresses and is referred to as target data. The starting address of the target data is the last address of the address range in the read instruction + 1, meaning the target data immediately follows the data specified in the read instruction.

[0097] Easy to understand Figure 3 For example, Figure 3 In the read instruction, the data content pointed to by the address range in the instruction is P1-P9. In this implementation, after reading P1-P9, for example, K=2, P10 will continue to be read from Flash2, P11 will be read from Flash1, P12 will be read from Flash2, and P13 will be read from Flash1.

[0098] K is a positive integer, but is usually not set too high, for example, it can usually be set to 1 or 2. After reading the data content specified by the read instruction, a certain amount of data is read. The read target data is usually needed in the subsequent process of loading the SoC system firmware. That is, the read target data is usually the data content specified in the subsequent read instruction, so that this implementation method effectively improves the overall SoC system startup speed.

[0099] In a specific embodiment of the present invention, the parallel reading of data content based on N firmware data memories described in step S104 may specifically include:

[0100] Determine the shard size;

[0101] Based on the slice size, the address interval in the read instruction is divided to obtain each divided sub-address interval;

[0102] According to each allocation sub-address intervals, and sequentially allocated from the first firmware data memory to the Nth firmware data memory, dividing the M sub-address intervals into corresponding firmware data memories; wherein M represents the number of the divided sub-address intervals;

[0103] Based on the divided sub-address intervals and N firmware data storage devices, data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0104] In this implementation, it is also necessary to determine the slice size, and then divide the address interval in the read instruction based on the slice size to obtain the divided sub-address intervals.

[0105] Still taking the data content pointed to by the address interval in the read instruction as P1-P9 and N=2 as an example, 9 sub-address intervals are divided based on the slice size. Therefore, the 1st to 5th sub-address intervals are allocated to the 1st firmware data memory, so that the data contents P1-P5 are read from the 1st firmware data memory, and the 6th to 9th sub-address intervals are allocated to the 2nd firmware data memory, so that the data contents P6-P9 are read from the 2nd firmware data memory.

[0106] In a specific embodiment of the present invention, the method may further include: receiving an instruction sent by the SoC system indicating a firmware data memory failure;

[0107] Accordingly, the data content is read in parallel based on the N firmware data memories, including:

[0108] Based on each non-faulty firmware data storage block among the N firmware data storage blocks, data contents are read in parallel.

[0109] When all N firmware data memories are functioning properly, the SoC system can read the correct and complete firmware data and boot normally. Conversely, when one or more firmware data memories fail, the SoC system cannot boot normally. The SoC system can determine which firmware data memory or memories the erroneous data originated from based on the erroneous data content, then identify these firmware data memories as failed firmware data memories and send a command indicating a firmware data memory failure. It is understood that the command should specify which firmware data memories are failed.

[0110] After determining the faulty firmware data memory, the SoC system will restart, i.e., resend each read instruction. At this time, when executing step S104, the data content is read in parallel based on each firmware data memory block that is not faulty among the N firmware data memories, which is equivalent to eliminating the faulty firmware data memory. For example, if N = 3 and Flash2 is faulty, the data content is read in parallel based on Flash1 and Flash3. For another example, if N = 2 and Flash2 is faulty, the complete firmware data can only be read based on Flash1.

[0111] In addition, it should be noted that after receiving the instruction sent by the SoC system indicating a firmware data memory failure, the system usually clears its own cache to avoid erroneous data being stored in the cache, which may cause the SoC system to still be abnormal when it restarts.

[0112] In a specific embodiment of the present invention, during the parallel reading of data content, before determining that the memory initialization of the SoC system is completed, the slice size used is a set first slice size, and after determining that the memory initialization of the SoC system is completed, the slice size used is a set second slice size;

[0113] The first fragment size is smaller than the second fragment size.

[0114] Setting the shard size too small or too large will affect the actual reading efficiency. Because when reading data, it is necessary to send read commands and other parameters to the Flash chip. If the shard is too small, read commands will need to be sent to the Flash chip frequently, resulting in additional reading overhead. If the shard is too large, the firmware data content required within a certain period of time may be read from a single Flash chip, and the parallel effect cannot be achieved. In addition, when the firmware program jumps or the data address changes, the shard is too large, resulting in most of the single-chip data being invalid data, which will also affect the reading efficiency.

[0115] Therefore, in the solution of the present application, it is considered that a fixed shard size may not be set, but two shard sizes are divided according to the situation.

[0116] Specifically, the Flash chip read behavior varies at different stages of the SoC system startup. During the initial power-up phase, the SoC system reads small sections of the lowest-level initialization program from the Flash chip to execute, initializing basic hardware such as system interrupts, clocks, serial ports, and memory. Once the SoC system's memory initialization is complete, it reads and executes larger sections of the firmware data from the Flash chip.

[0117] Therefore, in this embodiment, before determining that the memory initialization of the SoC system is complete, the slice size used is the set first slice size, which has a smaller value. After determining that the memory initialization of the SoC system is complete, the slice size is updated, that is, the slice size used at this time is the set second slice size, which has a larger value. This embodiment, by setting two slice sizes, is conducive to further improving reading efficiency.

[0118] By applying the technical solution provided in the embodiment of the present invention, after the SoC system is powered on, it is possible to receive various read instructions sent by the SoC system, and then feed back the corresponding data content to the SoC system according to each received read instruction. Therefore, the solution of the present application can effectively realize the reading of firmware data.

[0119] Specifically, when any one read instruction is received, it can be determined whether the data content specified by the read instruction is cached, that is, if the data content specified by the read instruction is cached, the data content specified by the read instruction in the cache can be directly fed back to the SoC system without reading from the firmware data memory, which effectively improves the reading speed of the firmware data. If the data content specified by the read instruction is not cached, in the solution of the present application, N blocks of firmware data memory are set up, N is a positive integer not less than 2, and the data content is read in parallel based on the N blocks of firmware data memory, thereby making the reading speed of the firmware data higher. After the parallel reading, the read data can be sorted and placed in the cache, and then the data content specified by the read instruction in the cache can be fed back to the SoC system. In addition, in the solution of the present application, each of the N blocks of firmware data memory stores complete SoC system startup firmware data, realizing redundant backup of the SoC system startup firmware data, which is beneficial to ensuring the reliability of the SoC system.

[0120] In summary, the solution of the present application can effectively improve the reading speed of firmware data and ensure the reliability of the SoC system.

[0121] Corresponding to the above method embodiment, an embodiment of the present invention further provides a firmware data loading system, which can be referred to in correspondence with the above.

[0122] See Figure 4 , is a structural diagram of a firmware data loading system in the present invention, comprising:

[0123] The instruction reading module 401 is used to receive various read instructions sent by the SoC system after the SoC system is powered on;

[0124] The judgment module 402 is used to judge whether the data content specified by the read instruction is cached when any read instruction is received;

[0125] If yes, the first feedback module 403 is triggered to feed back the data content specified by the read instruction in the cache to the SoC system;

[0126] If not, trigger the second feedback module 404 to read the data content in parallel based on the N firmware data memories, organize the read data and put it into the cache, and feed back the data content specified by the read instruction in the cache to the SoC system;

[0127] Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2.

[0128] In a specific embodiment of the present invention, parallel reading of data content based on N firmware data memories includes:

[0129] Determine the shard size;

[0130] Based on the slice size, the address interval in the read instruction is divided to obtain each divided sub-address interval;

[0131] According to a rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories; wherein M represents the number of divided sub-address intervals;

[0132] Based on the divided sub-address intervals and N firmware data storage devices, data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0133] In a specific embodiment of the present invention, N=2. Accordingly, according to the rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories, including:

[0134] According to the rule of interleaving the first firmware data memory and the second firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories.

[0135] In a specific embodiment of the present invention, the second feedback module 404 is further configured to:

[0136] After reading the data content specified by the read instruction, if no new read instruction is received, K slices of data are read from each of the N firmware data memories in a parallel reading manner to obtain N*K size data;

[0137] Wherein, K is a positive integer, data of size N*K constitutes target data with continuous addresses, and the first address of the target data is the last address of the address range in the read instruction + 1.

[0138] In a specific embodiment of the present invention, the instruction reading module 401 is further configured to: receive an instruction sent by the SoC system indicating a firmware data memory failure;

[0139] Accordingly, the data content is read in parallel based on the N firmware data memories, including:

[0140] Based on each non-faulty firmware data storage block among the N firmware data storage blocks, data contents are read in parallel.

[0141] In a specific embodiment of the present invention, parallel reading of data content based on N firmware data memories includes:

[0142] Determine the shard size;

[0143] Based on the slice size, the address interval in the read instruction is divided to obtain each divided sub-address interval;

[0144] According to each allocation sub-address intervals, and sequentially allocated from the first firmware data memory to the Nth firmware data memory, dividing the M sub-address intervals into corresponding firmware data memories; wherein M represents the number of the divided sub-address intervals;

[0145] Based on the divided sub-address intervals and N firmware data storage devices, data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

[0146] In a specific embodiment of the present invention, during the parallel reading of data content, before determining that the memory initialization of the SoC system is completed, the slice size used is a set first slice size, and after determining that the memory initialization of the SoC system is completed, the slice size used is a set second slice size;

[0147] The first fragment size is smaller than the second fragment size.

[0148] Corresponding to the above method and system embodiments, embodiments of the present invention further provide a firmware data loading device and a computer-readable storage medium, which can be referred to in correspondence with the above.

[0149] See Figure 5 , the firmware data loading device may include:

[0150] Memory 501, used for storing computer programs;

[0151] The processor 502 is configured to execute a computer program to implement the steps of the firmware data loading method in any of the above embodiments.

[0152] The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the firmware data loading method in any of the above embodiments are implemented.

[0153] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0154] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0155] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the technical solutions and core concepts of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A firmware data loading method, characterized in that: include: After the SoC system is powered on, receiving various read instructions sent by the SoC system; Upon receiving any one read instruction, determining whether the data content specified by the read instruction is cached; If yes, feeding back the data content specified by the read instruction in the cache to the SoC system; If not, the data content is read in parallel based on the N firmware data memories, the read data is sorted and placed in a cache, and the data content specified by the read instruction in the cache is fed back to the SoC system; Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2; The parallel reading of the data content based on N firmware data memories includes: Determine the shard size; Dividing the address interval in the read instruction based on the slice size to obtain divided sub-address intervals; According to a rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories; wherein M represents the number of divided sub-address intervals; Based on the divided sub-address intervals and the N firmware data memories, the data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data memory corresponding to the sub-address interval; Also includes: After the data content specified by the read instruction is read, if no new read instruction is received, data of K slices in size are read from each of the N firmware data memories in a parallel reading manner to obtain data of size N*K; Wherein, K is a positive integer, data of size N*K constitutes target data with continuous addresses, and the first address of the target data is the last address of the address interval in the read instruction + 1; During the parallel reading of the data content, before determining that the memory initialization of the SoC system is completed, the slice size used is a set first slice size, and after determining that the memory initialization of the SoC system is completed, the slice size used is a set second slice size; The first fragment size is smaller than the second fragment size.

2. The firmware data loading method according to claim 1, wherein: N=2. Accordingly, according to the rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories, including: According to the rule of interleaving the first firmware data memory and the second firmware data memory, the M sub-address intervals are divided into corresponding firmware data memories.

3. The firmware data loading method according to claim 1, wherein: Also includes: receiving an instruction sent by the SoC system indicating a firmware data memory failure; Accordingly, the parallel reading of the data content based on the N firmware data memories includes: The data content is read in parallel based on each non-faulty firmware data memory among the N firmware data memories.

4. The firmware data loading method according to claim 1, wherein: The parallel reading of the data content based on N firmware data memories includes: Determine the shard size; Dividing the address interval in the read instruction based on the slice size to obtain divided sub-address intervals; According to each allocation sub-address intervals, and sequentially allocated from the first firmware data memory to the Nth firmware data memory, dividing the M sub-address intervals into corresponding firmware data memories; wherein M represents the number of the divided sub-address intervals; Based on the divided sub-address intervals and N firmware data storage devices, the data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data storage device corresponding to the sub-address interval.

5. A firmware data loading system, characterized in that: include: An instruction reading module, configured to receive various read instructions sent by the SoC system after the SoC system is powered on; A judgment module, configured to, upon receiving any one read instruction, determine whether the data content specified by the read instruction is cached; If yes, triggering a first feedback module to feed back the data content specified by the read instruction in the cache to the SoC system; If not, triggering a second feedback module for reading the data content in parallel based on the N firmware data memories, arranging the read data and placing it in a cache, and feeding back the data content specified by the read instruction in the cache to the SoC system; Each of the N firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2; Parallel reading of data content based on N firmware data memories, including: Determine the shard size; Based on the slice size, the address interval in the read instruction is divided to obtain each divided sub-address interval; According to a rule of allocating one sub-address interval each time and cyclically allocating from the first firmware data memory to the Nth firmware data memory, M sub-address intervals are divided into corresponding firmware data memories; wherein M represents the number of divided sub-address intervals; Based on the divided sub-address intervals and the N firmware data memories, data content is read in parallel, wherein for any sub-address interval, the data content specified by the sub-address interval is read from the firmware data memory corresponding to the sub-address interval; The second feedback module is further configured to: After reading the data content specified by the read instruction, if no new read instruction is received, K slices of data are read from each of the N firmware data memories in a parallel reading manner to obtain N*K size data; Wherein, K is a positive integer, data of size N*K constitutes target data with continuous addresses, and the first address of the target data is the last address of the address range in the read instruction + 1; During the parallel reading of data content, before determining that the memory initialization of the SoC system is completed, the slice size used is the set first slice size, and after determining that the memory initialization of the SoC system is completed, the slice size used is the set second slice size; The first fragment size is smaller than the second fragment size.

6. A firmware data loading device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the firmware data loading method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the firmware data loading method according to any one of claims 1 to 4 are implemented.

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