A chip verification system, method and related equipment

Abstract

This invention provides a chip verification system, method, and related equipment. The chip verification system includes: an interface module for interconnecting with a chip under test (DUT); an inter-chip consistency extension unit connected to the interface module for converting simulation verification data of the DUT; and a configuration module connected to the inter-chip consistency extension unit for configuring the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the DUT. This invention can improve chip verification efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip technology, specifically to a chip verification system, method and related equipment. Background Technology

[0002] With the development of semiconductor technology, SOC (System-on-a-Chip) technology has become a development trend in integrated circuit design. Furthermore, as SOC chips become increasingly complex, the use of system-level cascading between multiple SOC chips is gradually becoming the direction of current chip design. Therefore, it is necessary to verify the interactive communication capabilities between SOC chips.

[0003] However, the verification efficiency of existing SOC chip inter-interaction communication capabilities is not high. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip verification system, method and related equipment to improve the verification efficiency of SOC chips.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, embodiments of the present invention provide a chip verification system, comprising:

[0007] An interface module, which is used to interconnect with the chip under test;

[0008] An inter-chip consistency extension unit connected to the interface module is used to convert the simulation verification data of the chip under test.

[0009] A configuration module connected to the inter-chip consistency extension unit is used to configure the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the chip under test.

[0010] Optionally, the configuration module is also used to initialize the interface module and the inter-chip consistency extension unit.

[0011] Optionally, the configuration module includes a consistency unit configuration model and a communication verification component;

[0012] The consistency unit configuration model is used to initialize the inter-chip consistency extension unit through a backdoor access method; the communication verification component is used to initialize the interface module using a forced assignment signal.

[0013] Optionally, the configuration module further includes: a general protocol model; the general protocol model is used to establish a data transmission process in the simulation verification environment based on a general protocol interface.

[0014] Optionally, the communication verification component includes: a verification request sequence model and a verification response sequence model;

[0015] The verification request sequence model is used to create a first data packet to send simulation verification request data stimulus to the chip under test based on the first data packet.

[0016] The verification response sequence model is used to create a second data packet to send simulation verification response data stimulus to the chip under test based on the second data packet.

[0017] Optionally, the verification response sequence model includes: a storage unit, which is used to store the received request information of the chip under test and to create the second data packet based on the request information.

[0018] In a second aspect, embodiments of the present invention provide a chip verification method, based on the chip verification system described in the first aspect above, the method comprising:

[0019] The configuration module is used to configure the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the chip under test.

[0020] The communication function of the chip under test is verified based on the simulation verification environment.

[0021] Optional, also includes:

[0022] The interface module and the inter-chip consistency extension unit are initialized using the configuration module.

[0023] Optionally, the configuration module includes a consistency unit configuration model and a communication verification component;

[0024] The initialization of the interface module and the inter-chip consistency extension unit using the configuration module includes:

[0025] The inter-chip consistency extension unit is initialized using a backdoor access method based on the consistency unit configuration model; and the communication verification component initializes the interface module using a forced assignment signal.

[0026] Optionally, the configuration module further includes: a general protocol model;

[0027] The provision of a simulation verification environment for the chip under test includes: establishing a data transmission process in the simulation verification environment based on a general protocol interface and using the general protocol model.

[0028] Optionally, verifying the communication function of the chip under test based on the simulation verification environment includes:

[0029] A first data packet is created and transmitted to the interface module to send a simulation verification request data stimulus to the chip under test, thereby verifying the slave device function of the chip under test.

[0030] Alternatively, a second data packet can be created and transmitted to the interface module to send simulation verification response data stimulus to the chip under test, thereby verifying the master device function of the chip under test.

[0031] Thirdly, embodiments of the present invention also provide a chip verification platform, the chip verification platform including the chip verification system as described in the first aspect above, for performing the chip verification method as described in the second aspect above.

[0032] Fourthly, embodiments of the present invention also provide a storage medium that stores one or more computer-executable instructions, which, when executed, implement the chip verification method as described in the second aspect above.

[0033] In the chip verification system provided in this embodiment of the invention, an interface module is interconnected with the chip under test (DUT). An inter-chip consistency extension unit connected to the interface module converts the simulation verification data of the DUT. Furthermore, when the DUT has verification requirements, a configuration module connected to the inter-chip consistency extension unit configures the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the DUT.

[0034] As can be seen, the chip verification system of this embodiment of the invention, compared with the scheme of configuring another auxiliary test chip to interconnect the test chip and the chip under test for interactive verification, can directly utilize the configuration module, interface module and inter-chip consistency extension unit to construct a simulation verification environment for realizing inter-chip interaction. Therefore, this embodiment of the invention does not need to provide a dedicated auxiliary test chip, avoids the process of configuring a large number of components and timings to enable the auxiliary test chip to have independent data processing capabilities, and saves the time of compiling and simulating these components and timings, thereby improving the chip verification efficiency. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the optional structure of a SOC chip.

[0037] Figure 2 This is a schematic diagram of an optional structure for verifying a SOC chip.

[0038] Figure 3 This is a schematic diagram of an optional structure of the chip verification system provided in an embodiment of the present invention.

[0039] Figure 4 This is a schematic diagram of an optional structure of the configuration module provided in an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of an optional structure of the communication verification component provided in an embodiment of the present invention.

[0041] Figure 6 This is an optional flowchart of the chip verification method provided in the embodiments of the present invention.

[0042] Figure 7 This is a schematic diagram of an optional structure for verifying a SOC chip provided in an embodiment of the present invention. Detailed Implementation

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] As described in the background section, existing verification methods for the inter-SoC chip communication capabilities are inefficient. Inter-SoC chip communication primarily establishes interconnectivity between multiple SoC chips through the PCS (Physical Coding Sublayer), PHY (Physical Layer), and data bus. Figure 1 An exemplary schematic diagram of an optional SOC chip is shown. For example... Figure 1 As shown, the SOC chip may include multiple pcs and phy modules (pcs0 ​​and phy0 modules, pcs1 and phy1 modules, ..., pcs N and phy N modules, respectively) as well as corresponding inter-chip consistency extension units and internal modules.

[0045] The PCS and PHY modules are protocol interfaces used for interconnection and communication with other SOC chips. PHY is a physical interface transceiver that enables physical layer communication of the SOC chip. The SOC chip uses the PHY interface as its external output interface. PCS is responsible for line transmission optimization algorithms, which can map the well-defined Ethernet MAC functions to the functions of existing coding and physical layer signal systems. It includes the Tx (transport) channel for transmitting data and the Rx (receive) channel for receiving data. The Tx and Rx interfaces are used to connect to the Rx and Tx channels of the inter-chip consistency extension unit, respectively.

[0046] The inter-chip consistency extension unit provides bidirectional data conversion between two SOC chips, ensuring that the data format conforms to the current transmission process's data format. This enables data transmission with other internal modules via a common protocol interface. The two SOC chips can be SOC chips that communicate with each other. In a specific example, when... Figure 1 When the SOC chip shown acts as the master chip to initiate external access, the inter-chip consistency extension unit can, based on input logic, convert data obtained from internal modules corresponding to the general protocol interface into data that meets the Tx channel's data format, thereby enabling it to be sent to the PCS and output to the interacting SOC chip via the PHY interface, whereby the destination module of other SOC chips provides a response. In another specific example, when Figure 1 When the SOC chip shown acts as a slave chip, if an internal module of another chip initiates access to it, the access data is sent through the SOC chip's PHY interface and in Tx data format via the PCS's Tx channel to the Rx channel of the inter-chip consistency extension unit. The output logic (engress) of the inter-chip consistency extension unit converts the data received from the PCS into the data format of the input to the Rx channel into the data format of the general protocol interface, and then sends the access data to the destination module of the internal module, which then responds.

[0047] Internal modules are modules that further process the data, such as data processing registers and other modules with data processing functions.

[0048] It should be noted that the external output interface of the SOC chip is the PHY interface. Therefore, when verifying the correct interconnection and communication between the SOC chip and other chips, the PHY interface needs to be considered and a corresponding verification environment needs to be set up. The verification environment drives the SOC chip's PHY interface to send requests to the SOC chip's internal modules and receive responses from the SOC chip's internal modules, or respond to requests received from the SOC chip's internal modules via the PHY interface. However, since the PHY interface is a serial interface, its data transmission method is serial data transmission, making it difficult to write a verification environment to directly drive it.

[0049] Therefore, when verifying the communication capabilities of a SoC chip, based on the interconnection relationships between SoC chips, as an optional implementation, the chip verification system can configure and control an auxiliary test chip to perform inter-chip interaction verification of the SoC chips. Specifically, an auxiliary test chip can be provided to establish a system-level cascaded interconnection relationship with the SoC chip under test, thereby providing a simulation verification environment for inter-chip interaction for the SoC chip under test, and thus realizing the simulation verification of the SoC chip under test.

[0050] Figure 2 An exemplary schematic diagram of an optional structure for verifying a SOC chip is shown, wherein SOC chip A is... Figure 1 The SOC chip shown is the SOC chip under test. SOC chip B is an auxiliary test chip configured and controlled by the chip verification system. Figure 2 As shown, the auxiliary test chip's external output interface is a PHY interface, which can be directly interconnected with the PHY interface of the SOC chip under test (DUT). Furthermore, based on the DUT's transmission and reception requirements, the interconnection between the DUT and auxiliary test chip's PHY interfaces can be achieved by connecting the DUT's PHY interface receiver to the auxiliary test chip's PHY interface transmitter, and vice versa, thus enabling serial data communication between the DUT and auxiliary test chip. Additionally, the auxiliary test chip can be used as the master, and the DUT as the slave. The system can determine whether a transmission request from the auxiliary test chip can be successfully transmitted to the DUT's internal module via the slave's PHY interface. Alternatively, the DUT can be used as the master, and the auxiliary test chip as the slave. The system can then determine whether a transmission request from the DUT's internal module can reach the auxiliary test chip's PHY interface, thereby verifying the communication capabilities of the DUT.

[0051] However, when the auxiliary test chip is used as part of the verification environment, the chip verification system needs to perform extensive configuration and compilation on it to enable it to have independent data processing capabilities. Based on these independent processing capabilities, the system can then control the chip to interact with the SoC under test. For example, the chip verification system needs to configure numerous components and timing sequences of the auxiliary test chip, such as the reset signal, the clock signal, and the registers involved in data routing. Furthermore, the numerous components and timing sequences configured within the auxiliary test chip need to be compiled and simulated before they can be used, and only then can the SoC under test be simulated and verified.

[0052] It is evident that using an auxiliary test chip to verify the communication of the SOC chip under test requires a significant amount of time to configure and compile the components and timing of the auxiliary test chip. Moreover, due to the large number of components configured within the auxiliary test chip, the access requests sent by the internal modules of the SOC chip under test (acting as slaves) to the target modules of the auxiliary test chip have a long path, which also leads to a longer simulation time for the SOC chip under test. Furthermore, if it is necessary to verify whether a large number of different types of request data can be sent through the internal modules of the SOC chip under test (acting as slaves) to their corresponding PHY interfaces, this will further consume a lot of time, resulting in a long verification time for the SOC chip under test and low chip verification efficiency.

[0053] Therefore, providing efficient and rapid chip verification solutions is particularly necessary.

[0054] In view of this, embodiments of the present invention propose an improved chip verification scheme. By directly utilizing the configuration module, configuring the interface module and the inter-chip consistency extension unit, a simulation verification environment for realizing inter-chip interaction is constructed. Compared with the scheme of configuring another auxiliary test chip to interconnect the test chip with the chip under test and then performing interactive verification, embodiments of the present invention do not require providing a dedicated auxiliary test chip, and avoid the process of configuring a large number of components and timings to enable the auxiliary test chip to have independent data processing capabilities. Furthermore, it saves the time of compiling and simulating these components and timings, thereby improving the chip verification efficiency.

[0055] Figure 3 An exemplary schematic diagram of an optional structure of a chip verification system according to an embodiment of the present invention is shown. For example... Figure 3 As shown, the chip verification system may include: an interface module 31, an inter-chip consistency extension unit 32, and a configuration module 33.

[0056] The interface module 31 is used to interconnect with the chip under test (DUT), which can be understood as the chip that needs to be verified. In one example, the DUT can specifically be... Figure 1 The SOC chip shown, based on the chip under test (DUT) including the PCS and PHY modules, with the PHY interface being the external output interface, can also be designed as a corresponding PCS and PHY module. This allows the DUT to connect to the chip verification system via the PHY interface of the interface module. Furthermore, the PCS has the function of encoding and decoding the sent and received information, making it easier for the PHY to recover the signal and further saving simulation verification time for the DUT.

[0057] It should be noted that the above example is only an optional implementation. The specific form of the interface module can be designed according to actual needs. This embodiment of the invention does not limit this, as long as the chip verification system can achieve interconnection with the chip under test through the interface module.

[0058] Inter-chip consistency extension unit 32, which is connected to the interface module, is used to convert the simulation verification data of the chip under test.

[0059] The configuration module 33 is connected to the inter-chip consistency extension unit. The configuration module 33 is used to configure the interface module and the inter-chip consistency extension unit, such as configuring the components and timing of data transmission between the interface module and the inter-chip consistency extension unit, so as to provide a simulation verification environment for the chip under test.

[0060] In a specific example, the configuration module can be the UVC (Universal Verification Component) module within a verification platform such as UVM (Universal Verification Methodology). This module can be written in languages ​​like SV (SystemVerilog) to establish a verification environment, thereby simulating and verifying the chip's communication functions. Multiple verification models, such as interface models and register models, can be designed within the UVC module according to the verification requirements. The UVC module allows direct configuration of interface modules and inter-chip consistency extension units, providing a simulation verification environment for the chip under test.

[0061] As can be seen, the embodiments of the present invention directly utilize the configuration module, the interface module, and the inter-chip consistency extension unit to construct a simulation verification environment for realizing inter-chip interaction. Compared with the scheme of configuring another auxiliary test chip to enable the test chip to interconnect with the chip under test and then perform interactive verification, it is not necessary to provide a dedicated auxiliary test chip, and it avoids the process of configuring a large number of components and timing to enable the auxiliary test chip to have independent data processing capabilities. In addition, it saves the time of compiling and simulating these components and timing, thereby improving the chip verification efficiency.

[0062] In some embodiments, before verifying the communication function of the chip under test, it is necessary to initialize the components and timing in the verification environment to guide the subsequent update of the link training state. Therefore, the configuration module can also be used to initialize the interface module and the inter-chip consistency extension unit, thereby generating stimulus signals to drive the execution of the verification process. Compared to Figure 2 The verification structure shown includes numerous components and timing information for the auxiliary test chip. Figure 3 The chip verification system shown has significantly reduced the number of components that need to be initialized. Furthermore, the excitation signal can be generated based on the initialization interface module and the inter-chip consistency extension unit, which also effectively shortens the time required to verify the chip under test.

[0063] It should be noted that the excitation signal (also called excitation) is generated by the platform or simulation components and is used to drive the simulation verification process. This signal is different from the test signals generated by each structure or the test signals generated by each structure in the chip design.

[0064] As an optional implementation, Figure 4 An exemplary schematic diagram of an optional structure of the configuration module in an embodiment of the present invention is shown. For example... Figure 4 As shown, the configuration module 33 may include: a consistency unit configuration model 331 and a communication verification component 332.

[0065] The consistency unit configuration model 331 is a register model for the inter-chip consistency extension unit in the chip verification system. This model enables the initialization of the inter-chip consistency extension unit. In a specific example, during a backdoor access process on the verification platform, the consistency unit configuration model can pass backdoor parameters to the inter-chip consistency extension unit by calling the `write` function, thereby initializing the inter-chip consistency extension unit through backdoor access. The `write` function is a built-in function of the UVM register model, not subject to hardware timing control, and can be called to directly read or modify registers.

[0066] It is understandable that the front-door access method for register initialization requires read and write operations via the bus protocol, and the front-door access can only end when the bus access ends, which is time-consuming. The consistency unit configuration model in this invention directly initializes the inter-chip consistency extension unit through the back-door access method, which can effectively shorten the time for register initialization and thus improve the chip verification efficiency.

[0067] The communication verification component 332 is used to initialize the interface module. In a specific example, the communication verification component may be initialized during the UVM run phase by using a force signal to reassign values ​​to the interface module and its timing. Here, "force" includes force / release / deposit, collectively referred to as "force." "Force" exists in the verification environment to create specific stimuli, such as simulating power connections, accelerating initialization in simulation, or simulating metastable propagation. Using "force" can quickly achieve the verification objective. Compared to initializing auxiliary test chips, the communication verification component in this embodiment uses the force signal to initialize the interface module, effectively shortening the initialization time of various components and timing in the simulation verification environment.

[0068] Reference Figure 4 In some embodiments, the configuration module 33 further includes a general protocol model 333. During the establishment of the simulation verification environment for the chip verification system, the general protocol model can be a general protocol interface based on the communication between the configuration module and the inter-chip consistency extension unit, establishing a data transmission process in the simulation verification environment, enabling the chip verification system to respond with data and drive verification data requests to the chip under test.

[0069] It should be noted that this differs from the actual chip structure (e.g., Figure 2 Unlike the auxiliary test chip shown in the example, the actual chip requires a clock circuit and a reset circuit. The configuration module in the chip verification system of this embodiment of the invention does not need to be equipped with a clock circuit and a reset circuit, thereby further simplifying the structure of the chip verification system and improving the chip verification efficiency.

[0070] In some embodiments, Figure 5 This is a schematic diagram of an optional structure of the communication verification component in an embodiment of the present invention, such as... Figure 5 As shown, the communication verification component 332 may include: a verification request sequence model 501 and a verification response sequence model 502.

[0071] The verification request sequence model 501 is used to create a first data packet, enabling the chip verification system to send simulation verification request data stimulus to the chip under test based on the first data packet. The first data packet can be understood as a data packet containing simulation verification data of the chip under test, with the chip verification system acting as the master and the chip under test as the slave, and the chip verification system issuing an access request to the chip under test.

[0072] The verification response sequence model 502 is used to create a second data packet, enabling the chip verification system to send simulation verification response data stimuli to the chip under test based on the second data packet. The second data packet can be understood as a data packet containing response request data to the chip under test, with the chip under test acting as the master and the chip verification system acting as the slave. The chip verification system returns response data to the access request received from the chip under test.

[0073] Furthermore, in some embodiments, to facilitate sending request data to the same address of the chip under test, refer to Figure 5 As shown, the verification response sequence model 502 may include a storage unit 5021, which stores the received request information from the chip under test, such as write request information, thereby enabling the creation of the second data packet based on the request information. Specifically, the verification response sequence model may read data from the storage unit, create a read response request data packet, and return it to the internal module of the chip under test.

[0074] As can be seen, the embodiments of the present invention can directly configure the interface module and the inter-chip consistency extension module through the configuration module to provide a simulation verification environment for the chip under test, thereby realizing the simulation verification of the chip under test. This avoids the time spent configuring a large number of components and timings to build the simulation verification environment, as well as compiling and simulating these components and timings, thus improving the chip verification efficiency.

[0075] As an optional implementation Figure 6 This is an optional flowchart of the chip verification method in an embodiment of the present invention. The method described below can be considered as the method steps required to perform communication verification of the chip under test based on the various components in the chip verification system. The content described below can be referred to in correspondence with the content described above. (Refer to...) Figure 6 The method process may include the following steps.

[0076] Step S60: Configure the interface module and inter-chip consistency extension unit using the configuration module to provide a simulation verification environment for the chip under test.

[0077] Step S62: Based on the simulation verification environment, verify the communication function of the chip under test.

[0078] Understandably, based on the constructed simulation verification environment, the communication functions of the chip under test can be verified, especially the communication functions of the functional connection module and the port physical layer when the chip under test is used as a master and slave respectively.

[0079] In the chip verification method of this invention, the configuration module, interface module and inter-chip consistency extension unit are directly used to construct a simulation verification environment for realizing inter-chip interaction. Compared with the scheme of configuring another auxiliary test chip to interconnect the test chip and the chip under test for interactive verification, it is not necessary to provide a dedicated auxiliary test chip, and it avoids the process of configuring a large number of components and timing to enable the auxiliary test chip to have independent data processing capabilities. In addition, it saves the time of compiling and simulating these components and timing, thereby improving the chip verification efficiency.

[0080] In some embodiments, before verifying the communication function of the chip under test, it is necessary to initialize the components and timing in the verification environment to guide the subsequent update of the link training state. Therefore, refer to Figure 6 The method steps further include:

[0081] Step S61: Initialize the interface module and the inter-chip consistency extension unit using the configuration module.

[0082] In further embodiments, the configuration module may include a consistency unit configuration model and a communication verification component, wherein the consistency unit configuration model is a register model of the inter-chip consistency extension unit, and the communication verification component is a component for initializing the interface module. In a specific example, based on backdoor access of the verification platform, step S61 may be to initialize the inter-chip consistency extension unit using the consistency unit configuration model via a backdoor access method, and during the initialization called in the UVM run_phase, the communication verification component uses a force signal to reassign values ​​to the interface module and its timing, thereby initializing the interface module.

[0083] In some embodiments, the configuration module may further include a general protocol model, thereby providing a simulation verification environment for the chip under test can be based on a general protocol interface, using the general protocol model to establish a data transmission process in the simulation verification environment, and then using the data transmission process to realize the communication function of the chip under test in the simulation verification environment.

[0084] In verifying the communication function of the chip under test (DUT), as an optional implementation, verifying the DUT's communication function based on the simulation verification environment can be achieved by creating a first data packet and transmitting it to the interface module to send a simulation verification request data stimulus to the DUT, thus verifying the DUT's slave device function (i.e., the DUT acting as a slave). The first data packet can be understood as a data packet containing the DUT's simulation verification data. Alternatively, in the simulation verification environment, verifying the DUT's communication function can be achieved by creating a second data packet and transmitting it to the interface module to send a simulation verification response data stimulus to the DUT, thus verifying the DUT's master device function (i.e., the DUT acting as a master). The second data packet can be understood as a data packet containing response request data to the DUT.

[0085] To facilitate understanding of the above chip verification method, in order to target Figure 2 The following explanation uses the SOC chip under test, as an example, to illustrate the establishment of a simulation verification environment based on the chip verification system of this embodiment. Figure 7 An exemplary schematic diagram of an optional structure for verifying a SOC chip in an embodiment of the present invention is shown, wherein the interface module of the chip verification system can be the pcs and phy modules corresponding to the SOC chip under test.

[0086] like Figure 7 As shown, the SOC chip under test (DUT) connects to the chip verification system via the PHY interface. The chip verification system then constructs the chip verification environment for the DUT. When the DUT has verification requirements, the configuration module of the chip verification system can use a backdoor access through the consistency unit configuration model to quickly initialize the timing files of the inter-chip consistency extension unit (i.e., the inter-chip consistency extension unit in the chip verification system shown in the figure). Furthermore, it uses the force signal to initialize the link timing configuration registers of the PCS and PHY modules (i.e., the PCS and PHY modules in the chip verification system shown in the figure), thereby completing the initialization of the PCS and PHY modules, as well as the inter-chip consistency extension unit, and constructing the chip verification environment. Thus, the request and response data of the chip verification system can be transmitted into the internal modules of the DUT through the DUT's PHY interface.

[0087] When the SOC chip under test acts as the master, its internal module sends request data to the chip verification environment. The request data is transmitted to the general protocol interface in the chip verification environment, and then transmitted by the general protocol model to the configuration module. The verification response sequence model then responds to the request data. The verification response sequence model includes a storage unit that can store the received write request information. If a read request data is sent to the same address of the SOC chip under test later, the data can be read from the storage unit to create a read response request data packet, which is then returned to the internal module of the SOC chip under test.

[0088] When the chip verification environment acts as the master, it needs to issue a request to access the internal module of the SOC chip under test. The chip verification environment uses the verification request sequence model to create an access data packet and transmits the access data packet from the general protocol model to the general protocol interface, and then to the internal module of the SOC chip under test, which then responds.

[0089] It should be noted that, in this embodiment of the invention, the transmission process of the request data of the SOC chip under test from the pcs and phys in the chip verification environment, the inter-chip consistency extension unit to the general protocol interface is the same as... Figure 2 The transmission process of the auxiliary test chip shown is the same, so it will not be described in detail here.

[0090] As can be seen, in the chip verification method of this embodiment, the interface module and the inter-chip consistency extension module are directly configured through the configuration module to provide a simulation verification environment for the chip under test. Then, based on the simulation verification environment, the communication function of the chip under test is verified. Compared with the scheme of configuring another auxiliary test chip to interconnect the test chip and the chip under test for interactive verification, it is not necessary to provide a dedicated auxiliary test chip, and it avoids the process of configuring a large number of components and timing to enable the auxiliary test chip to have independent data processing capabilities. In addition, it saves the time of compiling and simulating these components and timing, thereby improving the chip verification efficiency.

[0091] This invention also provides a chip verification platform, which includes the chip verification system described above, for executing the chip verification method described above.

[0092] This invention also provides a storage medium that stores one or more computer-executable instructions, which, when executed, implement the chip verification method described above.

[0093] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0094] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip verification system, characterized in that, include: An interface module, which is used to interconnect with the chip under test; An inter-chip consistency extension unit connected to the interface module is used to convert the simulation verification data of the chip under test. A configuration module connected to the inter-chip consistency extension unit is used to configure the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the chip under test, so that the communication verification of the chip under test can be realized without the need for an auxiliary test chip.

2. The chip verification system according to claim 1, characterized in that, The configuration module is also used to initialize the interface module and the inter-chip consistency extension unit.

3. The chip verification system according to claim 2, characterized in that, The configuration module includes a consistency unit configuration model and a communication verification component; The consistency unit configuration model is used to initialize the inter-chip consistency extension unit through a backdoor access method; the communication verification component is used to initialize the interface module using a forced assignment signal.

4. The chip verification system according to claim 3, characterized in that, The configuration module also includes a general protocol model; the general protocol model is used to establish a data transmission process in the simulation verification environment based on the general protocol interface.

5. The chip verification system according to claim 3, characterized in that, The communication verification component includes: a verification request sequence model and a verification response sequence model; The verification request sequence model is used to create a first data packet to send simulation verification request data stimulus to the chip under test based on the first data packet. The verification response sequence model is used to create a second data packet to send simulation verification response data stimulus to the chip under test based on the second data packet.

6. The chip verification system according to claim 5, characterized in that, The verification response sequence model includes a storage unit, which is used to store the request information received from the chip under test and to create the second data packet based on the request information.

7. A chip verification method, characterized in that, Based on the chip verification system according to any one of claims 1-6, the method includes: The configuration module is used to configure the interface module and the inter-chip consistency extension unit to provide a simulation verification environment for the chip under test. The communication function of the chip under test is verified based on the simulation verification environment.

8. The chip verification method according to claim 7, characterized in that, Also includes: The interface module and the inter-chip consistency extension unit are initialized using the configuration module.

9. The chip verification method according to claim 8, characterized in that, The configuration module includes a consistency unit configuration model and a communication verification component; The initialization of the interface module and the inter-chip consistency extension unit using the configuration module includes: The inter-chip consistency extension unit is initialized using a backdoor access method based on the consistency unit configuration model; and the communication verification component initializes the interface module using a forced assignment signal.

10. The chip verification method according to claim 9, characterized in that, The configuration module also includes: a general protocol model; The provision of a simulation verification environment for the chip under test includes: establishing a data transmission process in the simulation verification environment based on a general protocol interface and using the general protocol model.

11. The chip verification method according to claim 9, characterized in that, The verification of the communication function of the chip under test based on the simulation verification environment includes: A first data packet is created and transmitted to the interface module to send a simulation verification request data stimulus to the chip under test, thereby verifying the slave device function of the chip under test. Alternatively, a second data packet can be created and transmitted to the interface module to send simulation verification response data stimulus to the chip under test, thereby verifying the master device function of the chip under test.

12. A chip verification platform, characterized in that, The chip verification platform includes the chip verification system as described in any one of claims 1-6, for performing the chip verification method as described in any one of claims 7-11.

13. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which, when executed, implement the chip verification method as described in any one of claims 7-11.

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