A switch capacitor charge pump and control method thereof

Abstract

The present invention relates to a switched capacitor charge pump, which is connected to an input voltage and includes a first capacitor, a second capacitor, a charging switch group, an output switch group, an output capacitor, and a clock unit; the input voltage is respectively connected to the first end of the charging switch group and the first end of the output capacitor; the charging switch group is respectively connected to the first end of the first capacitor and the first end of the second capacitor, and the first end of the first capacitor and the first end of the second capacitor are also respectively connected to the output switch group, and the second end of the first capacitor and the second end of the second capacitor are respectively connected to the output end of the clock unit; the output switch group is connected to the second end of the output capacitor, and the second end of the output capacitor serves as the output end of the charge pump. The present invention improves the switched capacitor charge pump so that the charge pump can not only output a voltage higher than a certain threshold of the input voltage, but also that the voltage is in a stable and continuous voltage domain.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a switch capacitor charge pump and a control method thereof. Background Art

[0002] In high-voltage input sampling circuits, a voltage domain with a threshold higher than the input high-voltage signal is required to control the gate of the input sampling switch, such as the gate of a MOSFET. While traditional sampling circuits can generate a gate control signal with a threshold higher than the input high-voltage signal, they cannot generate a stable voltage source with a threshold higher than the input high-voltage signal to provide a stable voltage for other circuits. Summary of the Invention

[0003] The purpose of the present invention is to output a stable voltage source which is higher than the input voltage by a certain threshold value, and to provide a switch capacitor charge pump and a control method thereof.

[0004] In order to achieve the above-mentioned object of the invention, the embodiment of the present invention provides the following technical solutions:

[0005] A switched capacitor charge pump is connected to an input voltage, comprising a first capacitor, a second capacitor, a charging switch group, an output switch group, an output capacitor, and a clock unit;

[0006] The input voltage is connected to the charging switch group and the first end of the output capacitor respectively;

[0007] The charging switch group is connected to the first end of the first capacitor and the first end of the second capacitor respectively. The first end of the first capacitor and the first end of the second capacitor are also connected to the output switch group respectively. The second end of the first capacitor and the second end of the second capacitor are connected to the output end of the clock unit respectively.

[0008] The output switch group is connected to the second end of the output capacitor, and the second end of the output capacitor serves as the output end of the charge pump.

[0009] Furthermore, the charge pump further includes a first inverter and a second inverter;

[0010] The output end of the clock unit is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the second end of the first capacitor and the input end of the second inverter, and the output end of the second inverter is connected to the second end of the second capacitor.

[0011] As a first possible implementation manner, the charging switch group includes a first switch and a second switch, the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor;

[0012] The source of the first switch and the source of the second switch are respectively connected to the input voltage, the drain of the first switch and the gate of the second switch are respectively connected to the first end of the first capacitor, and the drain of the second switch and the gate of the first switch are respectively connected to the first end of the second capacitor.

[0013] As a second possible implementation method, the charging switch includes a first switch and a second switch, the first switch is a diode, and the second switch is a diode;

[0014] The anode of the first switch and the anode of the second switch are respectively connected to the input voltage, the cathode of the first switch is connected to the first end of the first capacitor, and the cathode of the second switch is connected to the first end of the second capacitor.

[0015] As a further solution of the first or second possible implementation mode, the output switch group includes a third switch and a fourth switch, the third switch is a P-type MOS transistor, and the fourth switch is a P-type MOS transistor;

[0016] The source of the third switch and the gate of the third switch are respectively connected to the first end of the first capacitor, the gate of the fourth switch and the source of the fourth switch are respectively connected to the first end of the second capacitor, and the drain of the third switch and the drain of the fourth switch are respectively connected to the second end of the output capacitor.

[0017] As a further solution of the first or second possible implementation mode, the output switch group includes a third switch and a fourth switch, the third switch is a diode, and the fourth switch is a diode;

[0018] The anode of the third switch is connected to the first end of the first capacitor, the anode of the fourth switch is connected to the first end of the second capacitor, and the cathodes of the third switch and the fourth switch are respectively connected to the second end of the output capacitor.

[0019] A method for controlling a switched capacitor charge pump comprises the following steps:

[0020] Step 1: providing an input voltage VIN to the charging switch group, charging the first capacitor and the second capacitor through the charging switch group; charging the output capacitor so that the voltage at the first terminal of the output capacitor is VIN;

[0021] In step 2, the clock unit generates a clock signal alternating between a high level Vclk1 and a low level Vclk2, and provides an inverted clock signal to the second ends of the first capacitor and the second capacitor, so that the first capacitor and the second capacitor alternately charge the output capacitor via the charging switch group and the output switch group, so that the output end connected to the second end of the output capacitor generates a continuous and stable output voltage, wherein the output voltage is the sum of the input voltage VIN and the first threshold voltage.

[0022] As a first possible implementation manner, the charging switch group includes a first switch and a second switch, wherein the first switch is an N-type MOS transistor and the second switch is an N-type MOS transistor; the output switch group includes a third switch and a fourth switch, wherein the third switch is a P-type MOS transistor and the fourth switch is a P-type MOS transistor;

[0023] When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the second switch to be turned on, so that the first end of the second capacitor is the input signal voltage VIN. In the next clock phase, the second end of the second capacitor receives a high-level clock signal, and the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase;

[0024] When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the first switch to be turned on, so that the first end of the first capacitor is the input signal voltage VIN. In the next clock phase, the second end of the first capacitor receives a high-level clock signal, and the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase.

[0025] As a second possible implementation manner, the charging switch group includes a first switch and a second switch, wherein the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor; the output switch group includes a third switch and a fourth switch, wherein the third switch is a diode, and the fourth switch is a diode;

[0026] When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the second switch to be turned on, so that the first end of the second capacitor is the input signal voltage VIN. In the next clock phase, the second end of the second capacitor receives a high-level clock signal, and the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the fourth switch;

[0027] When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the first switch to be turned on, so that the first end of the first capacitor is the input signal voltage VIN. In the next clock phase, the second end of the first capacitor receives a high-level clock signal, and the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the third switch.

[0028] As a third possible implementation manner, the charging switch group includes a first switch and a second switch, wherein the first switch is a diode and the second switch is a diode; the output switch group includes a third switch and a fourth switch, wherein the third switch is a P-type MOS transistor and the fourth switch is a P-type MOS transistor;

[0029] The input voltage VIN charges the first end of the first capacitor to the input voltage VIN minus the forward conduction voltage of the first switch through the first switch, and charges the first end of the second capacitor to the input voltage VIN minus the forward conduction voltage of the second switch through the second switch;

[0030] When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch;

[0031] When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the second switch.

[0032] As a fourth possible implementation manner, the charging switch group includes a first switch and a second switch, the first switch is a diode, the second switch is a diode, and the output switch group includes a third switch and a fourth switch, the third switch is a diode, and the fourth switch is a diode;

[0033] The input voltage VIN charges the first end of the first capacitor to the input voltage VIN minus the forward conduction voltage of the first switch through the first switch, and charges the first end of the second capacitor to the input voltage VIN minus the forward conduction voltage of the second switch through the second switch;

[0034] When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch and the third switch;

[0035] When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the second switch and the fourth switch.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention improves the charge pump of the switched capacitor so that the charge pump can not only output a voltage higher than a certain threshold of the input voltage, but also the voltage is in a stable and continuous voltage domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is a schematic diagram of a charge pump circuit according to a first embodiment of the present invention;

[0040] Figure 2 FIG1 is a schematic diagram of a charge pump circuit according to a second embodiment of the present invention;

[0041] Figure 3 FIG1 is a schematic diagram of a charge pump circuit according to a third embodiment of the present invention;

[0042] Figure 4 2 is a schematic diagram of a charge pump circuit according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0044] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and are not to be understood as indicating or implying relative importance, or implying any actual relationship or order between these entities or operations. In addition, the terms "connected" and "connected" can refer to direct connection between elements or indirect connection via other elements.

[0045] The present invention is realized by the following technical solution: a charge pump of a switched capacitor, see Figure 1 , connected to the input voltage. In one embodiment, the voltage value VIN output by the input voltage ranges from 0 to 80V. The charge pump includes a first capacitor C1, a second capacitor C2, a charging switch group, an output switch group, an output capacitor C3, and a clock unit. The input voltage is respectively connected to the first end of the charging switch group and the first end of the output capacitor C3; the charging switch group is respectively connected to the first end of the first capacitor C1 and the first end of the second capacitor C2, and the first end of the first capacitor C1 and the first end of the second capacitor C2 are also respectively connected to the output switch group, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are respectively connected to the output end of the clock unit; the output switch group is connected to the second end of the output capacitor C3, and the second end of the output capacitor C3 serves as the output end of the charge pump.

[0046] Please continue to see Figure 1 In detail, the charge pump also includes a first inverter and a second inverter; the output end of the clock unit is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the second end of the first capacitor C1 and the input end of the second inverter, and the output end of the second inverter is connected to the second end of the second capacitor C2.

[0047] As a first possible implementation, see Figure 1 The charging switch group includes a first switch NM1 and a second switch NM2, the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor; the output switch group includes a third switch PM1 and a fourth switch PM2, the third switch is a P-type MOS transistor, and the fourth switch is a P-type MOS transistor.

[0048] The source of the first switch NM1 and the source of the second switch NM2 are respectively connected to the input voltage, the drain of the first switch NM1 and the gate of the second switch NM2 are respectively connected to the first end of the first capacitor C1, and the drain of the second switch NM2 and the gate of the first switch NM1 are respectively connected to the first end of the second capacitor C2.

[0049] It is easy to understand that the N-type MOS tube is an NPN tube, whose source and drain are two symmetrical N terminals, and the gate is the middle P terminal, so the source and drain of the N-type MOS tube can be interchanged.

[0050] The source of the third switch PM1 and the gate of the third switch PM1 are respectively connected to the first end of the first capacitor C1, the gate of the fourth switch PM2 and the source of the fourth switch PM2 are respectively connected to the first end of the second capacitor C2, and the drain of the third switch PM1 and the drain of the fourth switch PM2 are respectively connected to the second end of the output capacitor C3.

[0051] It is easy to understand that the P-type MOS tube is a PNP tube, whose source and drain are two symmetrical P terminals, and the gate is the middle N terminal, so the source and drain of the P-type MOS tube can also be interchanged.

[0052] As a second possible implementation, see Figure 2 The charging switch group includes a first switch NM1 and a second switch NM2, the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor; the output switch group includes a third switch Dp1 and a fourth switch Dp2, the third switch is a diode, and the fourth switch is a diode.

[0053] The source of the first switch NM1 and the source of the second switch NM2 are respectively connected to the input voltage, the drain of the first switch NM1 and the gate of the second switch NM2 are respectively connected to the first end of the first capacitor C1, and the drain of the second switch NM2 and the gate of the first switch NM1 are respectively connected to the second end of the second capacitor C2.

[0054] The anode of the third switch Dp1 is connected to the first end of the first capacitor C1, the anode of the fourth switch Dp2 is connected to the first end of the second capacitor C2, and the cathodes of the third switch Dp1 and the fourth switch Dp2 are respectively connected to the second end of the output capacitor C3.

[0055] As a third possible implementation, see Figure 3 The charging switch includes a first switch Dn1 and a second switch Dn2, the first switch is a diode, and the second switch is a diode; the output switch group includes a third switch PM1 and a fourth switch PM2, the third switch is a P-type MOS tube, and the fourth switch is a P-type MOS tube.

[0056] The anode of the first switch Dn1 and the anode of the second switch Dn2 are respectively connected to the input voltage, the cathode of the first switch Dn1 is connected to the first end of the first capacitor C1, and the cathode of the second switch Dn2 is connected to the first end of the second capacitor C2.

[0057] The source of the third switch PM1 and the gate of the third switch PM1 are respectively connected to the first end of the first capacitor C1, the gate of the fourth switch PM2 and the source of the fourth switch PM2 are respectively connected to the first end of the second capacitor C2, and the drain of the third switch PM1 and the drain of the fourth switch PM2 are respectively connected to the second end of the output capacitor C3.

[0058] As a fourth possible implementation, see Figure 4 The charging switch includes a first switch Dn1 and a second switch Dn2, wherein the first switch is a diode and the second switch is a diode; the output switch group includes a third switch Dp1 and a fourth switch Dp2, wherein the third switch is a diode and the fourth switch is a diode;

[0059] The anode of the first switch Dn1 and the anode of the second switch Dn2 are respectively connected to the input voltage, the cathode of the first switch Dn1 is connected to the first end of the first capacitor C1, and the cathode of the second switch Dn2 is connected to the first end of the second capacitor C2.

[0060] The anode of the third switch Dp1 is connected to the first end of the first capacitor C1, the anode of the fourth switch Dp2 is connected to the first end of the second capacitor C2, and the cathodes of the third and fourth switches Dp1 are connected to the second end of the output capacitor C3 respectively.

[0061] In the above four possible implementation modes, the high level Vclk1 output by the clock unit may be 5V, and the low level may be 0V. However, this solution does not limit the specific sizes of the high level and the low level, which can be set according to the actual circuit requirements.

[0062] Based on the above charge pump, the present invention further proposes a control method for a switched capacitor charge pump, comprising the following steps:

[0063] Step 1: Provide an input voltage VIN to the charging switch group to charge the first capacitor C1 and the second capacitor C2 through the charging switch group; charge the output capacitor so that the voltage at the first terminal of the output capacitor is VIN;

[0064] In step 2, the clock unit generates a clock signal alternating between a high level Vclk1 and a low level Vclk2, and provides an inverted clock signal to the second ends of the first capacitor and the second capacitor, so that the first capacitor and the second capacitor alternately charge the output capacitor via the charging switch group and the output switch group, so that the output end connected to the second end of the output capacitor generates a continuous and stable output voltage, wherein the output voltage is the sum of the input voltage VIN and the first threshold voltage.

[0065] As a first possible implementation, see Figure 1The charging switch group includes a first switch NM1 and a second switch NM2, the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor; the output switch group includes a third switch PM1 and a fourth switch PM2, the third switch is a P-type MOS transistor, and the fourth switch is a P-type MOS transistor.

[0066] The specific steps of step 1 are:

[0067] An input voltage VIN is supplied to the source of the first switch NM1, and the first capacitor C1 is charged through the drain of the first switch NM1, so that the voltage at the first terminal of the first capacitor C1 is VIN-0.7V. An input voltage VIN is supplied to the source of the second switch NM2, and the second capacitor C2 is charged through the drain of the second switch NM2, so that the voltage at the first terminal of the second capacitor C2 is VIN-0.7V.

[0068] The output capacitor C3 is charged so that the voltage at the first terminal of the output capacitor C3 is VIN.

[0069] The specific steps of step 2 are:

[0070] When the clock unit outputs a low level Vclk2, the first inverter converts the low level Vclk2 into a high level Vclk1 and outputs it to the second end of the first capacitor C1 and the input end of the second inverter, so that the voltage at the first end of the first capacitor C1 is VIN-0.7V+Vclk1, and the voltage at the second end of the first capacitor C1 is Vclk1; the second inverter converts the high level Vclk1 output by the first inverter into a low level Vclk2 and outputs it to the second end of the second capacitor C2, so that the voltage at the first end of the second capacitor C2 is VIN-0.7V, and the voltage at the second end of the second capacitor C2 is Vclk2;

[0071] At this time, the first end of the first capacitor C1 controls the second switch NM2 to be turned on, so that the voltage at the first end of the second capacitor C2 is VIN, and the voltage at the second end of the second capacitor C2 is Vclk2;

[0072] In the next clock phase, that is, when the clock unit outputs a high level Vclk1, the first inverter converts the high level Vclk1 into a low level Vclk2 and outputs it to the second end of the first capacitor C1 and the input end of the second inverter, so that the voltage at the first end of the first capacitor C1 is VIN-0.7V+Vclk1, and the voltage at the second end of the first capacitor C1 is Vclk1; the second inverter converts the low level Vclk2 output by the first inverter into a high level Vclk1 and outputs it to the second end of the second capacitor C2, so that the voltage at the first end of the second capacitor C2 is VIN+Vclk1, and the voltage at the second end of the second capacitor C2 is Vclk1;

[0073] At this time, the first end of the second capacitor C2 controls the fourth switch PM2 to be turned on, so that the second capacitor C2 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2, that is, VIN+Vclk1-Vclk2.

[0074] When the clock unit outputs a high level Vclk1, the first inverter converts the high level Vclk1 into a low level Vclk2 and outputs it to the second end of the first capacitor C1 and the input end of the second inverter, so that the voltage at the first end of the first capacitor C1 is VIN-0.7V and the voltage at the second end of the first capacitor C1 is Vclk2; the second inverter converts the low level Vclk2 output by the first inverter into a high level Vclk1 and outputs it to the second end of the second capacitor C2, so that the voltage at the first end of the second capacitor C2 is VIN-0.7V+Vclk1 and the voltage at the second end of the second capacitor C2 is Vclk1;

[0075] At this time, the first end of the second capacitor C2 controls the first switch NM1 to be turned on, so that the upper plate voltage of the first capacitor C1 is VIN, and the lower plate voltage of the first capacitor C1 is Vclk2;

[0076] In the next clock phase, that is, when the clock unit outputs a low level Vclk2, the first inverter converts the high level Vclk1 into a low level Vclk2 and outputs it to the second end of the first capacitor C1 and the input end of the second inverter, so that the voltage at the first end of the first capacitor C1 is VIN+Vclk1, and the voltage at the second end of the first capacitor C1 is Vclk1; the second inverter converts the high level Vclk1 output by the first inverter into a low level Vclk2 and outputs it to the second end of the second capacitor C2, so that the voltage at the first end of the second capacitor C2 is VIN-0.7V+Vclk1, and the voltage at the second end of the second capacitor C2 is Vclk1;

[0077] At this time, the first end of the first capacitor C1 controls the third switch PM1 to be turned on, so that the first capacitor C1 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2, that is, VIN+Vclk1-Vclk2.

[0078] In summary, the clock unit alternately provides opposite clock signals to the second ends of the first capacitor C1 and the second capacitor C2. When the first switch NM1 and the second switch NM2 are turned on, the first capacitor C1 controls the third switch PM1 to turn on, and the second capacitor C2 controls the fourth switch PM2 to turn on alternately. This causes the first capacitor C1 and the second capacitor C2 to alternately charge the output capacitor C3, causing the output capacitor C3 to generate a continuous and stable output voltage. The output voltage is the sum of the input voltage VIN and a first threshold voltage. In this embodiment, the first threshold voltage is Vclk1-Vclk2.

[0079] As a second possible implementation, see Figure 2 The charging switch group includes a first switch NM1 and a second switch NM2, the first switch is an N-type MOS transistor, and the second switch is an N-type MOS transistor; the output switch group includes a third switch Dp1 and a fourth switch Dp2, the third switch is a diode, and the fourth switch is a diode.

[0080] The specific steps of step 1 are:

[0081] An input voltage VIN is supplied to the source of the first switch NM1, and the first capacitor C1 is charged through the drain of the first switch NM1, so that the voltage at the first terminal of the first capacitor C1 is VIN-0.7V. An input voltage VIN is supplied to the source of the second switch NM2, and the second capacitor C2 is charged through the drain of the second switch NM2, so that the voltage at the first terminal of the second capacitor C2 is VIN-0.7V.

[0082] The output capacitor C3 is charged so that the voltage at the first terminal of the output capacitor C3 is VIN.

[0083] The specific steps of step 2 are:

[0084] When the clock unit outputs a low level Vclk2, the second end of the first capacitor C1 receives a high level Vclk1, and the first end of the first capacitor C1 controls the second switch NM2 to be turned on, so that the voltage at the first end of the second capacitor C2 is VIN. The rest of the contents are the same as the first possible implementation method.

[0085] In the next clock phase, that is, when the clock unit outputs the low level Vclk2, the second end of the second capacitor C2 receives the high level Vclk1, and the first end of the second capacitor C2 controls the fourth switch Dp2 to be conductive, so that the second capacitor C2 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the high level Vclk1 and the low level Vclk2 in this clock phase, minus the forward conduction voltage of the fourth switch Dp2 of 0.7V, that is, VIN+Vclk1-Vclk2-0.7V.

[0086] When the clock unit outputs a high level Vclk1, the second end of the second capacitor C2 receives the high level Vclk1, and the first end of the second capacitor C2 controls the first switch NM1 to turn on, so that the voltage at the first end of the first capacitor C1 is VIN. The rest of the contents are the same as the first possible implementation method.

[0087] In the next clock phase, that is, when the clock unit outputs a low level Vclk2, the second end of the first capacitor C1 receives a high level Vclk1. The first end of the first capacitor C1 controls the third switch Dp1 to turn on, so that the first capacitor C1 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the high level Vclk1 and the low level Vclk2 in this clock phase, minus the forward conduction voltage of the third switch Dp1 of 0.7V, that is, VIN+Vclk1-Vclk2-0.7V.

[0088] In summary, the clock unit alternately provides opposite clock signals to the second ends of the first capacitor C1 and the second capacitor C2. When the first switch NM1 and the second switch NM2 are turned on, the first capacitor C1 controls the third switch PM1 to turn on, and the second capacitor C2 controls the fourth switch PM2 to turn on alternately. As a result, the first capacitor C1 and the second capacitor C2 alternately charge the output capacitor C3, causing the output capacitor C3 to generate a continuous and stable output voltage. The output voltage is the sum of the input voltage VIN and a first threshold voltage. In this embodiment, the first threshold voltage is Vclk1-Vclk2-0.7V.

[0089] Compared to the first possible implementation, the second possible implementation replaces the third and fourth switches with diodes instead of P-type MOS transistors. This results in a 0.7V forward voltage loss when the third and fourth switches are turned on, whereas the forward voltage is negligible in the first possible implementation. Therefore, the first possible implementation is the optimal solution of the present invention.

[0090] As a third possible implementation, see Figure 3 The charging switch includes a first switch Dn1 and a second switch Dn2, the first switch is a diode, and the second switch is a diode; the output switch group includes a third switch PM1 and a fourth switch PM2, the third switch is a P-type MOS tube, and the fourth switch is a P-type MOS tube.

[0091] The specific steps of step 1 are:

[0092] An input voltage VIN is supplied to the anode of the first switch Dn1, and the first capacitor C1 is charged through the cathode of the first switch Dn1, so that the voltage at the first terminal of the first capacitor C1 is VIN-0.7V, where 0.7V is the forward conduction voltage of the first switch Dn1. An input voltage VIN is supplied to the anode of the second switch Dn2, and the second capacitor C2 is charged through the cathode of the second switch Dn2, so that the voltage at the first terminal of the second capacitor C2 is VIN-0.7V, where 0.7V is the forward conduction voltage of the second switch Dn2.

[0093] The output capacitor C3 is charged so that the voltage at the first terminal of the output capacitor C3 is VIN.

[0094] The specific steps of step 2 are:

[0095] When the clock unit outputs a low level Vclk2, the second end of the first capacitor C1 receives a high level Vclk1. The first end of the first capacitor C1 controls the third switch PM1 to turn on, so that the first capacitor C1 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the high level Vclk1 and the low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch, that is, VIN + Vclk1 - Vclk2 - 0.7V.

[0096] When the clock unit outputs a high level Vclk1, the second end of the second capacitor C2 receives the high level Vclk1, and the first end of the second capacitor C2 controls the fourth switch PM2 to turn on, so that the second capacitor C2 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the high level Vclk1 and the low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch, that is, VIN+Vclk1-Vclk2-0.7V.

[0097] In summary, the clock unit alternately provides opposite clock signals to the second ends of the first capacitor C1 and the second capacitor C2. When the first switch Dn1 and the second switch Dn2 are turned on, the first capacitor C1 controls the third switch PM1 to turn on, and the second capacitor C2 controls the fourth switch PM2 to turn on alternately. As a result, the first capacitor C1 and the second capacitor C2 alternately charge the output capacitor C3, causing the output capacitor C3 to generate a continuous and stable output voltage. The output voltage is the sum of the input voltage VIN and a first threshold voltage. In this embodiment, the first threshold voltage is Vclk1-Vclk2-0.7V.

[0098] Compared with the first possible implementation, the third possible implementation replaces the first switch and the second switch from N-type MOS tubes to diodes. After the first switch and the second switch are turned on, a forward conduction voltage of 0.7V will be lost, while in the first possible implementation, the forward conduction voltage can be ignored after the first switch and the second switch are turned on.

[0099] As a fourth possible implementation, see Figure 4 The charging switch includes a first switch Dn1 and a second switch Dn2, the first switch is a diode, and the second switch is a diode; the output switch group includes a third switch Dp1 and a fourth switch Dp2, the third switch is a diode, and the fourth switch is a diode.

[0100] The specific steps of step 1 are:

[0101] The input voltage VIN charges the first end of the first capacitor C1 to VIN-0.7V through the first switch Dn1, charges the first end of the second capacitor C2 to VIN-0.7V through the second switch Dn2, and charges the first end of the output capacitor C3 to VIN. The rest of the contents are the same as the third possible implementation method.

[0102] The specific steps of step 2 are:

[0103] When the clock unit outputs a low level Vclk2, the second end of the first capacitor C1 receives a high level Vclk1. The first end of the first capacitor C1 controls the third switch Dp1 to turn on, so that the first capacitor C1 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch and the third switch, that is, VIN+Vclk1-Vclk2-0.7V-0.7V.

[0104] When the clock unit outputs a high level Vclk1, the second end of the second capacitor C2 receives the high level Vclk1, and the first end of the second capacitor C2 controls the fourth switch Dp2 to turn on, so that the second capacitor C2 charges the second end of the output capacitor C3 to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the second switch and the fourth switch, that is, VIN+Vclk1-Vclk2-0.7V-0.7V.

[0105] In summary, the clock unit alternately provides opposite clock signals to the second ends of the first capacitor C1 and the second capacitor C2. When the first switch Dn1 and the second switch Dn2 are turned on, the first capacitor C1 controls the third switch Dp1 to turn on, and the second capacitor C2 controls the fourth switch Dp2 to turn on alternately. As a result, the first capacitor C1 and the second capacitor C2 alternately charge the output capacitor C3, causing the output capacitor C3 to generate a continuous and stable output voltage. The output voltage is the sum of the input voltage VIN and the first threshold voltage. In this embodiment, the first threshold voltage is Vclk1-Vclk2-0.7V-0.7V.

[0106] Compared with the first possible implementation, the fourth possible implementation replaces the first switch and the second switch from N-type MOS tubes to diodes, and replaces the first switch and the second switch from P-type MOS tubes to diodes. Then, after the first switch and the second switch are turned on, a forward conduction voltage of 0.7V will be lost, and after the third switch and the fourth switch are turned on, a forward conduction voltage of 0.7V will also be lost.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A switched capacitor charge pump connected to an input voltage, comprising a first capacitor and a second capacitor, characterized in that: Also includes: Charging switch group, output switch group, output capacitor, clock unit; The input voltage is connected to the charging switch group and the first end of the output capacitor respectively; The charging switch group is connected to the first end of the first capacitor and the first end of the second capacitor respectively. The first end of the first capacitor and the first end of the second capacitor are also connected to the output switch group respectively. The second end of the first capacitor and the second end of the second capacitor are connected to the output end of the clock unit respectively. The output switch group is connected to the second end of the output capacitor, and the second end of the output capacitor serves as the output end of the charge pump.

2. The switched capacitor charge pump according to claim 1, wherein: The charge pump further includes a first inverter and a second inverter; The output end of the clock unit is connected to the input end of the first inverter, the output end of the first inverter is respectively connected to the second end of the first capacitor and the input end of the second inverter, and the output end of the second inverter is connected to the second end of the second capacitor.

3. The switched capacitor charge pump according to claim 1, wherein: The charging switch group includes a first switch and a second switch, wherein the first switch is an N-type MOS transistor and the second switch is an N-type MOS transistor; The source of the first switch and the source of the second switch are respectively connected to the input voltage, the drain of the first switch and the gate of the second switch are respectively connected to the first end of the first capacitor, and the drain of the second switch and the gate of the first switch are respectively connected to the first end of the second capacitor.

4. The switched capacitor charge pump according to claim 1, wherein: The charging switch includes a first switch and a second switch, wherein the first switch is a diode and the second switch is a diode; The anode of the first switch and the anode of the second switch are respectively connected to the input voltage, the cathode of the first switch is connected to the first end of the first capacitor, and the cathode of the second switch is connected to the first end of the second capacitor.

5. A switched capacitor charge pump according to claim 3 or 4, characterized in that: The output switch group includes a third switch and a fourth switch, wherein the third switch is a P-type MOS transistor and the fourth switch is a P-type MOS transistor; The source of the third switch and the gate of the third switch are respectively connected to the first end of the first capacitor, the gate of the fourth switch and the source of the fourth switch are respectively connected to the first end of the second capacitor, and the drain of the third switch and the drain of the fourth switch are respectively connected to the second end of the output capacitor.

6. A switched capacitor charge pump according to claim 3 or 4, characterized in that: The output switch group includes a third switch and a fourth switch, wherein the third switch is a diode and the fourth switch is a diode; The anode of the third switch is connected to the first end of the first capacitor, the anode of the fourth switch is connected to the first end of the second capacitor, and the cathodes of the third switch and the fourth switch are respectively connected to the second end of the output capacitor.

7. The method for controlling a switched capacitor charge pump according to any one of claims 1 to 6, wherein: The following steps are involved: Step 1: providing an input voltage VIN to the charging switch group, charging the first capacitor and the second capacitor through the charging switch group; charging the output capacitor so that the voltage at the first terminal of the output capacitor is VIN; In step 2, the clock unit generates a clock signal alternating between a high level Vclk1 and a low level Vclk2, and provides an inverted clock signal to the second ends of the first capacitor and the second capacitor, so that the first capacitor and the second capacitor alternately charge the output capacitor via the charging switch group and the output switch group, so that the output end connected to the second end of the output capacitor generates a continuous and stable output voltage, wherein the output voltage is the sum of the input voltage VIN and the first threshold voltage.

8. The method for controlling a switched capacitor charge pump according to claim 7, wherein: The charging switch group includes a first switch and a second switch, wherein the first switch is an N-type MOS transistor and the second switch is an N-type MOS transistor; the output switch group includes a third switch and a fourth switch, wherein the third switch is a P-type MOS transistor and the fourth switch is a P-type MOS transistor; When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the second switch to be turned on, so that the first end of the second capacitor is the input signal voltage VIN. In the next clock phase, the second end of the second capacitor receives a high-level clock signal, and the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase; When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the first switch to be turned on, so that the first end of the first capacitor is the input signal voltage VIN. In the next clock phase, the second end of the first capacitor receives a high-level clock signal, and the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase.

9. The method for controlling a switched capacitor charge pump according to claim 7, wherein: The charging switch group includes a first switch and a second switch, wherein the first switch is an N-type MOS transistor and the second switch is an N-type MOS transistor; the output switch group includes a third switch and a fourth switch, wherein the third switch is a diode and the fourth switch is a diode; When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the second switch to be turned on, so that the first end of the second capacitor is the input signal voltage VIN. In the next clock phase, the second end of the second capacitor receives a high-level clock signal, and the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the fourth switch; When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the first switch to be turned on, so that the first end of the first capacitor is the input signal voltage VIN. In the next clock phase, the second end of the first capacitor receives a high-level clock signal, and the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the third switch.

10. The method for controlling a switched capacitor charge pump according to claim 7, wherein: The charging switch group includes a first switch and a second switch, the first switch is a diode, the second switch is a diode, the output switch group includes a third switch and a fourth switch, the third switch is a P-type MOS transistor, and the fourth switch is a P-type MOS transistor; The input voltage VIN charges the first end of the first capacitor to the input voltage VIN minus the forward conduction voltage of the first switch through the first switch, and charges the first end of the second capacitor to the input voltage VIN minus the forward conduction voltage of the second switch through the second switch; When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch; When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the second switch.

11. The method for controlling a switched capacitor charge pump according to claim 7, wherein: The charging switch group includes a first switch and a second switch, the first switch is a diode, the second switch is a diode, the output switch group includes a third switch and a fourth switch, the third switch is a diode, and the fourth switch is a diode; The input voltage VIN charges the first end of the first capacitor to the input voltage VIN minus the forward conduction voltage of the first switch through the first switch, and charges the first end of the second capacitor to the input voltage VIN minus the forward conduction voltage of the second switch through the second switch; When the second end of the first capacitor receives a high-level clock signal, the first end of the first capacitor controls the third switch to be turned on, so that the first capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, minus the forward conduction voltage of the first switch and the third switch; When the second end of the second capacitor receives a high-level clock signal, the first end of the second capacitor controls the fourth switch to be turned on, so that the second capacitor charges the second end of the output capacitor to the sum of the input voltage VIN and the differential mode of the clock high level Vclk1 and the clock low level Vclk2 in this clock phase, and then subtracts the forward conduction voltage of the second switch and the fourth switch.

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