A signal processing method and device compatible with multi-order modulation and demodulation

Abstract

The present application provides a signal processing method and device compatible with multi-order modulation and demodulation, including: obtaining signal sampling sequence information, performing interpolation filter loop sampling rate conversion, performing timing error detection, calculating the timing error estimate of the estimated optimal signal sampling sequence, and judging whether the estimated optimal signal sampling sequence meets the optimal signal sampling sequence information rule; if the rule is met, outputting the optimal signal sampling sequence information. The method provided by the present application can be compatible with signal tuning of multi-order modulation and demodulation. Therefore, in various network environments, for modulation signals of different orders, the bit error rate of information transmission can be reduced, and the stability and reliability of the signal can be improved.

Description

Technical Field

[0001] The present invention relates to the field of communication design, and in particular to a signal processing method and device compatible with multi-order modulation and demodulation. Background Art

[0002] With the rapid development of the communications industry, modulation and demodulation technology has been widely used because it can improve the effectiveness of information transmission. On the one hand, the higher the order of the modulation technology (i.e., the size of M), the higher its effectiveness (e.g., in the same time, 16QAM can transmit more information than 8PSK); but on the other hand, affected by the communication environment, the higher the order of the modulation technology, the lower its reliability (e.g., in the same environment, 16QAM produces more errors than 8PSK). The currently commonly used communication system that switches the modulation and demodulation mode has a stable sampling signal sequence when working in a good environment, and a high-order modulation and demodulation mode can be used; when working in a harsh environment, the obtained sampling signal sequence is not stable enough, that is, a low-order modulation and demodulation mode is used. This modulation technology uses a bit synchronization algorithm to further reduce the bit error rate of information transmission and improve system reliability.

[0003] Among the bit synchronization algorithms, the most commonly used bit synchronization algorithm based on the Gardner timing error detection algorithm, the Gardner algorithm, is derived from the QPSK signal and is not applicable to the MQAM signal. That is, when the system selects a high-order modulation and demodulation method (such as 16QAM, 64QAM), the usual Gardner bit synchronization algorithm will lead to an increase in the system's bit error rate and generate a large amount of erroneous information. Therefore, a more compatible signal processing solution is needed to make it compatible with multi-order modulation and demodulation technology, process information transmission generated in a variety of network environments, effectively control the bit error rate of information transmission, and improve the stability and reliability of modulation and demodulation processing. Summary of the invention

[0004] In a first aspect, to achieve the above-mentioned purpose, the present application provides a signal processing method compatible with multi-order modulation and demodulation, comprising:

[0005] Acquire signal sampling sequence information, wherein the signal sampling sequence information is a received signal sampling sequence;

[0006] Execute interpolation filter loop sampling rate conversion, the sampling rate conversion means obtaining interpolation filter input parameter information, calculating the optimal sampling time of the signal sampling sequence, outputting the estimated optimal signal sampling sequence and the number of interpolation filter loop executions, the interpolation filter input parameter information including the received signal sampling sequence;

[0007] Perform timing error detection, calculate the timing error estimate of the estimated best signal sampling sequence, and determine whether the estimated best signal sampling sequence meets the best signal sampling sequence information rule;

[0008] If the timing error estimation value does not satisfy the rule, performing the optimization parameter processing; performing the optimization parameter processing means: inputting the timing error estimation value and the number of execution times of the interpolation filter loop, outputting the optimization processing parameters, and performing the interpolation filter loop sampling rate conversion;

[0009] If the specified rules are met, the optimal signal sampling sequence information is output;

[0010] The interpolation filter input parameter information also includes optimization processing parameters.

[0011] Furthermore, judging whether the estimated best signal sampling sequence satisfies the best signal sampling sequence information rule means judging the difference between the timing error estimate of the estimated best signal sampling sequence and 0. If the difference is less than a specified threshold, the estimated best signal sampling sequence can be determined to be the best signal sampling sequence.

[0012] Among them, the optimization parameter processing includes loop filter processing, digital control oscillator processing and optimization verification;

[0013] The loop filter processing is an optimization parameter processing step for calculating the control word of the digital controlled oscillator based on the timing error estimate;

[0014] The numerically controlled oscillator processing is another optimization parameter processing step, which is used to calculate the optimization processing parameters according to the numerically controlled oscillator control word;

[0015] The optimization check is used to control the loop filter processing count and select the optimization parameter processing step;

[0016] Among them, controlling the loop filter processing count refers to: obtaining the input interpolation filter loop execution times, obtaining the loop filter execution times under the interpolation filter loop execution times, and controlling the count value to increase. Therefore, the count value controlled to increase also includes the loop filter execution times.

[0017] Furthermore, the calculation method of the loop filter processing includes:

[0018] Determine whether the loop filter processing count is equal to 1. If it is equal to 1, the calculation method is:

[0019] w(2)=w(1)+c1×time_error(1)+c2×time_error(1),

[0020] Wherein, w(2) is the control word of the digital controlled oscillator output this time, w(1) is the initial value of the control word of the digital controlled oscillator, time_error(1) is the initial value of the timing error, c1 and c2 are the coefficients of the loop filter;

[0021] If the loop filter processing count is greater than 1, the calculation is:

[0022] w(m+1)=w(m)+c1×(time_error(m)-time_error(m-1))+c2×time_error(m-1);

[0023] Wherein, m is the execution count of the loop filter, w(m) is the output digital controlled oscillator control word when the loop filter processes for the mth time, time_error(m) is the timing error value when the loop filter processes for the mth time, time_error(m-1) is the timing error value when the loop filter processes for the m-1th time, and c1 and c2 are the coefficients of the loop filter.

[0024] The count value also includes a numerically controlled oscillation count; the numerically controlled oscillation count is used to control the execution upper limit of the numerically controlled oscillator updating the memory, and the execution upper limit is defined as the number of simulation points.

[0025] Further, the step of selecting the optimization parameter processing comprises:

[0026] Determine whether the numerically controlled oscillator control word has been generated, if the numerically controlled oscillator control word has been generated, determine whether the count value increment has been executed, if the count value increment has been executed, select the numerically controlled oscillator processing, and generate the optimized processing parameters.

[0027] The calculation method of the timing error value is determined according to the number of executions of the interpolation filter loop. When the number of executions of the interpolation filter loop is greater than 2, the calculation method of the timing error value is:

[0028] time_error(m)=(YI(k-1)-AI)×(YI(k)-YI(k-2))+(YQ(k-1)–AQ)×

[0029] (YQ(k)-YQ(k-2)),

[0030] Wherein, time_error(m) is the loop timing error value, k is the interpolation filter loop execution count, m is the loop filter processing count, AI and AQ are in-phase and quadrature correction variables, YI(k) is the in-phase sampling sequence, YQ(k) is the quadrature sampling sequence, and AI = (YI(k) + YI(k-2)) / 2, AQ = (YQ(k) + YQ(k-2)) / 2;

[0031] When the number of interpolation filter loop executions = 2, the timing error calculation method is:

[0032] time_error(m)=YI(k-1)×YI(k)+YQ(k-1)×YQ(k).

[0033] On the other hand, the present application provides a signal processing device compatible with multi-order modulation and demodulation, comprising:

[0034] A signal sampling sequence acquisition module is used to acquire signal sampling sequence information;

[0035] The loop sampling rate conversion module is used to loop-execute interpolation filter sampling rate conversion. The sampling rate conversion refers to obtaining interpolation filter input parameter information, calculating the optimal sampling time of the signal sampling sequence, and outputting the estimated optimal signal sampling sequence and the number of interpolation filter loop executions. The interpolation filter input parameter information includes the received signal sampling sequence and the optimized processing parameters.

[0036] The timing error detection module is used to perform timing error detection, calculate the timing error estimate of the estimated best signal sampling sequence, and determine whether the estimated best signal sampling sequence meets the best signal sampling sequence information rule; the rule refers to: determining the difference between the timing error estimate of the estimated best signal sampling sequence and 0, if the difference is less than a specified threshold, determining that the estimated best signal sampling sequence is the best signal sampling sequence.

[0037] The optimization parameter processing module is used to perform optimization parameter processing when the timing error estimation value does not meet the specified rules; performing optimization parameter processing means: inputting the timing error estimation value and the number of executions of the interpolation filter loop, outputting the optimization processing parameters, and calling the loop sampling rate conversion module to perform the interpolation filter loop sampling rate conversion;

[0038] The best signal sampling sequence output module is used to output the best signal sampling sequence information.

[0039] Further, the optimization parameter processing module includes a loop filter processing unit, a numerically controlled oscillator processing unit and an optimization verification unit;

[0040] The loop filter processing unit is used to calculate the control word of the digital controlled oscillator according to the timing error estimate;

[0041] The digital controlled oscillator processing unit is used to calculate the optimization processing parameters according to the digital controlled oscillator control word;

[0042] The optimization verification unit is used to control the loop filter processing count and select the optimization parameter processing step.

[0043] Furthermore, when the optimization verification unit selects the optimization parameter processing step, it determines whether to call the numerically controlled oscillator processing unit to generate a numerically controlled oscillator control word. If the numerically controlled oscillator control word has been generated, the optimization verification unit determines whether the count value increment has been executed. If the count value increment has been executed, the numerically controlled oscillator processing unit is called to generate the optimization processing parameters.

[0044] According to the present invention, sampling sequence optimization of signals such as 8PSK, 16QAM, and 64QAM can be supported. The present invention is suitable for common MPSK and MQAM signal processing, and is compatible with signal tuning of multi-order modulation and demodulation. Therefore, in various network environments, for modulation signals of different orders, the bit error rate of information transmission can be reduced, and the stability and reliability of the signal can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a step diagram of a signal processing method provided according to an embodiment of the present invention;

[0046] Figure 2 is a flowchart of a signal processing method according to an embodiment of the present invention;

[0047] Figure 3 is a logic flow chart of a signal processing method provided according to an embodiment of the present invention;

[0048] Figure 4 is a diagram of an interpolation filter operation structure in the steps of a signal processing method provided by an embodiment of the present invention;

[0049] Figure 5 is a comparison diagram of simulation calculation effects of a signal processing method provided by an embodiment of the present invention;

[0050] Figure 6 is a structural diagram of a signal processing device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The signal processing method compatible with multi-order modulation and demodulation disclosed in the present application is applied to the original received signal sampling sequence, and the signal sampling sequence is optimized before the modulation and demodulation processing to improve the reliability of information processing. The processing method provided in the present application improves the bit synchronization algorithm so that it can be applied to MPSK and MQAM signals, and obtains a good convergence effect when processing 8PSK, 16QAM, and 64QAM signals.

[0052] The specific implementation of the present invention is described in detail below with reference to the accompanying drawings.

[0053] like Figure 1 As shown, the signal processing method compatible with multi-order modulation and demodulation provided by the present application includes:

[0054] Step S100: Acquire signal sampling sequence information. The signal sampling sequence in this step is the original received signal sampling sequence;

[0055] The sampling time of the signal sampling sequence obtained in this step is affected by the network environment. When the network environment is not good, the sampling signal simulation is distorted. In this application, the signal sampling sequence is optimized and the sampling time is repeatedly adjusted to obtain the optimal sampling time, and finally generate the optimal sampling acquisition sequence.

[0056] The process of repeatedly adjusting the sampling time includes at least three types of counts, namely the interpolation filter loop execution count (represented by k), the loop filter processing count (represented by m), and the numerical control oscillation count (represented by i). i, m, and k are always positive integers. They need to be assigned values ​​in the initialization step. Then, the loop enters the calculation process. In the whole process, i, m, and k will increase under the corresponding conditions and are independent of each other (such as Figure 3 As shown), when i is greater than the number of simulation points, the program terminates. In the simulation of the present application, the number of simulation points supports 50,000, 70,000, etc., and the final values ​​of i, m and k will not exceed the size of the number of simulation points.

[0057] The parameters involved in the calculation in this method include the optimization processing parameter u(k-1), the output estimated best signal sampling sequence Y(k), the estimated value of the timing error time_error(m), the numerically controlled oscillator memory sequence l(i), and the numerically controlled oscillator control word w(m), which are continuously calculated in a loop. Before the loop calculation, initial assignments are performed.

[0058] Step S110: Execute interpolation filter loop sampling rate conversion:

[0059] The process of performing sampling rate conversion is: obtaining input parameter information, calculating the optimal sampling time of the signal sampling sequence, and outputting the estimated optimal signal sampling sequence and the number of loop executions. The input parameter information includes the original received signal sampling sequence obtained from step S110.

[0060] like Figure 3 As shown, in this step, the sampling rate conversion is performed as a loop execution. When the number of loop executions is an even number, after the sampling rate conversion is completed, the output estimated optimal signal sampling sequence is subjected to timing error detection and optimization processing, and the next sampling rate conversion is performed based on the optimization result. Therefore, the input for performing the sampling rate conversion also includes the optimization processing parameters, and the number of loop executions is counted.

[0061] like Figure 2 As can be seen from FIG. 1 , the input of the interpolation filter processing in step S210 includes the input sampling sequence in S201 and the optimized processing parameter u(k-1) in S202, and the output is the estimated optimal signal sampling sequence Y(k). The operation structure of the interpolation filter is as follows: Figure 4As shown, the common Farrow operation structure is adopted. The operation expressions of the three longitudinal branches f1, f2, f3 and the transverse combined road Y(k) in the figure are:

[0062] f1=gX(i)-gX(i-1)-gX(i-2)+gX(i-3),

[0063] f2=3gX(i-1)-gX(i)-gX(i-2)-gX(i-3),

[0064] f3=X(i-2),

[0065] Y(k)=(f1×u(k)+f2)×u(k)+f3;

[0066] The specific gravity parameter g is set to g=0.5 in this application.

[0067] Generally, MPSK and MQAM signals are divided into in-phase (I) and quadrature (Q) signals for modulation. In the calculation of this step, both I and Q signals are processed by bit synchronization algorithm and the estimated optimal signal sampling sequence is output. Therefore, Y(k) corresponding to I and Q signals can be expressed as YI(k) and YQ(k) respectively.

[0068] Step S120: performing timing error detection, calculating a timing error estimation value of the estimated best signal sampling sequence, and determining whether the estimated best signal sampling sequence meets the best signal sampling sequence information requirement;

[0069] In this step, the timing error estimation value time_error(m) is calculated for the estimated optimal signal sampling sequence Y(k) output in step S110, such as Figure 2 As shown in step S220.

[0070] In this step, the Gardner algorithm in the timing error detector samples each symbol twice, one sampling time is the estimated optimal sampling time, and the other is the middle time of the symbol jump. Then, the estimated value of the timing error time_error(m) is calculated based on the sampling sequence. The expression is as follows:

[0071] time_error(m)=YI(k-1 / 2)×

[0072] (YI(k)-YI(k-1))+YQ(k-1 / 2)×(YQ(k)-YQ(k-1));

[0073] For MQAM signals, since MQAM symbols have multiple level values, if the Gardner algorithm is used directly to process them, Y(k-1 / 2) will not be 0 or will not be close to 0 (taking 16QAM as an example, 16QAM symbols have four level values ​​of 1, 3, -1, and -3. When the symbol level changes from 3 to 1, the intermediate value of Y(k-1 / 2) is 2). This will introduce a large calculation deviation, and ultimately cause the bit synchronization algorithm loop to fail to converge. Therefore, in this application, two correction variables, AI and AQ, are introduced, which are obtained by adding and averaging YI(k) and YI(k-1), YQ(k) and YQ(k-1), and then YI(k-1 / 2) and YQ(k-1 / 2) are subtracted from the correction values ​​AI and AQ, so that YI(k-1 / 2) and YQ(k-1 / 2) are close to 0 again. Based on a small calculation deviation, an accurate timing error estimate can be obtained. At the same time, the improved algorithm is still applicable to the processing of MPSK signals.

[0074] After the algorithm is improved, the calculation expression of time_error(m) is as follows:

[0075] time_error(m)=(YI(k-1 / 2)-AI)*(YI(k)-YI(k-1))+(YQ(k-1 / 2)–AQ)

[0076] *(YQ(k)-YQ(k-1)),

[0077] AI=(YI(k)+YI(k-1)) / 2,

[0078] AQ=(YQ(k)+YQ(k-1)) / 2;

[0079] In the actual process of calculating time_error(m), the sequence number of Y(k) must be a positive integer, so the above formula needs to be adjusted. When k>2, it is adjusted to the timing error as follows:

[0080] time_error(m)=(YI(k-1)-AI)×(YI(k)-YI(k-2))+(YQ(k-1)–AQ)×

[0081] (YQ(k)-YQ(k-2)),

[0082] AI=(YI(k)+YI(k-2)) / 2,

[0083] AQ=(YQ(k)+YQ(k-2)) / 2;

[0084] When k=2, the timing error calculation method is as follows:

[0085] time_error(m)=YI(k-1)×YI(k)+YQ(k-1)×YQ(k).

[0086] In this step, judging whether the estimated best signal sampling sequence meets the best signal sampling sequence information requirements refers to: judging the difference between the timing error estimate of the estimated best signal sampling sequence and 0; if the difference is less than a specified threshold, determining that the estimated best signal sampling sequence is the best signal sampling sequence; the smaller the specified threshold, the closer it is to 0, that is, the smaller the error, the better the signal sampling sequence; the specific designation of the threshold can be adjusted according to actual conditions.

[0087] If the requirements are not met, step S130 is executed, i.e., parameter optimization processing;

[0088] Executing the optimization parameter processing means: inputting the timing error estimation value time_error(m) and the number of loop executions k, and outputting the optimization processing parameter u(k), wherein the above output result is used for performing the interpolation filter loop sampling rate conversion;

[0089] like Figure 2 As shown in step S230 in the above, the optimization parameter processing includes loop filter processing at S232, numerically controlled oscillator processing at S231, and optimization verification at S233;

[0090] S232 loop filter processing is an optimization parameter processing step for calculating a digital controlled oscillator control word according to the timing error estimate;

[0091] The calculations for loop filter processing include:

[0092] Determine whether the loop filter processing count is equal to 1. If it is equal to 1, the calculation method is:

[0093] w(2)=w(1)+c1×time_error(1)+c2×time_error(1),

[0094] Wherein, w(2) is the control word of the digital controlled oscillator output this time, w(1) is the initial value of the control word of the digital controlled oscillator, time_error(1) is the initial value of the timing error, c1 and c2 are the coefficients of the loop filter;

[0095] If the loop filter process count is greater than 1, the calculation is:

[0096] w(m+1)=w(m)+c1×(time_error(m)-time_error(m-1))+c2×time_error(m-1);

[0097] Wherein, m is the number of executions of the loop filter, w(m+1) is the output digital controlled oscillator control word when the loop filter is processed for the mth time, time_error(m) is the timing error value when the loop filter is processed for the mth time, time_error(m-1) is the timing error value when the loop filter is processed for the m-1th time, and c1 and c2 are the coefficients of the loop filter.

[0098] S231 numerically controlled oscillator processing is another optimization parameter processing step, which is used to calculate the optimization processing parameters according to the numerically controlled oscillator control word;

[0099] The input of the numerically controlled oscillator is the numerically controlled oscillator control word w(m), and the output is u(k). During the calculation process, l(i) is used to represent the internal storage sequence of the numerically controlled oscillator;

[0100] The calculation expression of the numerically controlled oscillator memory sequence l(i) is:

[0101] l(i+1)=(l(i)-w(m))mod(1).

[0102] The computational processing of the numerically controlled oscillator can be expressed as follows:

[0103] u(k)=l(i) / w(m).

[0104] In the optimization process of the numerically controlled oscillator processing and the loop filter processing, a sequence needs to be defined, so the processing conditions and sequence are controlled through the S233 optimization check.

[0105] S233 optimization check is used to control the loop filter processing count and select the optimization parameter processing step;

[0106] Select the optimization parameter processing step. The specific logic is as follows: Figure 3 As shown:

[0107] First, loop filter processing is performed. During the processing of the loop filter, a calculation method is selected according to the m value. After the loop filter processing is completed, the loop filter processing count is controlled, and then a numerically controlled oscillator processing is performed.

[0108] Optimization parameter processing includes:

[0109] Determine whether the numerically controlled oscillator control word has been generated. If the numerically controlled oscillator control word has been generated, determine whether the count value increment execution has been executed. If the count value increment execution has been executed, select the numerically controlled oscillator processing and generate optimized processing parameters.

[0110] The controlling the loop filter processing count refers to: obtaining an input loop execution count, obtaining a loop filter execution count under the loop execution count, and controlling a count value to increase, wherein the count value includes the loop filter execution count.

[0111] On the other hand, if the requirements are met, step S131 is executed: outputting the optimal signal sampling sequence information, and the output information can enter the next step of modulation and demodulation processing, such as Figure 2 As shown in step S221.

[0112] In this step, the optimal signal sampling sequence for the next step of modulation and demodulation processing can achieve convergence when processing 8PSK, 16QAM, and 64QAM signals. Figure 5 A comparison chart of the simulation calculation effects of the best signal sampling sequence after processing by the method of the present application and the signal sampling sequence not processed by the method when processing 16QAM signals is provided. By comparison, it can be clearly seen that the timing error of the processed signal sampling sequence stably approaches 0.

[0113] Figure 6 is a structural diagram of a signal processing device provided by the present application, such as Figure 5 As shown, including:

[0114] P610 signal sampling sequence acquisition module, used to obtain signal sampling sequence information;

[0115] The P620 loop sampling rate conversion module is used to perform interpolation filter sampling rate conversion in the loop. The sampling rate conversion refers to obtaining interpolation filter input parameter information, calculating the optimal sampling time of the signal sampling sequence, and outputting the estimated optimal signal sampling sequence and the number of interpolation filter loop executions. The interpolation filter input parameter information includes the received signal sampling sequence and optimized processing parameters.

[0116] The P630 timing error detection module is used to perform timing error detection, calculate the timing error estimate of the estimated optimal signal sampling sequence, and determine whether the estimated optimal signal sampling sequence meets the optimal signal sampling sequence information rule; the rule refers to: determining the difference between the timing error estimate of the estimated optimal signal sampling sequence and 0, if the difference is less than a specified threshold, determining that the estimated optimal signal sampling sequence is the optimal signal sampling sequence.

[0117] P640 optimization parameter processing module, used for performing optimization parameter processing when the timing error estimation value does not satisfy the rule; the performing optimization parameter processing means: inputting the timing error estimation value and the number of executions of the interpolation filter loop, outputting the optimization processing parameters, and calling the loop sampling rate conversion module to perform the interpolation filter loop sampling rate conversion;

[0118] The optimization parameter processing module includes a P641 loop filter processing unit, a P642 numerically controlled oscillator processing unit, and a P643 optimization verification unit;

[0119] The loop filter processing unit is used to calculate the control word of the digital controlled oscillator according to the timing error estimate;

[0120] The digital controlled oscillator processing unit is used to calculate the optimization processing parameters according to the digital controlled oscillator control word;

[0121] The optimization verification unit is used to control the loop filter processing count and select the optimization parameter processing step:

[0122] When the optimization verification unit selects the optimization parameter processing step, it determines whether the numerically controlled oscillator processing unit has been called to generate the numerically controlled oscillator control word. If the numerically controlled oscillator control word has been generated, the optimization verification unit determines whether the count value increment execution has been executed. If the count value increment execution has been executed, the numerically controlled oscillator processing unit is called to generate the optimization processing parameters.

[0123] P650 optimal signal sampling sequence output module, used to output the optimal signal sampling sequence information.

[0124] According to the above signal processing method, the optimal sampling signal sequence can be achieved when processing 8PSK, 16QAM, and 64QAM signals, that is, it is suitable for common MPSK and MQAM signal processing, and can be compatible with multi-order modulation and demodulation signals. Therefore, in various network environments, when the sampling signal is not stable enough, it can reduce the bit error rate of information transmission and improve the stability and reliability of the signal.

[0125] The above disclosures are only several specific embodiments of the present invention; however, the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A signal processing method compatible with multi-order modulation and demodulation, characterized in that: include: Acquire signal sampling sequence information, where the signal sampling sequence information is a received signal sampling sequence; Execute interpolation filter loop sampling rate conversion, the sampling rate conversion refers to obtaining interpolation filter input parameter information, calculating the optimal sampling time of the signal sampling sequence, outputting the estimated optimal signal sampling sequence and the number of interpolation filter loop executions, the interpolation filter input parameter information including the received signal sampling sequence; Performing timing error detection, calculating a timing error estimation value of the estimated best signal sampling sequence, and determining whether the estimated best signal sampling sequence satisfies the best signal sampling sequence information rule; If the timing error estimate does not satisfy the rule, perform optimization parameter processing; the execution of optimization parameter processing refers to: inputting the timing error estimate and the number of executions of the interpolation filter loop, outputting the optimization processing parameters, and then executing the interpolation filter loop sampling rate conversion; the optimization parameter processing includes loop filter processing, digital control oscillator processing and optimization verification; the loop filter processing is an optimization parameter processing step, which is used to calculate the digital control oscillator control word according to the timing error estimate; the digital control oscillator processing is another optimization parameter processing step, which is used to calculate the optimization processing parameters according to the digital control oscillator control word; the optimization verification is used to control the loop filter processing count and select the optimization parameter processing step; the control of the loop filter processing count refers to: obtaining the input interpolation filter loop execution count, obtaining the loop filter execution count under the interpolation filter loop execution count, and controlling the count value to increase, and the count value includes the loop filter execution count; If the rule is met, outputting the optimal signal sampling sequence information; Wherein, the interpolation filter input parameter information also includes optimization processing parameters.

2. The signal processing method according to claim 1, characterized in that: The determining whether the estimated best signal sampling sequence satisfies the best signal sampling sequence information rule refers to: determining the difference between the timing error estimate of the estimated best signal sampling sequence and 0; if the difference is less than a specified threshold, determining that the estimated best signal sampling sequence is the best signal sampling sequence.

3. The signal processing method according to claim 1, characterized in that: The calculation method of the loop filter processing includes: Determine whether the loop filter processing count is equal to 1. If it is equal to 1, the calculation method is: w(2)=w(1)+c1×time_error(1)+c2×time_error(1), Wherein, w(2) is the control word of the digital controlled oscillator output this time, w(1) is the initial value of the digital controlled oscillator control word, time_error(1) is the initial value of the timing error estimate, c1 and c2 are the coefficients of the loop filter; If the loop filter processing count is greater than 1, the calculation is: w(m+1)=w(m)+c1×(time_error(m)-time_error(m-1))+c2×time_error(m-1); Wherein, m is the execution count of the loop filter, w(m+1) is the output digital controlled oscillator control word during the m-th loop filter processing, time_error(m) is the timing error estimate during the m-th loop filter processing, time_error(m-1) is the timing error estimate during the m-1-th loop filter processing, and c1 and c2 are the coefficients of the loop filter.

4. The signal processing method according to claim 1, characterized in that: The count value also includes a numerically controlled oscillation count; The numerically controlled oscillation count is used to control the execution upper limit of the numerically controlled oscillator updating the memory, and the execution upper limit is defined as the number of simulation points.

5. The signal processing method according to claim 1, characterized in that: The step of selecting the optimization parameter processing comprises: Determine whether the numerically controlled oscillator control word has been generated. If the numerically controlled oscillator control word has been generated, determine whether the count value increment has been executed. If the count value increment has been executed, select the numerically controlled oscillator process and generate optimized process parameters.

6. The signal processing method according to claim 3, characterized in that: The calculation method of the timing error estimate value is determined according to the number of execution times of the interpolation filter loop. When the number of execution times of the interpolation filter loop is greater than 2, the calculation method of the timing error estimate value is: time_error(m)=(YI(k-1)-AI)×(YI(k)-YI(k-2))+(YQ(k-1)–AQ)× (YQ(k)-YQ(k-2)), Wherein, time_error(m) is the estimated value of the loop timing error, k is the interpolation filter loop execution count, m is the loop filter processing count, AI and AQ are in-phase and quadrature correction variables, YI(k) is the in-phase sampling sequence, YQ(k) is the quadrature sampling sequence, and AI = (YI(k) + YI(k-2)) / 2, AQ = (YQ(k) + YQ(k-2)) / 2; When the number of interpolation filter loop executions = 2, the timing error calculation method is: time_error(m)=YI(k-1)×YI(k)+YQ(k-1)×YQ(k).

7. A signal processing device compatible with multi-order modulation and demodulation, characterized in that: include: A signal sampling sequence acquisition module is used to acquire signal sampling sequence information; A loop sampling rate conversion module, used for loop execution of interpolation filter sampling rate conversion, wherein the sampling rate conversion refers to obtaining interpolation filter input parameter information, calculating the optimal sampling time of the signal sampling sequence, and outputting an estimated optimal signal sampling sequence and the number of interpolation filter loop executions, wherein the interpolation filter input parameter information includes a received signal sampling sequence and optimized processing parameters; A timing error detection module is used to perform timing error detection, calculate the timing error estimation value of the estimated best signal sampling sequence, and determine whether the estimated best signal sampling sequence meets the best signal sampling sequence information rule; the rule refers to: determining the difference between the timing error estimation value of the estimated best signal sampling sequence and 0, and if the difference is less than a specified threshold, determining that the estimated best signal sampling sequence is the best signal sampling sequence; An optimization parameter processing module, used for performing optimization parameter processing when the timing error estimation value does not satisfy the rule; the performing optimization parameter processing means: inputting the timing error estimation value and the number of executions of the interpolation filter loop, outputting the optimization processing parameters, and then calling the loop sampling rate conversion module to perform the interpolation filter loop sampling rate conversion; An optimal signal sampling sequence output module, used to output the optimal signal sampling sequence information; Wherein, the optimization parameter processing module includes a loop filter processing unit, a numerically controlled oscillator processing unit and an optimization verification unit; The loop filter processing unit is used to calculate a digital controlled oscillator control word based on the timing error estimate; The digital controlled oscillator processing unit is used to calculate the optimization processing parameters according to the digital controlled oscillator control word; The optimization verification unit is used to control the loop filter processing count and select the optimization parameter processing step.

8. The signal processing device according to claim 7, characterized in that: When the optimization verification unit selects the optimization parameter processing step, it determines whether the numerically controlled oscillator processing unit has been called to generate the numerically controlled oscillator control word. If the numerically controlled oscillator control word has been generated, the optimization verification unit determines whether the count value increment has been executed. If the count value increment has been executed, the numerically controlled oscillator processing unit is called to generate the optimization processing parameters.

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