Semiconductor memory device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor storage device and a manufacturing method thereof, and relates to the technical field of semiconductor technology. The semiconductor storage device comprises: a nitrogen layer and a storage combination unit which are alternately stacked; wherein the outer layer of the storage combination unit is a first insulator, the inner side of the first insulator is a ring-shaped floating body, the inner side of the floating body is a ring-shaped channel region, and the inner side of the channel region is provided with a gate; at least one pair of through holes respectively penetrating the storage combination unit to break the ring-shaped floating body, channel region and gate; in at least one pair of through holes, one through hole is filled with a source electrode, and the source electrode only contacts the channel regions on both sides; and the other through hole is filled with a drain electrode, and the drain electrode only contacts the channel regions on both sides. The present disclosure can improve the integration of the semiconductor storage device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor memory device and a manufacturing method thereof. BACKGROUND

[0002] To meet the needs of consumers for excellent performance and low price, high integration is the development direction of semiconductor memory devices. Generally, integration is determined by the area occupied by a unit memory cell.

[0003] To improve integration, on the basis of the conventional memory cell with one transistor and one capacitor, a capacitorless memory cell is proposed, which can greatly reduce the area occupied by the memory cell.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a semiconductor memory device and a manufacturing method thereof, which can improve the integration of the semiconductor memory device.

[0006] According to one aspect of the present disclosure, a semiconductor memory device is provided, comprising:

[0007] nitride layers and memory combination units are alternately stacked; wherein the outer layer of the memory combination unit is a first insulator, the inner side of the first insulator is a ring-shaped floating body, the inner side of the floating body is a ring-shaped channel region, and the inner side of the channel region is formed with a gate;

[0008] at least one pair of through holes, respectively penetrating the memory combination unit, to break the ring-shaped floating body, channel region and gate;

[0009] In the at least one pair of through holes, one of the through holes is filled with a source electrode, and the source electrode only contacts the channel regions on both sides; and the other through hole is filled with a drain electrode, and the drain electrode only contacts the channel regions on both sides.

[0010] Optionally, the gate includes:

[0011] a gate oxide layer formed on the inner side of the channel region, the gate oxide layer being ring-shaped;

[0012] a gate conductive layer formed on the inner side of the ring-shaped gate oxide layer.

[0013] Optionally, the gate conductive layer is filled with a second insulator inside.

[0014] Optionally, the doping concentration of the channel region is lower than the doping concentration of the floating body.

[0015] Optionally, quantum dots are doped in the floating body.

[0016] Optionally, in a direction perpendicular to the stacking direction, the storage combination unit has multiple units, and the multiple storage combination units are arranged at intervals.

[0017] Optionally, in the stacking direction, the storage combination unit has multiple layers.

[0018] Optionally, in the case where there are multiple pairs of through holes, in adjacent through holes, one through hole is used to fill the source, and the other through hole is used to fill the drain.

[0019] Optionally, in the stacking direction, the thicknesses of the floating body, the channel region, and the gate are the same.

[0020] According to one aspect of the present disclosure, a method for manufacturing a semiconductor storage device is provided, comprising:

[0021] A substrate is provided.

[0022] Nitride layers and oxide layers are deposited on the substrate in turn and alternately, forming a stack structure.

[0023] A first through hole is etched through the stack structure.

[0024] Through the first through hole, part of the oxide layer is etched to form an oxide layer groove.

[0025] A floating body, a channel region, and a gate are deposited in the oxide layer groove in turn and annularly.

[0026] At different positions, at least one pair of second through holes is etched through the stack structure, and the second through holes break the annular floating body, the channel region, and the gate.

[0027] Different materials are filled in at least one pair of the second through holes to form a source and a drain connected to the channel region.

[0028] Optionally, depositing a floating body, a channel region, and a gate in the oxide layer groove in turn and annularly comprises:

[0029] A floating body material layer is deposited in the first through hole, and the floating body material layer fills the oxide layer groove.

[0030] Part of the floating body material layer is etched to form the annular floating body in the oxide layer groove.

[0031] depositing a channel region material layer in the first via, the channel region material layer filling the remaining oxide layer recess;

[0032] etching part of the channel region material layer to form an annular channel region in the remaining oxide layer recess in contact with the floating body;

[0033] depositing a gate oxide layer and a gate conductive layer in the remaining oxide layer recess through the first via to form an annular gate in contact with the channel region.

[0034] Optionally, further comprising:

[0035] filling the first via with an insulating material layer to fill the first via and the remaining oxide layer recess.

[0036] Optionally, filling different materials in at least one pair of the second vias to form a source and a drain connected to the channel region comprises:

[0037] depositing an insulating material in the second via;

[0038] etching the insulating material in the second via to form a third via exposing the channel region;

[0039] depositing a source material in the third via to form the source, or depositing a drain material in the third via to form the drain.

[0040] Optionally, filling different materials in at least one pair of the second vias to form a source and a drain connected to the channel region comprises:

[0041] etching part of the floating body through the second via to form a floating body recess;

[0042] depositing an insulating material in the second via and filling the floating body recess;

[0043] etching the insulating material in the second via to leave insulating material in the floating body recess;

[0044] depositing a source material in the second via to form the source, or depositing a drain material in the second via to form the drain.

[0045] Optionally, in the case of multiple pairs of the second vias, depositing different materials in adjacent second vias.

[0046] Optionally, the first via etched through the stack structure comprises:

[0047] A plurality of first through holes are etched through the stack structure, and the plurality of first through holes are arranged at intervals.

[0048] The semiconductor memory device provided by the exemplary embodiment of the present disclosure includes a plurality of storage combination units arranged in a stack direction, and each of the storage combination units includes a floating body, a channel region, and a gate arranged in a ring shape, and a pair of a source and a drain filled in a pair of through holes which break the ring shape of the floating body, the channel region, and the gate. In one aspect, the storage combination unit after being broken can form at least two storage units, and the two storage units can share the pair of the source and the drain, so that the area occupied by the storage unit can be reduced. In another aspect, a plurality of storage combination units can be stacked in the stack direction, and the two storage units formed by the plurality of storage combination units can share the same pair of the source and the drain, so that the area occupied by the storage unit can be further reduced. In still another aspect, a plurality of pairs of through holes can be arranged in the same storage combination unit, so that the ring-shaped floating body, channel region, and gate can be broken into a plurality of segments, so that more storage units can be formed, and the integration of the storage units in the semiconductor memory device can be improved. In still another aspect, since the floating body is arranged outside the channel region and does not directly contact the source and the drain, there is no charge leakage, so that the data retention time of the floating body can be enhanced.

[0049] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0050] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0051] Figure 1 A cross-sectional view of a capacitorless dynamic random access memory is shown.

[0052] Figure 2a A structure schematic diagram of a semiconductor memory device provided by the exemplary embodiment of the present disclosure is shown.

[0053] Figure 2b A cross-sectional view of a capacitorless dynamic random access memory is shown. Figure 2a A cross-sectional view of a capacitorless dynamic random access memory is shown.

[0054] Figure 3 A cross-sectional view of a capacitorless dynamic random access memory is shown.

[0055] FIGS. 4(a)-4(k) are explanatory diagrams for manufacturing a semiconductor memory device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments should not be construed as limiting all example embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification.

[0057] The above described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, and the foregoing discussion with respect to one embodiment applies to all embodiments. In the above description, numerous specific details are recited to provide a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the application.

[0058] Although relative terms are used herein, such as "upper", "lower", to describe one component's relationship to another component of the icon, such terminology is used herein for convenience only and is not intended to limit the scope of the application, e.g., according to the orientation of the examples shown in the figures. It is to be understood that if the icon's device were turned over, such that the "upper" component would become the "lower" component, the application would function in the same way. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0059] The use of the terms "a" and "an" and "the" and "at least one" are intended to include both singular and plural referents unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", "including", "has", "having" and the like are inclusive and are intended to be equivalent to the term "consisting of". The terms "first" and "second" are used to label similar elements, and are not meant to be limiting.

[0060] Reference Figure 1 FIG. 1 shows a cross-sectional view of a capacitorless dynamic random access memory (DRAM) according to an embodiment of the present disclosure.

[0061] As Figure 1As shown, the gate 110 can be formed on a silicon substrate 120. The silicon substrate 120 is sequentially stacked by a first silicon layer 121, an oxide layer 123 and a second silicon layer 125. The gate 110 is sequentially stacked by a gate insulating layer 111 and a gate conductive layer 113. The source 130 and the drain 140 are formed in the second silicon layer 125 on both sides of the gate 110. The floating channel body 150, which is electrically isolated from the first silicon layer 121, is formed in the second silicon layer 125 between the source 130 and the drain 140. The capacitorless dynamic random access memory stores data values "1" or "0" by accumulating holes or electrons in the floating channel body 150.

[0062] The applicant has found in further research that the footprint of the memory cell in the capacitorless dynamic random access memory described above still has room for reduction.

[0063] Based on this, the example embodiment of the disclosure provides a semiconductor storage device to further reduce the footprint of the memory cell in the capacitorless dynamic random access memory, thereby improving the integration of the semiconductor storage device. Referring to FIGS. 2(a) and 2(b), the semiconductor storage device can include a nitride layer 210 and a memory combination unit 230 alternately stacked, and at least one pair of vias 250, wherein:

[0064] In actual operation, the bottommost nitride layer 210 can be deposited on a substrate 200, and then the nitride layer 210 and the memory combination unit 230 are alternately deposited on the substrate 200 in sequence. The nitride layer 210 can be deposited by a silicon nitride material, and the substrate 200 can be a silicon substrate, a germanium-silicon substrate, etc.

[0065] In actual application, the number of the nitride layer 210 and the memory combination unit 230 can be determined according to actual needs. When the memory combination unit 230 has only one layer, the nitride layer 210 can have two layers; when the memory combination unit 230 has multiple layers, the nitride layer 210 can be provided with one more layer than the memory combination unit 230. The example embodiment of the disclosure does not specially limit the number of the memory combination unit 230.

[0066] In the example embodiment of the disclosure, the memory combination unit 230 includes a first insulator 231, a floating body 232, a channel region 233 and a gate 234, wherein, along the direction perpendicular to the stacking direction, the first insulator 231 is located at the outermost layer of the memory combination unit 230, the floating body 232 is annular on the inner side of the first insulator 231, the channel region 233 is annular on the inner side of the annular floating body 232, and the gate 234 is formed on the inner side of the annular channel region 233.

[0067] From the perspective of storing data, the floating body 232 is equivalent to a hole storage unit. The floating body 232 is a heavily doped semiconductor structure, for example, a semiconductor silicon doped with a large amount of chromium, antimony, aluminum, gallium or the like to increase the conductivity of the floating body 232. The doping concentration of the floating body 232 is higher than that of the channel region 233, so that the valence band of the floating body 232 is higher than that of the channel region 233, that is, there are more electrons in the floating body 232.

[0068] In the exemplary embodiment of the present disclosure, in order to further increase the number of electrons stored in the floating body 232, quantum dots can also be doped in the floating body 232. Quantum dots are semiconductor nanostructures that confine excitons in three spatial directions. A quantum dot has a small number (1-100) of electrons, holes or electron-hole pairs, that is, the electric charge it carries is an integer multiple of the elementary charge. Therefore, by doping quantum dots in the floating body 232, the number of electrons in the floating body 232 can be increased.

[0069] In the exemplary embodiment of the present disclosure, the channel region 233 is obtained by simultaneously doping n-type or p-type ions when depositing the semiconductor material. The doping concentration of the channel region 233 is lower than that of the floating body 232, so that the valence band of the floating body 232 is higher than that of the channel region 233.

[0070] In the exemplary embodiment of the present disclosure, the gate 234 can include a gate oxide layer 2341 and a gate conductive layer 2342, wherein the gate oxide layer 2341 is an annular structure formed inside the channel region 233, and the gate conductive layer 2342 is formed inside the annular gate oxide layer 2341.

[0071] The semiconductor storage device provided by the exemplary embodiment of the present disclosure further includes at least one pair of through holes 250, which respectively pass through the storage combination unit 230 from different positions, as shown in FIG. 2(b). The purpose is to break the annular floating body 232, channel region 233 and gate 234 in the storage combination unit 230, so that one storage combination unit 230 is divided into two storage units.

[0072] In addition, a source 260 and a drain 270 need to be formed in the pair of through holes 250. The source 260 is filled in one of the through holes 250, and only contacts the channel regions 233 on both sides, and is spaced from the floating body 232 by an insulator. The drain 270 is filled in the other through hole 250, and also only contacts the channel regions 233 on both sides, and is spaced from the floating body 232 by an insulator. In this way, since the floating body does not directly contact the source and the drain, there is no charge leakage, and therefore the data retention time of the floating body is enhanced.

[0073] In order to separate two memory cells formed by one memory combination unit 230, a ring-shaped gate 234 can be formed inside the ring-shaped channel region 233, and a second insulator 235 can be filled inside the ring-shaped gate 234 to avoid the conductive connection between the gates 234 of the two memory cells.

[0074] As can be seen from the above structure, the semiconductor memory device provided by the exemplary embodiment of the present disclosure can share one pair of source 260 and drain 270 for two memory cells formed by one memory combination unit 230, thereby reducing the area occupied by the memory cells.

[0075] In addition, a plurality of memory combination units 230 can be stacked in the stacking direction, and the two memory cells formed by the plurality of memory combination units 230 can share the same pair of source 260 and drain 270, thereby further reducing the area occupied by the memory cells.

[0076] Further, a plurality of pairs of vias 250 can be provided in the same memory combination unit 230, so that the ring-shaped floating body 232, the channel region 233 and the gate 234 can be broken into multiple segments, thereby forming more memory cells and improving the integration of the memory cells in the semiconductor memory device.

[0077] It should be noted that in the case of multiple pairs of vias 250, in adjacent vias 250, one via 250 is used to fill the source 260, and the other via 250 needs to fill the drain 270.

[0078] Referring to Figure 3 In practical applications, a plurality of memory combination units 230 can be provided in a direction perpendicular to the stacking direction to increase the integration of the memory cells in the semiconductor memory device. Among them, the plurality of memory combination units 230 need to be spaced apart.

[0079] In practical applications, in order to facilitate processing, the thicknesses of the floating body 232, the channel region 233 and the gate 234 are the same in the stacking direction, and the floating body 232 and the gate 234 are located on both sides of the channel region 233 and are separated by the channel region 233. The exemplary embodiment of the present disclosure does not make special limitations on the specific thicknesses of the floating body 232, the channel region 233 and the gate 234.

[0080] The semiconductor memory device provided by the exemplary embodiment of the present disclosure is formed by alternately stacking a nitride layer and a memory combination unit, and the memory combination unit includes a ring-shaped floating body, a channel region and a gate, and a source and a drain are filled in a pair of through holes which break the ring-shaped floating body, the channel region and the gate. In one aspect, the memory combination unit after being broken can form at least two memory cells, and the two memory cells can share a pair of source and drain, so that the area occupied by the memory cells can be reduced. In another aspect, a plurality of memory combination units can be stacked in the stacking direction, and the two memory cells formed by the plurality of memory combination units can share the same pair of source and drain, so that the area occupied by the memory cells can be further reduced. In still another aspect, a plurality of pairs of through holes can be provided in the same memory combination unit, so that the ring-shaped floating body, the channel region and the gate can be broken into multiple segments, so that more memory cells can be formed, and the integration of the memory cells in the semiconductor memory device can be improved. In still another aspect, since the floating body is provided outside the channel region and does not directly contact the source and the drain, there is no charge leakage, and thus the data retention time of the floating body can be enhanced.

[0081] The manufacturing method of the semiconductor memory device in the exemplary embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0082] It should be understood that the drawings are not drawn according to the actual device structure proportion for the purpose of illustrating the process effect.

[0083] In the exemplary embodiment of the present disclosure, the main manufacturing process steps of the semiconductor memory device are as follows:

[0084] Step 10, providing a substrate;

[0085] Step 20, sequentially depositing a nitride layer and an oxide layer on the substrate alternately to form a laminated structure;

[0086] Step 30, etching a first through hole through the laminated structure;

[0087] Step 40, etching part of the oxide layer through the first through hole to form an oxide layer groove;

[0088] Step 50, sequentially depositing a ring-shaped floating body, a channel region and a gate in the oxide layer groove;

[0089] Step 60, etching at least one pair of second through holes through the laminated structure at different positions, and the second through holes break the ring-shaped floating body, the channel region and the gate. (In addition, the plurality of through holes 250 can be arranged on a circle with the first through hole as the center)

[0090] Step 70, filling different materials in the at least one pair of second through holes to form a source and a drain connected to the channel region.

[0091] The following will illustrate the manufacturing process of the semiconductor storage device through a specific implementation method.

[0092] Specifically, the manufacturing process steps of the semiconductor storage device are as follows:

[0093] As shown in FIG. 4(a), a substrate 200 is provided, and a nitride layer 210 and an oxide layer 410 are deposited on the surface of the substrate 200 in turn and alternately, forming a kind of laminated structure. The substrate 200 can be a silicon substrate, a germanium-silicon and a doped silicon substrate, etc. The nitride layer 210 can be deposited by silicon nitride, and the oxide layer 410 can be deposited by silicon oxide.

[0094] In actual application, the cross-sectional shape of the substrate 200 can be circular, rectangular or square, etc., which is not specially limited in the exemplary embodiments of the present disclosure.

[0095] As shown in FIG. 4(b), a first through hole 420 is etched through the laminated structure, for example, the laminated structure is etched by a patterned etching method. The first through hole 420 needs to at least pass through all the oxide layers 410, and can also pass through the entire laminated structure to leak out the substrate 200. In addition, in order to protect the laminated structure during etching, a polishing layer 430 can also be provided on the top of the laminated structure. The shape of the first through hole 420 is determined by the shape of the patterned mask layer, and the specific shape of the patterned mask layer can be determined according to actual conditions, which will not be described here.

[0096] In addition, it also needs to be explained that the bottom layer and the top layer of the deposited laminated structure need to be the nitride layer 210 to achieve the purpose of protecting the oxide layer 410.

[0097] As shown in FIG. 4(c), according to the etching selectivity of the nitride layer 210 and the oxide layer 410, an etching material is determined, and the etching material is introduced into the first through hole 420 to etch part of the oxide layer 410 through the first through hole 420 to form an oxide layer groove 440. The remaining oxide layer 410 forms a first insulator 231.

[0098] As shown in FIG. 4(d), a floating body material layer is deposited in the oxide layer groove 440 through the first through hole 420, which fills the oxide layer groove 440. The material of the deposited floating body material layer can be a semiconductor material, a metal material, etc. In addition, quantum dots can also be added to the material of the floating body material layer to store more electrons.

[0099] Then, part of the floating body material layer is etched through the first through hole 420 to form a ring-shaped floating body 232 in the oxide layer groove 440. In the process of etching part of the floating body material layer, dry etching process, self-aligned etching process, etc. can be used.

[0100] As shown in Fig. 4(e), through the first via hole 420, a channel region material layer is deposited in the remaining oxide layer recess 440, which fills up the remaining oxide layer recess 440. The material of the channel region material layer can be a semiconductor material, and n-type or p-type ions can be added in situ at the same time when the semiconductor material is deposited, to form a semiconductor conductive channel.

[0101] Next, through the first via hole 420, part of the channel region material layer is etched to form an annular channel region 233 in contact with the floating body 232, which is located inside the floating body 232. In the process of etching part of the channel region material layer, dry etching process, self-aligned etching process, etc. can be used.

[0102] As shown in Fig. 4(f), referring to the process of forming the floating body 232 and the channel region 233, through the first via hole 420, a gate oxide layer 2341 and a gate conductive layer 2342 are deposited in the remaining oxide layer recess 440 to form an annular gate 234 in contact with the channel region 233. The gate conductive layer 2342 can be metal, polysilicon, etc. Fig. 4(g) shows a sectional view of the semiconductor storage device shown in Fig. 4(f) in the direction of B-B. As can be seen from Fig. 4(g), the formed floating body 232, channel region 233 and gate 234 are all annular.

[0103] In addition, it is also necessary to fill an insulating material layer in the first via hole 420 shown in Fig. 4(g) to fill up the first via hole 420 and the remaining oxide layer recess 440.

[0104] As shown in Fig. 4(h), at least one pair of second via holes 450 are etched through the above-mentioned stack structure at different positions, which break the annular floating body 232, channel region 233 and gate 234.

[0105] The process of filling different materials in the at least one pair of second via holes 450 to form the source 260 and drain 270 connected to the channel region 233 will be described in two different ways as follows:

[0106] The first way: as shown in Fig. 4(i), an insulating material is deposited in the second via hole 450, and the insulating material in the second via hole 450 is patterned and etched to form a third via hole 460 exposing the channel region 233. A source material is deposited in the third via hole 460 to form the source 260, and a drain material is deposited in another third via hole 460 to form the drain 270.

[0107] Another way: as shown in Fig. 4(j), based on the etching ratio, the floating body 232 is etched partially through the second via 450 to form a floating body recess 470; insulating material is deposited in the second via 450 and fills the floating body recess 470. The insulating material in the second via 450 is etched, leaving the insulating material in the floating body recess 470; source material is deposited in the second via 450 to form the source 260, and drain material is deposited in another second via 450 to form the drain 270.

[0108] In actual application, as shown in Fig. 4(k), the second via 450 can have multiple pairs, and multiple second vias 450 can be arranged at intervals on a circumference with the first via 420 as the center. Different materials are deposited in adjacent two second vias 450 to form the source 260 and the drain 270.

[0109] For a semiconductor memory device, multiple first vias 420 can be etched through the stack structure to form a structure containing multiple memory cells as shown in Fig. 4(l). Figure 3

[0110] It should be noted that the method for manufacturing the semiconductor memory device provided by the exemplary embodiments of the present disclosure is only illustrative, and the present disclosure does not limit the manufacturing process of each component.

[0111] It should be understood that the sequence of the above processes in various embodiments of the present disclosure does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the exemplary embodiments of the present disclosure.

[0112] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within knownThe specification and examples are to be construed as illustrative only and not as limiting the scope of the present disclosure, which is defined by the claims.

Claims

1. A semiconductor memory device, characterized by comprising: Comprise: nitride layers and storage combination units arranged alternately; wherein the outer layer of the storage combination unit is a first insulator, the inner side of the first insulator is a ring-shaped floating body, the inner side of the floating body is a ring-shaped channel region, and the inner side of the channel region is formed with a gate; at least one pair of through holes, respectively penetrating the storage combination unit, to break the ring-shaped floating body, channel region and gate; in the at least one pair of through holes, one of the through holes is filled with a source electrode, and the source electrode only contacts the channel region on both sides; the other through hole is filled with a drain electrode, and the drain electrode only contacts the channel region on both sides.

2. The semiconductor storage device according to claim 1, wherein The gate comprises: a gate oxide layer formed on the inner side of the channel region, the gate oxide layer is ring-shaped; a gate conductive layer formed on the inner side of the ring-shaped gate oxide layer.

3. The semiconductor storage device according to claim 2, wherein The inner part of the gate conductive layer is filled with a second insulator.

4. The semiconductor storage device according to claim 1, characterized by The doping concentration of the channel region is lower than the doping concentration of the floating body.

5. The semiconductor storage device according to claim 4, wherein The floating body is doped with quantum dots.

6. The semiconductor storage device according to claim 1, wherein In the direction perpendicular to the stacking direction, the storage combination unit has a plurality of storage combination units arranged at intervals.

7. The semiconductor memory device according to claim 1, wherein In the stacking direction, the storage combination unit has a plurality of layers.

8. The semiconductor memory device according to claim 6, wherein In the case of multiple pairs of through holes, in adjacent through holes, one of the through holes is used to fill the source electrode, and the other through hole is used to fill the drain electrode.

9. The semiconductor storage device according to any one of claims 1 to 8, wherein In the stacking direction, the thickness of the floating body, the channel region and the gate is the same.

10. A method of manufacturing a semiconductor memory device, characterized by comprising: Comprise: provide a substrate; depositing a nitride layer and an oxide layer alternately on the substrate to form a stack structure; etching a first through hole through the stack structure; etching part of the oxide layer through the first through hole to form an oxide layer groove; depositing a ring-shaped floating body, a channel region and a gate in the oxide layer groove in sequence; etching at least one pair of second through holes through the stack structure at different positions, the second through holes break the ring-shaped floating body, channel region and gate; filling different materials in at least one pair of second through holes to form a source electrode and a drain electrode connected to the channel region.

11. The method of manufacturing a semiconductor memory device according to claim 10, wherein depositing a ring-shaped floating body, a channel region and a gate in the oxide layer groove in sequence comprises: depositing a floating body material layer in the first through hole, the floating body material layer fills the oxide layer groove; etching part of the floating body material layer to form a ring-shaped floating body in the oxide layer groove; depositing a channel region material layer in the first through hole, the channel region material layer fills the remaining oxide layer groove; etching part of the channel region material layer to form a ring-shaped channel region in contact with the floating body in the remaining oxide layer groove; depositing a gate oxide layer and a gate conductive layer in the remaining oxide layer groove through the first through hole to form a ring-shaped gate in contact with the channel region.

12. The method of manufacturing a semiconductor memory device according to claim 11, wherein Further comprise: filling an insulating material layer in the first through hole to fill the first through hole and the remaining oxide layer groove.

13. The method according to claim 10, wherein filling different materials in at least one pair of second through holes to form a source electrode and a drain electrode connected to the channel region comprises: depositing an insulating material in the second through hole; etching the insulating material within the second via to form a third via exposing the channel region; depositing a source material within the third via to form the source, or depositing a drain material within the third via to form the drain.

14. The method according to claim 10, wherein filling different materials in at least one pair of the second vias to form a source and a drain connected to the channel region includes: etching a portion of the floating body through the second via to form a floating body recess; depositing an insulating material within the second via and filling the floating body recess; etching the insulating material within the second via to leave insulating material within the floating body recess; depositing a source material within the second via to form the source, or depositing a drain material within the second via to form the drain.

15. The method according to claim 10, wherein where there are multiple pairs of the second vias, depositing different materials within adjacent ones of the second vias.

16. The method according to any one of claims 10 to 15, wherein etching a first via through the stack structure includes: etching a plurality of first vias through the stack structure, the plurality of first vias being spaced apart.

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