Semiconductor storage device

Abstract

This semiconductor storage device comprises: a plurality of memory blocks each including a memory cell and a word line; a voltage supply line commonly electrically connected to the plurality of word lines corresponding to the plurality of memory blocks; a plurality of transistors electrically connecting the plurality of word lines and a voltage supply line; a plurality of signal supply lines connected to gate electrodes of the plurality of transistors; a plurality of block decoder units capable of outputting a signal to any one from among the plurality of signal supply lines in accordance with the input of a signal corresponding to a block address; and a control circuit. Each among the plurality of block decoder units comprises a latch circuit. The control circuit rewrites data of the plurality of latch circuits corresponding to plurality of selected memory blocks in a multiple memory block erasure operation.

Description

Semiconductor memory

[0001] This embodiment relates to a semiconductor memory device.

[0002] A semiconductor memory device is known that comprises a plurality of memory blocks, each having a memory cell and a word line connected to the memory cell, and bit lines and source lines electrically connected in common to the plurality of memory cells corresponding to the plurality of memory blocks.

[0003] U.S. Patent Application Publication No. 2021 / 0096762, U.S. Patent Application Publication No. 2023 / 0223087, U.S. Patent Application Publication No. 2018 / 0102172

[0004] The present invention provides a semiconductor memory device capable of performing erase operations on multiple memory blocks in parallel.

[0005] A semiconductor memory device according to one embodiment includes: a plurality of memory blocks each having memory cells and word lines connected to the memory cells; bit lines and source lines electrically connected in common to the plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line electrically connected in common to the plurality of word lines corresponding to the plurality of memory blocks; a plurality of first transistors provided corresponding to the plurality of memory blocks and electrically connected between the word lines and the first voltage supply line; a plurality of first signal supply lines provided corresponding to the plurality of memory blocks and connected to the gate electrodes of the plurality of first transistors; a plurality of block decoder units provided corresponding to the plurality of memory blocks and capable of outputting a signal to any one of the plurality of first signal supply lines in response to the input of a signal corresponding to a block address; and a control circuit for controlling the plurality of block decoder units.

[0006] Each of the multiple block decoder units comprises multiple second transistors electrically connected in series between a second voltage supply line and a third voltage supply line, each having a signal corresponding to a block address input to its gate electrode; a third transistor electrically connected between the multiple second transistors and the second voltage supply line; a fourth transistor electrically connected between the multiple second transistors and the third voltage supply line; and a latch circuit connected to the gate electrode of the fourth transistor.

[0007] The control circuit is configured to perform a multiple memory block erase operation, which involves selecting two or more memory blocks from a plurality of memory blocks as multiple selected memory blocks and performing erase operations on these multiple selected memory blocks in parallel. In the multiple memory block erase operation, the data of multiple latch circuits corresponding to the multiple selected memory blocks is rewritten before the erase operation is performed.

[0008] This is a schematic block diagram showing the configuration of the memory system 10. This is a schematic side view showing an example of the configuration of the memory system 10. This is a schematic top view showing the same example. This is a schematic circuit diagram showing a part of the configuration of the memory die MD. This is a schematic perspective view showing a part of the configuration of the memory cell array MCA. This is a schematic cross-sectional view for explaining the read operation. This is a schematic cross-sectional view for explaining the write operation. This is a schematic cross-sectional view for explaining the erase operation. This is a schematic cross-sectional view for explaining the erase verify operation. This is a schematic block diagram showing the configuration of the peripheral circuit PC. This is a schematic circuit diagram showing the configuration of the voltage transfer circuit XFER as part of the raw decoder RD. This is a schematic circuit diagram showing the configuration of the block decoder BLKD as part of the raw decoder RD. This is a schematic circuit diagram showing the configuration of the block decoder unit blkd. This is a schematic circuit diagram showing the configuration of the latch circuit CBL. This is a schematic waveform diagram for explaining the memory block selection operation. This is a schematic waveform diagram for explaining the all memory block selection operation. This is a schematic waveform diagram for explaining the set operation of the latch circuit CBL. This is a schematic waveform diagram illustrating the reset operation of the latch circuit CBL. This is a schematic waveform diagram illustrating the full set operation of the latch circuit CBL. This is a schematic waveform diagram illustrating the full reset operation of the latch circuit CBL. This is a flowchart illustrating the multiple memory block erase operation. This is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erase operation. This is a schematic circuit diagram showing the configuration of the raw decoder RD2 according to the second embodiment. This is a schematic circuit diagram showing the configuration of the raw decoder RD2 according to the second embodiment. This is a schematic waveform diagram illustrating the multiple memory block selection operation. This is a flowchart illustrating the multiple memory block erase operation according to the second embodiment. This is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erase operation. This is a schematic circuit diagram showing the configuration of the raw decoder according to the third embodiment. This is a schematic block diagram showing the configuration of the peripheral circuit PC4 according to the fourth embodiment.This is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erasure operation according to the fourth embodiment.

[0009] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. It should be noted that the following embodiments are merely examples and are not intended to limit the scope of the present invention.

[0010] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die (memory chip), or to a memory system including a controller die, such as a memory card or SSD. It may also refer to a configuration including a host computer, such as a smartphone, tablet, or personal computer. In this specification, NAND flash memory is used as an example of a semiconductor memory device. However, the semiconductor memory device may be a memory other than NAND flash memory.

[0011] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0012] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0013] Furthermore, in this specification, when it is said that a circuit "makes two wires conductive," it may mean, for example, that the circuit includes a transistor, that the transistor is located in the current path between the two wires, and that the transistor is in the ON state.

[0014] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10.

[0015] The memory system 10 performs operations such as reading, writing, and erasing user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of memory dies MD for storing user data, and a controller die CD connected to these plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, RAM, etc., and performs operations such as logical address-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0016] Figure 2 is a schematic side view showing an example configuration of the memory system 10. Figure 3 is a schematic top view showing the same configuration. For the sake of explanation, some components are omitted in Figures 2 and 3.

[0017] As shown in Figure 2, the memory system 10 according to this embodiment comprises a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided on the upper surface of the mounting substrate MSB at the Y-direction end region, and some other regions are bonded to the lower surface of the memory dies MD via adhesive or the like. Pad electrodes P are provided on the upper surface of the memory dies MD at the Y-direction end region, and other regions are bonded to the lower surface of other memory dies MD or controller die CD via adhesive or the like. Pad electrodes P are provided on the upper surface of the controller die CD at the Y-direction end region.

[0018] As shown in Figure 3, the mounting substrate MSB, the multiple memory dies MD, and the controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P provided on the mounting substrate MSB, the multiple memory dies MD, and the controller die CD are each connected to one another via bonding wires B.

[0019] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, controller dies CD are stacked on multiple memory dies MD, and these components are connected by bonding wires B. In such a configuration, multiple memory dies MD and controller dies CD are contained within a single package. However, the controller die CD may be contained in a separate package from the memory dies MD. Also, multiple memory dies MD and controller dies CD may be connected to each other via through-electrodes or the like, instead of bonding wires B.

[0020] [Memory Die MD Configuration] Figure 4 is a schematic circuit diagram showing a part of the configuration of the memory die MD. As shown in Figure 4, the memory die MD comprises a memory cell array MCA that stores user data and a peripheral circuit PC connected to the memory cell array MCA.

[0021] [Configuration of Memory Cell Array MCA] The memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0022] The memory string MS comprises drain-side selection transistors STDT and STD, multiple memory cells MC (memory cell transistors), and source-side selection transistors STS and STSB, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistors STDT and STD and the source-side selection transistors STS and STSB may simply be referred to as selection transistors STDT, STD, STS, and STSB, etc.

[0023] A memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of user data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are each commonly connected to all memory string MS in one memory block BLK.

[0024] The selection transistors STDT, STD, STS, and STSB are field-effect transistors comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors STDT, STD, STS, and STSB are connected to selection gate lines SGDT, SGD, SGS, and SGSB, respectively. The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all memory strings MS in one string unit SU. The drain-side selection gate line SGDT and the source-side selection gate lines SGS and SGSB are commonly connected to all memory strings MS in a memory block BLK.

[0025] Figure 5 is a schematic perspective view showing a part of the configuration of the memory cell array MCA. The memory cell array MCA is provided above the semiconductor substrate 100. In addition, a plurality of transistors Tr that constitute the peripheral circuit PC are provided on the upper surface of the semiconductor substrate 100. Each of these plurality of transistors Tr comprises a channel region which is part of the upper surface of the semiconductor substrate 100, a gate insulating film formed on the upper surface of the semiconductor substrate 100, and a gate electrode which faces the channel region via the gate insulating film.

[0026] The memory cell array MCA comprises multiple memory blocks BLK aligned in the Y direction. Furthermore, between two adjacent memory blocks BLK in the Y direction, silicon oxide (SiO₂) is used. ２Block-to-block insulating layers ST are provided. In addition, above the memory cell array MCA, multiple bit lines BL are provided, aligned in the X direction and extending in the Y direction.

[0027] The memory block BLK comprises a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor columns 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor columns 120, respectively.

[0028] The conductive layer 110 is a substantially plate-shaped conductive layer stretched in the X direction. The conductive layer 110 may also contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Between the multiple conductive layers 110 aligned in the Z direction, silicon oxide (SiO ２ An insulating layer 101 such as the above is provided.

[0029] Furthermore, one or more of the bottommost conductive layers 110 function as the gate electrodes of the source-side selection gate line SGSB (Figure 4) and the multiple source-side selection transistors STSB (Figure 4) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0030] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the source-side selection gate line SGS (Figure 4) and the multiple source-side selection transistors STS (Figure 4) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0031] Furthermore, the multiple conductive layers 110 located above this function as gate electrodes for the word line WL (Figure 4) and the multiple memory cells MC (Figure 4) connected thereto. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0032] Furthermore, one or more conductive layers 110 located above this function as the gate electrodes of the drain-side selection gate line SGD (Figure 4) and the multiple drain-side selection transistors STD (Figure 4) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the conductive layer 110 that functions as a word line WL, etc.

[0033] Furthermore, one or more conductive layers 110 located above this function as the gate electrodes of the drain-side selection gate line SGDT (Figure 4) and the multiple drain-side selection transistors STDT (Figure 4) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the conductive layer 110 that functions as a word line WL, etc.

[0034] A semiconductor layer 112 is provided below the multiple conductive layers 110. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, silicon oxide (SiO) is placed between the semiconductor layer 112 and the conductive layer 110. ２ An insulating layer 101 such as the above is provided.

[0035] The semiconductor layer 112 functions as a source line SL (Figure 4). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0036] The semiconductor columns 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor columns 120 function as channel regions for multiple memory cells MC and selection transistors STDT, STD, STS, and STSB included in one memory string MS (Figure 4). The semiconductor columns 120 are semiconductor layers such as polycrystalline silicon (Si). The semiconductor columns 120 have a substantially cylindrical shape, as shown in Figure 5, for example, and an insulating layer 125 such as silicon oxide is provided in the central portion. The outer surfaces of the semiconductor columns 120 are each surrounded by conductive layers 110 and face the conductive layers 110.

[0037] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the end of the semiconductor column 120 on the bit line BL side. The impurity region 121 is connected to the bit line BL via contacts Ch and Cb.

[0038] The gate insulating film 130 has a substantially cylindrical shape that covers the outer surface of the semiconductor column 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are made of, for example, silicon oxide (SiO₂ ２ The insulating film is an insulating film such as ). The charge storage film is a charge-storable film such as silicon nitride (SiN). The tunnel insulating film, charge storage film, and block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer surface of the semiconductor column 120, excluding the contact portion between the semiconductor column 120 and the semiconductor layer 112.

[0039] Furthermore, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0040] Multiple conductive layers 110 are connected to multiple contact CCs. The multiple conductive layers 110 are electrically connected to the peripheral circuit PC via these multiple contact CCs. As shown in Figure 5, these multiple contact CCs extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contact CCs may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0041] Furthermore, the memory cell array MCA may be formed upside down. For example, the bit line BL may be provided below multiple memory blocks BLK. Also, the semiconductor layer 112 may be provided above multiple conductive layers 110.

[0042] [Operation of Memory Cell Array MCA] Next, the operation of the memory cell array MCA will be described. The memory cell array MCA according to this embodiment is configured to perform read operations, write operations, and erase operations.

[0043] FIG. 6 is a schematic cross-sectional view for explaining a read operation. In the following description, the word line WL that is the target of the operation will be referred to as the selected word line WL Ｓ and the other word lines WL will be referred to as unselected word lines WL Ｕ in some cases.

[0044] In the read operation, for example, an operating voltage V ＤＤ is supplied to the bit line BL. Also, a voltage V ＳＲＣ is supplied to the source line SL. The voltage V ＳＲＣ may be greater than the ground voltage V ＳＳ or may be equal to the ground voltage V ＳＳ . The operating voltage V ＤＤ is greater than the voltage V ＳＲＣ .

[0045] Also, in the read operation, a voltage V ＳＧ is supplied to the drain side selection gate lines SGDT, SGD. The voltage V ＳＧ is greater than the operating voltage V ＤＤ . Also, the voltage difference between the voltage V ＳＧ and the operating voltage V ＤＤ is greater than the threshold voltage of the drain side selection transistors STDT, STD. Therefore, an electron channel is formed in the channel regions of the drain side selection transistors STDT, STD, and the operating voltage V ＤＤ is transferred.

[0046] Also, in the read operation, a voltage V ＳＧ is supplied to the source side selection gate lines SGS, SGSB. The voltage V ＳＧ is greater than the voltage V ＳＲＣ . Also, the voltage difference between the voltage V ＳＧ and the voltage V ＳＲＣ is greater than the threshold voltage of the source side selection transistors STS, STSB. Therefore, an electron channel is formed in the channel regions of the source side selection transistors STS, STSB, and the voltage V ＳＲＣ is transferred.

[0047] Also, in the read operation, a read path voltage V Ｕ is applied to the unselected word line WL ＲＥＡＤIt supplies the read path voltage V. ＲＥＡＤ The operating voltage is V ＤＤ and voltage V ＳＲＣ It is larger than that. Also, the read path voltage V ＲＥＡＤ and operating voltage V ＤＤ and voltage V ＳＲＣ The voltage difference is greater than the threshold voltage of the memory cell MC, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the operating voltage V is applied to the selected memory cell MC. ＤＤ and voltage V ＳＲＣ It will be forwarded.

[0048] Furthermore, during the reading operation, the selected word line WL Ｓ Readout voltage V ＣＧＲ It supplies the read voltage V. ＣＧＲ The read path voltage V ＲＥＡＤ Smaller than. Readout voltage V ＣＧＲ and voltage V ＳＲＣ The voltage difference is greater than the threshold voltage of the memory cell MC where some data has been recorded. Therefore, the memory cell MC where some data has been recorded turns ON. Consequently, current flows through the bit line BL connected to such a memory cell MC. On the other hand, the read voltage V ＣＧＲ and V ＳＲＣ The voltage difference is smaller than the threshold voltage of the memory cell MC where some data has been recorded. Therefore, the memory cell MC where some data has been recorded is in the OFF state. Consequently, no current flows through the bit line BL connected to such a memory cell MC.

[0049] Furthermore, during the read operation, the sense amplifier SA (described later) detects the current or voltage of each bit line BL, stores it as user data, and outputs it to the cache memory CM (described later).

[0050] Figure 7 is a schematic cross-sectional view illustrating the writing operation.

[0051] In the writing operation, for example, the bit line BL connected to the one among the multiple selected memory cells MC that adjusts the threshold voltage. Ｗ Voltage V ＳＲＣIt supplies the bit line BL connected to the memory cell MC that does not have its threshold voltage adjusted. Ｐ Operating voltage V ＤＤ This supplies the following. Below, among the multiple selectable memory cells (MCs), those that adjust the threshold voltage are sometimes referred to as "write memory cells (MCs)," and those that do not adjust the threshold voltage are sometimes referred to as "prohibition memory cells (MCs)."

[0052] Furthermore, during the writing operation, a voltage V is applied to the drain-side selected gate lines SGDT and SGD. ＳＧＤ It will be supplied.

[0053] Voltage V ＳＧＤ is the voltage V ＳＲＣ It is larger than that. Also, voltage V ＳＧＤ and voltage V ＳＲＣ The voltage difference is greater than the threshold voltage of the drain-side selection transistors STDT and STD. Therefore, the bit line BL Ｗ In the channel region of the drain-side selection transistors STDT and STD connected to the voltage V, an electron channel is formed, and the voltage V ＳＲＣ It will be forwarded.

[0054] On the other hand, voltage V ＳＧＤ and operating voltage V ＤＤ The voltage difference is smaller than the threshold voltage of the drain-side selection transistors STDT and STD. Therefore, the bit line BL Ｐ The drain-side selection transistors STDT and STD connected to it will be in the OFF state.

[0055] Furthermore, during the writing operation, a voltage V is applied to the source line SL. ＳＲＣ A ground voltage V is supplied to the source-side selected gate lines SGS and SGSB. ＳＳ This is supplied. As a result, the source-side selection transistors STS and STSB are turned OFF.

[0056] Furthermore, during the writing operation, the non-selected word line WL Ｕ Write path voltage V ＰＡＳＳ It supplies the write path voltage V. ＰＡＳＳ The read path voltage V ＲＥＡＤ It is greater than. Also, the write path voltage V ＰＡＳＳ and voltage VＳＲＣ The voltage difference is greater than the threshold voltage of the memory cell MC, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and the voltage V is applied to the written memory cell MC. ＳＲＣ It will be forwarded.

[0057] Furthermore, during the writing operation, the selected word line WL Ｓ Program voltage V ＰＧＭ It supplies the program voltage V. ＰＧＭ The write path voltage V ＰＡＳＳ It is larger than that.

[0058] Here, bit line BL Ｗ The channels of the semiconductor column 120 connected to it have a voltage V ＳＲＣ Such a semiconductor column 120 and a selected word line WL are supplied. Ｓ A relatively large electric field is generated between the two. As a result, electrons in the channel of the semiconductor column 120 tunnel into the charge storage film in the gate insulating film 130 (Figure 5). This increases the threshold voltage of the write memory cell MC.

[0059] Meanwhile, bit line BL Ｐ The channel of the semiconductor column 120 connected to it is electrically floating, and the potential of this channel is the non-selected word line WL Ｕ Capacitive coupling with the write path voltage V ＰＡＳＳ It has risen to this extent. Such semiconductor column 120 and selected word line WL Ｓ Only an electric field smaller than the one described above is generated between them. Therefore, electrons in the channel of the semiconductor column 120 do not tunnel into the charge storage film in the gate insulating film 130 (Figure 5). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0060] Figure 8 is a schematic cross-sectional view illustrating the erase operation.

[0061] During the erase operation, the erase voltage V is applied to the bit line BL and the source line SL. ＥＲＡ The following is supplied: Eraser voltage V ＥＲＡ For example, the program voltage V ＰＧＭIt may be larger or equal to the program voltage V ＰＧＭ as well.

[0062] Also, in the erasing operation, a voltage V ＳＧ ´ is supplied to the drain side selection gate line SGDT. The voltage V ＳＧ ´ is smaller than the erasing voltage V ＥＲＡ . As a result, GIDL (Gate Induced Drain Leakage) occurs in the drain side selection transistor STDT, generating electron-hole pairs. Also, electrons move to the bit line BL side and holes move to the memory cell MC side.

[0063] Also, in the erasing operation, a voltage V ＳＧ ´´ is supplied to the drain side selection gate line SGD. The voltage V ＳＧ ´´ is smaller than the erasing voltage V ＥＲＡ and larger than the voltage V ＳＧ ´. As a result, a hole channel is formed in the channel region of the drain side selection transistor STD, and holes are transferred to the memory cell MC side.

[0064] Also, in the erasing operation, a voltage V ＳＧ ´ is supplied to the source side selection gate line SGSB. As a result, GIDL occurs in the source side selection transistor STSB, generating electron-hole pairs. Also, electrons move to the source line SL side and holes move to the memory cell MC side.

[0065] Also, in the erasing operation, a voltage V ＳＧ ´´ is supplied to the source side selection gate line SGS. As a result, a hole channel is formed in the channel region of the source side selection transistor STS, and holes are transferred to the memory cell MC side.

[0066] Also, in the erasing operation, a ground voltage V ＳＳ is supplied to the word line WL. As a result, holes in the channel of the semiconductor column 120 tunnel to the charge storage film in the gate insulating film 130 (Fig. 5). Thereby, the threshold voltage of the memory cell MC decreases.

[0067] FIG. 9 is a schematic cross-sectional view for explaining the erase verification operation. The erase verification operation is an operation for determining whether an erase operation has been suitably executed on a memory block BLK.

[0068] The erase verification operation is executed for each string unit SU described with reference to FIG. 4. For example, when the memory block BLK includes five string units SU, after an erase operation is executed once on the memory block BLK, five erase verification operations corresponding to each string unit SU are executed.

[0069] The erase verification operation is basically executed in the same manner as the read operation.

[0070] However, in the erase verification operation, an erase verification voltage V ＣＧＲ or read path voltage V ＲＥＡＤ is not supplied to the word line WL, but an erase verification voltage V ＶＦＹＥｒ is supplied. The erase verification voltage V ＶＦＹＥｒ is smaller than the read voltage V ＣＧＲ . The voltage difference between the erase verification voltage V ＶＦＹＥｒ and the voltage V ＳＲＣ is smaller than the threshold voltage of all memory cells MC other than the memory cells MC in the erased state. Therefore, the memory cells MC that have reached the erased state become ON state, and the memory cells MC that have not reached the erased state become OFF state. Therefore, a current flows through the bit line BL in which all the memory cells MC in the corresponding memory string MS have reached the erased state. On the other hand, no current flows through the bit line BL in which a memory cell MC that has not reached the erased state is included in the corresponding memory string MS.

[0071] Also, in the erase verification operation, the current or voltage of each bit line BL is detected by a sense amplifier SA described later. When a current flows through all the bit lines BL or a certain number or more of the bit lines BL, it is determined that the erase operation has been suitably executed. On the other hand, when no current flows through all the bit lines BL or a certain number or more of the bit lines BL, it is determined that the erase operation has not been suitably executed.

[0072] [Peripheral Circuit PC Configuration] Figure 10 is a schematic block diagram showing the configuration of the peripheral circuit PC.

[0073] Figure 10 illustrates multiple control terminals. These control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals), control terminals corresponding to low-active signals (negative logic signals), or control terminals corresponding to both high-active and low-active signals. In Figure 10, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 10 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be made low-active signals, or some or all low-active signals may be made high-active signals.

[0074] Furthermore, arrows indicating input / output directions are shown next to the multiple control terminals shown in Figure 10. In Figure 10, control terminals with arrows pointing from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. In Figure 10, control terminals with arrows pointing from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. In Figure 10, control terminals with bidirectional arrows can be used for both inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0075] The peripheral circuit PC comprises a row decoder RD and a sense amplifier SA connected to the memory cell array MCA, and a cache memory CM connected to the sense amplifier. The peripheral circuit PC also comprises a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC comprises an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, and a status register STR.

[0076] The row decoder RD includes, for example, a block decoder that decodes the block address in the row address RA included in the address data Add, and a voltage transfer circuit that, in accordance with the output signal of the block decoder, connects multiple word lines WL (Figure 4) included in one of the multiple memory blocks BLK to multiple voltage supply lines (not shown). The detailed configuration of the row decoder RD will be described later with reference to Figures 11 to 14.

[0077] The sense amplifier SA comprises multiple sense circuits and multiple voltage transfer circuits connected to multiple bit lines BL, and a data latch circuit. The sense circuits latch "0" or "1" data based on the voltage or current of the bit lines BL in the data latch circuit, for example, according to a control signal from the sequencer SQC. The voltage transfer circuits adjust the voltage of the bit lines BL to "H" or "L" based on the "0" or "1" data latched in the data latch circuit, for example, according to a control signal from the sequencer SQC. User data Dat in the data latch circuit is output to the input / output control circuit I / O via the cache memory CM and data bus DB. User data Dat output from the input / output control circuit I / O is latched to the data latch circuit in the sense amplifier SA via the data bus DB and cache memory CM.

[0078] The voltage generation circuit VG includes, for example, a boost circuit such as a charge pump circuit and a buck circuit such as a regulator. These boost and buck circuits each control the power supply voltage V ＣＣ and ground voltage V ＳＳIt is connected to a voltage supply line to which the voltage V is supplied. These voltage supply lines are connected to the pad electrodes P, as described with reference to Figures 2 and 3. The voltage generation circuit VG generates multiple operating voltages to be applied to the bit line BL, source line SL, word line WL, and selection gate lines SGD, SGS during read, write, and erase operations on the memory cell array MCA, according to a control signal from the sequencer SQC, and supplies these voltages to the bit line BL, source line SL, word line WL, and selection gate lines SGDT, SGD, SGS, SGSB via multiple voltage supply lines. The operating voltages output from the voltage supply lines are adjusted as appropriate according to the control signal from the sequencer SQC. The voltage generation circuit VG also generates the operating voltage V ＤＤ It also generates and supplies it to each circuit via the voltage supply line.

[0079] The SQC sequencer outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG, according to the command data Cmd input to the command register CMR. The SQC sequencer also outputs status data Stt, which indicates the state of the memory die MD, to the status register STR as appropriate.

[0080] Furthermore, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state when an operation that supplies voltage to the memory cell array MCA is being performed, such as a read operation, write operation, or erase operation, and in the "H" state at all other times. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. The terminal RY / / BY is implemented, for example, by the pad electrode P described with reference to Figures 2 and 3.

[0081] As shown in Figure 10, the address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR comprises, for example, multiple 8-bit register sequences. When an internal operation such as a read operation, write operation, or erase operation is performed, the register sequence holds the address data Add corresponding to the internal operation being performed.

[0082] The address data Add includes, for example, the column address CA and the row address RA. The row address RA includes, for example, the block address that identifies the memory block BLK (Figure 4), the page address that identifies the string unit SU and the word line WL, the plane address that identifies the memory cell array MCA, and the chip address that identifies the memory die MD.

[0083] The command register CMR is connected to the input / output control circuit I / O, and command data Cmd is input from the input / output control circuit I / O. When command data Cmd is input to the command register CMR, a control signal is sent to the sequencer SQC.

[0084] The status register STR is connected to the input / output control circuit I / O and stores status data Stt to be output to the input / output control circuit I / O. The status register STR comprises, for example, multiple 8-bit register sequences. The register sequences hold status data Stt related to the internal operation being performed, for example, when an internal operation such as a read operation, write operation, or erase operation is executed. The register sequences also hold, for example, ready / busy information for the memory cell array MCA.

[0085] The input / output control circuit (I / O) comprises data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, and a plurality of input and output circuits connected to the data signal input / output terminals DQ0 to DQ7, respectively. The input circuits are, for example, receivers such as comparators, and the output circuits are, for example, drivers such as OCD (Off Chip Driver) circuits.

[0086] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS are implemented by, for example, the pad electrodes P described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is input to the cache memory CM, address register ADR, or command register CMR in accordance with the internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is output from the cache memory CM or status register STR in accordance with the internal control signal from the logic circuit CTR.

[0087] Signals input via the data strobe signal input / output terminals DQS, / DQS (for example, the data strobe signal and its complementary signal) are used when inputting data via the data signal input / output terminals DQ0 to DQ7.

[0088] The logic circuit CTR comprises multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O accordingly. In the following description, the external control terminal / CE may be referred to as the "chip enable signal input terminal / CE".

[0089] Furthermore, each of the external control terminals / CE, CLE, ALE, / WE, / RE, and RE is implemented by the pad electrode P described with reference to Figures 2 and 3, for example.

[0090] Signals input via the external control terminal / CE (e.g., chip enable signal) are used when selecting the memory die MD. When "L" is input to the external control terminal / CE, the memory die MD becomes capable of inputting and outputting user data Dat, command data Cmd, and address data Add (hereinafter sometimes simply referred to as "data"). When "H" is input to the external control terminal / CE, the memory die MD becomes incapable of inputting and outputting data.

[0091] Signals input via the external control terminal CLE (for example, the command latch enable signal) are used when using the command register CMR. When "H" is input to the external control terminal CLE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as command data Cmd in the buffer memory of the input / output control circuit I / O and transferred to the command register CMR.

[0092] Signals input via the external control terminal ALE (for example, the address latch enable signal) are used when using the address register ADR. When "H" is input to the external control terminal ALE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as address data Add in the buffer memory within the input / output control circuit I / O and transferred to the address register ADR.

[0093] Furthermore, if "L" is input to both external control terminals CLE and ALE, the data input via data signal input / output terminals DQ0 to DQ7 is stored as user data Dat in the buffer memory within the input / output control circuit I / O. The user data Dat stored in the buffer memory is transferred to the cache memory CM via the bus DB.

[0094] Signals input via the external control terminal / WE (e.g., write enable signal) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the rising voltage of the external control terminal / WE (switching of the input signal).

[0095] Furthermore, when inputting data, you may use the external control terminal / WE or the data strobe signal input / output terminals DQS, / DQS.

[0096] Signals input via the external control terminals RE, RE (for example, the read enable signal and its complementary signal) are used when outputting data via the data signal input / output terminals DQ0 to DQ7.

[0097] [Configuration of the Raw Decoder RD] Next, the configuration of the Raw Decoder RD will be explained in more detail with reference to Figures 11 to 14. Figures 11 to 14 are schematic circuit diagrams showing the configuration of the Raw Decoder RD.

[0098] As described above, the row decoder RD comprises a block decoder and a voltage transfer circuit. Figure 11 shows the configuration of the voltage transfer circuit XFER. Figure 12 shows the configuration of the block decoder BLKD. Figure 13 shows the configuration of the block decoder unit blkd. Figure 14 shows the configuration of the latch circuit CBL.

[0099] [Configuration of Voltage Transfer Circuit XFER] As shown in Figure 11, the voltage transfer circuit XFER comprises multiple voltage transfer units xfer. The multiple voltage transfer units xfer correspond to multiple memory blocks BLK in the memory cell array MCA. The voltage transfer unit xfer comprises multiple transistors T ＢＬＫ It includes multiple transistors T ＢＬＫ This corresponds to multiple word lines WL in the memory block BLK. Transistor T ＢＬＫ For example, a field-effect NMOS transistor is a transistor T. ＢＬＫ The drain electrode of transistor T is connected to the word line WL. ＢＬＫ The source electrode is connected to the voltage supply line CG. The voltage supply line CG is connected to all voltage transfer units xfer in the voltage transfer circuit XFER. Transistor T ＢＬＫ The gate electrode is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided to correspond to all voltage transfer units xfer. The signal supply line BLKSEL also connects to all transistors T in the voltage transfer unit xfer. ＢＬＫ It connects to the network.

[0100] During read and write operations, for example, one signal supply line BLKSEL corresponding to the block address in the address register ADR (Figure 10) becomes "H" and the other signal supply lines BLKSEL become "L". For example, a predetermined drive voltage with a positive magnitude is supplied to one signal supply line BLKSEL, and a ground voltage V is supplied to the other signal supply lines BLSEL. ＳＳ These are supplied. As a result, all word lines WL in one memory block BLK corresponding to this block address become conductive with all voltage supply lines CG. In addition, all word lines WL in other memory blocks BLK become floating.

[0101] [Configuration of Block Decoder BLKD] As shown in Figure 12, the block decoder BLKD comprises multiple block decoder units blkd corresponding to multiple signal supply lines BLKSEL in the voltage transfer circuit XFER, multiple level shifters LS connected to the output terminals (signal supply line RDEC_SEL, described later) of these multiple block decoder units blkd and outputting signals to the signal supply line BLKSEL, and an inverting signal generation circuit IAG connected to these multiple block decoder units blkd.

[0102] As shown in Figure 13, the block decoder unit blkd comprises a block address receiving circuit CAR, a selection information holding circuit CSL, and a latch circuit CBL. The block address receiving circuit CAR conducts between node n11 and the drain electrode of transistor N16, which will be described later, when the block address input to the block decoder blkd matches the block address corresponding to itself. The selection information holding circuit CSL holds the signal information of node n11 and can output it via the signal supply line RDEC_SEL.

[0103] The block address receiving circuit CAR comprises a plurality of transistors N11, N12, N13, N14, and N15 connected in series. Transistors N11, N12, N13, N14, and N15 are, for example, field-effect NMOS transistors. The gate electrodes of transistors N11, N12, N13, N14, and N15 are connected to address supply lines AROWA, AROWB, AROWC, AROWD, and AROWE, respectively. In the following description, address supply lines AROWA, AROWB, AROWC, AROWD, and AROWE may be referred to as "address supply line AROW."

[0104] One end of the block address receiving circuit CAR (the drain electrode of transistor N11) is connected to transistor P11 via node n11. Transistor P11 is, for example, a field-effect PMOS transistor. The source electrode of transistor P11 is connected to the operating voltage V ＤＤ It is connected to the voltage supply line that provides the power. The drain electrode of transistor P11 is connected to node n11. The gate electrode of transistor P11 is connected to the signal supply line RDEC.

[0105] The other end of the block address receiving circuit CAR (the source electrode of transistor N15) is connected to node n12 via transistor N16. Transistor N16 is, for example, a field-effect NMOS transistor. The source electrode of transistor N16 is connected to node n12. The drain electrode of transistor N16 is connected to the source electrode of transistor N15. The gate electrode of transistor N16 is connected to the signal supply line RDEC.

[0106] Node n12 is connected to transistors N17 and N18. Transistors N17 and N18 are, for example, field-effect NMOS transistors.

[0107] The source electrode of transistor N17 is at ground voltage V ＳＳIt is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N17 is connected to node n12. The gate electrode of transistor N17 is connected to the signal supply line ROMBAEN.

[0108] The source electrode of transistor N18 is at ground voltage V ＳＳ It is connected to a voltage supply line that provides the voltage. The drain electrode of transistor N18 is connected to node n12. The gate electrode of transistor N18 is connected to node GOOD, which will be described later with reference to Figure 14.

[0109] The selection information holding circuit CSL comprises a transistor P12 and an inverter circuit INV1.

[0110] Transistor P12 is, for example, a field-effect PMOS transistor. The source electrode of transistor P12 is at the operating voltage V ＤＤ It is connected to the voltage supply line that provides the power. The drain electrode of transistor P12 is connected to node n11. The gate electrode of transistor P11 is connected to the signal supply line RDEC_SEL. Note that the ON current of transistor P12 is smaller than the ON currents of transistors N11, N12, N13, N14, N15, N16, and N18. Also, the ON current of transistor P12 is smaller than the ON currents of transistors N11, N12, N13, N14, N15, N16, and N17.

[0111] The input terminal of inverter circuit INV1 is connected to node n11. The output terminal of inverter circuit INV1 is connected to the signal supply line RDEC_SEL.

[0112] The latch circuit CBL holds information about the bad block. In this memory cell array MCA, some memory blocks BLK may be unusable due to short circuits between wiring or other reasons. In this specification, such memory blocks BLK are referred to as "bad blocks".

[0113] The latch circuit CBL is normally in a reset state. In the reset state, node GOOD in the latch circuit CBL is in the "H" state, and node BAD (Figure 14) in the latch circuit CBL is in the "L" state. In the reset state, transistor N18 is in the ON state. When the memory system 10 starts up, a set operation, described later, is performed on the latch circuit CBL corresponding to the bad block. As a result, the latch circuit CBL is put into a set state. In the set state, node GOOD in the latch circuit CBL is in the "L" state, and node BAD (Figure 14) in the latch circuit CBL is in the "H" state. In the set state, transistor N18 is in the OFF state.

[0114] The latch circuit CBL, as shown in Figure 14, comprises transistors P21, P22, P23, P24, N21, N22, N23, N24, and N25. Transistors P21, P22, P23, and P24 are, for example, field-effect type PMOS transistors. Transistors N21, N22, N23, N24, and N25 are, for example, field-effect type NMOS transistors.

[0115] The source electrode of transistor P21 is at the operating voltage V ＤＤ It is connected to a voltage supply line that is supplied with the voltage V. The drain electrode of transistor P21 is connected to the source electrode of transistor P22. The gate electrode of transistor P21 is connected to the ground voltage V. ＳＳ It is connected to a voltage supply line that provides the power.

[0116] As described above, the source electrode of transistor P22 is connected to the drain electrode of transistor P21. The drain electrode of transistor P22 is connected to node GOOD. The gate electrode of transistor P22 is connected to node BAD.

[0117] The source electrode of transistor P23 is at the operating voltage V ＤＤ It is connected to a voltage supply line that is supplied with V. The drain electrode of transistor P23 is connected to the source electrode of transistor P24. The gate electrode of transistor P23 is connected to the ground voltage V. ＳＳ It is connected to a voltage supply line that provides the power.

[0118] As described above, the source electrode of transistor P24 is connected to the drain electrode of transistor P23. The drain electrode of transistor P24 is connected to node BAD. The gate electrode of transistor P24 is connected to node GOOD.

[0119] The source electrode of transistor N21 is at ground voltage V ＳＳ It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N21 is connected to node GOOD. The gate electrode of transistor N21 is connected to node BAD.

[0120] The source electrode of transistor N22 is at ground voltage V ＳＳ It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N22 is connected to node BAD. The gate electrode of transistor N22 is connected to node GOOD.

[0121] Furthermore, transistors P22 and N21 constitute an inverter circuit. Similarly, transistors P24 and N22 also constitute an inverter circuit. In addition, these two inverter circuits constitute a latch circuit.

[0122] The source electrode of transistor N23 is connected to node n21. The drain electrode of transistor N23 is connected to node GOOD. The gate electrode of transistor N23 is connected to the signal supply line RST.

[0123] The source electrode of transistor N24 is connected to node n21. The drain electrode of transistor N24 is connected to node BAD. The gate electrode of transistor N24 is connected to the signal supply line SET.

[0124] The source electrode of transistor N25 is at ground voltage V ＳＳ It is connected to the voltage supply line that provides the power. The drain electrode of transistor N25 is connected to node n21. The gate electrode of transistor N25 is connected to the signal supply line RDEC_SEL.

[0125] As shown in Figure 12, the signal supply lines RDEC, ROMBAEN, RST, and SET are connected in common to all block decoder units blkd.

[0126] [Configuration of the Inverting Signal Generation Circuit IAG] As shown in Figure 12, the inverting signal generation circuit IAG comprises five nodes nAA, nAB, nAC, nAD, and nAE, each receiving a 5-bit address signal corresponding to each bit in a 5-bit block address. Each node nAA, nAB, nAC, nAD, and nAE receives the corresponding bit from the block address. Hereafter, these five nodes nAA, nAB, nAC, nAD, and nAE may be referred to as "node nA".

[0127] Furthermore, the inverting signal generation circuit IAG includes five inverter circuits INV3, each corresponding to one of the five nodes nA. The input terminals of the inverter circuits INV3 are connected to the nodes nA. The inverter circuits INV3 output an inverted signal of the corresponding bit in the block address.

[0128] Furthermore, the inverting signal generation circuit IAG includes 10 OR circuits COR, each corresponding to a 5-bit address signal and a corresponding 5-bit inverting signal. One input terminal of the OR circuit COR receives either the 5-bit address signal or one of the 5-bit inverting signals. The other input terminal of the OR circuit COR is connected to the signal supply line ALLBLK.

[0129] Here, the inverting signal generation circuit IAG typically outputs a 5-bit address signal and its corresponding 5-bit inverted signal (i.e., the signal supply line ALLBLK is typically input to "L"). In addition, the address supply lines AROW in each of the multiple block decoder units blkd are connected to the output terminals of the OR circuit COR such that all bits become "H" when the block addresses input to the five nodes nA match their own block addresses.

[0130] For example, in the block decoder unit blkd (the second block decoder unit blkd from the top in Figure 12) corresponding to block address "11101", the address supply lines AROWA, AROWB, AROWC, and AROWE are connected to the output terminals of the OR circuit COR corresponding to the address signal. On the other hand, the address supply line AROWD is connected to the output terminal of the OR circuit COR corresponding to the inverted signal. Therefore, when block address "11101" is input to the inverted signal generation circuit IAG, in the corresponding block decoder unit blkd, transistors N11, N12, N13, N14, and N15 (Figure 13) all turn ON. On the other hand, in the other block decoder units blkd, at least one of transistors N11, N12, N13, N14, and N15 (Figure 13) turns OFF.

[0131] [Operation of Block Decoder BLKD] Next, the operation of the block decoder BLKD will be described. The block decoder BLKD according to this embodiment is configured to perform memory block selection operation, all memory block selection operation, set operation, reset operation, all set operation, and all reset operation of the latch circuit CBL (Figure 14).

[0132] [Memory Block Selection Operation] Figure 15 is a schematic waveform diagram illustrating the memory block selection operation. The controller die CD causes the memory die MD to perform an operation by sending a command set containing command data Cmd and address data Add. For example, when the memory die MD receives the command set, the block decoder BLKD performs a memory block selection operation based on the information indicating the block address contained in the address data Add. In the memory block selection operation, one memory block BLK corresponding to the input block address is selected as the selected memory block BLK from among multiple memory blocks BLK in the memory cell array MCA, and the other memory blocks BLK become unselected memory blocks BLK.

[0133] Before the memory block selection operation begins, the signals on the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state. In this state, transistor P11 (Figure 13) is ON and transistor N16 (Figure 13) is OFF. Therefore, the voltage at node n11 is the operating voltage V ＤＤ It is fully charged, and "L" is output from the signal supply line RDEC_SEL.

[0134] At timing t101, the block decoder BLKD receives the block address corresponding to the selected memory block BLK, and the signal on the address supply line AROW switches. Consequently, in the block address receiving circuit CAR (Figure 13) corresponding to the selected memory block BLK, transistors N11, N12, N13, N14, and N15 all turn ON. On the other hand, in the other block address receiving circuits CAR, at least one of transistors N11, N12, N13, N14, and N15 turns OFF.

[0135] At timing t102, the signal on the signal supply line RDEC rises to the "H" state. Consequently, transistor P11 (Figure 13) turns OFF and transistor N16 (Figure 13) turns ON.

[0136] As a result, in the block decoder unit blkd corresponding to the selected memory block BLK, nodes n11 and n12 conduct to each other. If the corresponding memory block BLK is not a faulty block, the latch circuit CBL included in the block decoder unit blkd is in a reset state. Therefore, transistor N18 (Figure 13) turns ON, and node n11 conducts to the ground voltage V ＳＳ The voltage supply line that provides the voltage is in conductivity with the voltage supply line, and the voltage at node n11 is the ground voltage V ＳＳ The voltage decreases to a certain level. Additionally, an "H" signal is output from the signal supply line RDEC_SEL, and the signal on the signal supply line BLKSEL connected to the corresponding level shifter LS (Figure 12) also becomes "H," causing multiple word lines WL in the selected memory block BLK to conduct to multiple voltage supply lines CG (Figure 11).

[0137] On the other hand, in the block decoder unit blkd corresponding to the unselected memory block BLK, nodes n11 and n12 are not conducting to each other. Therefore, the voltage at node n11 is the operating voltage V ＤＤ This state is maintained, and the output of the signal supply line RDEC_SEL is also maintained at "L".

[0138] Furthermore, even if the selected memory block BLK is a faulty block, nodes n11 and n12 in the block decoder unit blkd corresponding to the faulty block will conduct to each other. However, the latch circuit CBL included in the block decoder unit blkd corresponding to the faulty block is in the set state. Therefore, transistor N18 (Figure 13) is in the OFF state, and nodes n11 and n12 are not conducting to each other. Consequently, the voltage at node n11 is the operating voltage V. ＤＤ This state is maintained, and the output of the signal supply line RDEC_SEL is also maintained at "L".

[0139] Furthermore, when "L" is output from the signal supply line RDEC_SEL, node n11 is charged via transistor P12. Therefore, if the ON current of transistor P12 is approximately the same as the ON current of transistors N11, N12, N13, N14, N15, N16, and N18, the voltage at node n11 will be equal to the ground voltage V ＳＳ There is a risk that it may not be possible to reduce it to that level. Therefore, in this embodiment, as described above, the ON current of transistor P12 is made smaller than the ON currents of transistors N11, N12, N13, N14, N15, N16, and N18.

[0140] During the period from timing t102 to timing t103, multiple word lines WL in the selected memory block BLK are connected to multiple voltage supply lines CG, making it possible to perform the read operation described with reference to Figure 6, the write operation described with reference to Figure 7, and the erase operation described with reference to Figure 8. In this way, each block decoder unit blkd included in the block decoder BLKD has the function of connecting or electrically disconnecting multiple word lines WL and multiple voltage supply lines CG in the corresponding memory block BLK depending on whether the address data Add (block address) points to the corresponding memory block BLK. Furthermore, each block decoder unit blkd maintains an electrically disconnected state between multiple word lines WL and multiple voltage supply lines CG in the memory block BLK, even when the address data Add (block address) points to the corresponding memory block BLK, by setting the latch circuit CBL to a set state that indicates, for example, that the corresponding memory block BLK is a bad block. In other words, each block decoder unit blkd has the function of keeping multiple word lines WL and multiple voltage supply lines CG in the corresponding memory block BLK electrically isolated, depending on the state of the latch circuit CBL.

[0141] At timing t103, the signal on the signal supply line RDEC falls to the "L" state. Consequently, transistor P11 (Figure 13) turns ON and transistor N16 (Figure 13) turns OFF. As a result, in the block decoder unit blkd corresponding to the selected memory block BLK, node n11 turns to the operating voltage V ＤＤ It is charged to this level. Also, an "L" is output from the signal supply line RDEC_SEL, and the signal of the signal supply line BLKSEL connected to the corresponding level shifter LS (Figure 12) also becomes "L", and multiple word lines WL in the selected memory block BLK are electrically disconnected from multiple voltage supply lines CG (Figure 11).

[0142] [All Memory Block Selection Operation] Figure 16 is a schematic waveform diagram illustrating the all memory block selection operation. In the all memory block selection operation, all memory block BLKs in the memory cell array MCA are selected, except for those corresponding to latch circuits CBLs in the set state. In other words, in the all memory block selection operation, all memory block BLKs corresponding to latch circuits CBLs in the reset state become selected memory block BLKs, and all memory block BLKs corresponding to latch circuits CBLs in the set state become unselected memory block BLKs.

[0143] Before the start of the full memory block selection operation, the signals on the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state.

[0144] At timing t201, the signal supply line ALLBLK, as explained with reference to Figure 12, is raised to "H". Consequently, in the block address receiving circuit CAR (Figure 13) corresponding to all memory blocks BLK in the memory cell array MCA, transistors N11, N12, N13, N14, and N15 all turn ON.

[0145] At timing t202, the signal on the signal supply line RDEC rises to the "H" state. Consequently, transistor P11 (Figure 13) turns OFF and transistor N16 (Figure 13) turns ON.

[0146] As a result, in block decoder unit blkd where the latch circuit CBL is in the reset state, node n11 is at ground voltage V ＳＳ The voltage supply line that provides the voltage is in conductivity with the voltage supply line, and the voltage at node n11 is the ground voltage V ＳＳ The voltage decreases to a certain level. Additionally, a "H" signal is output from the signal supply line RDEC_SEL, and the signal on the signal supply line BLKSEL connected to the corresponding level shifter LS also becomes "H," causing multiple word lines WL in the selected memory block BLK to conduct to multiple voltage supply lines CG.

[0147] On the other hand, in the block decoder unit blkd where the latch circuit CBL is in the set state, nodes n11 and n12 receive the ground voltage V via transistor N18 (Figure 13). ＳＳ It is electrically disconnected from the voltage supply line that provides the voltage. Therefore, the voltage at node n11 is the operating voltage V ＤＤ This state is maintained, and the output of the signal supply line RDEC_SEL is also kept at "L". As a result, multiple word lines WL in the unselected memory block BLK do not conduct to multiple voltage supply lines CG.

[0148] During the period from timing t202 to timing t203, multiple word lines WL in all memory blocks BLK corresponding to block decoder unit blkd, where the latch circuit CBL is in a reset state, are in conduction with multiple voltage supply lines CG.

[0149] At timing t203, the signal on the signal supply line RDEC falls to the "L" state. Consequently, transistor P11 (Figure 13) turns ON and transistor N16 (Figure 13) turns OFF. As a result, in the block decoder unit blkd, where the latch circuit CBL is in the reset state, node n11 is at the operating voltage V ＤＤ It is charged to this point. Also, the signals of the signal supply lines RDEC_SEL and BLKSEL become "L" and multiple word lines WL in the selected memory block BLK are electrically disconnected from multiple voltage supply lines CG.

[0150] [Setting Operation of Latch Circuit CBL] Figure 17 is a schematic waveform diagram illustrating the setting operation of the latch circuit CBL. In the setting operation, the latch circuit CBL, which is included in one of the multiple block decoder units blkd, is set to the set state.

[0151] Before the start of the set operation, the signals for the signal supply lines RDEC, ROMBAEN, SET, and RST are all in the "L" state.

[0152] At timing t301, the block decoder BLKD receives the block address corresponding to the latch circuit CBL that performs the set operation, and the signal on the address supply line AROW switches. Consequently, in the block address receiving circuit CAR (Figure 13) corresponding to the block decoder unit blkd that performs the set operation, transistors N11, N12, N13, N14, and N15 all turn ON.

[0153] At timing t302, the signals on the signal supply lines RDEC and ROMBAEN rise to the "H" state. Consequently, transistor P11 (Figure 13) turns OFF, and transistors N16 and N17 (Figure 13) turn ON.

[0154] As a result, in the block decoder unit blkd that performs the set operation, node n11 is at ground voltage V ＳＳ The voltage supply line that provides the voltage is in conductivity with the voltage supply line, and the voltage at node n11 is the ground voltage V ＳＳ It decreases to [a certain value]. Also, "H" is output from the signal supply line RDEC_SEL. In addition, transistor N25 (Figure 14) turns ON.

[0155] At timing t303, the signal on the signal supply line SET rises to the "H" state. Consequently, transistor N23 (Figure 14) turns ON. As a result, node GOOD is connected to the ground voltage V ＳＳ The voltage supply line that provides the voltage is in conductivity, and the voltage at node GOOD is equal to the ground voltage V ＳＳ It decreases to this state. As a result, node GOOD becomes "L" and node BAD becomes "H". In other words, the latch circuit CBL becomes set.

[0156] Furthermore, in the reset state, node GOOD is charged via transistors P21 and P22. Therefore, if the ON current of transistors P21 and P22 is approximately the same as the ON current of transistors N23 and N25, the voltage of node GOOD will be equal to the ground voltage V ＳＳ There is a risk that it may not be possible to reduce it to that level. Therefore, in this embodiment, as described above, the ON current of transistors P21 and P22 is made smaller than the ON current of transistors N23 and N25.

[0157] At timing t304, the signal on the signal supply line SET falls to the "L" state. Consequently, transistor N23 (Figure 14) turns OFF.

[0158] At timing t305, the signals on the signal supply lines RDEC and ROMBAEN fall to the "L" state. Consequently, transistor P11 (Figure 13) turns ON and transistor N16 (Figure 13) turns OFF. As a result, in the block decoder unit blkd where the set operation was performed, node n11 turns to the operating voltage V ＤＤ It will be charged to this point. Also, the signals on the signal supply lines RDEC_SEL and BLKSEL will be in the "L" state.

[0159] [Reset Operation of Latch Circuit CBL] Figure 18 is a schematic waveform diagram illustrating the reset operation of the latch circuit CBL. In the reset operation, the latch circuit CBL, which is included in one of the multiple block decoder units blkd, is set to the reset state.

[0160] The reset operation is performed in much the same way as the set operation.

[0161] However, at the reset timing t303, the signal on the signal supply line RST rises to a "H" state, rather than the signal supply line SET. This causes the latch circuit CBL to enter a reset state.

[0162] Furthermore, at the reset timing t304, the signal of the signal supply line RST falls to the "L" state, rather than the signal supply line SET.

[0163] Furthermore, in the set state, node BAD is charged via transistors P23 and P24. Therefore, if the ON current of transistors P23 and P24 is approximately the same as the ON current of transistors N24 and N25, the voltage of node BAD will be equal to the ground voltage V ＳＳ There is a risk that it may not be possible to reduce it to that level. Therefore, in this embodiment, as described above, the ON current of transistors P23 and P24 is made smaller than the ON current of transistors N24 and N25.

[0164] [Full Set Operation of Latch Circuit CBL] Figure 19 is a schematic waveform diagram illustrating the full set operation of the latch circuit CBL. In full set operation, all latch circuits CBL contained in all block decoder units blkd included in the block decoder BLKD are set to the set state.

[0165] The full set operation is performed in much the same way as the set operation. However, at the timing t301 of the full set operation, instead of inputting the block address to the block decoder BLKD, the signal supply line ALLBLK, as explained with reference to Figure 12, is raised to "H".

[0166] [Full Reset Operation of Latch Circuit CBL] Figure 20 is a schematic waveform diagram illustrating the full reset operation of the latch circuit CBL. In the full reset operation, all latch circuits CBL contained in all block decoder units blkd included in the block decoder BLKD are reset.

[0167] The full reset operation is performed in much the same way as the reset operation. However, at the timing t301 of the full reset operation, instead of inputting the block address to the block decoder BLKD, the signal supply line ALLBLK, as explained with reference to Figure 12, is raised to "H".

[0168] [Multiple Memory Block Erase Operation] The erase operation described with reference to Figure 8 takes a long time compared to the read operation described with reference to Figure 6 and the write operation described with reference to Figure 7, and it is desirable to speed it up. Therefore, the semiconductor memory device according to this embodiment is configured to simultaneously select multiple memory blocks BLK included in the memory cell array MCA and to perform erase operations on these multiple memory blocks BLK in parallel. In this specification, such an operation is called a "multiple memory block erase operation".

[0169] Figure 21 is a flowchart illustrating the operation of erasing multiple memory blocks.

[0170] In step S101, the entire set operation described with reference to Figure 19 is performed, and all latch circuits CBL in the block decoder BLKD are set to the set state.

[0171] In step S102, one of the multiple memory blocks BLK included in the memory cell array MCA is selected, and the corresponding latch circuit CBL is subjected to the reset operation described with reference to Figure 18.

[0172] In step S103, it is determined whether a reset operation has been performed for all memory blocks BLK that are subject to the multiple memory block erase operation. If it has been performed, the process proceeds to step S104. If it has not been performed, the process returns to step S102.

[0173] In step S104, the number of loops is n. Ｅ Set to 1. Loop count n Ｅ This variable indicates the number of iterations of the erase loop.

[0174] In step S105, the multiple selected memory blocks BLK selected in step S102 are selected by the total memory block selection operation described with reference to Figure 16, and erase operations are performed on these multiple selected memory blocks BLK in parallel.

[0175] In step S106, one of the multiple selected memory blocks BLK is selected by the memory block selection operation described with reference to Figure 15, and an erase verification operation is performed on this selected memory block BLK.

[0176] In step S107, the result of the erase verification operation is determined for the selected memory block BLK on which the erase verification operation was performed. If it is determined that the erase operation was performed satisfactorily, the process proceeds to step S108. If it is determined that the erase operation was not performed satisfactorily, the process proceeds to step S109.

[0177] In step S108, status data indicating that the erase operation was completed successfully is stored in the status register STR (Figure 10). The status data is output to the controller die CD via a status read operation.

[0178] In step S109, status data indicating that the erase operation did not complete successfully is stored in the status register STR (Figure 10).

[0179] In step S110, it is determined whether or not an erase verification operation has been performed on all selected memory blocks BLK. If it has been performed, the process proceeds to step S111. If it has not been performed, the process returns to step S106.

[0180] In step S111, it is determined whether or not to terminate the multiple memory block erase operation. The determination of whether or not to terminate the multiple memory block erase operation can be adjusted as appropriate. For example, if it is determined that the erase operation has not been suitably performed for all selected memory blocks BLK, it is possible not to terminate the multiple memory block erase operation. Also, for example, if it is determined that the erase operation has been suitably performed for at least one selected memory block BLK, it is possible to terminate the multiple memory block erase operation. If the multiple memory block erase operation is not terminated, the process proceeds to step S112. If it is terminated, the process proceeds to step S114.

[0181] In step S112, the number of loop iterations is n. Ｅ the predetermined number of times N Ｅ Determine whether the condition has been met. If it has not been met, proceed to step S113. If it has been met, proceed to step S114.

[0182] In step S113, the number of loop iterations is n. Ｅ Add 1 to it and return to step S105. Also, in step S110, for example, the erase voltage V ＥＲＡ A predetermined voltage ΔV is added to it. Therefore, the elimination voltage V ＥＲＡ The number of loop iterations is n. Ｅ It increases along with the increase of [something].

[0183] In step S114, a recovery operation is performed. In the recovery operation, for example, a full reset operation is performed as described with reference to Figure 20, and all latch circuits CBL in the block decoder BLKD are reset. If the memory cell array MCA contains one or more bad blocks, a set operation as described with reference to Figure 17 is performed sequentially on one or more latch circuits CBL corresponding to these one or more bad blocks.

[0184] Figure 22 is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erase operation. Below, an example of performing a multiple memory block erase operation on two memory blocks BLK in the memory cell array MCA is shown.

[0185] As explained with reference to Figure 10, the memory die MD is equipped with eight data signal input / output terminals DQ0 to DQ7. In the following explanation, the 8-bit data input to these eight data signal input / output terminals DQ0 to DQ7 may be represented using two-digit hexadecimal numbers. For example, when "0,0,0,0,0,0,0,0,0" is input to the eight data signal input / output terminals DQ0 to DQ7, this data may be represented as data 00h, etc. Also, when "1,1,1,1,1,1,1,1" is input, this data may be represented as data FFh, etc.

[0186] Furthermore, the 8-bit data that makes up the data XXh, YYh, and ZZh described later can each be either "0" or "1". Also, the data from the 1st to the 4th bit and the data from the 5th to the 8th bit of the 8-bit data that make up the data XXh, YYh, and ZZh may be the same or different.

[0187] Figure 22 illustrates the command set CS11 input to the memory die MD during a multiple memory block erase operation. This command set includes data 60h, A101, A102...A1XX, XXh.

[0188] At timing t401, the controller die CD (Figure 1) inputs data 60h as command data Cmd to the memory die MD. Specifically, the voltages of the data signal input / output terminals DQ0 to DQ7 (Figure 10) are set to "H" or "L" according to each bit of data 60h, "H" is input to the external control terminal CLE (Figure 10), and with "L" input to the external control terminal ALE (Figure 10), the external control terminal / WE is raised from "L" to "H". Data 60h is a command input when executing a multiple memory block erase operation, and is the first data input in the command set CS11.

[0189] At timing t402, the controller die CD (Figure 1) inputs data A101 to the memory die MD as address data Add. Specifically, the voltages of the data signal input / output terminals DQ0 to DQ7 (Figure 10) are set to "H" or "L" according to each bit of data A101, "L" is input to the external control terminal CLE (Figure 10), and with "H" input to the external control terminal ALE (Figure 10), the external control terminal / WE is raised from "L" to "H". Data A101 includes a portion of the address data Add corresponding to the first selected memory block BLK.

[0190] Similarly, between timings t403 and t404, the controller die CD (Figure 1) inputs data A102 to A1XX as address data Add to the memory die MD. Each of the data A102 to A1XX contains a portion of the address data Add corresponding to the first selected memory block BLK.

[0191] At timing t405, the controller die CD (Figure 1) inputs data XXh to the memory die MD as command data Cmd. In this embodiment, data XXh is a command input when executing a multiple memory block erase operation, and is the last data input in the command set CS11.

[0192] At timing t406, the terminal RY / / BY changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. In addition, a full set operation and a reset operation corresponding to the first selected memory block BLK are performed on the memory die MD.

[0193] At timing t407, the reset operation corresponding to the first selected memory block BLK is completed. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0194] Figure 22 also illustrates the command set CS12 that is input to the memory die MD during a multiple memory block erase operation. This command set includes data 60h, A201, A202...A2XX, YYh.

[0195] At timing t411, the controller die CD (Figure 1) inputs data 60h as command data Cmd to the memory die MD.

[0196] At timing t412, the controller die CD (Figure 1) inputs data A201 to the memory die MD as address data Add. Data A201 includes a portion of the address data Add corresponding to the second selected memory block BLK.

[0197] Similarly, between timings t413 and t414, the controller die CD (Figure 1) inputs data A202 to data A2XX as address data Add to the memory die MD. Each of the data A202 to data A2XX contains a portion of the address data Add corresponding to the second selected memory block BLK.

[0198] At timing t415, the controller die CD (Figure 1) inputs data YYh to the memory die MD as command data Cmd. Data YYh is a command input when executing a multiple memory block erase operation, and is the last data input in the command set CS12.

[0199] At timing t416, the terminal RY / / BY changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. Also, on the memory die MD, a reset operation corresponding to the second selected memory block BLK and an erase operation for all selected memory blocks BLK are performed.

[0200] At timing t417, the erase operation is completed. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0201] Figure 22 also illustrates the command set CS13 that is input to the memory die MD during a multiple memory block erase operation. This command set includes data 60h, A101, A102...A1XX, and AFh.

[0202] At timing t421, the controller die CD (Figure 1) inputs data 60h as command data Cmd to the memory die MD.

[0203] At timing t422, the controller die CD (Figure 1) inputs data A101 as address data Add to the memory die MD.

[0204] Similarly, between timings t423 and t424, the controller die CD (Figure 1) inputs data A102 to data A1XX as address data Add to the memory die MD.

[0205] At timing t425, the controller die CD (Figure 1) inputs data AFh to the memory die MD as command data Cmd. Data AFh is a command input when executing the erase verify operation, and is the last data input in the command set CS13.

[0206] At timing t426, the terminal RY / / BY changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. Also, on the memory die MD, the erase and verify operation corresponding to the first selected memory block BLK is performed.

[0207] At timing t427, the erase operation is completed. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0208] At timing t428, the controller die CD (Figure 1) inputs data 7Xh as command data Cmd to the memory die MD. Data 7Xh is a command requesting the output of status data Stt, which is latched in the status register STR (Figure 10). After inputting data 7Xh, the controller die CD retrieves status data Stt from the memory die MD.

[0209] Next, although not shown in the diagram, the operation described with reference to timings t421 to t428 is also performed on the second selected memory block BLK.

[0210] Next, the controller die CD (Figure 1) determines whether or not to terminate the multiple memory block erasure operation (step S111 in Figure 21), and the loop count n. Ｅ the predetermined number of times N Ｅ A determination is made as to whether the condition has been reached (step S112 in Figure 21). If an erase operation is to be performed again, the operations corresponding to timings t411 to t428 are performed again.

[0211] At timing t431, the controller die CD (Figure 1) inputs data ZZh to the memory die MD as command data Cmd. Data ZZh is the command input at the end of the multiple memory block erase operation.

[0212] At timing t432, the terminal RY / / BY changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. Also, a recovery operation (step S114 in Figure 21) is performed on the memory die MD.

[0213] At timing t433, the recovery operation is completed. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0214] [Second Embodiment] Next, a semiconductor memory device according to the second embodiment will be described.

[0215] Figures 23 and 24 are schematic circuit diagrams showing the configuration of the row decoder RD2 according to the second embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0216] The semiconductor memory device according to the second embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, as shown in Figure 23, the semiconductor memory device according to the second embodiment includes a row decoder RD2 instead of a row decoder RD.

[0217] The raw decoder RD2 is basically configured the same way as the raw decoder RD. However, the raw decoder RD2 has a block decoder BLKD2 instead of a block decoder BLKD.

[0218] The block decoder BLKD2 is basically configured the same way as the block decoder BLKD. However, instead of multiple block decoder units blkd, the block decoder BLKD2 has multiple block decoder units blkd2.

[0219] The block decoder unit blkd2 is basically configured the same as the block decoder unit blkd. However, as shown in Figure 24, the block decoder unit blkd2 is equipped with a block address receiving circuit CAR2 and a selection information holding circuit CSL2 instead of the block address receiving circuit CAR and the selection information holding circuit CSL.

[0220] The block address receiving circuit CAR2 is basically configured the same as the block address receiving circuit CAR. However, in the block address receiving circuit CAR2, the gate electrode of transistor P11 is connected to the signal supply line RDECP instead of RDEC. Also, the gate electrode of transistor N16 is connected to the signal supply line RDECN instead of RDEC.

[0221] As shown in Figure 23, the signal supply lines RDECP and RDECN are connected in common to all block decoder units blkd2.

[0222] The selection information holding circuit CSL2 is basically configured the same as the selection information holding circuit CSL. However, the selection information holding circuit CSL2 includes an inverter circuit INV2 instead of transistor P12. The input terminal of the inverter circuit INV2 is connected to the signal supply line RDEC_SEL. The output terminal of the inverter circuit INV2 is connected to node n11.

[0223] Furthermore, when inverter circuit INV2 outputs "H", the ON current is smaller than the ON current of transistors N11, N12, N13, N14, N15, N16, and N18. Also, when inverter circuit INV2 outputs "H", the ON current is smaller than the ON current of transistors N11, N12, N13, N14, N15, N16, and N17.

[0224] The block decoder BLKD2 according to this embodiment is capable of performing the same operations as the block decoder BLKD. When the block decoder BLKD2 performs the same operations as the block decoder BLKD, the signal supply lines RDECP and RDECN are operated in the same way as the signal supply line RDEC.

[0225] Furthermore, the block decoder BLKD2 according to this embodiment is configured to perform multiple memory block selection operations.

[0226] Figure 25 is a schematic waveform diagram illustrating the multiple memory block selection operation. In the multiple memory block selection operation, from among the multiple memory block BLKs in the memory cell array MCA, multiple memory block BLKs corresponding to multiple block addresses input in multiple steps are selected as selected memory block BLKs, and the other memory block BLKs become unselected memory block BLKs. The following shows an example in which two memory block BLKs are selected.

[0227] Before the start of the multiple memory block selection operation, the signals on the signal supply lines RDECP, RDECN, ROMBAEN, SET, and RST are all in the "L" state.

[0228] At timing t501, the first block address is input to the block decoder BLKD2, and the signal on the address supply line AROW switches. Consequently, in the block address receiving circuit CAR2 (Figure 24) corresponding to the first selected memory block BLK, transistors N11, N12, N13, N14, and N15 all turn ON. On the other hand, in the other block address receiving circuits CAR2, at least one of transistors N11, N12, N13, N14, and N15 turns OFF.

[0229] At timing t502, the signals on the signal supply lines RDECP and RDECN rise to the "H" state. Consequently, transistor P11 (Figure 24) turns OFF and transistor N16 (Figure 24) turns ON.

[0230] As a result, in the block decoder unit blkd2 corresponding to the first selected memory block BLK, if transistor N18 (Figure 24) is ON, the voltage at node n11 is the ground voltage V ＳＳ It decreases to that point. Also, "H" is output from the signal supply lines RDEC_SEL and BLKSEL, and multiple word lines WL in the first selected memory block BLK become conductive with multiple voltage supply lines CG.

[0231] At timing t503, the signal on the signal supply line RDECN falls to the "L" state. Consequently, transistor N16 (Figure 24) turns OFF. As a result, in the block decoder unit blkd2 corresponding to the first selected memory block BLK, node n11 is set to the ground voltage V ＳＳ It is electrically disconnected from the voltage supply line that provides it.

[0232] Here, for example, if the block decoder unit blkd2 according to the second embodiment is equipped with a selection information holding circuit CSL instead of the selection information holding circuit CSL2, node n11 may become floating at timing t503, and the voltage of node n11 may fluctuate. Therefore, in this embodiment, the inverter circuit INV2 sets the voltage of node n11 to the ground voltage V ＳＳ It is fixed in place.

[0233] At timing t504, the second block address is input to the block decoder BLKD2, and the signal on the address supply line AROW is switched. Consequently, in the block address receiving circuit CAR2 (Figure 24) corresponding to the second selected memory block BLK, transistors N11, N12, N13, N14, and N15 all turn ON. On the other hand, in the other memory block BLK, at least one of transistors N11, N12, N13, N14, and N15 turns OFF.

[0234] At timing t505, the signal on the signal supply line RDECN rises to the "H" state. Consequently, transistor P11 (Figure 24) turns OFF and transistor N16 (Figure 24) turns ON.

[0235] As a result, in the block decoder unit blkd2 corresponding to the second selected memory block BLK, if transistor N18 (Figure 24) is ON, the voltage at node n11 is the ground voltage V ＳＳ It decreases to that point. Also, "H" is output from the signal supply lines RDEC_SEL and BLKSEL, and multiple word lines WL in the second selection memory block BLK become conductive with multiple voltage supply lines CG.

[0236] At timing t506, the signal on the signal supply line RDECN falls to the "L" state. Consequently, transistor N16 turns OFF. As a result, in the block decoder unit blkd2 corresponding to the second selected memory block BLK, node n11 is set to the ground voltage V ＳＳ It is electrically disconnected from the voltage supply line that provides it.

[0237] During the period from timing t505 to timing t507, multiple word lines WL in the two selected memory blocks BLK are connected to multiple voltage supply lines CG. Therefore, by performing the erase operation described with reference to Figure 8 in this state, for example, it is possible to perform an operation similar to the multiple memory block erase operation according to the first embodiment.

[0238] Furthermore, if three or more memory blocks (BLK) are selected, the operations corresponding to timings t504 to t506 are repeated.

[0239] At timing t507, the signal on the signal supply line RDECP falls to the "L" state. Consequently, transistor P11 (Figure 24) turns ON, and in the multiple block decoder units blkd2 corresponding to the multiple selection memory blocks BLK, node n11 turns to the operating voltage V ＤＤ It is charged to this level. Also, an "L" is output from the signal supply line RDEC_SEL, and the signal of the signal supply line BLKSEL connected to the corresponding level shifter LS also goes to the "L" state, electrically disconnecting multiple word lines WL in the two selection memory blocks BLK from multiple voltage supply lines CG.

[0240] Figure 26 is a flowchart illustrating the multiple memory block erasure operation according to the second embodiment.

[0241] The multiple memory block erasure operation according to the second embodiment is basically performed in the same manner as the multiple memory block erasure operation according to the first embodiment.

[0242] However, in the multiple memory block erasure operation according to the second embodiment, steps S101 to S103 in Figure 21 are not executed.

[0243] Furthermore, in the multiple memory block erasure operation according to the second embodiment, step S205 is executed instead of step S105. In step S205, multiple selected memory blocks BLK are selected by the multiple memory block selection operation described with reference to Figure 25, and erasure operations are performed in parallel on these multiple selected memory blocks BLK.

[0244] Furthermore, in the multiple memory block erasure operation according to the second embodiment, step S114 in Figure 21 is not executed.

[0245] Figure 27 is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erase operation. Below, an example of performing a multiple memory block erase operation on two memory blocks BLK in the memory cell array MCA is shown.

[0246] The multiple memory block erasure operation according to the second embodiment is basically performed in the same manner as the multiple memory block erasure operation according to the first embodiment.

[0247] However, at timing t406, instead of the full set operation and the reset operation corresponding to the first selected memory block BLK, the operations up to timing t503 of the multiple memory block selection operation, as explained with reference to Figure 25, are executed.

[0248] At timing t416, instead of the reset operation corresponding to the second selected memory block BLK, the operations up to timing t506 of the multiple memory block selection operation, as explained with reference to Figure 25, are executed.

[0249] Furthermore, the recovery operation corresponding to the timing t431 (Figure 22) of the first embodiment is not performed.

[0250] According to the semiconductor memory device of the second embodiment, multiple memory block erasure operations can be performed without operating the latch circuit CBL. Therefore, compared to the semiconductor memory device of the first embodiment, multiple memory block erasure operations can be performed at a higher speed.

[0251] [Third Embodiment] Next, a semiconductor memory device according to the third embodiment will be described.

[0252] Figure 28 is a schematic circuit diagram showing the configuration of a low decoder according to the third embodiment. In the following description, parts similar to those in the second embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0253] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the second embodiment. However, as shown in Figure 28, the block decoder unit blkd3 according to the third embodiment is equipped with a selection information holding circuit CSL3 instead of the selection information holding circuit CSL2.

[0254] The selection information holding circuit CSL3 is basically configured the same way as the selection information holding circuit CSL2. However, the selection information holding circuit CSL3 includes an inverter circuit INV3 instead of an inverter circuit INV2.

[0255] The inverter circuit INV3 includes transistors P12, N31, and N32. Transistors N31 and N32 are, for example, field-effect NMOS transistors.

[0256] The source electrode of transistor N31 is connected to the drain electrode of transistor N32. The drain electrode of transistor N31 is connected to node n11. The gate electrode of transistor N31 is connected to the signal supply line RDEC_SEL.

[0257] The source electrode of transistor N32 is connected to the ground voltage V. ＳＳ It is connected to the voltage supply line to which the voltage is supplied. The drain electrode of transistor N32 is connected to the source electrode of transistor N31, as described above. The gate electrode of transistor N32 is connected to the signal supply line RDECP.

[0258] [Fourth Embodiment] Next, a semiconductor memory device according to the fourth embodiment will be described.

[0259] Figure 29 is a schematic block diagram showing the configuration of the peripheral circuit PC4 according to the fourth embodiment. Parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0260] The semiconductor memory device according to the fourth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, as shown in Figure 29, the semiconductor memory device according to the fourth embodiment includes a peripheral circuit PC4 instead of a peripheral circuit PC.

[0261] Peripheral circuit PC4 is basically configured the same way as peripheral circuit PC. However, peripheral circuit PC4 has an address register ADR4 instead of address register ADR.

[0262] Address register ADR4 is basically configured the same way as address register ADR. However, address register ADR4 is configured to store more address data Add than address register ADR.

[0263] Figure 30 is a schematic waveform diagram illustrating an example of operation when performing a multiple memory block erase operation according to the fourth embodiment. Below, an example of performing a multiple memory block erase operation on two memory blocks BLK in the memory cell array MCA is shown.

[0264] Figure 30 illustrates the command set CS51 that is input to the memory die MD during a multiple memory block erase operation. This command set includes data XXh, A101, A102...A1XX, A201, A202...A2XX, and D0h.

[0265] At timing t501, the controller die CD (Figure 1) inputs data XXh to the memory die MD as command data Cmd. In this embodiment, data XXh is a command input when executing a multiple memory block erase operation, and is the first data input in the command set CS51.

[0266] At timing t502, the controller die CD (Figure 1) inputs data A101 as address data Add to the memory die MD.

[0267] Similarly, from timing t503 to timing t504, the controller die CD (Figure 1) inputs data A102 to data A1XX as address data Add to the memory die MD.

[0268] At timing t506, the controller die CD (Figure 1) inputs data A201 as address data Add to the memory die MD.

[0269] Similarly, between timings t507 and t508, the controller die CD (Figure 1) inputs data A202 to data A2XX as address data Add to the memory die MD.

[0270] At timing t509, the controller die CD (Figure 1) inputs data D0h to the memory die MD as command data Cmd. Data D0h is a command input when executing the multiple memory block erase operation according to this embodiment, and is the last data input in the command set CS51.

[0271] At timing t510, the terminal RY / / BY changes from the "H" state to the "L" state, and access to the memory die MD is prohibited. Also, on the memory die MD, the following operations are performed: full set operation, reset operation corresponding to the first and second selected memory block BLK, erase operation for all selected memory block BLK, multiple erase verify operations corresponding to the multiple selected memory block BLK, determination of whether or not to terminate the multiple memory block erase operation (step S111 in Figure 21), and loop count n. Ｅ the predetermined number of times N Ｅ A determination is made as to whether or not the condition has been reached (step S112 in Figure 21), and a recovery operation is performed.

[0272] At timing t511, the erase operation is completed. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0273] At timing t512, the controller die CD (Figure 1) inputs data 70h as command data Cmd to the memory die MD. Data 70h is a command requesting the output of status data Stt, which is latched in the status register STR (Figure 10). After inputting data 70h, the controller die CD retrieves status data Stt from the memory die MD.

[0274] In the semiconductor memory device according to the fourth embodiment, a single command set CS51 selects all memory blocks BLK that are the target of the multiple memory block erase operation. For this reason, the address register ADR4 according to the fourth embodiment is configured to store more address data Add than the address register ADR according to the first embodiment.

[0275] [Other Embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the above configurations are merely examples, and the specific configurations can be adjusted as appropriate.

[0276] For example, in the multiple memory block erasure operation according to the first embodiment, as described with reference to Figure 21, a full set operation is performed in step S101, and in steps S102 and S103, a reset operation is performed multiple times corresponding to the multiple memory block BLKs that are the target of the multiple memory block erasure operation.

[0277] However, it is also possible, for example, to perform a full reset operation instead of a full set operation in step S101, and to perform a set operation instead of a reset operation in steps S102 and S103.

[0278] Furthermore, the semiconductor memory device according to the fourth embodiment may be equipped with a row decoder RD2 according to the second embodiment (Figure 23) or a row decoder according to the third embodiment instead of the row decoder RD. Also, in the multiple memory block erase operation according to the fourth embodiment, an erase operation using the multiple memory block selection operation may be performed instead of a full set operation, a reset operation corresponding to the first and second selected memory blocks BLK, an erase operation using the full memory block selection operation, and a restore operation.

[0279] [Other] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0280] BL...bit line, BLK...memory block, CBL...latch circuit, CG...voltage supply line, MC...memory cell, P11, P12, N11, N12, N13, N14, N15, N16, N17, N18...transistors, SL...source line, WL...word line.

Claims

1. A plurality of memory blocks each having a memory cell and a word line connected to the memory cell; bit lines and source lines electrically connected in common to the plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line electrically connected in common to the plurality of word lines corresponding to the plurality of memory blocks; a plurality of first transistors provided corresponding to the plurality of memory blocks and electrically connected between the word line and the first voltage supply line; a plurality of first signal supply lines provided corresponding to the plurality of memory blocks and connected to the gate electrodes of the plurality of first transistors; a plurality of block decoder units provided corresponding to the plurality of memory blocks and capable of outputting a signal to any one of the plurality of first signal supply lines in response to the input of a signal corresponding to a block address; and a control circuit for controlling the plurality of block decoder units, wherein each of the plurality of block decoder units comprises: a plurality of second transistors electrically connected in series between a second voltage supply line and a third voltage supply line and to which a signal corresponding to the block address is input to the gate electrode; a third transistor electrically connected between the plurality of second transistors and the second voltage supply line; and a fourth transistor electrically connected between the plurality of second transistors and the third voltage supply line. A semiconductor memory device comprising a latch circuit connected to the gate electrode of the fourth transistor, wherein the control circuit is configured to perform a multiple memory block erase operation, which selects two or more memory blocks from the plurality of memory blocks as a plurality of selected memory blocks and performs an erase operation on these plurality of selected memory blocks in parallel, and in the multiple memory block erase operation, the data of a plurality of latch circuits corresponding to the plurality of selected memory blocks is rewritten before the erase operation is performed.

2. The semiconductor memory device according to claim 1, wherein, in the multiple memory block erase operation, the control circuit performs a full set operation to set the multiple latch circuits to a set state, and performs a reset operation to set one of the multiple latch circuits to a reset state multiple times before executing the erase operation.

3. The semiconductor memory device according to claim 1, wherein the control circuit performs a full reset operation in which the plurality of latch circuits are reset after the execution of the erase operation in the plurality of memory block erase operation.

4. The semiconductor memory device according to claim 1, wherein the control circuit selects all of the plurality of memory blocks when executing the erase operation during the plurality of memory block erase operation.

5. A semiconductor memory device according to claim 1, comprising: a plurality of inverter circuits provided in correspondence with a plurality of address signals corresponding to each bit in the block address, which output a plurality of inverted signals of the plurality of address signals; and a plurality of OR circuits provided in correspondence with the plurality of address signals and the plurality of inverted signals, which have one of the plurality of address signals and the plurality of inverted signals input to one input terminal, the other input terminal electrically connected to a second signal supply line, and which output a signal corresponding to the block address, wherein the control circuit, in the erase operation during the plurality of memory block erase operation, switches the signal of the second signal supply line, supplies an erase voltage to at least one of the bit line and the source line while the signal of the second signal supply line is switched, and supplies a voltage smaller than the erase voltage to the first voltage supply line.

6. A plurality of memory blocks each having a memory cell and a word line connected to the memory cell; bit lines and source lines electrically connected in common to the plurality of memory cells corresponding to the plurality of memory blocks; a first voltage supply line electrically connected in common to the plurality of word lines corresponding to the plurality of memory blocks; a plurality of first transistors provided corresponding to the plurality of memory blocks and electrically connected between the word line and the first voltage supply line; a plurality of first signal supply lines provided corresponding to the plurality of memory blocks and connected to the gate electrodes of the plurality of first transistors; a plurality of block decoder units provided corresponding to the plurality of memory blocks and capable of outputting a signal to any one of the plurality of first signal supply lines in response to the input of a signal corresponding to a block address; and a control circuit for controlling the plurality of block decoder units, wherein each of the plurality of block decoder units comprises: a plurality of second transistors electrically connected in series between a second voltage supply line and a third voltage supply line and to which a signal corresponding to the block address is input to the gate electrode; a third transistor electrically connected between the plurality of second transistors and the second voltage supply line; and a fourth transistor electrically connected between the plurality of second transistors and the third voltage supply line. A semiconductor memory device comprising a latch circuit connected to the gate electrode of the fourth transistor, and a fifth transistor electrically connected between the plurality of second transistors and the fourth transistor, wherein the signal input to the gate electrode of the third transistor and the signal input to the gate electrode of the fifth transistor are configured to be independently controllable.

7. The semiconductor memory device according to claim 6, wherein the control circuit is configured to perform a multiple memory block selection operation in which two or more memory blocks are selected from the plurality of memory blocks, and in the multiple memory block selection operation, at a first timing, a signal corresponding to the block address is supplied to the plurality of block decoder units; at a second timing, a signal is supplied to the gate electrode of the third transistor to turn the third transistor OFF and a signal is supplied to the gate electrode of the fifth transistor to turn the fifth transistor ON; at a third timing, a signal is supplied to the gate electrode of the fifth transistor to turn the fifth transistor OFF; at a fourth timing, another signal corresponding to the block address is supplied to the plurality of block decoder units; at a fifth timing, the signal is supplied to the gate electrode of the fifth transistor to turn the fifth transistor ON; and at a sixth timing, the signal is supplied to the gate electrode of the fifth transistor to turn the fifth transistor OFF.

8. The semiconductor memory device according to claim 7, wherein the control circuit is configured to perform a plurality of memory block erasure operation, which involves selecting two or more memory blocks from the plurality of memory blocks as a plurality of selected memory blocks and performing an erasure operation on these plurality of selected memory blocks in parallel, and in the plurality of memory block erasure operation, the plurality of memory block selection operation is performed, and after the fifth timing, with the signal that turns the third transistor OFF being input to the gate electrode of the third transistor, an erasure voltage is supplied to at least one of the bit line and the source line, and a voltage smaller than the erasure voltage is supplied to the first voltage supply line.

9. The semiconductor memory device according to claim 6, wherein each of the plurality of block decoder units further comprises: a first node electrically connected between the plurality of second transistors and the third transistor; a first inverter circuit whose input terminal is electrically connected to the first node; and a second inverter circuit whose input terminal is electrically connected to the output terminal of the first inverter circuit and whose output terminal is electrically connected to the first node.

10. The semiconductor memory device according to claim 6, wherein each of the plurality of block decoder units further comprises: a first node electrically connected between the plurality of second transistors and the third transistor; a first inverter circuit whose input terminal is electrically connected to the first node; a sixth transistor whose source electrode is electrically connected to the second voltage supply line, whose drain electrode is electrically connected to the first node, and whose gate electrode is connected to the output terminal of the first inverter circuit; a seventh transistor whose source electrode is electrically connected to the third voltage supply line, whose drain electrode is electrically connected to the first node, and whose gate electrode is connected to the output terminal of the first inverter circuit; and an eighth transistor electrically connected between the third voltage supply line and the seventh transistor, whose gate electrode is electrically connected to the gate electrode of the third transistor.

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