Metal-oxide-metal (MOM) capacitor for integrated circuit monitoring

Abstract

An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure can be used to evaluate misalignment between patterned layers of the IC structure. The array of MOM capacitors can be formed in a selected set of patterned layers, such as a via layer between a pair of metal interconnect layers. The MOM capacitors can be programmed with different patterned layer alignments (e.g., built into a photomask or reticle used to form the patterned layers) to define arrays of different alignments. When the MOM capacitors are formed on a wafer, the actual patterned layer alignments of the capacitors can differ from the programmed layer alignments due to process-related misalignments. The MOM capacitors can be subjected to electrical testing to identify the process-related misalignments, which can be used to initiate corrective actions, such as adjusting the manufacturing process or discarding misaligned IC structures or devices.

Description

[0001] Related patent applications

[0002] This application claims priority to jointly owned U.S. Provisional Patent Application No. 63 / 105,169, filed October 23, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to the manufacture of integrated circuits (ICs), and more specifically, to the use of metal-oxide-metal (MOM) capacitors to evaluate or monitor IC structures and processes, such as interconnect structures and processes. Background Technology

[0004] Integrated circuits (ICs) typically comprise various IC components (e.g., transistors, capacitors, resistors, etc.) that are interconnected with each other or connected to other electrical devices via metal wiring called “interconnects” (e.g., aluminum, copper, or cobalt interconnects). As IC devices continue to shrink, the level of interconnect metal layers increases, making interconnect quality a significant factor affecting the yield and reliability of the manufactured IC devices. Therefore, interconnect manufacturing has become particularly important in industry. However, existing systems and techniques for monitoring interconnect manufacturing processes (“interconnect processes”) have significant shortcomings. For example, existing means for monitoring via-to-metal misalignment, low k-values ​​in Cu interconnects, high-density plasma (HDP) voids between metal lines in Al interconnects, or metal corrosion (Al or Cu) are insufficient and ineffective to the extent they occur. Therefore, effective systems and methods are needed to monitor interconnect process quality, such as aluminum and copper interconnect formation.

[0005] Figures 1 to 3 Three conventional structures for monitoring interconnect manufacturing quality are shown. Figure 1 A top view of a conventional monitoring arrangement 100 is shown, comprising metal comb structures 102 and 104 arranged in an interleaved but separate manner. The monitoring arrangement 100 can be tested by measuring the conductance or resistance between the two comb structures 102 and 104. Detection of a reduced resistance (e.g., below a defined threshold resistance value) between the metal comb structures 102 and 104 can indicate a short circuit between them, which could be caused by inaccurate or defective processes, such as insufficient metal etching processes that leave longitudinal beams between metal wires, thus resulting in a short circuit. An exemplary short circuit is indicated at 106.

[0006] Other conventional monitoring setups are configured to monitor interconnect quality by detecting open circuits. For example, Figure 2A top view of a long serpentine metal structure 200 is shown for detecting openings in a metal wire, for example, by measuring the resistance through the serpentine metal structure 200. The detection of high resistance (e.g., above a defined threshold resistance value) can indicate an open circuit caused by a break in the serpentine metal structure 200, for example, as indicated at 202.

[0007] Figure 3 A side sectional view of a conventional monitoring arrangement 300 is shown, which includes interconnecting elements 302 formed in a plurality of metal lines 304a, 304b (two shown, but not limited thereto) and connected by vias 306 to define a chain structure 310. This structure can be used to detect the quality of the vias 306. For example, the resistance through the chain structure 310 can be measured and compared to an expected resistance, for example, based on the number of vias 306 in the chain structure 310. The detection of high resistance (e.g., above an upper threshold resistance value) may indicate an open via, while the detection of low resistance (e.g., below a lower threshold resistance value) may indicate a short circuit in the chain structure 310.

[0008] However, conventional monitoring structures and techniques are often too simple and insufficient for monitoring various parameters of interconnect process quality. For example, the conventional monitoring structures and techniques discussed above cannot effectively detect misalignments between different interconnect layers (e.g., metal layers and / or via layers), such as misalignments caused by optical misalignment of a particular interconnect layer relative to adjacent interconnect layers (i.e., photolithography variations or allowances). As another example, conventional monitoring structures cannot effectively detect damage to low-k dielectric materials, such as that caused by plasma etching or ashing processes. As yet another example, conventional monitoring structures cannot effectively detect voids in filled regions (e.g., dielectric regions between interconnect structures in IC devices), which can lead to yield losses and reliability failures. Improved structures and methods are needed for detecting or monitoring interconnect process quality. Summary of the Invention

[0009] Embodiments of the present invention provide structures and methods for forming and using metal-oxide-metal (MOM) capacitors to monitor integrated circuit structures and / or manufacturing processes (e.g., alignment of interconnect structures, presence of low-k process damage, and / or other interconnect quality parameters).

[0010] When forming multilayer IC devices, the programming (design) alignment (referred to herein as "programming layer alignment") between different patterned layers (e.g., interconnect layers) in the IC device may differ from the actual alignment (referred herein as "actual layer alignment") of the patterned layers formed on the wafer due to process variations, inaccuracies, defects, or other reasons. This difference between the programming layer alignment and the actual layer alignment on the wafer is referred to herein as "process-dependent layer misalignment". For example, process-dependent layer misalignment between a via layer and a metal layer (or multiple metal layers) can lead to via / metal misalignment in the IC device, which can negatively impact the performance of the IC device.

[0011] Therefore, some embodiments of this disclosure provide a method for detecting, analyzing, and correcting process-dependent layer misalignment in an IC device structure using one or more MOM capacitors. In some embodiments, an array of MOM capacitors formed in selected patterned layers can be used to detect and analyze process-dependent layer misalignment between selected patterned layers (e.g., to determine the direction and size of the misalignment). Each MOM capacitor in the array can be designed to have a different programming layer alignment between the selected patterned layers. For example, the array of MOM capacitors may include:

[0012] (a) A MOM capacitor having a programming layer alignment configured with a predefined target alignment, and

[0013] (b) Multiple MOM capacitors having various programmed layer alignment offsets with the target alignment (misalignment), for example, providing the size of the offset (misalignment) with via / metal misalignment and / or with the target alignment in different directions.

[0014] As used in this article, "target alignment" can refer to the alignment specified in the device design specification, such as via / metal alignment, where each via is precisely aligned with the overlying and underlying metal interconnect structures, for example... Figure 5A and Figures 6A to 6B As shown.

[0015] When an array of MOM capacitors is formed on a wafer, process-dependent layer misalignment can affect the array, causing the actual layer alignment of each MOM capacitor on the wafer to differ from its programming layer alignment. Due to process-dependent layer misalignment, the actual layer alignment of each MOM capacitor can be closer to or further away from the target alignment compared to its programming layer alignment. For example, for a particular MOM capacitor with a programming layer alignment offset from the target alignment in the +x direction, process-dependent layer misalignment in the -x direction can provide an actual layer alignment closer to the target alignment than the programming layer alignment of that particular MOM capacitor.

[0016] Each MOM capacitor in the array can be electrically tested to identify the MOM capacitor with the closest actual alignment to the target alignment. For example, a breakdown voltage can be determined for each MOM capacitor in the array, where the breakdown voltage increases as the actual layer alignment and the target alignment become aligned, and decreases as the actual layer alignment and the target alignment become further misaligned. Thus, the MOM capacitor with the highest breakdown voltage in the array can be identified, indicating the optimal alignment with the target alignment.

[0017] The programming layer alignment of the optimally aligned MOM capacitor can then be used to determine and implement corrective actions, such as (a) discarding IC structures or devices with misalignment or misalignment-related performance exceeding defined threshold limits, (b) adjusting at least one aspect of the manufacturing process to reduce process-related layer misalignment (e.g., adjusting the lithography process or process steps), or (c) any other type of corrective action.

[0018] In other implementations, MOM capacitors can be used to monitor damage present in low-k dielectric materials within IC devices. In advanced CMOS (Complementary Metal-Oxide-Semiconductor) technologies, low-k dielectric materials (e.g., as silicate glasses and their porous forms) are typically used to reduce RC delays associated with interconnect structures in devices (i.e., delays in signal speed through circuit wiring due to resistance and capacitance). Carbon and porosity are often introduced into low-k dielectric materials to reduce the dielectric constant. However, low-k dielectric materials can be subjected to plasma-induced damage during manufacturing processes, such as plasma etching, particularly during resist ashing. For example, low-k materials that are hydrophobic due to high concentrations of methyl groups become hydrophilic upon exposure to oxygen-containing plasma, where methyl groups (-CH3) are replaced by hydroxyl groups (-OH). As another example, low-k materials may crack due to mechanical stress (e.g., during chemical mechanical polishing (CMP) processes) or thermal stress. Damaged low-k materials can have significantly higher dielectric constant (k) values, which can be detrimental to circuit performance.

[0019] Therefore, some embodiments include forming a MOM capacitor with a low-k dielectric (e.g., organosilicon glass and its porous form) between elongated metal fingers (e.g., instead of oxides used in conventional MOM capacitors), which can be used, for example, to monitor the dielectric constant of the low-k material over time by measuring the breakdown voltage of the MOM capacitor over time.

[0020] Other embodiments provide a method for detecting voids in dielectric material regions formed between metal interconnect structures in an integrated circuit (IC) device. Multiple MOM capacitors can be formed, each MOM capacitor comprising metal fingers separated by dielectric regions. The capacitance of each MOM capacitor can be measured and compared with each other and / or with reference data, and the presence of dielectric region voids in each MOM capacitor (which may indicate the presence of dielectric region voids in other areas on the wafer) can be evaluated based on such comparisons.

[0021] Other embodiments provide methods for monitoring metal corrosion in IC structures. MOM capacitors can be formed with elongated metal finger structures, for example, made of aluminum or copper, and the capacitance and / or breakdown voltage of the MOM capacitor can be monitored over time. Changes in the measured electrical parameters over time can be determined, which can indicate the presence of metal corrosion based on the IC structure.

[0022] One aspect provides a method for evaluating an integrated circuit structure. The method includes forming a plurality of MOM capacitors in a plurality of patterned layers of the integrated circuit structure, each capacitor being configured to have different alignments between the patterned layers in at least one direction; performing electrical tests on the plurality of capacitors; and determining, based on the electrical tests, that patterned layers in the plurality of patterned layers are misaligned.

[0023] In one embodiment, forming multiple capacitors includes forming multiple MOM capacitors.

[0024] In one implementation, determining patterned layer misalignment includes determining process-related misalignment associated with forming multiple patterned layers.

[0025] In one implementation, determining patterned layer misalignment includes determining process-related misalignment in two orthogonal directions.

[0026] In one implementation, multiple capacitors are aligned with different programming layers in two orthogonal directions relative to the target alignment.

[0027] In one embodiment, the method further includes initiating a correction action in response to a determined patterning layer misalignment. For example, the correction action may include discarding an IC structure or device manufactured using a misalignment process. As another example, the process or process step for forming at least one patterned layer in the patterned layers may be adjusted based on the determined patterning layer misalignment.

[0028] In one embodiment, forming a plurality of capacitors in a plurality of patterned layers of an integrated circuit structure includes: (a) forming a first metal layer and a second metal layer, each of the first metal layer and the second metal layer including a comb-like component including a plurality of elongated metal fingers; and (b) forming a via layer between the first metal layer and the second metal layer, the via layer including at least one via connecting at least one elongated metal finger formed in the first metal layer to at least one elongated metal finger formed in the second metal layer.

[0029] In one embodiment, electrical testing of multiple capacitors includes determining the breakdown voltage of each capacitor and identifying the capacitor with the highest breakdown voltage among the multiple capacitors.

[0030] In one implementation, determining patterned layer misalignment based on electrical testing includes identifying the best alignment capacitor from a plurality of capacitors through electrical testing based on the plurality of capacitors, and determining patterned layer misalignment based on the identified best alignment capacitor.

[0031] In one embodiment, the step of forming a plurality of capacitors may include defining a different programming layer alignment for each of the plurality of capacitors relative to a target alignment, and forming a plurality of capacitors, each capacitor having an actual layer alignment different from the programming layer alignment of that capacitor due to process-related misalignment associated with forming the plurality of patterned layers. Furthermore, the step of determining patterned layer misalignment among the plurality of patterned layers based on electrical testing may include using electrical testing of the plurality of capacitors to identify the capacitor among the plurality of capacitors with the actual layer alignment closest to the target alignment, and determining at least one of the direction and magnitude of process-related misalignment based on the programming layer alignment of the identified capacitor with the actual layer alignment closest to the target alignment.

[0032] In one embodiment, the method further includes adjusting at least one patterned layer in the patterned layers used to form an integrated circuit manufacturing process based on at least one of the determined process-related misalignment orientation and size.

[0033] On the other hand, a method is provided for assessing damage to low-k dielectric materials in an integrated circuit (IC) structure. This method may include forming a MOM capacitor comprising a plurality of elongated metal fingers separated by a low-k dielectric material; performing electrical tests on the MOM capacitor; and determining the low-k damage condition based on the electrical tests.

[0034] In some implementations, the low-k dielectric material includes organosilicon glass and its porous form.

[0035] In one implementation, the method further includes initiating a correction action based on the determined low-k damage condition.

[0036] In one embodiment, performing electrical tests on a MOM capacitor includes measuring the breakdown voltage of the MOM capacitor and evaluating the measured breakdown voltage.

[0037] On the other hand, a method for detecting voids in dielectric regions of an integrated circuit (IC) structure is provided. This method may include forming a plurality of MOM capacitors, the plurality of MOM capacitors comprising metal structures separated by dielectric regions; measuring the capacitance of each of the plurality of MOM capacitors; analyzing the measured capacitance of the plurality of MOM capacitors; and identifying the presence of voids in the dielectric regions of at least one of the plurality of MOM capacitors based on the analyzed capacitance. In some embodiments, analyzing the measured capacitance of the plurality of MOM capacitors includes analyzing the distribution of the measured capacitance; comparing the capacitance distribution to a normal or Gaussian distribution; and identifying MOM capacitors with outlier capacitance values, which may indicate the presence of voids in the dielectric regions of the identified outlier MOM capacitors.

[0038] Another aspect provides a method for monitoring metal corrosion in an integrated circuit (IC) structure. The method may include forming a MOM capacitor comprising a metal structure; measuring at least one electrical parameter of the MOM capacitor over time; identifying changes in the at least one measured electrical parameter over time; and identifying metal corrosion in the IC structure based on the identified changes in the at least one measured electrical parameter over time. In some embodiments, the method may include monitoring the capacitance and breakdown voltage of the MOM capacitor over time, identifying changes in the capacitance and / or breakdown voltage (e.g., changes exceeding a threshold), and identifying metal corrosion in the IC structure based on the identified changes in the capacitance and / or breakdown voltage of the MOM capacitor.

[0039] In one embodiment, measuring the electrical parameters of the MOM capacitor over time includes measuring the capacitance of the MOM capacitor over time.

[0040] In one embodiment, forming a MOM capacitor includes forming a copper structure comprising elongated copper fingers spaced apart by dielectric regions; and depositing a dielectric barrier layer on the elongated copper fingers. The interface between the copper structure and the dielectric barrier layer can be critical to the reliability of the copper interconnect. For example, the quality of this interface can deteriorate due to residues from the copper CMP process, due to the formation of voids resulting from the deposition of the copper barrier layer (e.g., a Ta / TaN layer) and / or the copper seed layer, due to the formation of voids during the copper plating process, and / or due to the formation of hillocks during the deposition of the dielectric barrier layer. The quality of the copper / dielectric barrier layer interface can be monitored by monitoring the breakdown voltage of the capacitor.

[0041] Another aspect provides a MOM capacitor array configured for analyzing patterned layer misalignment between different patterned layers. The MOM capacitor array includes multiple MOM capacitor structures formed in multiple patterned layers of an integrated circuit structure. Each MOM capacitor structure includes (a) a first patterned layer including a first comb-shaped metal member having a plurality of first layer elongated fingers; (b) a second patterned layer including a second comb-shaped metal member having a plurality of second layer elongated fingers; and (c) a third patterned layer located between the first and second patterned layers and including a plurality of vias, each via connecting a distal end of the first layer elongated fingers to a distal end of the second layer elongated fingers. Each MOM capacitor structure in the MOM capacitor array may have different patterned layer alignments in at least one direction, wherein the patterned layer alignment of each MOM capacitor structure is defined by the relative alignment between the first, second, and third patterned layers. Attached Figure Description

[0042] Example aspects of this disclosure are described below with reference to the accompanying drawings, in which:

[0043] Figure 1 A top view of a conventional monitoring structure including an interlaced metal comb structure for detecting electrical short circuits that can indicate inaccuracies in the manufacturing process is shown.

[0044] Figure 2 A top view of a conventional monitoring structure including long serpentine metal wires is shown, which is used to monitor interconnect quality by detecting the presence of open circuits defined by fractures in the serpentine metal wires.

[0045] Figure 3 A cross-sectional view of a conventional monitoring arrangement is shown, which includes interconnecting elements formed in multiple metal lines and connected by through-holes to define a chain-like structure for evaluating the quality of manufactured through-holes;

[0046] Figure 4A and Figure 4B An example of a conventional MOM capacitor 400 is shown, particularly a conventional lateral flux MOM capacitor;

[0047] Figure 5A and Figure 5B Top view and three-dimensional cross-sectional view of a conventional MOM capacitor including slotted through-holes connecting metal fingers in adjacent metal layers;

[0048] Figure 6A and Figure 6B The diagram shows a top view and a three-dimensional cross-sectional view of a MOM capacitor for analyzing patterned layer alignment according to an exemplary embodiment, wherein via layers are formed with target alignment relative to adjacent metal layers;

[0049] Figure 7A and Figure 7B The illustration shows a top view and a three-dimensional cross-sectional view of a MOM capacitor for analyzing patterned layer alignment according to an exemplary embodiment, wherein the via layer is formed to be misaligned with the adjacent metal layer in the x-direction;

[0050] Figure 8A and Figure 8B The diagram shows a top view and a three-dimensional cross-sectional view of a MOM capacitor for analyzing patterned layer alignment according to an exemplary embodiment, wherein the via layer is formed to be misaligned with the adjacent metal layer in the y-direction;

[0051] Figure 9A and Figure 9B The diagram shows a top view and a three-dimensional cross-sectional view of a MOM capacitor for analyzing the alignment of patterned layers according to an exemplary embodiment, wherein the via layer is formed to be misaligned with the adjacent metal layer in both the x and y directions.

[0052] Figure 10 A three-dimensional cross-sectional view of a portion of an exemplary MOM capacitor according to an exemplary embodiment is shown. The MOM capacitor includes six metal layers and a single via layer formed between a selected pair of six metal layers for evaluating the alignment of the via layer with respect to the selected pair of metal layers.

[0053] Figure 11 A three-dimensional cross-sectional view of a portion of an exemplary MOM capacitor according to an exemplary embodiment is shown. The MOM capacitor includes six metal layers and corresponding via layers formed between each adjacent pair of six metal layers for evaluating the overall layer alignment of the patterned layers.

[0054] Figure 12 An exemplary two-dimensional 5×5 array of MOM capacitors formed in a set of common patterned layers is shown according to an exemplary embodiment for detecting and analyzing process-related layer misalignment associated with the patterned layers;

[0055] Figure 13 An exemplary method is shown, according to an exemplary embodiment, for determining process-related misalignments between patterned layers in an IC structure and taking corrective action;

[0056] Figure 14 A top view of an exemplary MOM capacitor for monitoring damage to low-k dielectric materials, according to an exemplary embodiment, is shown;

[0057] Figure 15 An exemplary method for monitoring damage to low-k dielectric materials in an IC structure and taking corrective action, according to an exemplary embodiment, is shown.

[0058] Figure 16 A top view of an exemplary MOM capacitor for monitoring the presence of voids in a dielectric gap filling material, according to an exemplary embodiment;

[0059] Figure 17 An exemplary method for monitoring dielectric material voids in an IC structure and taking corrective action is shown according to an exemplary embodiment;

[0060] Figure 18 A top view of an exemplary MOM capacitor for monitoring aluminum corrosion according to an exemplary embodiment is shown;

[0061] Figure 19 An exemplary method for monitoring aluminum corrosion in an IC structure and taking corrective actions according to an exemplary embodiment is shown;

[0062] Figure 20 A side sectional view of a portion of an exemplary MOM capacitor for monitoring copper corrosion, according to an exemplary embodiment, is shown; and

[0063] Figure 21 An exemplary method for monitoring copper corrosion in an IC structure and taking corrective action is shown according to an exemplary embodiment.

[0064] It should be understood that reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any illustrated element mentioned or discussed herein in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0065] Embodiments of the present invention provide structures and methods for forming and using metal-oxide-metal (MOM) lateral flux capacitors to monitor interconnect process quality (e.g., relative alignment of different interconnect layers, presence of low-k process defects, and / or other interconnect quality parameters). MOM capacitors are commonly used as low-cost capacitors in analog and mixed-signal circuits because they can be formed without additional process steps in the background IC manufacturing process, and are often referred to as “free” devices. This disclosure describes various modified versions of conventional MOM capacitors (referred to herein as “MOM capacitors”).

[0066] As discussed below, in some embodiments, an array of MOM capacitors may be formed in a patterned layer (e.g., an interconnect layer) within an integrated circuit (IC) structure and analyzed to identify misalignments between the patterned layers (e.g., caused by manufacturing process variations, inaccuracies, or defects). The patterned layer (e.g., an interconnect layer) in which the MOM capacitors are formed may include multiple metal layers and at least one via layer formed between adjacent metal layers. Each MOM capacitor may include a comb-like metal structure defining elongated metal fingers, each elongated metal finger being separated from adjacent elongated metal fingers by an oxide or other dielectric; and a via connecting the elongated metal fingers of two adjacent metal layers.

[0067] In some implementations, the array of MOM capacitors can be formed with different programming layer alignments, for example, defining different programmed via / metal alignments between vias formed in a via layer and metal fingers formed in an adjacent metal layer. After formation on the wafer, the actual via / metal alignment of the MOM capacitors may differ from the programmed via / metal alignment due to process-dependent layer misalignment. Each MOM capacitor in the array can be electrically tested to identify the MOM capacitor with the best actual via / metal alignment that is closest to the target alignment. For example, a breakdown voltage can be determined for each MOM capacitor, with the MOM capacitor having the highest breakdown voltage identified as the MOM capacitor with the best alignment. The programmed via / metal alignment of this best-aligned MOM capacitor can then be used to adjust the fabrication process of at least one patterned layer to reduce process-dependent layer misalignment or to take other corrective actions.

[0068] First, we discuss a pair of conventional MOM capacitors to provide a better understanding of the MOM capacitors disclosed in this paper. Figure 4A and Figure 4B An example of a first conventional MOM capacitor 400 is shown, particularly a lateral flux MOM capacitor. Figure 4A A top view of the MOM capacitor 400 is shown, and Figure 4B It shows the result of Figure 4A The dashed rectangle marked "4B" indicates a selected portion of the MOM capacitor 400 in a three-dimensional cross-sectional view. As shown, the MOM capacitor 400 includes capacitor elements 402 formed in a plurality of patterned layers 404, which in this example are six metal layers 406a-406f, which may be referred to as "metal 1" (layer 406a) to "metal 6" (layer 406f). In some IC devices, metal layers 406a-406f are interconnect layers that include patterned interconnect structures for connecting various semiconductor devices and the capacitor elements 402 of the MOM capacitor 400. For example, metal layers 406a-406f may be formed of aluminum or copper.

[0069] Figure 4AThe top view of the MOM capacitor shown illustrates the top metal layer 406f. Each metal layer 406a-406f may have a similar construction, such that each metal layer 406b-406f may have the same... Figure 4A The top metal layer 406f shown has a similar structure. Figure 4A As shown, metal layer 406a includes a pair of metal comb-like members 410 and 412, each having a plurality of elongated fingers 420 and 422, which are arranged in parallel in an interdigitated (staggered) manner and spaced apart from each other by a dielectric material 430 (e.g., oxide). Figure 4B As shown, the elongated fingers 420 and 422 in adjacent metal layers 406a-406f are also separated from each other by a dielectric material 430 (e.g., oxide). The operation of the MOM capacitor 400 is based on the coupling capacitance between the staggered parallel metal fingers 420 and 422. The width and spacing of the metal fingers 420 and 422 are typically defined by a minimum process dimension (e.g., 0.2 μm finger width and spacing in a 130 nm technology embodiment) to achieve maximum capacitance density.

[0070] In some designs, slotted vias are formed between metal fingers in adjacent metal layers to further increase capacitance density by increasing capacitive coupling between the fingers in adjacent metal layers.

[0071] For example, Figure 5A and Figure 5B It shows something similar to Figures 4A to 4B The example shown is of MOM capacitor 500, but also includes slotted through-holes between metal fingers in adjacent metal layers. Figure 5A and Figure 5B Top view and three-dimensional cross-sectional view of MOM capacitor 500 are shown respectively. As shown, MOM capacitor 500 includes capacitor elements 502 formed in a plurality of patterned layers 504. In this example, these patterned layers include (a) six metal layers 506a-506f and (b) five via layers 508a-508e, which are arranged in an alternating stacked arrangement between the metal layers 506a-506f. In some IC devices, metal layers 506a-506f and via layers 508a-508e are interconnect layers that include patterned interconnect structures for connecting various semiconductor devices and capacitor elements 502 of MOM capacitor 500. For example, metal layers 506a-506f may include patterned aluminum, copper, or other suitable metals. For example, via layers 508a-508e may include patterned tungsten, copper, or other suitable metals.

[0072] Similar to the MOM capacitor 400 discussed above, each metal layer 506a-506f of the MOM capacitor 500 includes a pair of metal comb-like members 510 and 512, each having a plurality of elongated fingers 520 and 522 arranged in parallel in an interdigitated (staggered) manner and spaced apart from each other by a dielectric material 530 (e.g., oxide). Unlike the MOM capacitor 400 (where the elongated fingers 420 and 422 of adjacent metal layers 406a-406f are separated by a dielectric material 430), the elongated fingers 520 and 522 of adjacent metal layers 506a-506f of the MOM capacitor 500 are electrically coupled to each other through elongated metal vias (or “slotted vias”) 540 formed in each of the via layers 508a-508e. For example, the slotted via 540 connecting the corresponding elongated fingers 520 and 522 of the adjacent metal layers 506a-506f can further increase the capacitance density of the MOM capacitor 500 compared to the MOM capacitor 400 formed without the slotted via 540.

[0073] Some embodiments of this disclosure relate to forming and using MOM capacitors, such as modified versions of the MOM capacitors 400 or 500 discussed above, for evaluating or monitoring the structural and / or process quality of patterned layers in an IC device structure, such as the relative alignment of different patterned layers (e.g., interconnect layers), the presence of low-k process defects in the patterned layers, and / or other quality parameters.

[0074] As discussed below, in some embodiments, MOM capacitors may form strategically positioned vias, such as vias located at the distal ends (“fingertips”) of elongated metal fingers of an interlaced comb-like component, to detect and analyze via / metal layer misalignment in both the x and y directions. MOM capacitors can be electrically tested to evaluate via / metal alignment. In some embodiments, an array of MOM capacitors may be programmed with different programmed layer alignments and formed on a common patterned layer on a wafer. The array of MOM capacitors can be electrically tested to evaluate the actual layer alignment of the MOM capacitors, which may differ from the programmed layer alignment due to process-related misalignment affecting the array of MOM capacitors. For example, based on the understanding that the breakdown voltage of an MOM capacitor decreases as via / metal misalignment increases in one or both of the x and y directions, a breakdown voltage can be determined for each MOM capacitor in the array, indicating the accuracy of the actual layer alignment (e.g., relative to the target alignment) in each MOM capacitor.

[0075] Compared to conventional MOM capacitors 400 or 500, strategically positioned vias, for example at the distal fingertip of an elongated metal finger, provide an improved ability to detect patterned misalignment (e.g., optical misalignment). Firstly, Figures 4A to 4B The conventional MOM capacitor 400 shown does not include vias. MOM breakdown voltage is typically controlled by the distance between adjacent metal fingers in each layer and / or by defects during the etching process (e.g., insufficient etching) or post-etch cleaning (e.g., leaving metal struts), rather than by photoalignment or misalignment. Secondly, Figures 5A to 5B The MOM capacitor 500 shown, which includes multiple slotted (elongated) vias 540, is also insufficient for evaluating patterned misalignment / optical misalignment. The slotted vias 540 are typically less controlled, and any slight increase in the via size along the via's elongation direction (e.g., due to roughening of the line edges) can significantly reduce the breakdown voltage. Therefore, the breakdown voltage of a conventional MOM capacitor 500 is typically very low and does not reflect patterned alignment or misalignment. In contrast, the breakdown voltage of the disclosed MOM capacitor structure (including strategically positioned vias, e.g., at the distal fingertip of a metallic finger) is significantly more sensitive to patterned alignment / misalignment.

[0076] Figures 6A to 6B arrive Figures 9A to 9B Four exemplary MOM capacitors 600a-600d formed on a wafer are shown, each with a different physical layer alignment (between the via layer and the adjacent metal layer) in both the x and y directions. See below for reference. Figure 12 The different actual layer alignments of the four exemplary MOM capacitors 600a-600d discussed can be generated by different programmed layer alignments of the MOM capacitors 600a-600d.

[0077] Figure 6A and Figure 6B An exemplary MOM capacitor 600a (specifically, a modified version of a conventional MOM lateral flux capacitor) according to an exemplary embodiment is shown, which can be used to analyze the relative alignment of patterned layers formed in an IC structure, for example, to monitor via / metal layer misalignment. Specifically, the MOM capacitor 600a (or a similar array of MOM capacitors with different layer alignments, as discussed below) can be used to detect patterned layer misalignment caused by inaccurate or defective manufacturing processes, enabling corrective actions to be initiated (e.g., discarding IC structures or devices with undesirable misalignment or misalignment-related properties, or adjusting the manufacturing process to reduce process-related misalignment). In some embodiments, the MOM capacitor 600a (or an array of similar MOM capacitors) may be formed in a scribe line, or as part of a wafer acceptability test (WAT) structure, or formed at any other suitable location on the wafer.

[0078] Figure 6A A top view of the MOM capacitor 600a is shown, and Figure 6B It shows the result of Figure 6A The dashed rectangle marked "6B" indicates a selected portion of the MOM capacitor 600a in a three-dimensional cross-sectional view. As shown, the MOM capacitor 600a includes capacitor elements 602 formed in a plurality of patterned layers 604. In this example, the plurality of patterned layers are a pair of adjacent metal layers 606a and 606b and a via layer 608 formed between the metal layers 606a and 606b. In some IC devices, the metal layers 606a and 606b and the via layer 608 are interconnect layers that include a patterned interconnect structure for connecting various semiconductor devices and the capacitor elements 602 of the MOM capacitor 600a. The metal layers 606a and 606b may include, for example, patterned aluminum, copper, or other suitable metals, and may be formed at any depth in the IC structure. For example, the via layer 608 may include patterned tungsten, copper, or other suitable metals.

[0079] Similar to the conventional MOM capacitors 400 and 500 discussed above, each metal layer 606a and 606b of the MOM capacitor 600a includes a pair of metal comb-like members 610 and 612. Each metal comb-like member 610 includes a plurality of elongated fingers 620 extending from a comb base 621, and each metal comb-like member 612 includes a plurality of elongated fingers 622 extending from a comb base 623. The elongated fingers 620 and 622 of the metal comb-like members 610 and 612 are arranged in parallel in an interdigitated (staggered) manner and spaced apart from each other by a dielectric material 630 (e.g., oxide). The via layer 608 includes vias 650a and 650b, wherein each via 650a is formed at the distal tip (“fingertip”) 624 of each elongated finger 622, and each via 650b is formed at the fingertip 626 of each elongated finger 620, such that each via 650a, 650b provides a conductive connection between the corresponding fingertip 624, 626 of the particular elongated finger 620, 622 formed in the metal layer 606b and the corresponding fingertip 624, 626 of the corresponding elongated finger 620, 622 formed in the underlying metal layer 606a.

[0080] The lateral alignment of vias 650a and 650b relative to other capacitor elements 602 (particularly the metal comb members 610 and 612 formed in metal layers 606a and 606b) can affect various electrical characteristics of the MOM capacitor 600a. For example, the lateral alignment of vias 650a and 650b in the x-direction affects the distance between each via 650a and 650b and the laterally adjacent (in the x-direction) metal fingers 620 and 622 in metal layers 606a and 606b, and the lateral alignment of vias 650a and 650b in the y-direction affects the distance (in the y-direction) between each via 650a and the comb base 621 and between each via 650b and the comb base 623.

[0081] The corresponding distances between vias 650a and 650b and adjacent capacitor element 602 affect the breakdown voltage (V) of MOM capacitor 600a. 击穿 Specifically, reducing the distance between vias 650a or 650b and adjacent capacitor elements 602 reduces the breakdown voltage of MOM capacitor 600a. Therefore, as discussed below, the alignment between vias 650a, 650b and the metal comb members 610 and 612, representing the alignment between via layer 608 and metal layers 606a and 606b, can be analyzed by measuring the breakdown voltage of MOM capacitors 600a. In some embodiments, as discussed below, the breakdown voltage can be measured and analyzed for multiple MOM capacitors 600a, each MOM capacitor having a different programmed alignment, to identify and correct misalignments between via layer 608, metal layer 606a, and / or metal layer 606b.

[0082] Figures 6A to 6B The vias 650a and 650b shown are precisely aligned with their respective fingertips 624 and 626 in both the x and y directions. Therefore, the actual layer alignment (ALA) of the via layer 608 matches the target alignment of the via layer 608. In this aligned arrangement, each via 650a is spaced apart from each adjacent elongated finger 620 in the x direction, and each via 650b is spaced apart from each adjacent elongated finger 622 by a distance D in the x direction. x =D x_对准 Furthermore, each through-hole 650a is spaced apart from the comb base 621 in the y-direction, and each through-hole 650b is spaced apart from the comb base 623 in the y-direction by a distance D. y =D y_对准 .

[0083] The misalignment of vias 650a and 650b in the x-direction reduces the distance D between each via 650a and 650b and certain laterally adjacent elongated fingers 620 or 622. x This typically reduces the breakdown voltage (V) of a 600A MOM capacitor. 击穿 Similarly, the misalignment of through holes 650a and 650b in the y-direction reduces the distance D between through hole 650a and comb base 621 or between through hole 650b and comb base 623. y This depends on the specific direction of the misalignment. (Discussed below) Figures 7A to 9B The figure shows an example of misalignment in the x and y directions.

[0084] Figure 7A and Figure 7B The top view and three-dimensional cross-sectional view of an exemplary MOM capacitor 600b are shown. This MOM capacitor is similar to Figures 6A to 6B The MOM capacitor 600a shown has a via layer 608, including vias 650a and 650b, which are misaligned with metal layers 606a and 606b in the x-direction. Therefore, vias 650a and 650b are misaligned with fingertips 624 and 626 in the x-direction, respectively. As shown, the actual layer alignment (ALA) of the via layer 608 is misaligned by 20 nm with the target via / metal alignment in the x-direction, but matches the target alignment in the y-direction. Consequently, the distance D between each via 650a, 650b and the adjacent metal finger 620 or 622 is... x Less than Figures 6A to 6B The alignment distance D shown x_对准 ,and Figures 6A to 6B Compared to the MOM capacitor 600a with aligned vias shown, this reduces the breakdown voltage (V) of the MOM capacitor 600b. 击穿 ).

[0085] Figure 8A and Figure 8B A top view and a three-dimensional cross-sectional view of an exemplary MOM capacitor 600c are shown, which is similar to Figures 6A to 6B The MOM capacitor 600a shown has a via layer 608, including vias 650a and 650b, which are misaligned with metal layers 606a and 606b in the y-direction. Therefore, vias 650a and 650b are misaligned with fingertips 624 and 626 in the y-direction, respectively. As shown, the actual layer alignment (ALA) of the via layer 608 is misaligned by +20 nm with the target via / metal alignment in the y-direction, but matches the target alignment in the x-direction. Consequently, the distance D between each via 650a and the comb base 621 is... y Less than Figures 6A to 6B The alignment distance D shown y_对准 ,and Figures 6A to 6B Compared to the MOM capacitor 600a with aligned through-holes shown, this reduces the breakdown voltage (V) of the MOM capacitor 600c. 击穿 ).

[0086] Figure 9A and Figure 9B The top view and three-dimensional cross-sectional view of an exemplary MOM capacitor 600d are shown. This MOM capacitor is similar to Figures 6A to 6B The MOM capacitor 600a shown has a via layer 608, including vias 650a and 650b, which are misaligned with metal layers 606a and 606b in both the x and y directions. As shown, the actual layer alignment (ALA) of the via layer 608 is misaligned with the target alignment by -20 nm in the x direction and by +20 nm in the y direction. As a result, (a) the distance D between each via 650a and the comb base 621.y Less than Figures 6A to 6B The alignment distance D shown y_对准 (b) The distance D between each through-hole 650a and the comb base 621 y Less than Figures 6A to 6B The alignment distance D shown y_对准 ,and Figures 6A to 6B Compared to the MOM capacitor 600a with aligned through-holes shown, this reduces the breakdown voltage (V) of the MOM capacitor 600d. 击穿 ).

[0087] although Figures 6A to 6B arrive Figures 9A to 9B The exemplary MOM capacitors 600a-600d shown include two metal layers 606a and 606b, wherein a single via layer 608 is formed between the two metal layers 606a and 606b. However, in other embodiments or instances, the MOM capacitor may include any other number of metal layers, wherein any number of via layers are formed between two or more metal layers.

[0088] For example, Figure 10 A three-dimensional cross-sectional view of a portion of an exemplary MOM capacitor 1000 is shown, which corresponds to Figure 6B , Figure 7B , Figure 8B and Figure 9B The diagram shows a three-dimensional cross-sectional view. The MOM capacitor 1000 and its components are similar to the MOM capacitors 600a-600d discussed above; however, the MOM capacitor 1000 is formed from a component consisting of seven patterned layers, including six metal layers 606a-606f and a single via layer 608. This via layer includes a via 650 formed between a selected pair of six metal layers 606a-606f (in this example, metal layers 606b and 606c). Therefore, the exemplary MOM capacitor 1000 can be used to analyze the relative alignment between the via layer 608 and the metal layers 606b and / or 606c. The single via layer 608 can be formed between any adjacent pairs of six metal layers 606a-606f to analyze the alignment of such a via layer 608 relative to a selected pair of metal layers.

[0089] As another example, Figure 11A three-dimensional cross-sectional view of a portion of an exemplary MOM capacitor 1100 is shown. The MOM capacitor 1100 and its components are similar to the MOM capacitor 1000 discussed above; however, the MOM capacitor 1100 is formed from components of 11 patterned layers, including five via layers 608a-608e formed alternately between six metal layers 606a-606f. The exemplary MOM capacitor 1100 can be used to detect the presence of patterned layer misalignment among the 11 patterned layers, which can initiate further analysis (e.g., microscopy or scanning cross-section) to detect the location and details of the patterned layer misalignment.

[0090] As discussed above, multiple MOM capacitors can be formed with different programming layer alignments (e.g., via / metal alignments) to analyze the actual layer alignment of different patterned layers formed on the wafer. Due to process variations, inaccuracies, or defects (e.g., lithography process variations, inaccuracies, or defects), the actual layer alignment may differ from the programming alignment of such patterned layers. For example, in some embodiments, an array of MOM capacitors can be formed on the wafer, with each MOM capacitor designed with a different programming layer alignment.

[0091] Figure 12 This illustrates MOM capacitors 6001-600 formed in a common patterned layer within an IC structure according to an exemplary embodiment. 25 An exemplary table 1200 of a two-dimensional 5×5 array of MOM capacitors is provided, which is used to detect and analyze process-related layer misalignment associated with patterned layers, such as due to process variations, inaccuracies, or defects. For example, MOM capacitors 6001-600. 25 Similar to Figures 6A to 6B arrive Figures 9A to 9B The MOM capacitors 600a-600d shown and discussed above. Therefore, in this example, the MOM capacitors 6001-600... 25 Via layers are formed in three vertically adjacent patterned layers, particularly via layers formed between two metal layers, such as via layer 608 formed between metal layers 606a and 606b. Figures 6A to 6B arrive Figures 9A to 9B As shown. MOM capacitor 6001-600 25 A common photomask or photomask can be formed in the same patterned layer. Therefore, any process-related misalignment between patterned layers will similarly affect all MOM capacitors 6001-600. 25 Alignment.

[0092] MOM capacitors 6001-600 25Different programming layer alignments can be designed, for example, defining programming alignments in the x and y directions between the via layer and at least one adjacent metal layer. Table 1200 indicates 25 MOM capacitors 6001-600. 25 Each of these has a programming layer alignment (PLA) in the x and y directions (in nm), indicating a programming misalignment of the via layer relative to the target alignment of the two metal layers. In this exemplary array, MOM capacitor 600 13 Programmed with target alignment (i.e., 0nm, 0nm via / metal misalignment), while MOM capacitor 6001-600 12 and 600 14 -600 25 The programmable layer can have various misalignments with the target. For example, the MOM capacitor 6009 has a +10nm programmed layer alignment (PLA), meaning that the via layer is designed to be misaligned by 10nm with two adjacent metal layers in the positive x-direction and by 10nm with two adjacent metal layers in the positive y-direction. MOM capacitor 6001-600 25 The programming layer alignment can be performed on photomasks, photomasks, or other materials used to form MOM capacitors 6001-600. 25 The patterned layer is programmed and encoded in other process devices.

[0093] As discussed above, when MOM capacitors 6001-600... 25 When the array is actually formed on the wafer, process-related layer misalignment between the via layer and the metal layer can affect the MOM capacitor 6001-600. 25 The array makes each MOM capacitor 6001-600 25 The actual layer alignment (ALA) differs from its programmed layer alignment (PLA). Therefore, each MOM capacitor 6001-600 25 The ALA is the net misalignment of the corresponding PLA and process-related layers. Table 1200 shows the net misalignment of each MOM capacitor 6001-600 produced by the manufacturing process. 25The actual layer alignment (ALA) includes process-dependent layer misalignment of -10nm and +10nm. For example, as shown in Table 1200, the MOM capacitor 6009 discussed above with a programming layer alignment (PLA) of +10nm and +10nm is formed on the wafer with an actual layer alignment (ALA) of 0nm and +20nm. This means that the vias of the formed MOM capacitor 6009 are aligned with the metal layer in the x-direction, but misaligned with the metal layer by 20nm in the positive y-direction. Therefore, compared with the programming layer alignment (+10nm, +10nm) of the MOM capacitor 6009, the process-dependent layer misalignment (-10nm, +10nm) causes the vias of the MOM capacitor 6009 to enter the target alignment (0nm misalignment) in the x-direction, but further away from the target alignment (20nm misalignment) in the x-direction.

[0094] Table 1200 also indicates that it has the following characteristics: Figure 6A To Figure 6D Figure 9A The four MOM capacitors of ALA are indicated by 9D. Specifically, the MOM capacitor is 600. 19 With Figures 6A to 6B The MOM capacitor 600a shown corresponds to the ALA; MOM capacitor 600 17 With Figures 7A to 7B The MOM capacitor 600b (-20nm, 0nm) shown corresponds to the ALA (-20nm, 0nm); the MOM capacitor 6009 has the same... Figures 8A to 8B The MOM capacitor 600c shown corresponds to ALA (0nm, +20nm); the MOM capacitor 6007 has the same... Figures 9A to 9B The MOM capacitor 600d shown corresponds to ALA (-20nm, +20nm).

[0095] To determine or approximate the effects on MOM capacitors 6001-600 25 The process involves misalignment of related layers, allowing for electrical testing of each MOM capacitor in the array. For example, as discussed above, this can be applied to each MOM capacitor 6001-600 in the array. 25 Determine the breakdown voltage, where the breakdown voltage increases as the ALA approaches target alignment and decreases as the ALA becomes further misaligned from the target alignment. Table 1200 indicates the breakdown voltage for each MOM capacitor 6001-600. 25 Exemplary breakdown voltage V measured 击穿 As shown in the figure, the MOM capacitor is 600. 19 It has the highest breakdown voltage (V 击穿 =50). Therefore, it can be deduced that the MOM capacitor is 600. 19 Align with the target as closely as possible.

[0096] In some implementations, corrective action can be initiated based on identified process-related layer misalignment. For example, the identified process-related layer misalignment or the resulting performance characteristics (e.g., breakdown voltage V) can be used as a basis. 击穿 The results can be compared with defined limits or otherwise analyzed, and based on the results, a determination can be made to discard IC structures or devices manufactured using processes associated with misalignment of process-related layers.

[0097] In other implementations, MOM capacitor 600 19 The programmed layer alignment (PLA) of a MOM capacitor (i.e., one with optimal ALA) can be used to adjust the manufacturing process to reduce process-related layer misalignment. In other words, due to the MOM capacitor 600... 19 The PLA is +10nm and -10nm, therefore the process-related misalignment can be inferred to be approximately -10nm and +10nm. This approximate process-related misalignment can then be used to evaluate and / or improve the manufacturing process, for example, by triggering additional process evaluations and / or adjusting one or more process steps to reduce the approximate process-related misalignment.

[0098] MOM capacitors 6001-600 25 The array can be formed as a physical two-dimensional array, or as a MOM capacitor 6001-600. 25 It can be arranged in any other physical arrangement, for example, as stripes arranged in a scribing pattern, or scattered over available areas within the scribing region, and then a two-dimensional array of data can be constructed during data analysis. Therefore, in the context of a two-dimensional array of MOM capacitors, the term "two-dimensional" or "2D" refers to two aligned or misaligned directions between the different patterned layers forming the MOM capacitor, specifically alignment / misalignment in the x and y directions. Additionally, while MOM capacitors 6001-600... 25 An exemplary array is a 5×5 array comprising 25 MOM capacitors, but an array of MOM capacitors for evaluating process-related layer alignment as disclosed herein may include any number of MOM capacitors.

[0099] A large array of MOM capacitors can be used to detect large process-related misalignments or to increase the resolution (granularity) of misalignment detection. The resolution of misalignment detection can be increased or decreased by changing the step size between adjacent MOM capacitors in the array. For example, Figure 12 The exemplary implementation shown uses a step size of 10 nm in both the x and y directions. The resolution of misalignment detection can be increased by reducing this step size to, for example, 5 nm, and vice versa.

[0100] Figure 13An exemplary method 1300 is shown according to an exemplary embodiment for determining process-related misalignments between patterned layers in an IC structure and taking corrective action. At 1302, an array of MOM capacitors can be designed, wherein the array includes a plurality of MOM capacitors having different programming layer alignments relative to a target alignment, such as those described above relative to... Figure 12 The discussion focuses on a 5×5 MOM capacitor array. At 1304, an IC structure can be fabricated, including the fabrication of a patterned layer comprising the MOM capacitor array. As discussed above, each MOM capacitor in the array can be formed with an actual layer alignment (ALA), which can differ from the programmed layer alignment (PLA) due to process-dependent layer misalignment.

[0101] At 1306, the breakdown voltage of each MOM capacitor can be measured. At 1308, the MOM capacitor with the highest breakdown voltage can be identified, which can represent the best-aligned MOM capacitor in the array, i.e., the MOM capacitor with the closest ALA to the target alignment. At 1310, process-related layer misalignment can be determined based on the PLA of the identified best-aligned MOM capacitor. In particular, process-related layer misalignment can be determined as a reversal of the PLA in both the x and y directions. At 1312, the manufacturing process of at least one of the patterned layers in which the MIM capacitors are formed can be adjusted to reduce process-related layer misalignment in the subsequently formed structure.

[0102] In other implementations, MOM capacitors can be used to monitor damage present in low-k dielectric materials within IC devices. In advanced CMOS (Complementary Metal-Oxide-Semiconductor) technologies, low-k dielectric materials (e.g., as silicate glasses and their porous forms) are typically used to reduce RC delays associated with interconnect structures in devices (i.e., delays in signal speed through circuit wiring due to resistance and capacitance). Carbon and porosity are often introduced into low-k dielectric materials to reduce the dielectric constant. However, low-k dielectric materials can undergo plasma-induced damage during manufacturing processes, such as plasma etching, particularly during resist ashing. For example, low-k materials that are hydrophobic due to high concentrations of methyl groups become hydrophilic upon exposure to oxygen-containing plasma, where methyl groups (-CH3) are replaced by hydroxyl groups (-OH). As another example, low-k materials may fracture due to mechanical stress (e.g., during CMP processes) or thermal stress. Damaged low-k materials may have significantly higher dielectric constant (k) values ​​or significantly reduced breakdown voltages, which can be detrimental to circuit performance.

[0103] Some embodiments of this disclosure provide MOM capacitors with a low-k dielectric material (instead of a typical oxide dielectric) between metal fingers, which can be used as process monitors to assess or detect changes in the dielectric constant (k) of the low-k dielectric material.

[0104] Figure 14 A top view of an exemplary MOM capacitor 1400 for monitoring damage to low-k dielectric materials, according to an exemplary embodiment, is shown. The MOM capacitor 1400 may comprise, for example, patterned aluminum, copper, or other suitable metal, and may be formed at any depth within an IC structure. Specifically, the MOM capacitor 1400 may include a pair of metal comb-like components 1410 and 1412. Each metal comb-like component 1410 includes a plurality of elongated fingers 1420 extending from a comb base 1421, and each metal comb-like component 1412 includes a plurality of elongated fingers 1422 extending from a comb base 1423. The elongated fingers 1420 and 1422 of the metal comb-like components 1410 and 1412 are arranged parallel in an interdigitated (staggered) manner and spaced apart from each other by a low-k dielectric material 1430 (e.g., silicate glass and its porous form).

[0105] A MOM capacitor 1400 comprising a low-k dielectric material 1430 can be tested to detect or assess damage to the low-k dielectric material 1430. Low-k dielectric materials are commonly used in integrated circuit interconnect structures to reduce RC delay and improve chip speed. Carbon and porosity are typically introduced into low-k dielectric materials to reduce the dielectric constant. Compared to typical silicon oxide, which has a dielectric constant of about 4, the dielectric constant of the low-k dielectric material OSG (organosilicate glass) is about 2.7, and its porous form (porous OSG) has a dielectric constant of about 2.4. Any damage to the low-k material will significantly increase its dielectric constant and will not achieve the original purpose of introducing the low-k material. For example, the capacitance value of the MOM capacitor 1400 can be measured and compared with reference data to detect or assess damage to the low-k dielectric material 1430. For example, an increase in capacitance value may indicate damage to the low-k dielectric material 1430.

[0106] Figure 15An exemplary method 1500 for monitoring damage to low-k dielectric material in an IC structure and taking corrective action is illustrated according to an exemplary embodiment. At 1502, a MOM capacitor is formed, wherein a low-k dielectric material (e.g., silicate glass and its porous form) is used as a filler material between metal components (e.g., metal fingers), as discussed above. At 1504, the capacitance value of the MOM capacitor can be measured. At 1506, the capacitance value can be evaluated, for example, compared with one or more thresholds. For example, determining that the capacitance value is above a certain threshold may indicate a significant increase in the dielectric constant value of the low-k dielectric material. At 1508, corrective action can be taken, such as discarding a device with damaged low-k dielectric material, or adjusting the manufacturing process to reduce damage to low-k dielectric material in subsequently formed devices.

[0107] In other implementations, MOM capacitors can be used to monitor voids in the gap-fill material formed in an IC device. For IC devices using aluminum interconnects, dielectric materials (e.g., oxides or fluorosilicate glass (FSG)) are typically used to fill the spaces between metal lines in the same metal layer and / or between adjacent metal layers. Such dielectric materials are typically deposited using a high-density plasma (HDP) oxide deposition process, where an HDP chemical vapor deposition (CVD) process with multi-step deposition / etching / deposition gap filling is used to fill the gaps between metal lines. In some cases, the deposition process may not completely fill the gaps between metal lines, leaving voids, which can lead to yield losses and reliability failures.

[0108] Figure 16 This image shows a side sectional view of a portion of an exemplary MOM capacitor 1600 for monitoring voids in a dielectric gap-filling material, according to an exemplary embodiment. Specifically, Figure 16 A cross-sectional view of two elongated fingers 1602 and 1604 of a MOM capacitor 1600 is shown, wherein dielectric material 1606 is deposited, for example, using an HDP deposition process as described above, in the gap between the metal fingers 1602 and 1604. As shown, a void 1610 may be formed in the dielectric filling material 1606, for example, as caused by the HDP deposition process.

[0109] The presence of voids (e.g., excessive voids) in the dielectric filling material can reduce the capacitance of the MOM capacitor. Therefore, in some embodiments, the capacitance of the MOM capacitor 1600 over time can be monitored to electrically detect the presence of voids. Furthermore, since the presence of voids is typically intermittent, varying from one site to another or from one wafer to another, multiple MOM capacitors 1600 formed at different sites on a wafer or on different wafers can be tested and compared with each other and / or with reference data (e.g., reference data defining an established distribution) to detect the presence of voids at a specific wafer site or on a specific wafer.

[0110] Figure 17 An exemplary method 1700 is shown according to an exemplary embodiment for monitoring voids in dielectric gap-filling material in an IC structure and taking corrective actions. At 1702, a plurality of MOM capacitors are formed, each MOM capacitor including metal parts (e.g., fingers) spaced apart by dielectric regions. At 1704, the capacitance of each MOM capacitor is measured. At 1706, the distribution of the measured capacitance is analyzed and compared with a normal or Gaussian distribution to identify MOM capacitors with outlier capacitance values, which may indicate the presence of dielectric region voids in the identified outlier MOM capacitors. At 1708, corrective actions may be taken, such as discarding the device or structure including the outlier MOM capacitors, or adjusting the manufacturing process to reduce the formation of voids in the dielectric material.

[0111] In other implementations, MOM capacitors can be used to monitor aluminum corrosion in IC devices. Under certain stress conditions (e.g., moisture in the environment or voltage or current in metal wires), corrosion in aluminum will be accelerated, and MOM capacitors can serve as an early warning structure for corrosion detection.

[0112] Figure 18 This image shows a side cross-sectional view of a portion of an exemplary MOM capacitor 1800 for monitoring aluminum corrosion according to an exemplary embodiment. Specifically, Figure 18A cross-sectional view of elongated fingers 1802 and 1804 formed from free aluminum in a MOM capacitor 1800 is shown, wherein dielectric material 1806 is deposited in the gaps between the elongated fingers 1802 and 1804, for example, using an HDP deposition process as described above. As shown, voids 1810 may form in the dielectric filling material 1806, for example, due to a defective HDP deposition process. As described above, under certain stress conditions (e.g., moisture in the environment, or voltage or current through the aluminum fingers 1802 and / or 1804), the elongated fingers 1802 and / or 1804 may undergo micro-corrosion growth into the voids 1810, as shown at 1812. In some embodiments, the capacitance and breakdown voltage of the MOM capacitor 1800 over time can be monitored to detect such aluminum corrosion in the MOM capacitor 1800.

[0113] Figure 19 An exemplary method 1900 for monitoring aluminum corrosion in an IC structure and taking corrective actions according to an exemplary embodiment is shown. At 1902, a MOM capacitor is formed, including aluminum components (e.g., fingers) spaced apart by dielectric regions. At 1904, the capacitance and breakdown voltage of the MOM capacitor are measured over time. At 1906, changes in capacitance and / or breakdown voltage over time (e.g., changes exceeding a threshold) are detected, and aluminum corrosion in the IC structure is identified based on the identified changes in the capacitance and / or breakdown voltage of the MOM capacitor. At 1908, corrective actions can be taken, such as discarding devices or structures containing aluminum corrosion, or adjusting the process to reduce the development of aluminum corrosion.

[0114] In other implementations, MOM capacitors can be used to monitor the reliability of copper interconnects in IC devices. In copper interconnects, the interface between the copper and the dielectric barrier layer (e.g., SiC or SiN) deposited after copper CMP can be critical, as most reliability failures may originate from this interface. For example, voids or residues in the interface can lead to open circuits or electrical short circuits under certain stress conditions. In some implementations, MOM capacitance under stress (in-row or at the end of a row) can be measured to monitor the copper / dielectric barrier layer interface. In one implementation, a large number of MOM capacitors can be formed and tested to generate statistics for reliability assessment.

[0115] Figure 20 This image shows a side sectional view of a portion of an exemplary MOM capacitor 2000 for monitoring the quality or reliability of a copper interconnect by monitoring the interface between the copper structure and the dielectric barrier layer, according to an exemplary embodiment. Specifically, Figure 20A cross-sectional view of elongated copper fingers 2002 and 2004 of a MOM capacitor 2000 is shown, with dielectric material 2006 in the space between the elongated copper fingers 2002 and 2004. Following a copper CMP process, a dielectric barrier layer 2008 (e.g., SiC or SiN) is deposited on the elongated copper fingers 2002 and 2004. Potential residual sites are indicated by arrow 2012, which may originate from undesired connections (metallic short circuits) between the two copper fingers 2002 and 2004 under current stress. In some embodiments, the breakdown voltage of the MOM capacitor 2000 or an array of MOM capacitors 2000 can be monitored to evaluate the copper / dielectric barrier layer interface.

[0116] Figure 21 An exemplary method 2100 for monitoring copper interconnect reliability in an IC structure and taking corrective actions, according to an exemplary embodiment, is shown. At 2102, a MOM capacitor is formed, including a dielectric barrier layer (e.g., SiC or SiN) deposited on a copper component (e.g., fingers) to define a copper / dielectric barrier layer interface. At 2104, the breakdown voltage of the MOM capacitor is measured over time. At 2106, a change in the breakdown voltage over time (e.g., a change exceeding a threshold) is detected, and a copper interconnect reliability problem is identified based on the identified breakdown voltage change. At 2108, corrective actions can be taken, such as discarding devices or structures that include copper reliability problems, or adjusting processes to address the reliability problem.

Claims

1. A method for evaluating integrated circuit structure, the method comprising: A plurality of MOM capacitors are formed in a plurality of patterned layers of the integrated circuit structure, wherein each of the plurality of MOM capacitors is configured to have different alignments between the patterned layers in at least one direction; Perform electrical tests on the plurality of MOM capacitors; as well as Based on the electrical test, it was determined that one of the patterned layers was misaligned. The electrical tests performed on the plurality of MOM capacitors include: Determine the breakdown voltage of each MOM capacitor; as well as Identify the MOM capacitor with the highest breakdown voltage among the plurality of MOM capacitors.

2. The method of claim 1, wherein determining the patterned layer misalignment includes determining a process-related misalignment associated with forming the plurality of patterned layers.

3. The method of claim 2, wherein determining the patterned layer misalignment includes determining process-related misalignment in two orthogonal directions.

4. The method of claim 1, wherein the plurality of MOM capacitors are formed with different programming layer alignments in two orthogonal directions relative to the target alignment.

5. The method of claim 1, further comprising initiating a correction action in response to the determined misalignment of the patterned layer.

6. The method of claim 5, wherein the correction action includes a process of adjusting at least one of the patterned layers based on the determined patterned layer misalignment.

7. The method of claim 1, wherein forming the plurality of MOM capacitors in the plurality of patterned layers of the integrated circuit structure comprises: A first metal layer and a second metal layer are formed, each of the first metal layer and the second metal layer including a comb-like component, the comb-like component including a plurality of elongated fingers; as well as A via layer is formed between the first metal layer and the second metal layer, the via layer including at least one via connecting at least one elongated finger formed in the first metal layer to at least one elongated finger formed in the second metal layer.

8. The method of claim 1, wherein determining the misalignment of the patterned layer based on the electrical test comprises: The best-aligned MOM capacitor is identified from the plurality of MOM capacitors based on the electrical tests performed on the plurality of MOM capacitors. as well as The misalignment of the patterned layer is determined based on the best-aligned MOM capacitor identified.

9. The method according to claim 1, wherein: The plurality of MOM capacitors include: For each of the plurality of MOM capacitors, a different programming layer alignment is defined relative to the target alignment; and The plurality of MOM capacitors are formed, each of the formed MOM capacitors having actual layer alignment; and Determining that a patterned layer among the plurality of patterned layers is misaligned based on the electrical test includes: Based on the electrical tests of the plurality of MOM capacitors, identify the MOM capacitor among the plurality of MOM capacitors that has the closest actual layer alignment to the target alignment; and The programmed layer alignment of the MOM capacitor with the actual layer alignment that is closest to the target alignment is used to determine at least one of the process-related misalignment direction and size.

10. A method for assessing damage to low-k dielectric materials in an integrated circuit structure, the method comprising: A MOM capacitor is formed, the MOM capacitor comprising a plurality of elongated fingers separated by a low-k dielectric material; Perform electrical tests on the MOM capacitor; as well as The condition of the low-k dielectric material is evaluated based on the aforementioned electrical tests. The electrical test performed on the MOM capacitor includes measuring the breakdown voltage of the MOM capacitor and evaluating the measured breakdown voltage.

11. The method of claim 10, wherein the low-k dielectric material comprises organosilicon glass.

12. The method of claim 10, further comprising initiating a correction action based on the determined low-k damage condition.

13. A method for monitoring metal corrosion in an integrated circuit structure, the method comprising: Forming MOM capacitors that include metallic structures; Measure the electrical parameters of the MOM capacitor over time; Identify the changes in the measured electrical parameters over time; as well as Metal corrosion in the integrated circuit structure is identified based on the changes in the measured electrical parameters over time. The measurement of the electrical parameters of the MOM capacitor over time includes measuring the capacitance and breakdown voltage of the MOM capacitor over time.

14. The method of claim 13, wherein forming the MOM capacitor comprises: A copper structure is formed, comprising elongated copper fingers spaced apart by dielectric regions; as well as A dielectric barrier layer is deposited on the elongated copper fingers.

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