A detection circuit for maintaining time margin

Abstract

The embodiment of the present application discloses a detection circuit for holding time margin, which relates to the field of circuit technology and improves the problem of poor detection accuracy of holding time margin in the chip in the prior art. The specific scheme is: the detection circuit includes: a generator and a decision circuit; the generator includes at least one group of test circuits, each group of test circuits includes N first registers, N second registers, and N data delay units, the delays of the N data delay units increase in sequence, and the delay difference between two adjacent data delay units is less than or equal to a preset value; wherein the data output ends of the N first registers are respectively connected to the input ends of the N data delay units, the output ends of the N data delay units are respectively connected to the data input ends of the N second registers, and the data output ends of the N second registers are connected to the decision circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of circuit technology, and in particular to a detection circuit for maintaining a time margin. Background Art

[0002] Timing design and analysis is one of the important links in chip design. In the design of large-scale system on chip (SOC), static timing analysis (STA) method is usually used to ensure the timeliness of the design iteration cycle. STA is an analysis method that covers boundary conditions. For example, it can cover boundary conditions pessimistically to simulate the performance changes of different tubes inside the chip due to process deviation, voltage drop, and temperature change. However, if the boundary conditions are set too strictly, it will greatly increase the difficulty of design, and occupy too many resources in the die, making the product competitiveness decline. If the boundary conditions are set too loosely, quality problems may occur, resulting in a series of indicator problems in the chip or even failure to work.

[0003] Figure 1 For an existing intellectual property (IP) design (patent number: US7930663B2), such as Figure 1 As shown, the data output terminal Q0 of the register (flip flop, FF0) is connected to the data input terminal D of the register FF1, and the data output terminal Q1 of the register FF1 is connected to the data input terminal D of the register FF2. A delay line delay0 (delay line) is formed by using a standard cell (stdcell) between the clock terminal of the register FF0 and the clock terminal Clk1 of the register FF1, and a delay line delay0 is formed by using stdcell between the clock terminal Clk1 of the register FF1 and the clock terminal Clk2 of the register FF2. The initial state of the circuit is configured to be a hold success state. By adjusting the signal configuration of the delay selection modules delaySel1 and delaySe2, different delay delay values ​​are selected until the circuit has a hold failure state. The peripheral circuit detects the hold success state and the hold failure state of the timing of the circuit to be tested, and then reads the detection result through the bus to obtain the hold time margin, thereby providing a basis for the upgrade of the next generation of chips.

[0004] In this IP design, the delay line composed of standard cells (stdcell) has poor accuracy in detecting hold time. However, in 28nm and below processes, depending on the scale of the SOC, the number of timing violations caused by 1 ps uncertainty may be hundreds of thousands or even millions. Therefore, if the lack of accuracy is applied in actual projects, it means that there will be a great risk of timing violations, so this solution has no obvious practical engineering significance. Summary of the invention

[0005] The embodiment of the present application provides a detection circuit for a hold time margin, which can improve the detection accuracy of the hold time margin.

[0006] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0007] In a first aspect of an embodiment of the present application, a detection circuit for holding time margin is provided, the detection circuit comprising: a controller, a generator and a decision circuit; the generator comprises at least one group of test circuits, each group of test circuits comprises N first registers, N second registers, and N data delay units, the delays of the N data delay units are successively increased, the delay difference between two adjacent data delay units is less than or equal to a preset value, and N is an integer greater than 1; wherein the clock end of the controller and the N first registers and the clock end of the N second registers are connected to the same clock output end of the controller, the data output ends of the N first registers are respectively connected to the input ends of the N data delay units, the output ends of the N data delay units are respectively connected to the data input ends of the N second registers, and the data output ends of the N second registers are connected to the decision circuit; the decision circuit is used to detect the output states of the N second registers and transmit the output states of the N second registers to the controller. Based on this scheme, by setting N data delay units between the N first registers and the N second registers, and the delays of the N data delay units are successively increased, the delays of the data paths of the N groups of registers are different. When the delay of the data path from the first register to the second register is greater than the delay of the clock path, the output state of the second register is a hold success state; when the delay of the data path from the first register to the second register is less than the delay of the clock path, the output state of the second register is a hold failure state. Therefore, by setting N data delay units with increasing delays between the N first registers and the N second registers, the delays of the data paths from the N first registers to the N second registers are different from each other, so the output states of some of the second registers in the N registers are a hold failure state, and the output states of the other registers are a hold success state. According to the second register from hold failure to hold success, the hold time margin can be detected, and the step accuracy of the delay increment of the N data delay units in the present application is less than the preset value. Therefore, based on the hold failure state and the hold success state of the second register, the hold time margin obtained by the detection has a high accuracy. Based on the detection result, a strong basis can be provided for the design of the next generation chip, making the product competitiveness of the next generation chip stronger. It can be understood that a first register and a second register connected to the register through a data delay unit can be called a group of registers.

[0008] In combination with the first aspect, in a possible implementation, the N data delay units respectively include N S-shaped metal windings, and the lengths of the N S-shaped metal windings are increased in sequence. Based on this solution, the lengths of the N S-shaped metal windings are increased in sequence, so that the delay of the data path of the N groups of registers is increased in sequence, and the detection accuracy of the hold time margin can be controlled by designing the length difference between two adjacent S-shaped metal windings, so that the accuracy of the detected hold time margin is high.

[0009] In combination with the first aspect and the above-mentioned possible implementation, in another possible implementation, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings is the same. Based on this solution, by setting the length difference between two adjacent S-shaped metal windings, the detection accuracy of the hold time margin can be controlled, so that the accuracy of the detected hold time margin is higher. It can be understood that due to the nonlinear characteristics of metal, when the lengths of the N S-shaped metal windings increase successively, and the two adjacent S-shaped windings increase by the same length, the delays of the N data delay units increase successively, but the delay difference (step accuracy) of the two adjacent data delay units is not exactly the same.

[0010] In combination with the first aspect and the above-mentioned possible implementations, in another possible implementation, the S-shaped metal winding includes a first turning portion, a second turning portion, and one or more splicable portions, and different S-shaped metal windings include different numbers of splicable portions. Based on this solution, by designing the S-shaped metal winding into a splicable module, S-shaped metal windings of different lengths can be achieved by increasing the number of splicable portions. This method has good controllability, can freely realize splicing according to different design scales and different required delay values, and is convenient for secondary inspection, and has good practical engineering significance.

[0011] In combination with the first aspect and the above possible implementations, in another possible implementation, the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding; or the second turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding. Based on this solution, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding can be arranged on the same side.

[0012] In combination with the first aspect and the above possible implementations, in another possible implementation, the first turning portion includes an input end of the S-shaped metal winding, and the second turning portion includes an output end of the S-shaped metal winding; or the first turning portion includes an output end of the S-shaped metal winding, and the second turning portion includes an input end of the S-shaped metal winding. Based on this solution, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding can be set on different sides.

[0013] In combination with the first aspect and the above possible implementations, in another possible implementation, the detection circuit further includes a clock selector and a clock delay circuit, the controller is connected to the input end of the clock selector, the data selection end of the clock selector, and the clock ends of the N first registers, the output end of the clock selector is connected to the input end of the clock delay circuit, and the output end of the clock delay circuit is connected to the clock ends of the N second registers. Based on this solution, a large range of adjustments can be performed by selecting the clock selection module through the clock selector, so that the output states of the N second registers have both a hold fail state and a hold pass state.

[0014] In combination with the first aspect and the above possible implementations, in another possible implementation, the clock delay circuit includes M clock delay units, and the M clock delay units each have M different delays. Based on this solution, the delay on the clock path can be adjusted by using the clock delay units with M different delays.

[0015] In combination with the first aspect and the above possible implementations, in another possible implementation, the controller is specifically used to control the clock selector to select each of the M clock delay units in turn in time-sharing. Based on this solution, by selecting different clock delay units in time-sharing by the controller, a large range of adjustments can be performed, so that the output states of the N second registers have both a hold fail state and a hold pass state.

[0016] In combination with the first aspect and the above possible implementations, in another possible implementation, the controller is specifically used to: control the clock selector to select the first clock delay unit among the M clock delay units; if the output states of the N second registers are all hold success, the controller controls the clock selector to select the second clock delay unit among the M clock delay units, and the delay of the second clock delay unit is greater than the delay of the first clock delay unit; if the output states of the N second registers are all hold failures, the controller controls the clock selector to select the third clock delay unit among the M clock delay units, and the delay of the third clock delay unit is less than the delay of the first clock delay unit. Based on this solution, the controller closes the loop to control the clock selector to select the clock delay unit, so that the output states of the N second registers have both a hold failure state and a hold success state.

[0017] In combination with the first aspect and the above possible implementations, in another possible implementation, the detection circuit further includes an interface circuit, the controller is connected to the interface circuit, and the controller is further configured to transmit the output states of the N second registers to the interface circuit. Based on this solution, the output states of the N second registers can be transmitted to an external device through the interface circuit, and based on the output states of the N second registers and the simulation results, it can be determined whether the boundary conditions in the design stage are too strict or too loose.

[0018] In combination with the first aspect and the above possible implementation, in another possible implementation, the process voltage temperature PVT of the N first registers and the N second registers in the same group of test circuits is the same, and the PVT is a standard voltage threshold SVT, a low voltage threshold LVT, or an ultra-low voltage threshold ULVT. Based on this solution, test circuits with different PVTs can be set in the detection circuit to adapt to the processes of different chips.

[0019] According to a second aspect of an embodiment of the present application, a device is provided, which includes a circuit board and a detection circuit for holding time margin as described in the first aspect or any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of an IP design for detecting time margin provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a synchronous timing circuit provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a detection circuit for maintaining a time margin provided in an embodiment of the present application;

[0023] Figure 4 A structural schematic diagram of a data delay unit provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the delay and step accuracy of a data delay unit provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of a simulation result and a test result provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of another simulation result and test result provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the division of an S-shaped metal winding provided in an embodiment of the present application;

[0028] Fig. 9A schematic diagram of wiring of an S-shaped metal winding provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of another wiring diagram of an S-shaped metal winding provided in an embodiment of the present application;

[0030] Fig.11 A schematic diagram of another detection circuit for maintaining a time margin provided in an embodiment of the present application;

[0031] Fig.12 A schematic diagram of another detection circuit for maintaining a time margin provided in an embodiment of the present application;

[0032] Fig.13 A schematic diagram of another detection circuit for maintaining a time margin provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solution in the embodiment of the present application will be described below in conjunction with the drawings in the embodiment of the present application. In the present application, "at least one group" refers to one or more groups, and "multiple groups" refers to two or more groups. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c It can be single or multiple. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order. For example, the "first" in the first register in the embodiment of the present application and the "second" in the second register are only used to distinguish different registers. The descriptions of first, second, etc. that appear in the embodiments of the present application are only for illustration and distinction of the description objects. There is no order, nor does it represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0034] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0035] Figure 2 is a synchronous sequential circuit, such as Figure 2 As shown, the data output terminal Q of register D1 is connected to the input terminal of combinatorial logic, and the output terminal of combinatorial logic is connected to the data input terminal D of register D2. The clock terminal CP of register D1 and the clock terminal CP of register D2 are connected to the clock signal CLK. The effective clock edge of the clock terminals of registers D1 and D2 can be a rising edge or a falling edge. When the effective clock edge of registers D1 and D2 is a falling edge, when the clock terminal changes from a high level to a low level, register D1 or register D2 samples the data input terminal and sends the sampled value to the data output terminal. When the clock terminal is in other conditions, the data output terminal maintains the original sampled value until the clock terminal changes from a high level to a low level for the second time. It can be understood that the output of the combinatorial logic at any time depends only on the input at that time, has nothing to do with the original state of the circuit, and does not involve the processing of the signal jump edge. The output of the sequential logic at any time depends not only on the input at that time, but also on the original state of the circuit. When the effective edge (rising edge or falling edge) of the clock arrives, it is possible to change the output.

[0036] To achieve Figure 2 For the correct synchronization of the circuit shown, the data must be stable for a period of time before the arrival of the effective edge of the clock (for example, the rising edge or the falling edge). This period of time is called the setup time. The data must also be stable for a period of time after the arrival of the effective edge of the clock. This period of time is called the hold time. That is, the data input must remain stable before the actual sampling time arrives, and the data input must also be maintained for a period of time after the sampling time. In other words, the circuit can only be correctly synchronized when the setup time and the hold time are met.

[0037] Understandably, Figure 2 When performing timing analysis on the circuit in the example, the delay of the data path and the clock path can be used to determine whether the timing requirements of setup time and hold time are met. Figure 2As shown. The data path refers to the path that the data takes from the entire transmission input end to the transmission output end, and the clock path refers to the path that the clock takes to reach each register. When the delay of the data path is greater than the delay of the clock path, the hold time will meet the timing requirements. When the delay of the data path is less than the delay of the clock path, the setup time will meet the timing requirements.

[0038] Usually, in the chip design process, simulation is performed based on the process file (spice model) released by the foundry that is responsible for producing and manufacturing the chip. During the simulation, the internal delay of the chip is fixed. However, during the production and manufacturing process of the chip, due to process deviation, voltage drop, and temperature change, the internal delay of the chip may not be a fixed value, but a random value. In order to make the difference between chip design and manufacturing closer, the static timing analysis (STA) method can usually be used to ensure the timeliness of the design iteration cycle.

[0039] For example, in STA, on-chip variation (OCV) can be used to simulate the performance variation between different devices inside the chip due to process deviation, voltage drop, and temperature variation. When analyzing hold timing violations, the boundary conditions can be pessimistically covered, multiplying the delay value on the data path by a coefficient less than 1, and multiplying the delay value on the clock path by a coefficient greater than 1. However, if the boundary conditions are set too strictly, it will greatly increase the difficulty of design, while occupying too many resources in the die, reducing the competitiveness of the product. If the boundary conditions are set too loosely, quality problems may occur, causing a series of indicator problems in the chip or even causing it to fail to work.

[0040] In order to relax some of the boundary conditions when they are set too strictly and improve the product competitiveness of the chip, a test circuit can be set in the chip to detect the hold time margin of the chip and adjust the design of the next generation chip based on the hold time margin, thereby improving the product competitiveness of the next generation chip.

[0041] Figure 1 For an IP design that detects time margin, such as Figure 1As shown, the IP mainly uses stdcell to form a delayline, and configures the initial state of the circuit to hold success (hold pass). By adjusting the signal configuration of delaySel, different delay values ​​can be selected until the circuit is in a hold fail state. The peripheral circuit detects the pass and fail states of the timing of the circuit to be tested, and then reads the test results through the bus to obtain the hold time margin, thereby providing a basis for the upgrade of the next generation of chips.

[0042] but, Figure 1 In the IP design shown, when the hold time margin is detected by the delay line composed of stdcell, the accuracy of the hold time detected by stdcell is ideally about 7 to 8ps. However, in the 28nm and below processes, the number of timing violations caused by 1ps hold uncertainty may be hundreds of thousands or even millions depending on the scale of the SOC. Therefore, if the lack of 7 to 8ps accuracy is applied in actual projects, it means that there will be a great risk of timing violations, so this solution has no obvious practical engineering significance.

[0043] In order to improve the problem of poor detection accuracy of the hold time margin within the chip, an embodiment of the present application provides a hold time margin detection circuit. The hold time margin detected by the detection circuit has high accuracy and can provide a basis for the design of the next generation of chips to improve the product competitiveness of the next generation of chips.

[0044] It should be noted that when the detection circuit provided in the following embodiments of the present application detects the hold time margin of the chip, it is assumed that the chip meets the timing requirements of the setup time.

[0045] Figure 3 A detection circuit for maintaining a time margin is provided in an embodiment of the present application, such as Figure 3As shown, the detection circuit includes: a controller, a generator and a decision circuit. The generator includes at least one group of test circuits, each group of test circuits includes N first registers, N second registers, and N data delay units, the delays of the N data delay units are increased in sequence, the delay difference between two adjacent data delay units is less than or equal to a preset value, and N is an integer greater than 1. Among them, the clock ends of the N first registers (CP ends of the first registers) and the clock ends of the N second registers (CP ends of the second registers) are connected to the same clock output end of the controller, the data output ends of the N first registers (QN ends of the first registers) are respectively connected to the input ends of the N data delay units, the output ends of the N data delay units are respectively connected to the data input ends of the N second registers (D ends of the second registers), and the data output ends of the N second registers (Q ends of the second registers) are connected to the decision circuit. The decision circuit is used to detect the output states of the N second registers and transmit the output states of the N second registers to the controller.

[0046] For example, Figure 3 In the figure, only the data output terminal of the first register is QN terminal as an example. Figure 3 As shown, when the data output terminal of the first register is the QN terminal, the data input terminal of the first register (the D terminal of the first register) is connected to the data output terminal of the first register (the QN terminal of the first register). Optionally, the data output terminal of the first register may also be the Q terminal. When the data output terminal of the first register is the Q terminal, the data input terminal of the first register (the D terminal of the first register) is connected to the data output terminal of the first register (the Q terminal of the first register) through an inverter. It can be understood that the data output terminal QN of the first register is the inverse of the data input terminal D of the first register.

[0047] For example, the embodiment of the present application does not limit the specific value of N. In practical applications, the value of N can be determined in combination with the range of clock delay. The value of N affects the delay size on the data path. This value can make the delay on the data path of a part of the registers in the N group of registers smaller than the delay on the clock path, and the delay on the data path of another part of the registers larger than the delay on the clock path. It can be understood that a first register and a second register connected to the register through a data delay unit can be called a group of registers. The embodiment of the present application is only illustrated by taking N as 94 as an example.

[0048] Exemplarily, the N data delay units mentioned above respectively include N S-shaped metal windings. The data delay unit can be made of S-shaped metal windings, and the lengths of the S-shaped metal windings of different data delay units in the N data delay units are different. It can be understood that the turning portion of the S-shaped metal winding can be a right-angle turning, an obtuse-angle turning, or a curved turning, and the embodiments of the present application are not limited to this. The following embodiments are only illustrated by taking the turning portion of the S-shaped metal winding as a right angle as an example.

[0049] For example, Figure 4 As shown, each data delay unit is made of an S-shaped metal winding, and the N data delay units are respectively made of N S-shaped metal windings, and the lengths of the N S-shaped metal windings increase successively, so the delays of the N data delay units increase successively.

[0050] Exemplarily, the delay difference between two adjacent data delay units in the N data delay units is related to the length difference between two adjacent S-shaped metal windings. The smaller the length difference between the two adjacent S-shaped metal windings, the smaller the delay difference between the two adjacent data delay units, and the higher the stepping accuracy of the delay time. The larger the length difference between the two adjacent S-shaped metal windings, the larger the delay difference between the two adjacent data delay units, and the lower the stepping accuracy of the delay time. It can be understood that the delay difference between the two data delay units can be adjusted by designing the length difference between the two adjacent S-shaped metal windings to ensure that the detection accuracy of the time margin is kept high.

[0051] Optionally, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings can be equal, that is, the lengths of the N S-shaped metal windings increase successively, and the lengths of the two adjacent S-shaped windings are increased by the same length. It should be noted that due to the nonlinear characteristics of metal, when the lengths of the N S-shaped metal windings increase successively, and the two adjacent S-shaped windings increase by the same length, the delays of the N data delay units increase successively, but the delay difference (step accuracy) of the two adjacent data delay units is not exactly the same.

[0052] For example, Figure 5 As shown in FIG. 1 , when the lengths of the S-shaped metal windings from data delay unit 0 to data delay unit 21 are increased by the same value in sequence, the delays from data delay unit 0 to data delay unit 21 are increased in sequence, but the delay difference between two adjacent data delay units is nonlinear, that is, the stepping accuracy of the delay time between two adjacent data delay units is nonlinear. Figure 5 It can be seen that the step accuracy of the delay time of two adjacent data delay units is about 1.5ps, so the accuracy of the hold time margin detected by the detection circuit is relatively high.

[0053] Exemplary, combined Figure 3 and Figure 5As shown, since the delays of the N data delay units connected between the data output ends of the N first registers and the data input ends of the N second registers are different, the delays on the data paths of the N groups of registers are different. When the delay of the data delay unit is small, if the delay of the data path from the first register to the second register is smaller than the delay of the clock path, then the output state of the second register is hold fail, that is, it does not meet the timing requirements of the chip hold time. When the delay of the data delay unit increases to a larger delay, if the delay of the data path from the first register to the second register is larger than the delay of the clock path, then the output state of the second register is hold pass, that is, it meets the timing requirements of the chip hold time.

[0054] It can be understood that, since the delay on the data path of the above-mentioned N groups of registers increases in sequence, the output states of some of the N second registers may be in a hold fail state, and the output states of another part of the registers may be in a hold pass state. Based on the output states of the N second registers, combined with the simulation results after adding OCV during design or simulation, it can be determined whether the boundary conditions of the design are too strict or too loose.

[0055] For example, taking the test result that the output states of the second registers 0 to 9 are in the hold fail state and the output states of the second registers 10 to 93 are in the hold pass state, as an example, Figure 6 As shown, if the simulation result after adding OCV is that the output state of the second register 0 to the second register 7 is the hold fail state, and the output state of the second register 8 to the second register 93 is the hold pass state. Then, according to the test results, it can be determined that the time margin reserved in the design stage is insufficient, resulting in the risk of hold violation in the test results, that is, the boundary conditions in the design stage are too loose, resulting in the risk of violation of the chip. It is understandable that Figure 6 Only the simulation results and test results of the second register 0 to the second register 11 are shown. Since the delay of the data path of the second register 0 to the second register 93 increases in sequence, if the simulation result or test result of the second register 11 is hold pass, then the simulation results or test results of the second register 12 to the second register 93 are also hold pass. Figure 6 The simulation results and test results of the second register 0 to the second register 11 are shown only as examples. It should be noted that: Figure 6The Pass in the code represents hold pass, and the Fail represents hold fail.

[0056] For another example, taking the test result that the output states of the second registers 0 to 4 are in the hold fail state, and the output states of the second registers 5 to 93 are in the hold pass state, as an example, Figure 7 As shown, if the simulation result after adding OCV is that the output state of the second register 0 to the second register 7 is a hold fail state, and the output state of the second register 8 to the second register 93 is a hold pass state. Then, according to the test results and the simulation results, since the hold fail of the test is between the simulation result without adding OCV (no OCV) and the simulation result with adding OCV, it can be determined that the time margin reserved in the design stage is too much (that is, the boundary conditions in the design stage are too strict), and some constraints can be appropriately relaxed according to the test results to release some boundary conditions, so that the next generation of chips has more product competitiveness.

[0057] Optional, such as Figure 7 As shown, if the boundary conditions of the design stage are determined to be too strict based on the test results, the boundary conditions of the two stages can be liberated when designing the next generation of chips based on the test results and simulation results, making the next generation of products more competitive.

[0058] It can be understood that the test circuit in the embodiment of the present application sets N S-shaped metal windings between N first registers and N second registers, and the lengths of the N S-shaped metal windings increase successively, and the increasing step accuracy is related to the length difference between two adjacent S-shaped metal windings. Therefore, by designing the length difference between two adjacent S-shaped metal windings, the detection accuracy of the hold time margin can be controlled, so that the accuracy of the detected hold time margin is higher. Therefore, based on the test results, it can provide a strong basis for the design of the next generation of chips, making the next generation of chips more competitive.

[0059] Since it is difficult to control the metal winding and conduct secondary inspection during the physical design of the chip, the S-shaped metal winding in the embodiment of the present application can be designed into a spliced ​​module and actually physically spliced ​​in the top-level module, thereby indirectly obtaining a stepped S-shaped winding.

[0060] Exemplarily, the S-shaped metal winding may include a first turning portion, a spliceable portion, and a second turning portion. The S-shaped metal winding may be a left-right S-shaped winding, or an upper-lower S-shaped winding. When the S-shaped metal winding is a left-right S-shaped winding, the first turning portion is the turning portion on the left, the second turning portion is the turning portion on the right, and the middle unturned portion is the spliceable portion. When the S-shaped metal winding is an upper-lower S-shaped winding, the first turning portion is the turning portion on the upper side, the second turning portion is the turning portion on the lower side, and the middle unturned portion is the spliceable portion.

[0061] Exemplarily, different S-shaped metal windings include different numbers of spliceable parts. Figure 8 Take the S-shaped metal winding as the left and right S-shaped winding as an example. Figure 8 As shown in (a) of FIG. 1 , the S-shaped metal winding includes a first turning portion, a second turning portion and a splicable portion. Figure 8 As shown in (b), the S-shaped metal winding includes a first turning part, a second turning part and two splicable parts. That is, S-shaped metal windings of different lengths can be achieved by increasing the number of splicable parts. This method has good controllability, and can freely realize splicing according to different design scales and different required delay values. It is also convenient for secondary inspection and has good practical engineering significance. It can be understood that the present application can modularize the S-shaped metal winding, and each S-shaped metal winding can include three parts (a first turning part, a splicable part and a second turning part). In this way, S-shaped metal windings of different lengths can be made by increasing the number of splicable parts, so that in multiple rounds of design or tape-out, the length of the S-shaped metal winding can be changed by changing the number of splicable parts to adjust the delay of the data delay unit.

[0062] Exemplarily, the input end and the output end of the S-shaped metal winding can be arranged on the same side or on different sides. When the input end and the output end of the S-shaped metal winding are arranged on the same side, the first turning portion includes the input end and the output end of the S-shaped metal winding, or the second turning portion includes the input end and the output end of the S-shaped metal winding. When the input end and the output end of the S-shaped metal winding are arranged on different sides, the first turning portion includes the input end of the S-shaped metal winding, and the second turning portion includes the output end of the S-shaped metal winding; or the first turning portion includes the output end of the S-shaped metal winding, and the second turning portion includes the input end of the S-shaped metal winding.

[0063] It can be understood that the input end of the S-shaped metal winding is connected to the data output end QN of the first register, and the output end of the S-shaped metal winding is connected to the data input end D of the second register. That is, the input end of the S-shaped metal winding is the starting point of the S-shaped metal winding, and the output end of the S-shaped metal winding is the end point of the S-shaped metal winding.

[0064] Optionally, the input end and the output end of the S-shaped metal winding may be located on the same horizontal line or on different horizontal lines.

[0065] For example, Fig. 9 Take the S-shaped metal winding as the left and right S-shaped winding as an example. Fig. 9 As shown in (a), the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. Fig. 9 As shown in (b), the second turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. Fig. 9 As shown in (c), the first turning portion includes the input end of the S-shaped metal winding, and the second turning portion includes the output end of the S-shaped metal winding. The input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. Fig. 9 As shown in (d), the second turning part includes the input end of the S-shaped metal winding, the first turning part includes the output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines.

[0066] For another example, Fig.10 Take the S-shaped metal winding as an example, the upper and lower S-shaped winding. Fig.10 As shown in (a), the second turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on the same horizontal line. Fig.10 As shown in (b), the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on the same horizontal line. Fig.10 As shown in (c), the second turning portion includes the input end of the S-shaped metal winding, the first turning portion includes the output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. Fig.10 As shown in (d), the first turning part includes the input end of the S-shaped metal winding, and the second turning part includes the output end of the S-shaped metal winding. The input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines.

[0067] Optionally, the detection circuit provided in the embodiment of the present application may further include a clock selector and a clock delay circuit, such as Fig.11As shown, the controller is connected to the input end of the clock selector, the data selection end of the clock selector, and the clock ends of the N first registers, the output end of the clock selector is connected to the input end of the clock delay circuit, and the output end of the clock delay circuit is connected to the clock ends of the N second registers.

[0068] For example, Fig.11 As shown, the clock delay circuit may include M clock delay units, and the M clock delay units have different time delays. It should be noted that the embodiment of the present application does not limit the value of M. Fig.11 M is assumed to be 32 for illustration only.

[0069] The controller is specifically used for time-sharingly controlling the clock selector to select each clock delay unit in the M clock delay units in sequence.

[0070] Exemplarily, the clock selector may be a multiplexer MUX, and the controller may control the multiplexer MUX in a time-sharing manner. The MUX may be an M-to-1 selector, and the number of data selection terminals A0 to Ak in the MUX is related to the specific value of M. For example, the controller controls the multiplexer MUX to select one of the 32 clock delay units at regular intervals to obtain a group of N output states of the second registers. The controller selects each of the 32 clock delay units in turn to obtain 32 groups of output results, and each group of output results is used to indicate the output state of each second register. It is understandable that when the clock delay circuit includes 32 clock delay units, the MUX may be a 32-to-1 selector, and the number of data selection terminals may be 5, that is, the data selection terminals may be A. 0 To A 4 .

[0071] It should be noted that when the output results of the N second registers are all in the hold fail state or all in the hold pass state, the test result has no practical guiding significance and the hold time margin cannot be determined. Only when the output states of the N second registers have both the hold fail state and the hold pass state, can the test result be combined with the simulation results of the design phase to determine whether the boundary conditions of the design phase are too strict or too loose. Therefore, by selecting different clock delay units by the controller in time-sharing, a large range of adjustments can be performed, so that the output states of the N second registers have both the hold fail state and the hold pass state.

[0072] Optionally, the controller can also control the clock selector to select the first clock delay unit in the clock delay module; if the output states of the N second registers are all hold success (hold pass), the controller controls the clock selector to select the second clock delay unit in the clock delay module, and the delay of the second clock delay unit is greater than the delay of the first clock delay unit; if the output states of the N second registers are all hold failure (hold fail), the controller controls the clock selector to select the third clock delay unit in the clock delay module, and the delay of the third clock delay unit is less than the delay of the first clock delay unit. Through the closed-loop control of the controller, the output states of the N second registers can have both a hold failure (hold fail) state and a hold success (hold pass) state.

[0073] Optionally, the detection circuit provided in the embodiment of the present application may further include an interface circuit, such as Fig.12 As shown, the controller is connected to the interface circuit, and the controller is also used to transmit the output states of the N second registers to the interface circuit. The interface circuit is used to transmit data to other devices. For example, the interface circuit can transmit the detection result of the test circuit to the external device.

[0074] For example, the above Figure 3 , Figure 8 and Fig. 9 The example in which the generator includes one group of test circuits is used for illustration. The embodiment of the present application does not limit the specific number of test circuits included in the generator. For example, the generator may also include two groups of test circuits or three groups of test circuits.

[0075] It should be noted that the process voltage temperature (PVT) of the N first registers and the N second registers included in the same group of test circuits is the same, and the PVT can be a standard voltage threshold (SVT), a low voltage threshold (LVT) or an ultra low voltage threshold (ULVT).

[0076] For example, Fig.13 As shown, the generator includes three groups of test circuits, and the PVTs of the N first registers and the N second registers in the first group of test circuits are all SVTs. The PVTs of the N first registers and the N second registers in the second group of test circuits are all LVTs. The PVTs of the N first registers and the N second registers in the third group of test circuits are all ULVTs.

[0077] The test circuit in the embodiment of the present application sets N S-shaped metal windings between N first registers and N second registers, and the lengths of the N S-shaped metal windings increase successively, and the increasing step accuracy is related to the length difference between two adjacent S-shaped metal windings. Therefore, by designing the length difference between two adjacent S-shaped metal windings, the detection accuracy of the hold time margin can be controlled, so that the accuracy of the detected hold time margin is higher. Therefore, based on the test results, a strong basis can be provided for the design of the next generation of chips, making the products of the next generation of chips more competitive.

[0078] The steps of the method or algorithm described in conjunction with the disclosure of the present application may be implemented in hardware or by executing software instructions by a processor. The software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an ASIC. In addition, the ASIC may be located in a core network interface device. Of course, the processor and the storage medium may also exist in a core network interface device as discrete components.

[0079] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented using software, the functions may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium may be any available medium that a general or special-purpose computer can access.

[0080] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A detection circuit for maintaining a time margin, characterized in that: The detection circuit comprises: a controller, a generator and a decision circuit; the generator comprises at least one group of test circuits, each group of the test circuits comprises N first registers, N second registers, and N data delay units, the delays of the N data delay units are increased in sequence, the delay difference between two adjacent data delay units is less than or equal to a preset value, and N is an integer greater than 1; wherein the clock ends of the N first registers and the clock ends of the N second registers are connected to the same clock output end of the controller, the data output ends of the N first registers are respectively connected to the input ends of the N data delay units, the output ends of the N data delay units are respectively connected to the data input ends of the N second registers, and the data output ends of the N second registers are connected to the decision circuit; The decision circuit is used to detect the output states of the N second registers and transmit the output states of the N second registers to the controller.

2. The circuit according to claim 1, characterized in that The N data delay units respectively include N S-shaped metal windings, and the lengths of the N S-shaped metal windings increase sequentially.

3. The circuit according to claim 2, characterized in that The length differences between two adjacent S-shaped metal windings among the N S-shaped metal windings are the same.

4. The circuit according to claim 3, characterized in that The S-shaped metal winding includes a first turning portion, a second turning portion, and one or more spliceable portions, and different S-shaped metal windings include different numbers of spliceable portions.

5. The circuit according to claim 4, characterized in that The first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding; or, the second turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding.

6. The circuit according to claim 4, characterized in that The first turning portion includes the input end of the S-shaped metal winding, and the second turning portion includes the output end of the S-shaped metal winding; or, the first turning portion includes the output end of the S-shaped metal winding, and the second turning portion includes the input end of the S-shaped metal winding.

7. The circuit according to any one of claims 1 to 6, characterized in that: The detection circuit also includes a clock selector and a clock delay circuit. The controller is connected to the input end of the clock selector, the data selection end of the clock selector, and the clock ends of the N first registers. The output end of the clock selector is connected to the input end of the clock delay circuit, and the output end of the clock delay circuit is connected to the clock ends of the N second registers.

8. The circuit according to claim 7, characterized in that The clock delay circuit includes M clock delay units, where M is a positive integer, and the M clock delay units respectively have M different time delays.

9. The circuit according to claim 8, characterized in that The controller is specifically used for controlling the clock selector in time-sharing manner to select each clock delay unit in the M clock delay units in sequence.

10. The circuit according to claim 8, characterized in that The controller is specifically used for: Controlling the clock selector to select a first clock delay unit among the M clock delay units; If the output states of the N second registers are all maintained successfully, the controller controls the clock selector to select a second clock delay unit among the M clock delay units, and the delay of the second clock delay unit is greater than the delay of the first clock delay unit; If the output states of the N second registers are all maintained failures, the controller controls the clock selector to select a third clock delay unit among the M clock delay units, and the delay of the third clock delay unit is smaller than the delay of the first clock delay unit.

11. The circuit according to any one of claims 1 to 6, characterized in that: The detection circuit further includes an interface circuit, the controller is connected to the interface circuit, and the controller is further configured to transmit output states of the N second registers to the interface circuit.

12. The circuit according to any one of claims 1 to 6, characterized in that: The process voltage temperature PVT of the N first registers and the N second registers in the same group of the test circuits is the same, and the PVT is a standard voltage threshold SVT, a low voltage threshold LVT, or an ultra-low voltage threshold ULVT.

13. A device, characterized in that: The device comprises a circuit board and a detection circuit for holding time margin according to any one of claims 1 to 12.

Images