Circuit board

Abstract

A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on upper surfaces of the first to third regions of the insulating layer; and a solder resist including a first portion disposed in the first region of the insulating layer, a second portion disposed in the second region, and a third portion disposed in the third region, wherein the outer layer circuit pattern has a first height, the third portion of the solder resist is disposed on an upper surface of the outer layer circuit pattern to have a second height, the first region includes a first sub-region and a second sub-region, the first portion includes a first sub-portion disposed in the first sub-region and a second sub-portion disposed in the second sub-region, an upper surface of the first sub-portion is positioned higher than the upper surface of the outer layer circuit pattern and lower than an upper surface of the third portion, an upper surface of the second sub-portion is positioned lower than the upper surface of the outer layer circuit pattern, and a surface roughness of the third portion of the solder resist is different from a surface roughness of the first portion of the solder resist.

Description

Technical Field

[0001] The embodiments relate to a circuit board, and more specifically, to a circuit board capable of supporting and protecting the outermost circuit pattern in an open area using solder resist, and a method thereof for manufacturing the same. Background Technology

[0002] With the acceleration of miniaturization, weight reduction, and integration of electronic components, circuit linewidths have become increasingly fine. In particular, because the design rules of semiconductor chips are integrated at the nanoscale, the linewidths of packaging substrates or printed circuit boards on which semiconductor chips are mounted have become as fine as a few micrometers or smaller.

[0003] Various methods have been proposed to increase the circuit integration of printed circuit boards, i.e., to reduce circuit linewidth. To prevent linewidth loss during the etching step that forms patterns after copper plating, the semi-additive process (SAP) method and the improved semi-additive process (MSAP) method have been proposed.

[0004] Then, the embedded trace substrate (hereinafter referred to as "ETS") method has been used in industry for embedding copper foil in an insulating layer to facilitate the realization of fine circuit patterns. In the ETS method, instead of forming copper foil circuits on the surface of the insulating layer, the copper foil circuits are fabricated in an embedded form in the insulating layer, and therefore there is no circuit loss due to etching and it is advantageous for making the circuit pitch fine.

[0005] Meanwhile, efforts have recently been made to develop improved 5G (5th generation) communication systems or pre-5G communication systems to meet the demand for wireless data services. Here, 5G communication systems use ultra-high frequency (millimeter wave) bands (sub-6GHz, 28GHz, 38GHz or higher frequencies) to achieve high data transmission rates.

[0006] Furthermore, to reduce path loss and increase transmission distance in the UHF band, technologies such as beamforming, massive MIMO, and integrated array antennas have been developed for 5G communication systems. Considering that it may consist of active antennas with hundreds of wavelengths across the frequency band, the antenna system becomes relatively large.

[0007] Because these antennas and AP modules are patterned or mounted on printed circuit boards, low loss on the printed circuit board is crucial. This means that the several substrates that make up the active antenna system—namely, the antenna substrate, the antenna feed substrate, the transceiver substrate, and the baseband substrate—should be integrated into a compact unit.

[0008] In addition, the circuit boards used in 5G communication systems are trending towards thinner and more compact designs during manufacturing, and correspondingly, the circuit patterns are becoming increasingly refined.

[0009] However, circuit boards including those with traditional fine circuit patterns have a structure in which the circuit pattern located on the outermost edge protrudes above the insulating layer, and therefore there is a problem that the outermost circuit pattern is prone to collapse. Summary of the Invention

[0010] Technical issues

[0011] The embodiment provides a circuit board with a novel structure and a method for manufacturing the same.

[0012] Furthermore, the embodiments provide a circuit board capable of using solder resist to support and protect the outermost circuit pattern included in the SR opening area, and a method thereof for manufacturing the same.

[0013] Furthermore, in the embodiments, a circuit board with a layered structure of solder resist having different heights for each region, and a method of manufacturing the solder resist, is provided, comprising a solder resist having a layered structure with different heights for each region by performing a progressive exposure and development process of the solder resist.

[0014] The technical problems to be solved by the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems can be clearly understood by those skilled in the art to which the proposed embodiments pertain.

[0015] Technical solution

[0016] The circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer circuit pattern disposed on the upper surface of the first to third regions of the insulating layer; and a solder resist including a first part disposed in the first region of the insulating layer, a second part disposed in the second region of the insulating layer, and a third part disposed in the third region of the insulating layer, wherein the outer circuit pattern has a first height, the third part of the solder resist is disposed on the upper surface of the outer circuit pattern to have a second height, the first region includes a first sub-region and a second sub-region, the first part includes a first sub-part disposed in the first sub-region and a second sub-part disposed in the second sub-region, the upper surface of the first sub-part is positioned above the upper surface of the outer circuit pattern and below the upper surface of the third part, the upper surface of the second sub-part is positioned below the upper surface of the outer circuit pattern, and the surface roughness of the third part of the solder resist is different from the surface roughness of the first part of the solder resist.

[0017] Furthermore, the first sub-region is the area in the outer circuit pattern where traces are provided, and the second sub-region is the area in the outer circuit pattern where the first pad is provided.

[0018] Furthermore, the second region is the area within the outer circuit pattern where a second pad is provided, and the width of the second pad is greater than the width of the first pad.

[0019] In addition, the second sub-part is configured to contact at least one outer surface of the first pad.

[0020] Furthermore, the second sub-part includes a first portion disposed on a first outer surface of the first pad and a second portion disposed on a second outer surface of the first pad opposite to the first outer surface. The width of the first portion is equal to the width of the second portion, and the width of the first portion or the second portion is in the range of 10 μm to 12 μm.

[0021] Furthermore, the second sub-part includes a first portion disposed on a first outer surface of the first pad and a second portion disposed on a second outer surface of the first pad opposite to the first outer surface. The width of the first portion is different from the width of the second portion, and the sum of the widths of the first portion and the second portion is in the range of 20 μm to 24 μm.

[0022] In addition, the second sub-part includes a first portion disposed on the first outer surface of the first pad, the second outer surface of the first pad opposite to the first outer surface is in direct contact with the first sub-part, and the width of the first portion is in the range of 20μm to 24μm.

[0023] In addition, the height of the second sub-part is within the range of 70% to 90% of the height of the first pad.

[0024] Furthermore, the second height of the third part protruding from the outer circuit pattern satisfies the range of 7μm to 17μm.

[0025] Furthermore, a third portion of the solder resist is disposed on the upper surface of the second pad to have a second height and includes an opening that exposes the upper surface of the second pad, and the width of the opening is smaller than the width of the second pad.

[0026] Furthermore, the surface roughness Ra of the centerline of the upper surface of the first or second sub-part is greater than that of the centerline of the upper surface of the third part.

[0027] In addition, the first and second regions are opening areas for the solder resist.

[0028] In addition, the insulating layer includes multiple insulating layers, the outer circuit pattern is configured to protrude on the upper surface of the uppermost insulating layer among the multiple insulating layers, and the circuit board includes a primer layer disposed between the uppermost insulating layer, the outer circuit pattern and the solder resist.

[0029] Meanwhile, the method for manufacturing a circuit board according to the embodiment includes: manufacturing an inner layer substrate; forming an uppermost insulating layer on the inner layer substrate on which a primer layer is disposed on its upper surface; forming an outer layer circuit pattern on the primer layer of the uppermost insulating layer; forming a solder resist covering the outer layer circuit pattern and divided into a first region, a second region, and a third region on the primer layer; initially exposing areas of the solder resist that exclude openings in the first and second regions; initially developing the first region and the openings excluding the initially exposed areas; performing a second exposure on a first sub-region of the initially developed first region; and performing a second exposure on the second sub-region of the first region and the areas excluding the second exposure. The opening is subjected to secondary development, wherein the solder resist includes a first sub-part disposed in a first sub-region, a second sub-part disposed in a second sub-region, a second part disposed in the second region, and a third part disposed in a third region. The outer layer circuit pattern has a first height, the third part of the solder resist is disposed above the upper surface of the outer layer circuit pattern and has a second height, the upper surface of the first sub-part is disposed above the upper surface of the outer layer circuit pattern and below the upper surface of the third sub-part, the upper surface of the second sub-part is below the upper surface of the outer layer circuit pattern, and the surface roughness of the third part of the solder resist is different from the surface roughness of the first part of the solder resist.

[0030] Furthermore, the first sub-region is the region in the outer circuit pattern where traces are provided, the second sub-region is the region in the outer circuit pattern where the first pad is provided, and the second region is the region in the outer circuit pattern where the second pad is provided. The width of the second pad is greater than the width of the first pad. The first pad includes mounting pads on which devices are mounted, and the second pad includes BGA pads or core pads.

[0031] Furthermore, the second sub-region is configured to contact at least one outer surface of the first pad, the width of the second sub-region is greater than the width of the first pad, and the width of the second sub-region has a range of 20 μm to 24 μm.

[0032] In addition, the height of the second sub-part is within the range of 70% to 90% of the height of the first pad.

[0033] Furthermore, a third portion of the solder resist is disposed on the upper surface of the second pad to have a second height and includes an opening that exposes the upper surface of the second pad, and the width of the opening is smaller than the width of the second pad.

[0034] Furthermore, the surface roughness Ra of the centerline of the upper surface of the first or second sub-part is greater than that of the centerline of the upper surface of the third part.

[0035] Beneficial effects

[0036] The circuit board in this embodiment is a multilayer circuit board with eight or more layers, and includes an outer circuit pattern that is positioned on an outer insulating layer at the top of the multilayer and protrudes above the surface of the outer insulating layer. In this case, the outer circuit pattern includes a first outer circuit pattern positioned in a first and second region where no solder resist is applied, and a second outer circuit pattern positioned in a third region where solder resist is applied. In this case, the second outer circuit pattern can be supported and protected by solder resist, but the first outer circuit pattern does not have a support layer capable of supporting it, and therefore there is a problem that the first outer circuit pattern may easily collapse due to various factors.

[0037] Therefore, in the embodiments, the solder resist in the first and second regions is not completely removed and is retained, thereby supporting and protecting the first outer layer circuit pattern. Thus, in the embodiments, problems such as collapse or friction of the first outer layer circuit pattern in the first and second regions can be solved by refining the outer layer circuit pattern, thereby improving product reliability. Specifically, in the embodiments, problems such as collapse or friction of traces included in the first outer layer circuit pattern in the first region can be solved, thereby improving product reliability.

[0038] Meanwhile, the solder resist according to the embodiment includes a first portion disposed in a first region, a second portion disposed in a second region, and a third portion disposed in a third region. Furthermore, the second portion may have an opening and have the same height as the third portion. Additionally, the first portion includes a first sub-part having a height lower than the heights of the second and third portions, and a sub-part having a height lower than the height of the first sub-part. The first sub-part may be formed to cover the surface of the traces of the first outer layer circuit pattern disposed in the first region. Furthermore, the second sub-part may have a height lower than the height of the first pad, while exposing the surface of the first pad of the first outer layer circuit pattern disposed in the first region. That is, in the embodiment, the first sub-part, second sub-part, second portion, and third portion are formed by exposing and developing the solder resist in two steps. Therefore, in the embodiment, the exposure resolution can be improved. Additionally, in the embodiment, the surface of the traces can be stably protected by the first sub-part in the first region, thereby improving product reliability.

[0039] Furthermore, in this embodiment, both the surface of the insulating layer and the surface of the primer layer have a structure covered by solder resist, thus resolving reliability issues caused by exposure of the surface of the insulating layer or a portion of the primer layer. Specifically, exposure of the surface of the insulating layer or a portion of the primer layer refers to the existence of a specific space between the outer circuit pattern and the solder resist. Additionally, when such a space exists, residual solution, such as adhesive components, may remain within it, or voids may be created due to this residual solution, leading to reliability problems. On the other hand, in this embodiment, the space can be filled with solder resist, thereby resolving the reliability issue.

[0040] Additionally, in this embodiment, a second sub-part of the solder resist is disposed around the first pad, and a first sub-part is disposed around the second sub-part. Furthermore, the first sub-part prevents movement of the adhesive member (e.g., solder ball) to be disposed on the first pad. That is, the first sub-part acts as a barrier (dam) capable of fixing the position of the adhesive member. Therefore, in this embodiment, reliability issues such as short circuits caused by a portion of the adhesive member flowing downwards can be resolved.

[0041] Furthermore, in this embodiment, exposure and development methods are used instead of sandblasting or plasma methods for removing solder resist. In this case, when removing solder resist by sandblasting or plasma methods, deformation of the outer layer circuit pattern may occur, and in some cases, the cross-section of the outer layer circuit pattern may have a triangular shape. Moreover, when the cross-section of the outer layer circuit pattern is triangular, the adhesive member may not be stably mounted on the outer layer circuit pattern, leading to reliability issues. Conversely, in this embodiment, the solder resist can be removed without deforming the outer layer circuit pattern, thereby improving reliability.

[0042] Furthermore, the circuit board in this embodiment can be applied to 5G communication systems, and therefore, can minimize high-frequency transmission losses, thereby further improving reliability. Specifically, the circuit board in this embodiment can be used at high frequencies and can reduce wave loss. Attached Figure Description

[0043] Figure 1a and Figure 1b This is a view showing a circuit board manufactured using the SAP method according to a comparative example.

[0044] Figure 2 This is a view showing a circuit board manufactured using the ETS method in the comparative example.

[0045] Figure 3 This is a view showing a circuit board according to an embodiment.

[0046] Figure 4 yes Figure 3A magnified view of region B.

[0047] Figure 5 This is an enlarged view of the second subsection according to the embodiment.

[0048] Figure 6a This is a view used to describe the first shift of the second sub-part according to an embodiment.

[0049] Figure 6b This is a view used to describe the second shift of the second sub-part according to an embodiment.

[0050] Figure 7 This is a view used to illustrate the reliability of the solder resist structure according to the embodiments and comparative examples.

[0051] Figure 8 This is a view used to describe the surface roughness of each part of the solder resist according to an embodiment.

[0052] Figures 9 to 19 This shows the manufacturing process in sequence. Figure 3 A view of the circuit board method shown. Detailed Implementation

[0053] In the following description, embodiments disclosed herein will be described in detail with reference to the accompanying drawings. However, regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and repeated descriptions thereof will be omitted. The component suffixes “module” and “part” used in the following description are given or combined only for ease of specification creation, and they do not inherently distinguish one another or any other role. Furthermore, in describing embodiments disclosed herein, detailed descriptions of relevant prior art will be omitted where it is determined that such detailed descriptions unnecessarily obscure the gist of the embodiments disclosed herein. Further, the drawings are provided only for ease of understanding of the embodiments disclosed herein, and the scope of the technology disclosed herein is not limited by the drawings and should be understood to include all modifications, equivalents, and substitutions falling within the spirit and scope of the invention.

[0054] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0055] It will be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to another component or there can be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, it will be understood that there are no intermediate components.

[0056] As used in this article, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0057] It will be understood that the terms “comprising,” “including,” or “having” specify the presence of the features, integers, steps, operations, elements, components, and / or groups disclosed in this specification, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0058] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0059] Before describing this embodiment, a comparative example will be described.

[0060] Figure 1a and Figure 1b This is a view showing the circuit board according to the comparison example.

[0061] refer to Figure 1a The circuit board in the comparative example includes a circuit pattern manufactured using a typical SAP method.

[0062] Specifically, the circuit board includes an insulating layer 10, a circuit pattern 20, and a protective layer 30.

[0063] Circuit patterns 20 are respectively disposed on the upper and lower surfaces of the insulating layer 10.

[0064] In this case, at least one circuit pattern 20 disposed on the surface of the insulating layer 10 includes a fine circuit pattern.

[0065] exist Figure 1a and Figure 1b In this process, the circuit pattern 20 disposed on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes traces 21 as signal transmission wiring lines and pads 22 for mounting chips, etc.

[0066] In this context, in the embodiments, because a support layer using solder resist is formed to protect the fine circuit pattern, the structure in the region where the fine circuit pattern is formed in the comparative example will be described.

[0067] In addition, a protective layer 30 for protecting the circuit pattern 20 is disposed on the surface of the insulating layer 10.

[0068] In this case, the upper region of the insulating layer 10 includes a first region where the protective layer 30 is provided and a second region that is an opening region where the protective layer 30 is not provided.

[0069] Therefore, a portion of the circuit pattern 20 disposed on the upper surface of the insulating layer 10 is covered by the protective layer 30, and the remaining portion is exposed to the outside without being covered by the protective layer 30.

[0070] In this case, the traces 21 and pads 22 corresponding to the fine circuit pattern described above are set in the second region, which is the opening area of ​​the protective layer 30.

[0071] For example, at least one of traces 21 and pads 22 are formed with a width / spacing of 15μm / 15μm or less.

[0072] In this case, when the circuit pattern formed in the opening area of ​​the protective layer 30 is a pattern with a width of more than 15 μm rather than a fine circuit pattern, the circuit pattern can strongly resist external impacts.

[0073] However, as Figure 1b As shown, as the circuit pattern gradually becomes finer, the width and spacing of the traces 21 and pads 22 of the fine circuit pattern as the outermost layer gradually decrease. Therefore, when the fine circuit pattern protruding above the upper surface of the insulating layer 10 is set in the second region, which is the opening area of ​​the protective layer, there is a problem that the fine circuit pattern is prone to collapse due to external impact.

[0074] That is, such as Figure 1b As shown in B, the trace 21 corresponding to the fine circuit pattern of the outermost layer has an extremely fine pattern shape, and therefore is prone to collapse or friction even with small external impacts.

[0075] Meanwhile, recently, a fine circuit pattern with a structure buried in an insulating layer and located in the opening region of the protective layer has been formed by using the ETS method.

[0076] Figure 2 This is a view showing a circuit board manufactured using the ETS method in the comparative example.

[0077] refer to Figure 2 Specifically, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0078] The circuit pattern 20A is set on the upper and lower surfaces of the insulating layer 10A, respectively.

[0079] In this case, at least one of the circuit patterns 20A disposed on the surface of the insulating layer 10A includes a fine circuit pattern.

[0080] Here, when a circuit pattern is formed using the ETS method, the initially formed circuit pattern has a structure embedded in the insulating layer 10A. Therefore, even in the comparative example, when the initially formed circuit pattern is formed as a fine circuit pattern, the fine circuit pattern can also have a structure in which the fine circuit pattern is embedded in the insulating layer 10A.

[0081] In other words, the circuit board manufactured by the ETS method includes a fine circuit pattern with a structure buried in the surface of the insulating layer 10A. Specifically, the fine circuit pattern includes traces 21A as signal transmission wiring lines and pads 22A for mounting chips, etc.

[0082] Furthermore, when a circuit board is manufactured using the aforementioned ETS method, the fine circuit pattern is protected from external impacts because it has a structure that is buried in an insulating layer.

[0083] In this case, for those with such Figure 2 For two-layer substrates (based on the number of layers in the circuit pattern), the main problems associated with manufacturing circuit boards using the ETS method do not exist. However, when manufacturing circuit boards with eight or more layers, especially ten or more layers, using the ETS method, the lead time for manufacturing them can be at least two months or more, resulting in reduced productivity.

[0084] Furthermore, in order to fabricate the fine circuit patterns of the buried structure using the ETS method, the fine circuit patterns should first be formed during the manufacturing process of the multilayer circuit board. Moreover, recently, for application in AP modules with high integration / high specifications, circuit boards with eight to ten layers are required. In this case, in the process of first forming the fine circuit patterns during the ETS process and then performing the multilayer stacking process, damage occurs due to thermal stress and other factors being applied to the fine circuit patterns, thus making it difficult to properly achieve the fine circuit patterns.

[0085] Furthermore, when manufacturing circuit boards using the ETS method, a separate ETS core layer is required. In this case, additional processes are needed for the eventual removal of the ETS core layer when manufacturing circuit boards using the ETS method.

[0086] Furthermore, when manufacturing circuit boards using the ETS method, when layers are stacked more than a certain number of times, there is a problem of reduced production volume due to accumulated tolerances, which in turn increases product costs. Also, because the stacking process is performed on two surfaces around the ETS core layer, there is a problem of increased pattern damage due to stress.

[0087] Furthermore, with the development of 5G technology in recent years, interest in circuit boards that may reflect it is increasing. In this context, for the application of 5G technology, the circuit board should have a highly multilayered structure, and therefore the circuit pattern should be intricate. However, in the comparative example, although intricate patterns can be formed, there is a problem of unstable protection of these intricate patterns.

[0088] Therefore, the embodiments aim to provide a new type of circuit board and its control method that can solve the reliability problem of fine patterns set at the outermost part.

[0089] Figure 3 This is a view showing a circuit board according to an embodiment, and Figure 4 yes Figure 3 A magnified view of region B.

[0090] exist Figure 3 and Figure 4 Prior to the description, the circuit board of this embodiment, the circuit board according to the embodiment, may have a multi-layer structure. Preferably, the circuit board according to the embodiment may have a structure of ten or more layers based on the number of layers of the circuit pattern. However, this is merely an example and the embodiments are not limited thereto. That is, the circuit board in the embodiment may have fewer than 10 layers, or alternatively, the circuit board may have more than 10 layers.

[0091] However, the circuit board in the embodiment is used to address the problem of the ETS method in the comparative example. In this case, the ETS method in the comparative example has the problem that manufacturing a circuit board with eight or more layers requires a significant amount of time, and therefore, in the embodiment, it will be described as having a ten-layer structure for comparison.

[0092] refer to Figures 3 to 4 The circuit board 100 includes an insulating layer 110.

[0093] Preferably, the circuit board 100 may include first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118 and 119 to achieve a ten-layer structure.

[0094] In this case, the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117 of the insulating layer 110 can be inner insulating layers disposed within the stacked insulating layer structure, and the eighth insulating layer 118 can be the uppermost insulating layer (first outermost insulating layer) disposed on the inner insulating layer, and the ninth insulating layer 119 can be the lowermost insulating layer (second outermost insulating layer) disposed below the inner insulating layer.

[0095] The first insulating layer 111 may be a core insulating layer located at the center of the stacked structure of insulating layers 110. The second insulating layer 112, the fourth insulating layer 114, the sixth insulating layer 116, and the eighth insulating layer 118 may be upper insulating layers sequentially disposed on the first insulating layer 111. In addition, the third insulating layer 113, the fifth insulating layer 115, the seventh insulating layer 117, and the ninth insulating layer 119 may be lower insulating layers sequentially disposed below the first insulating layer 111.

[0096] The insulating layer 110 may be a substrate on which a circuit capable of changing wiring is formed, and may include the entirety of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming circuit patterns on its surface.

[0097] For example, the insulating layer 110 can be rigid or flexible. For example, the insulating layer 110 can include glass or plastic. Specifically, the insulating layer 110 can include chemically tempered / semi-tempered glass such as soda-lime glass, aluminosilicate glass, etc., tempered or flexible plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc., or sapphire.

[0098] Furthermore, the insulating layer 110 may include an optically isotropic film. As an example, the insulating layer 110 may include cyclic olefin copolymers (COC), cyclic olefin polymers (COP), optically isotropic PC, optically isotropic polymethyl methacrylate (PMMA), etc.

[0099] Furthermore, at least one of the insulating layers 110 can be partially bent while having a curved surface. That is, at least one of the insulating layers 110 can be partially planar and can be partially bent while having a curved surface. Specifically, the end of at least one of the insulating layers 110 can be bent while having a curved surface, or bent or twisted while having a surface with arbitrary curvature.

[0100] Furthermore, at least one of the insulating layers 110 can be a flexible substrate. Additionally, at least one of the insulating layers 110 can be a bent or flexed substrate. In this case, at least one of the insulating layers 110 can form a wiring layout for connecting circuit components based on a circuit design, and electrical conductors can be disposed on the insulating material. Furthermore, electronic components can be mounted on at least one of the insulating layers 110, and the insulating layer 110 can form wiring configured to connect electronic components to form a circuit, and in addition to functioning as an electrical connection component, it can also mechanically fix the components.

[0101] The circuit pattern can be set on the surface of the insulating layer 110.

[0102] In other words, the circuit pattern can be set on the corresponding surfaces of the first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118 and 119 that make up the insulating layer 110.

[0103] Here, the circuit pattern may include an inner layer circuit pattern 120 and outer layer circuit patterns 130 and 140. The inner layer circuit pattern 120 may be a circuit pattern disposed inside the insulating layer 110 in the stacked structure of the circuit board, and the outer layer circuit patterns 130 and 140 may be circuit patterns disposed on the outermost side of the insulating layer 110 in the stacked structure of the circuit board.

[0104] The inner circuit pattern 120 may include a first circuit pattern 121, a second circuit pattern 122, a third circuit pattern 123, a fourth circuit pattern 124, a fifth circuit pattern 125, a sixth circuit pattern 126, and a seventh circuit pattern 127.

[0105] A first circuit pattern 121 can be disposed on the upper surface of the first insulating layer 111, and therefore the first circuit pattern 121 can be covered by the second insulating layer 112. A second circuit pattern 122 can be disposed on the lower surface of the first insulating layer 111, and therefore the second circuit pattern 122 can be covered by the third insulating layer 113. A third circuit pattern 123 can be disposed on the upper surface of the second insulating layer 112, and therefore the third circuit pattern 123 can be covered by the fourth insulating layer 114. A fourth circuit pattern 124 can be disposed on the lower surface of the third insulating layer 113, and therefore the fourth circuit pattern 124 can be covered by the fifth insulating layer 115. A fifth circuit pattern 125 can be disposed on the upper surface of the fourth insulating layer 114, and therefore the fifth circuit pattern 125 can be covered by the sixth insulating layer 116. A sixth circuit pattern 126 can be disposed on the lower surface of the fifth insulating layer 115, and therefore the sixth circuit pattern 126 can be covered by the seventh insulating layer 117. The seventh circuit pattern 127 can be disposed on the upper surface of the sixth insulating layer 116, and therefore the seventh circuit pattern 127 can be covered by the eighth insulating layer 118. The eighth circuit pattern 128 can be disposed on the lower surface of the seventh insulating layer 117, and therefore the eighth circuit pattern 128 can be covered by the ninth insulating layer 119.

[0106] The outer circuit pattern can be disposed on the surface of the outermost insulating layer disposed on the outermost side of the insulating layer 110. Preferably, the outer circuit pattern may include a lower outer circuit pattern 130, which is disposed on the lower surface of the ninth insulating layer 119 disposed at the lowermost part of the insulating layer 110.

[0107] In addition, the outer layer circuit pattern may include an upper outer layer circuit pattern 140, which is disposed on the upper surface of an eighth insulating layer 118 disposed on the uppermost part of the insulating layer 110.

[0108] In this configuration, at least one of the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 may be formed to protrude above the surface of the insulating layer. Preferably, the lower outer layer circuit pattern 130 may be formed to protrude below the lower surface of the ninth insulating layer 119. Furthermore, the upper outer layer circuit pattern 140 may be formed to protrude above the upper surface of the eighth insulating layer 118.

[0109] In other words, the upper surface of the lower outer layer circuit pattern 130 can be positioned on the same plane as the lower surface of the ninth insulating layer 119. Furthermore, the lower surface of the upper outer layer circuit pattern 140 can be positioned on the same plane as the upper surface of the primer layer 150 disposed on the upper surface of the eighth insulating layer 180.

[0110] In other words, the primer layer 150 can be disposed on the upper surface of the upper outer layer circuit pattern 140 and the eighth insulating layer 180.

[0111] In other words, the upper outer layer circuit pattern 140 may include a fine circuit pattern. Preferably, the upper outer layer circuit pattern 140 may be a fine circuit pattern with a linewidth of 10 μm or less and an inter-pattern spacing of 10 μm or less. Therefore, when the upper outer layer circuit pattern 140 is directly disposed on the eighth insulating layer 118, the contact area between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 is small, and therefore, it is possible for the upper outer layer circuit pattern 140 to separate from the eighth insulating layer 118.

[0112] Therefore, in this embodiment, a primer layer 150 is disposed between the upper outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can improve the adhesion between the upper outer layer circuit pattern 140 and the eighth insulating layer. The primer layer 150 can be disposed to completely cover the upper surface of the eighth insulating layer 118. Furthermore, the upper outer layer circuit pattern 140 can be partially disposed on the primer layer 150. Therefore, the upper surface of the primer layer 150 in the first embodiment can include a first portion contacting the upper outer layer circuit pattern 140 and a second portion contacting the lower surface of the supporting insulating layer 160, which will be described later. That is, when the upper outer layer circuit pattern 140 is formed by the SAP process, the primer layer 150 can be used to strengthen the adhesion between the eighth insulating layer 118 and the upper outer layer circuit pattern 140. Such a primer layer 150 can include polyurethane-based resin, acrylic resin, or silicone-based resin, but the embodiments are not limited to these.

[0113] At the same time, Figure 3 In the diagram, the primer layer is not disposed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130, but the primer layer may also be formed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130. However, the lower outer layer circuit pattern 130 may not be a fine circuit pattern, and therefore, the primer layer between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 may be selectively omitted.

[0114] Therefore, when the fine circuit pattern is disposed on the inner layer, the primer layer can be omitted because the circuit pattern is covered by at least one insulating layer 110. On the other hand, in the embodiment, when the fine circuit pattern is disposed on the outermost layer, since there is no insulating layer covering the fine circuit pattern, a primer layer 150 is provided to improve the adhesion between the fine circuit pattern and the insulating layer.

[0115] In the following description, the upper outer layer circuit pattern 140 will be formed from a fine circuit pattern. However, the embodiments are not limited thereto, and the lower outer layer circuit pattern 130 may also be formed from a fine circuit pattern. It will be apparent that structures for improving reliability, such as structures for strengthening bonding and preventing the collapse of the upper outer layer circuit pattern 140 described below, may also be applied to the lower outer layer circuit pattern 130.

[0116] The inner circuit pattern 120, lower outer circuit pattern 130, and upper outer circuit pattern 140 can be wiring for transmitting electrical signals and can be formed of a highly conductive metallic material. Therefore, the inner circuit pattern 120, lower outer circuit pattern 130, and upper outer circuit pattern 140 can be formed of at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the inner circuit pattern 120, lower outer circuit pattern 130, and upper outer circuit pattern 140 can be formed of a paste or solder paste comprising at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) which have excellent bonding strength. Preferably, the inner circuit pattern 120, lower outer circuit pattern 130, and upper outer circuit pattern 140 can be formed of copper (Cu), which has high conductivity and relatively low cost.

[0117] At least one of the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be formed by general circuit board manufacturing processes such as additive process, subtractive process, modified semi-additive process (MSAP), semi-additive process (SAP), etc., and their detailed description will be omitted here.

[0118] Preferably, the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are the outermost circuit patterns set on the outermost side of the circuit board, and therefore they can be formed by the SAP (semi-additive process) method.

[0119] Simultaneously, a through-hole V can be provided in the insulating layer 110. The through-hole V is provided in each insulating layer, and therefore the through-hole V can be used to electrically connect circuit patterns provided in different layers to each other.

[0120] A first through-hole Vl can be disposed in the first insulating layer 111. The first through-hole Vl can electrically connect a first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 and a second circuit pattern 122 disposed on the lower surface of the first insulating layer 111.

[0121] The second through hole V2 can be disposed in the second insulating layer 112. The second through hole V2 can be electrically connected to the first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 and the third circuit pattern 123 disposed on the upper surface of the second insulating layer 112.

[0122] The third through hole V3 can be disposed in the third insulating layer 113. The third through hole V3 can be electrically connected to the second circuit pattern 122 disposed on the lower surface of the first insulating layer 111 and the fourth circuit pattern 124 disposed on the lower surface of the third insulating layer 113.

[0123] A fourth through-hole V4 can be disposed in the fourth insulating layer 114. The fourth through-hole V4 can be electrically connected to the third circuit pattern 123 disposed on the upper surface of the second insulating layer 111 and the fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114.

[0124] The fifth through hole V5 can be disposed in the fifth insulating layer 115. The fifth through hole V5 can be electrically connected to the fourth circuit pattern 124 disposed on the lower surface of the third insulating layer 113 and the sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115.

[0125] The sixth through hole V6 can be disposed in the sixth insulating layer 116. The sixth through hole V6 can be electrically connected to the fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114 and the seventh circuit pattern 127 disposed on the upper surface of the sixth insulating layer 116.

[0126] The seventh through hole V7 can be disposed in the seventh insulating layer 117. The seventh through hole V7 can be electrically connected to the sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115 and the eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117.

[0127] The eighth through hole V1 can be provided in the eighth insulating layer 118. The eighth through hole V8 can be electrically connected to the seventh circuit pattern 127 provided on the upper surface of the sixth insulating layer 116 and the upper outer layer circuit pattern 140 provided on the upper surface of the primer layer 150.

[0128] The ninth through-hole V9 can be disposed in the ninth insulating layer 119. The ninth through-hole V9 can be electrically connected to the eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117 and the lower outer layer circuit pattern 130 disposed on the lower surface of the ninth insulating layer 119.

[0129] The through-hole V, as described above, can be formed by filling the interior of each through-hole formed in the insulating layer with a metallic material.

[0130] Through-holes can be formed by any of mechanical, laser, and chemical processing methods. When forming through-holes by mechanical processing, methods such as milling, drilling, and routing can be used. When forming through-holes by laser processing, UV or CO2 laser methods can be used. And when forming through-holes by chemical processing, chemicals including aminosilanes, ketones, etc., can be used to open the insulating layer 110.

[0131] Meanwhile, laser processing is a cutting method that concentrates light energy on a surface to melt and evaporate parts of the material to obtain a desired shape. It can easily process complex formations programmed by computer and can process composite materials that are difficult to cut by other methods.

[0132] Furthermore, laser processing can achieve a cutting diameter of at least 0.005 mm and has a wide range of thicknesses that can be processed.

[0133] Yttrium aluminum garnet (YAG) lasers, CO2 lasers, or ultraviolet (UV) lasers are preferred as laser processing drill bits. YAG lasers can process both copper foil layers and insulating layers, while CO2 lasers can only process insulating layers.

[0134] When forming through-holes, the first to ninth through-holes V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be formed by filling the interior of the through-holes with a conductive material. The metallic material forming the first to ninth through-holes V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be any material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material can be filled by any of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing, or a combination thereof.

[0135] Meanwhile, a protective layer can be disposed on the outermost side of the circuit board 100. Preferably, the first protective layer 170 can be disposed on the eighth insulating layer 118 (preferably on the primer layer 150). In addition, the second protective layer 175 can be disposed below the ninth insulating layer 119.

[0136] The first protective layer 170 and the second protective layer 175 may be formed by at least one layer using any one or more of solder resist (SR), oxide, and Au. Preferably, the first protective layer 170 and the second protective layer 175 may be solder resist.

[0137] Meanwhile, a first protective layer 170 is disposed on the primer layer 150. The first protective layer 170 can be used to protect the surface of the upper outer layer circuit pattern 140 while supporting the upper outer layer circuit pattern 140 disposed on the primer layer 150.

[0138] In other words, the first protective layer 170 may partially overlap with the upper outer layer circuit pattern 140 disposed on the primer layer 150. The area of ​​the first protective layer 170 may be smaller than the area of ​​the eighth insulating layer 118. The area of ​​the first protective layer 170 may be smaller than the area of ​​the primer layer 150. The first protective layer 170 is partially or entirely disposed on the primer layer 150 and the upper outer layer circuit pattern 140, and therefore the first protective layer 170 may include an opening region exposing the surface of the upper outer layer circuit pattern 140.

[0139] The first protective layer 170 may include an opening region having a shape such as a groove. Preferably, the first protective layer 170 includes an opening region exposing an upper outer layer circuit pattern 140 disposed in the first region R1 and the second region R2. In this case, the first region R1 and the second region R2 may be opening regions in which the surfaces of the upper outer layer circuit pattern 140 are exposed. That is, device mounting pads on which chip devices are mounted, core pads or BGA pads used as dies for connection to external boards, and traces used as signal transmission lines are included in the first region R1 and the second region R2. Furthermore, the first protective layer 170 has opening regions exposing the surfaces of the device mounting pads, core pads, and BGA pads in the first region R1 and the second region R2.

[0140] Therefore, the first region R1 and the second region R2 can refer to the areas on the surface of the outer circuit pattern 140 that are exposed by the first protective layer 170 in the upper region of the outer circuit pattern 140 and the primer layer 150.

[0141] That is, the circuit board includes a first region R1, a second region R2, and a third region R3. The first region R1 and the second region R2 are opening regions in which the surface of the upper outer layer circuit pattern 140 should be exposed through the first protective layer 170, and the third region R3 can be a buried region in which the surface of the upper outer layer circuit pattern 140 should be covered by the protective layer 170.

[0142] That is, the first region R1 is the region of the upper outer layer circuit pattern 140, in which the first pad 142 and traces 141 for electrical connection to components such as chips are disposed within the upper outer layer circuit pattern 140. Therefore, the first protective layer 170 may have an opening region that exposes the surface of the first pad 142 included in the first region R1. Furthermore, the second region R2 is the region in the upper outer layer circuit pattern 140 in which second pads 143 are disposed corresponding to core pads or BGA pads used as bonding pads for dies to an external board.

[0143] Furthermore, the upper outer layer circuit pattern 140 disposed in the first region R1 as described above may have reliability issues such as collapse or friction due to various factors. Moreover, the traces 141 constituting the upper outer layer circuit pattern 140 are fine circuit patterns, and therefore the traces 141 have a linewidth W1 of 10 μm or less and a spacing of 10 μm or less, and are disposed on the primer layer 150. Therefore, the traces 141 disposed in the first region R1 may have the problem of being easily collapsed or rubbed by various small external impacts.

[0144] Therefore, in this embodiment, in order to improve the reliability of the upper outer layer circuit pattern 140 provided on the first region Rl, a protective layer 170 is also formed on the primer layer 150 corresponding to the first region Rl.

[0145] In other words, the first protective layer 170 can be disposed in the area on the upper surface of the primer layer 150 where the upper outer layer circuit pattern 140 is not disposed. For example, the first protective layer 170 can be disposed on the upper surface of the primer layer 150, and therefore the first protective layer 170 can be disposed between the upper outer layer circuit patterns 140 on the first region R1.

[0146] In this case, the upper outer layer circuit pattern 140 includes a first outer layer circuit pattern disposed in the first region R1 and the second region R2, and a second outer layer circuit pattern formed in the third region R3.

[0147] In addition, the upper surface of the primer layer 150 may include a first upper surface corresponding to the first region R1, a second upper surface corresponding to the second region R2, and a third upper surface R3 corresponding to the third region.

[0148] In this case, such as Figure 3 and Figure 4 As shown, the first protective layer 170 can be completely disposed on the primer layer 150 without dividing the first region R1, the second region R2, and the third region R3. That is, the first protective layer 170 can be disposed in the region between the first outer layer circuit pattern and the region between the second outer layer circuit pattern.

[0149] Therefore, the first protective layer 170 includes a first portion disposed in the first region R1, a second portion disposed in the second region R2, and a third portion disposed in the third region R3.

[0150] In this case, the first protective layer 170 can have a different height for each area.

[0151] In the first region R1 and the second region R2, the surface of the upper outer layer circuit pattern 140 should be exposed, and in the third region R3, the surface of the upper outer layer circuit pattern 140 should be covered by a protective layer.

[0152] Here, the upper outer layer circuit pattern 140 disposed in the first region R1 and the second region R2 may have different widths depending on the function. For example, as described above, the upper outer layer circuit pattern 140 disposed in the first region R1 and the second region R2 may include a first pad 142, a second pad 143 and a trace 141.

[0153] In this configuration, trace 141 can have a width of 10 μm or less. Furthermore, the first pad can have a width of approximately 45 μm. Additionally, the second pad 143 can have a width W3 between 100 μm and 300 μm.

[0154] Therefore, in the embodiment, in the opening region of the solder resist described above, a first protective layer 170 with a different height is formed relative to the region where the trace 141 is provided, the region where the first pad 142 is provided, and the region where the second pad 143 is provided.

[0155] That is, the first protective layer 170 may include a first part disposed in the first region R1, a second part disposed in the second region R2, and a third part disposed in the third region R3. Furthermore, at least one of the first, second, and third parts may have a different height than at least the other.

[0156] For example, the upper surface of the first part located in the first region R1 can be positioned lower than the upper surfaces of the second part located in the second region R2 and the third part located in the third region R3.

[0157] Furthermore, the upper surface of the second part can be positioned higher than the upper surface of the first part. Additionally, the upper surface of the second part can have the same height as the upper surface of the third part. That is, the upper surface of the second part can be positioned on the same plane as the upper surface of the third part.

[0158] Furthermore, the first part may include a first sub-part and a second sub-part. Additionally, the upper surfaces of the first and second sub-parts may have different heights. For example, the upper surface of the first sub-part may be positioned higher than the upper surface of the second sub-part. In this case, the first sub-part may correspond to the region in the first region R1 where the trace 141 is provided. Furthermore, the second sub-part may correspond to the region in the first region R1 where the first pad 142 is provided.

[0159] The first protective layer 170 will be described in detail below.

[0160] The first protective layer 170 can be applied over the primer layer 150. The first protective layer 170 is a solder resist.

[0161] The first protective layer 170 can be disposed between the upper outer layer circuit patterns 140 on the primer layer 150. That is, the upper outer layer circuit patterns 140 are disposed on the primer layer 150 at predetermined intervals. Furthermore, the first protective layer 170 can be disposed on the upper surface of the primer layer 150 where no upper outer layer circuit patterns 140 are disposed. Additionally, the first protective layer 170 can be selectively disposed on the upper outer layer circuit patterns 140.

[0162] In the following text, the first protective layer 170 will be described as solder resist 170.

[0163] Solder resist 170 can be applied to the area on the upper surface of the primer layer 150 where the outer circuit pattern 140 is not applied.

[0164] Therefore, the lower surface of the solder resist 170 can directly contact the upper surface of the primer layer 150. Additionally, the solder resist 170 can have a structure that directly contacts the upper outer layer circuit pattern 140.

[0165] For example, a first portion of the solder resist 170 disposed in the first region R1 can directly contact the side surface of the upper outer layer circuit pattern 140. Furthermore, a portion of the first portion of the solder resist 170 disposed in the first region R1 can directly contact the upper surface of the upper outer layer circuit pattern 140. Additionally, at least a portion of the first portion of the solder resist 170 disposed in the first region R1 can expose both the upper surface and the side surface of the upper outer layer circuit pattern 140.

[0166] Furthermore, the second portion of the solder resist 170 disposed in the second region R2 can directly contact the side surface of the upper outer layer circuit pattern 140. Additionally, the second portion of the solder resist 170 disposed in the second region R2 can directly contact a portion of the upper surface of the upper outer layer circuit pattern 140. Furthermore, the second portion of the solder resist 170 disposed in the second region R2 can expose the upper surface of the upper outer layer circuit pattern 140.

[0167] Furthermore, the third portion of the solder resist 170 disposed in the third region R3 can directly contact the side surface of the upper outer layer circuit pattern 140. Additionally, the third portion of the solder resist 170 disposed in the third region R3 can directly contact the upper surface of the upper outer layer circuit pattern 140. That is, the third portion of the solder resist 170 disposed in the third region R3 can protrude above the upper surface of the upper outer layer circuit pattern 140 at a predetermined height and can be configured to cover the upper outer layer circuit pattern 140. Specifically, the third portion of the solder resist 170 disposed in the third region R3 can be configured to surround both the side surface and the upper surface of the upper outer layer circuit pattern 140.

[0168] In this case, the solder resist 170 can have different heights for each section. Here, the height of each section of the solder resist 170 can be determined by the height of the upper outer layer circuit pattern 140.

[0169] The upper outer layer circuit pattern 140 may have a first height H1 and may be disposed on the insulating layer 110. In this case, the insulating layer 110 may refer to the insulating layer disposed on the uppermost side of a plurality of insulating layers. However, for ease of description, it will be referred to as the insulating layer 110 below. Meanwhile, a primer layer 150 may be disposed between the insulating layer 110 and the upper outer layer circuit pattern 140. In this case, the upper outer layer circuit pattern 140 may be disposed on the primer layer 150 to have a first height H1. Furthermore, the term "height" described below may correspond to "thickness".

[0170] The first height H1 of the upper outer layer circuit pattern 140 can be 12μm ± 2μm. For example, the first height H1 of the upper outer layer circuit pattern 140 can be in the range of 10μm to 14μm.

[0171] A third portion of the solder resist 170 can be disposed on the upper outer layer circuit pattern 140 to have a second height H2. In this case, the third portion of the solder resist 170 is disposed to cover the upper outer layer circuit pattern 140 in order to stably protect the upper outer layer circuit pattern 140. In this case, the second height H2 can be from 7 μm to 17 μm. When the second height H2 is less than 7 μm, the upper outer layer circuit pattern 140 buried in the third portion of the solder resist 170 may not be stably protected from various factors. Furthermore, when the second height H2 is greater than 17 μm, the overall thickness of the circuit board may increase. In addition, when the second height H2 is greater than 17 μm, the manufacturing cost of the circuit board may increase.

[0172] Meanwhile, the second portion 173 of the solder resist 170 disposed in the second region R2 includes an opening region R2-2 and may have a second height H2 from the upper surface of the solder resist 170. That is, the second portion 173 of the solder resist 170 can be configured to cover the edge region while exposing the central region of the upper surface of the upper outer layer circuit pattern 140 disposed in the second region R2. In other words, the second portion 173 may include an opening region R2-2 exposing a first portion of the upper surface of the upper outer layer circuit pattern 140, and may be configured to have a second height H2 above the second portion of the upper outer layer circuit pattern 140. In this case, the second height H2 may correspond to the height of the third portion of the solder resist 170.

[0173] In this case, the upper outer layer circuit pattern 140 included in the second region R2 is the second pad 143. The second pad 143 can be a BGA pad or a core pad as described above. Therefore, the second pad 143 can have a relatively larger width than other pads. As an example, the second pad 143 can have a width W3 of 100 μm to 300 μm. Furthermore, because the second pad 143 has a larger width, it is not significantly affected by the exposure resolution. That is, the second pad 143 has a relatively large width, and therefore there is no reliability problem even when only a portion of the upper surface of the second pad 143, rather than the entire surface, is exposed. In other words, even when only a portion of the upper surface of the second pad 143 is exposed, the die function for bonding with another outer board is not significantly affected. Therefore, the second portion 173 can be configured to cover a portion of the upper surface of the second pad 143 as described above. In detail, the second part 173 has a second height H2, is provided to protrude above the upper surface of the second pad 143, and has an opening region R2-2 that exposes a portion of the upper surface of the second pad 143.

[0174] Meanwhile, the first part of the solder resist 170 disposed in the first region Rl can have a height lower than the second height. In this case, the first part can have a different height for each region.

[0175] In other words, the first region R1 can be divided into multiple sub-regions. For example, the first region R1 may include a first sub-region R1-1 and a second sub-region R1-2. In this case, the first sub-region R1-1 may be the region of the first region R1 where the trace 141 is provided. Furthermore, the second sub-region R1-2 may be the region of the first region R1 where the first pad 142 is provided.

[0176] Meanwhile, the second region R2 can also be referred to as the third sub-region of the first region R1. That is, when the solder resist 170 is divided into open and non-open regions, the open region of the solder resist 170 can be divided into a first sub-region R1-1 in which traces 141 are provided, a second sub-region R1-2 in which first pads 142 are provided, and a third sub-region R2 in which second pads 143 are provided. Furthermore, when the regions are divided as described above, the non-open region of the solder resist 170 can be referred to as the second region.

[0177] Meanwhile, the first part of the solder resist 170 may include a first sub-part 171 and a second sub-part 172.

[0178] The first sub-part 171 can be provided in the first sub-region R1-1 of the first region R1, where the trace 141 is provided. In addition, the second sub-part 172 can be provided in the second sub-region R1-2 of the first region R1, where the first pad 142 is provided.

[0179] In this case, the first sub-part 171 and the second sub-part 172 can have different heights. For example, the first sub-part 171 can be configured to be higher than the second sub-part 172. Specifically, the upper surface of the first sub-part 171 can be configured to be higher than the upper surface of the second sub-part 172.

[0180] The first sub-part 171 can be disposed in the first sub-region R1-1 to have a third height H3. In this case, the third height H3 can be greater than the first height H1. Therefore, the first sub-part 171 can protrude above the upper surface of the trace 141 in the first sub-region R1-1 at a predetermined height. That is, the trace 141 disposed in the first region R1 can be covered by the first sub-part 171 of the solder resist 170. Therefore, in the embodiment, the trace 141 disposed in the first region R1 corresponding to the opening region can be stably protected.

[0181] Simultaneously, the upper surface of the first sub-part 171 is positioned lower than the upper surface of the second sub-part 173. For example, the first sub-part 171 may protrude above the upper surface of the trace 141 with a height of 3 μm to 5 μm. When the protrusion height of the first sub-part 171 from the upper surface of the trace 141 is less than 3 μm, it may not stably protect the trace 141 from external factors, leading to reliability issues. Furthermore, when the protrusion height of the first sub-part 171 from the upper surface of the trace 141 is greater than 5 μm, the second sub-part 172 may not be precisely formed in the intended position. In other words, when the protrusion height of the first sub-part 171 from the upper surface of the trace 141 is greater than 5 μm, the exposure resolution is reduced, and therefore, the second sub-part 172 may not be precisely formed in the intended position. Moreover, when the second sub-part 172 cannot be precisely formed in the intended position, a portion of the upper surface of the first pad 142 may be covered by solder resist 170, leading to reliability issues.

[0182] In this configuration, the second portion 173 protrudes above the second pad 143 to have a height of 7 μm to 17 μm. Therefore, the upper surface of the first portion 171 can be positioned below the upper surface of the second portion 173.

[0183] That is, the first sub-section 171 of the solder resist 170 may be the portion initially developed during the thinning process of the solder resist 170. Furthermore, the first sub-section 171 of the solder resist 170 may be the initial exposure and development area for forming the second sub-section 172 in a precise location, as will be described later, while stably protecting the surface of the trace 141 included in the first region R1.

[0184] The second sub-region 172 of the solder resist 170 can be formed in the second sub-region R1-2 of the first region R1 where the first pad 142 is provided.

[0185] The second sub-part 172 can expose the upper surface of the first pad 142. That is, the second sub-part 172 can have a fourth height H4 that is smaller than the first height H1 of the first pad 142. Therefore, the upper surface of the second sub-part 172 can be positioned below the upper surface of the first pad 142.

[0186] The second sub-section 172 may be a portion that is developed a second time during the thinning process of the solder resist 170. That is, the second sub-section 172 may be a part of the initial developed portion. In other words, the second sub-section 172 may have a height lower than the first sub-section 171 by performing a second development on the initial developed portion.

[0187] The fourth height H4 can be determined by the first height H1. For example, the fourth height H4 can be 70% to 90% of the first height H1. For example, when the fourth height H4 is less than 70% of the first height H1, the first pad 142 may not be stably supported by the second sub-part 172 of the solder resist 170. For example, when the fourth height H4 is less than 70% of the first height H1, there may be process difficulties in forming the second sub-part 172 of the solder resist. For example, when the fourth height H4 is greater than 90% of the first height H1, a portion of the filler included in the solder resist 170 may remain on the first pad 142. For example, when the fourth height H4 is greater than 90% of the first height H1, there may be a problem of the surface of the first pad 142 being covered due to deviations in the process of forming the solder resist 160.

[0188] In this case, the first pad 142 may be a mounting pad on which a chip device is mounted and typically has a width W2 of approximately 45 μm. For example, the width W2 of the first pad 142 in the horizontal direction may be approximately 45 μm. Therefore, when the first pad 142 needs to be exposed, exposure and development should be performed precisely only in the area where the first pad 142 is located. In this case, the resolution used for exposure and development (e.g., the accuracy relative to the size and position of the exposure and development area) can increase as the thickness of the solder resist 170 in the portion to be developed decreases. Therefore, in an embodiment, the initial exposure and development of the solder resist 170 reduces the height of the solder resist 170 in the first region R1 to the level of the third height H3 described above. Furthermore, in an embodiment, a second exposure and development of the solder resist 170 reduces the height of the solder resist 170 in the second sub-region R1-2 of the first region R1 to the fourth height H4.

[0189] In this embodiment, the first sub-portion 171, the second sub-portion 172, the second portion 173, and the third portion of the solder resist 170 are formed by performing a two-step exposure and development process as described above. Therefore, in this embodiment, the first sub-portion 171 of the solder resist 170 is positioned to protrude above the upper surface of the trace 141 in the first sub-region R1-1, and thus can stably protect the trace 141. Furthermore, the second sub-portion 172 of the solder resist 170 can expose the entire upper surface of the first pad 142 in the second sub-region R1-2.

[0190] In this configuration, during the secondary exposure and development process, when only the portion containing the first pad 142 can be precisely exposed and developed, the second sub-part 172 can be essentially absent. That is, in this configuration, the solder resist 170 can be configured to have an overall third height H3, while also including an opening on the upper surface of the exposed pad.

[0191] However, due to process variations or various reasons, it is difficult to precisely expose and develop only the portion where the first pad 142 is located, and therefore, the exposure and development positions may be shifted due to process variations. In this case, during the secondary exposure and development process, the solder resist on the first pad 142 may not be fully developed, and some may remain. Furthermore, because the upper surface of the first pad 142 is not exposed, this leads to reliability issues.

[0192] Therefore, in the embodiment, taking into account the possible positional shifts due to process deviations or various reasons, in the secondary exposure and development process, the width W4, which is greater than the width W2 of the first pad 142, is exposed and developed.

[0193] Therefore, the second sub-part 172 can be configured to surround at least a portion of the side surface of the first pad 142. Additionally, a secondary development process can be performed so that the second sub-part 172 has the same height as the first pad 142. However, in this case, a portion of the solder resist may remain on the first pad 142, potentially causing reliability issues. Therefore, in this embodiment, the upper surface of the second sub-part 172 is positioned lower than the upper surface of the first pad 142 to resolve the aforementioned reliability problem.

[0194] Solder resist 170 can be a photoresist film. Solder resist 170 can have a structure in which resin and filler are mixed.

[0195] For example, solder resist 170 may include fillers such as BaSO4, SiO2 and Talc, and its content may be from 20wt% to 35wt%.

[0196] In this case, when the filler content included in the solder resist 170 is less than 20 wt%, the upper outer layer circuit pattern 140 may not be stably protected by the solder resist 170. Additionally, when the filler content included in the solder resist 170 is greater than 35 wt%, some of the filler may remain on the upper outer layer circuit pattern 140 during the development of the solder resist 170, and therefore, reliability issues may arise, or an additional filler removal process should be performed.

[0197] Meanwhile, in the embodiment, the upper surface of the third part of the solder resist 170 is the part that is not exposed and developed.

[0198] In addition, the first sub-section 171, the second sub-section 172, and the second sub-section 173 of the solder resist 170 are the parts that are exposed and developed.

[0199] Therefore, the filler can be partially exposed on the upper surfaces of the first sub-section 171, the second sub-section 172, and the second section 173. However, in the third section of the solder resist 170, the filler may not be directly exposed.

[0200] Therefore, the surface roughness of each of the first sub-part 171, the second sub-part 172, and the second part 173 may be different from the surface roughness of the third part of the solder resist 170. For example, the surface roughness of each of the first sub-part 171, the second sub-part 172, and the second part 173 may be greater than the surface roughness of the third part of the solder resist 170.

[0201] The circuit board in this embodiment is a multilayer circuit board with eight or more layers, and includes an outer circuit pattern disposed on an outer insulating layer positioned at the top of the multilayer and protruding above the surface of the outer insulating layer. In this case, the outer circuit pattern includes a first outer circuit pattern positioned in first and second regions without solder resist and a second outer circuit pattern positioned in a third region with solder resist. In this case, the second outer circuit pattern can be supported and protected by solder resist, but the first outer circuit pattern does not have a support layer capable of supporting it, and therefore there is a problem that the first outer circuit pattern may easily collapse due to various factors.

[0202] Therefore, in the embodiments, the solder resist in the first and second regions is not completely removed and is retained, thereby supporting and protecting the first outer layer circuit pattern. Thus, in the embodiments, problems such as collapse or friction of the first outer layer circuit pattern in the first and second regions can be solved by refining the outer layer circuit pattern, thereby improving product reliability. Specifically, in the embodiments, problems such as collapse or friction of traces included in the first outer layer circuit pattern in the first region can be solved, thereby improving product reliability.

[0203] Meanwhile, the solder resist according to the embodiment includes a first portion disposed in a first region, a second portion disposed in a second region, and a third portion disposed in a third region. Furthermore, the second portion may have an opening and have the same height as the third portion. Additionally, the first portion includes a first sub-part having a height lower than the heights of the second and third portions, and a sub-part having a height lower than the height of the first sub-part. The first sub-part may be formed to cover the surface of the traces of the first outer layer circuit pattern disposed in the first region. Furthermore, the second sub-part may have a height lower than the height of the first pad while exposing the surface of the first pad of the first outer layer circuit pattern disposed in the first region. That is, in the embodiment, the first sub-part, second sub-part, second portion, and third portion are formed by exposing and developing the solder resist in two steps. Therefore, in the embodiment, the exposure resolution can be improved. Additionally, in the embodiment, the surface of the traces can be stably protected by the first sub-part in the first region, thereby improving product reliability.

[0204] Furthermore, in this embodiment, the surfaces of the insulating layer and the primer layer have a structure covered by solder resist, thus resolving reliability issues caused by exposure of the surface of the insulating layer or a portion of the primer layer. Specifically, exposure of the surface of the insulating layer or a portion of the primer layer refers to a specific space existing between the outer circuit pattern and the solder resist. Additionally, when such a space exists, residual solution, such as adhesive components, may remain within it, or voids may be created due to this residual solution, leading to reliability problems. On the other hand, in this embodiment, the solder resist can be used to fill the space, thereby resolving the reliability issue.

[0205] Additionally, in this embodiment, a second sub-part of the solder resist is disposed around the first pad, and a first sub-part is disposed around the second sub-part. Furthermore, the first sub-part prevents movement of the adhesive member (e.g., solder ball) to be disposed on the first pad. That is, the first sub-part acts as a barrier that can fix the position of the adhesive member. Therefore, in this embodiment, reliability problems such as short circuits caused by a portion of the adhesive member flowing downwards can be solved.

[0206] Furthermore, in this embodiment, exposure and development methods are used instead of sandblasting or plasma methods for removing the solder resist. In this case, when removing the solder resist by sandblasting or plasma methods, deformation of the outer layer circuit pattern may occur, and in some cases, the cross-section of the outer layer circuit pattern may have a triangular shape. Moreover, when the cross-section of the outer layer circuit pattern is triangular, the adhesive member may not be stably mounted on the outer layer circuit pattern, leading to reliability issues. Conversely, in this embodiment, the solder resist can be removed without deforming the outer layer circuit pattern, thereby improving reliability.

[0207] Furthermore, the circuit board in this embodiment can be applied to 5G communication systems, and therefore, can minimize high-frequency transmission losses, thereby further improving reliability. Specifically, the circuit board in this embodiment can be used at high frequencies and can reduce wave loss.

[0208] Furthermore, in the embodiments, various methods can be used to remove a portion of the solder resist 170 from the first region R1 and the second region R2 during the formation of the solder resist 170 as described above. For example, a portion of the solder resist 170 can be removed by physical or chemical methods. For example, the solder resist 170 can be removed by methods such as plasma or sandblasting.

[0209] However, when the solder resist 170 is removed by physical or chemical methods, the upper outer layer circuit pattern 140 is also removed during this process, causing the upper outer layer circuit pattern 140 to deform. For example, because a portion of the upper outer layer circuit pattern 140 is removed along with the solder resist 170 during the removal process, the upper outer layer circuit pattern 140 may have a triangular cross-section. Furthermore, when the upper portion of the upper outer layer circuit pattern 140 has a triangular shape, bonding components such as solder balls may not be stably fixed to the upper outer layer circuit pattern 140, thus leading to reliability issues. In addition, removing the protective layer by physical or chemical methods requires expensive equipment, which may increase manufacturing costs.

[0210] On the other hand, in the embodiment, the solder resist 170 can be removed by applying a thinning method via exposure and development processes, so that each area has the desired height. Furthermore, the upper outer layer circuit pattern 140 is not deformed during the exposure and development processes, and the cross-sectional shape of the upper outer layer circuit pattern 140 can be maintained as a quadrilateral shape.

[0211] The second sub-part 172 of the solder resist 170 according to the embodiment will be described in detail below.

[0212] Figure 5 This is an enlarged view of the second sub-part according to the embodiment. Figure 6a This is a view used to describe the first shift of the second sub-part according to an embodiment, and Figure 6b This is a view used to describe the second shift of the second sub-part according to an embodiment.

[0213] refer to Figure 5 , 6a And 6b, the second sub-part 172 can be formed by performing a second exposure and development, such that a portion of the first sub-part 171 in the first region R1 that was initially exposed and developed has a width W4 that is greater than the width W2 of the first pad 142.

[0214] In this case, the second sub-part 172 can have a height lower than the height of the first pad 142. That is, the upper surface of the second sub-part 172 can be positioned lower than the upper surface of the first pad 142.

[0215] The second sub-part 172 can be configured to contact at least a portion of the side surface of the first pad 142.

[0216] The first pad 142 may include a major axis and a minor axis. Furthermore, the width W2-1 of the major axis of the first pad 142 may be approximately 80 μm. Furthermore, the width W2-2 of the minor axis of the first pad 142 may be approximately 45 μm.

[0217] Furthermore, the width W4 of the area to be subjected to secondary exposure and development can have a width W4-1 in the longitudinal axis direction of the first pad 142 and a width W4-2 in the transverse axis direction of the first pad 142. In this case, the width W4-1 can be 10 μm to 12 μm larger than the width W2-1 of the major axis of the first pad 142. Additionally, the width W4-2 can be 10 μm to 12 μm larger than the width W2-2 of the minor axis of the first pad 142.

[0218] In this case, the second sub-parts 172 can be respectively disposed on multiple side surfaces of the first pad 142. For example, the second sub-parts 172 can be disposed around the periphery of the first pad 142.

[0219] For example, the second sub-part 172 can be formed to have a width of 5-1 W5-1 on the first side surface of the first pad 142. Furthermore, the second sub-part 172 can be formed to have a width of 5-2 W5-2 on the second side surface of the first pad 142. Furthermore, the second sub-part 172 can be formed to have a width of 5-3 W5-3 on the third side surface of the first pad 142. Furthermore, the second sub-part 172 can be formed to have a width of 5-4 W5-4 on the fourth side surface of the first pad 142.

[0220] In this case, as an example, widths W5-1 (5-1), W5-2 (5-2), W5-3 (5-3), and W5-4 (5-4) can be identical. This is because exposure and development are performed at precise locations during the secondary exposure and development process. In this case, widths W5-1 (5-1), W5-2 (5-2), W5-3 (5-3), and W5-4 (5-4) can be between 10 μm and 12 μm.

[0221] Meanwhile, one side surface of the first pad 142 can be directly connected to the trace 141. Therefore, a portion of the second sub-part 172 can be configured to expose a portion of the upper surface of the trace 141.

[0222] In other words, trace 141 includes a first portion 141a directly connected to the side surface of the first pad 142 and a second portion other than the first portion 141a. Furthermore, the surface of the first portion 141a can be exposed by the second sub-portion 172. Additionally, the surface of the second portion 141b can be covered by the first sub-portion 171.

[0223] Meanwhile, in the embodiment, the widths W5-1 (5-1), W5-2 (5-2), W5-3 (5-3), W5-3 (5-3), and W5-4 (5-4) of the second sub-part 172 can be different from each other. This is because the exposure and development were not performed at the precise position corresponding to the center of the first pad 142, and positional shifts occurred due to process deviations in the secondary exposure and development process. Furthermore, in the embodiment, to prepare for this situation, the width of the area to be secondary exposed and developed is greater than the width of the first pad 142.

[0224] Therefore, as Figure 6a As shown, the 5-3 width 'W5-3' of the second sub-part 172 provided on the third side surface of the first pad 142 and the 5-4 width 'W5-4' of the second sub-part 172 provided on the fourth side surface opposite to the third side surface can be different from each other.

[0225] In this case, the sum of the widths of 5-3 width 'W5-3' and 5-4 width 'W5-4' can be between 20 μm and 24 μm.

[0226] In addition, such as Figure 6b As shown, the maximum positional offset to one side surface of the first pad 142 can occur in the second sub-part 172. In this case, the second sub-part 172 can be configured to have a width of 5-3 "W5-3" only on the third side surface of the first pad 142. Alternatively, the second sub-part 172 may not be provided on the fourth side surface of the first pad 142, but the first sub-part 171 may be provided thereon. In this case, the 5-3 width "W5-3" can be 20 μm to 24 μm.

[0227] Figure 7 This is a view used to illustrate the reliability of the solder resist structure according to the embodiments and comparative examples.

[0228] like Figure 7 As shown in (a), in the comparative example, solder resist may be applied around trace 141a and first pad 142a, but the solder resist is formed to have a height lower than the first pad 142a or trace 141a.

[0229] Therefore, in the comparative example, when an adhesive component such as solder ball SB is disposed on the first pad 142a, there is no structure for fixing the position of the adhesive component, and therefore, in the state where the first pad 142a is disposed, this position may be moved by various factors. As an example, in the state where the adhesive component is disposed on the first pad 142a, the adhesive component may be moved to the position where the trace 141a is disposed by various factors (e.g., temperature or positional deviation, etc.), and therefore, reliability problems such as short circuits may occur because the trace 141a and the first pad 142a are in electrical contact with each other.

[0230] On the other hand, such as Figure 7 As shown in (b), in this embodiment, a second sub-part 172 of solder resist 170 is disposed around the first pad 142, and a first sub-part 171 is disposed around it. Furthermore, the first sub-part 171 can prevent movement of the adhesive member (e.g., solder ball SB) to be disposed on the first pad 142. That is, the upper surface of the first sub-part 171 is positioned above the upper surface of the first pad 142 and thus acts as a barrier capable of fixing the position of the adhesive member. Therefore, in this embodiment, reliability problems such as short circuits caused by a portion of the adhesive member flowing downwards can be solved.

[0231] Figure 8 This is a view used to describe the surface roughness of each part of the solder resist according to an embodiment.

[0232] In this embodiment, the solder resist 170 may have different surface roughness for each portion. For example, the upper surface of the third portion or the upper surface of the second portion 173 of the solder resist 170 may be an undeveloped surface. Conversely, the upper surface of the first portion of the solder resist 170, specifically the upper surface of the first sub-portion 171 or the upper surface of the second sub-portion 172, may be a progressively developed surface. Furthermore, filler is present in the solder resist 170. Therefore, filler may be exposed on the upper surface of the first sub-portion 171 or the upper surface of the second sub-portion 172 through progressive development. Moreover, the surface roughness of the upper surface of the first sub-portion 171 or the upper surface of the second sub-portion 172 may be greater than the surface roughness of the upper surface of the third portion or the second portion 173.

[0233] For example, the upper surface of the third part of the solder resist 170 or the upper surface of the second part 173 may have a surface roughness different from the surface roughness of the upper surface of the first sub-part 171 or the upper surface of the second sub-part 172.

[0234] In other words, the upper surface of the first sub-part 171 or the upper surface of the second sub-part 172 is a surface thinned by the developer after the exposure and development process is performed. Furthermore, the third or second part 173 of the solder resist 170 is a surface cured by exposure.

[0235] Therefore, the surface roughness Ra of the centerline of the upper surface of the first sub-part 171 or the upper surface of the second sub-part 172 can be 1.0 μm or greater.

[0236] Furthermore, the surface roughness Ra of the centerline of the upper surface of the third or second part 173 of the solder resist 170 can be in the range of 0.01 μm to 0.1 μm.

[0237] Figures 9 to 19 It shows the manufacturing process in sequence. Figure 3 A view of the circuit board method shown.

[0238] refer to Figure 9 In one embodiment, firstly, a process for manufacturing an internal substrate 100-1 for manufacturing the interior of the circuit board 100 can be performed.

[0239] The process used to manufacture the inner layer substrate 100-1 will be briefly described.

[0240] The inner substrate 100-1 may include an insulating layer, or optionally include multiple insulating layers.

[0241] exist Figure 9 The figure shows an inner substrate 100-1 having a seven-layer insulating layer structure, but the embodiments are not limited thereto. For example, the inner substrate 100-1 may include fewer than seven layers, or alternatively more than seven insulating layers.

[0242] The inner layer substrate 100-1 may include any remaining insulating layers other than the insulating layer disposed on the outermost layer of the circuit board 100. For example, the inner layer substrate 100-1 may include an insulating layer disposed on the uppermost part of the circuit board 100 and any remaining insulating layers other than the insulating layer disposed on the lowermost part of the circuit board 100.

[0243] The process for fabricating the inner layer substrate 100-1 is briefly described. First, the first insulating layer 111 is fabricated.

[0244] Then, when the first insulating layer 111 is prepared, a first through hole V1 is formed in the first insulating layer 111, and a circuit pattern 121 and a second circuit pattern 122 are formed on the upper and lower surfaces of the first insulating layer 111, respectively.

[0245] Subsequently, a second insulating layer 112 is formed on the first insulating layer 111, and a third insulating layer 113 is formed below the first insulating layer 111.

[0246] Next, a second through-hole V2 is formed in the second insulating layer 112, and a third circuit pattern 123 is formed on the upper surface of the second insulating layer 112. In addition, a third through-hole V3 is formed in the third insulating layer 113, and a fourth circuit pattern 124 is formed below the lower surface of the third insulating layer 113.

[0247] Subsequently, a fourth insulating layer 114 is formed on the second insulating layer 112, and a fifth insulating layer 115 is formed below the third insulating layer 113.

[0248] Next, a fourth through-hole V4 is formed in the fourth insulating layer 114, and a fifth circuit pattern 125 is formed on the upper surface of the fourth insulating layer 114. In addition, a fifth through-hole V5 is formed in the fifth insulating layer 115, and a sixth circuit pattern 126 is formed below the lower surface of the fifth insulating layer 115.

[0249] Subsequently, a sixth insulating layer 116 is formed on the fourth insulating layer 114, and a seventh insulating layer 117 is formed below the fifth insulating layer 115.

[0250] Next, a sixth through-hole V6 is formed in the sixth insulating layer 116, and a seventh circuit pattern 127 is formed on the upper surface of the sixth insulating layer 116. In addition, a seventh through-hole V7 is formed in the seventh insulating layer 117, and an eighth circuit pattern 128 is formed below the lower surface of the seventh insulating layer 117.

[0251] Since the process for manufacturing the inner layer substrate 100-1 is a known technology in the technical field to which this invention pertains, its detailed description will be omitted.

[0252] refer to Figure 10 When manufacturing the inner layer substrate 100-1, an eighth insulating layer 118 corresponding to the first outermost insulating layer is formed on the upper surface of the inner layer substrate 100-1. In addition, a ninth insulating layer 119 corresponding to the second outermost insulating layer is formed below the lower surface of the inner layer substrate 100-1.

[0253] In this configuration, when the eighth insulating layer 118 and the ninth insulating layer 119 are stacked, a primer layer 150 can be disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, respectively, and a metal layer 155 can be disposed on the primer layer 150. The metal layer 155 can be used to planarize the eighth insulating layer 118 and the ninth insulating layer 119 to achieve a uniform height. For example, the metal layer 155 can be disposed to improve the stacking reliability of the eighth insulating layer 118 and the ninth insulating layer 119.

[0254] The primer layer 150 can be used to increase the bonding strength between the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 respectively disposed on and below the eighth insulating layer 118 and the ninth insulating layer 119. That is, when the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are disposed without the primer layer 150, the bonding strength between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 is low, and therefore they may separate from each other.

[0255] At the same time, Figure 10 The diagram illustrates that a primer layer 150 is disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, but the embodiment is not limited to this. For example, the primer layer 150 can be selectively disposed on the surface of the insulating layer where a fine circuit pattern is to be disposed. That is, when only the lower outer layer circuit pattern 130 is a fine circuit pattern, the primer layer 150 can be disposed only on the lower surface of the ninth insulating layer 119. Similarly, when only the upper outer layer circuit pattern 140 is a fine circuit pattern, the primer layer 150 can be disposed only on the upper surface of the eighth insulating layer 118. Furthermore, when both the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are fine circuit patterns, the primer layer 150 can be disposed on both the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119.

[0256] refer to Figure 11 When the eighth insulating layer 118 and the ninth insulating layer 119 are provided, through-holes VH are formed in the eighth insulating layer 118 and the ninth insulating layer 119, respectively. In this case, the through-holes VH can be formed not only in the eighth insulating layer 118 and the ninth insulating layer 119, but also in the primer layer 150 and the metal layer 155, respectively.

[0257] Next, refer to Figure 12 When a via VH is formed, an etching process can be performed to remove the metal layer 155 disposed on the primer layer 150. For example, after the via VH is formed, a rapid etching process can be performed to remove the metal layer 155, and thus a process for exposing the surface of the primer layer 150 can be performed.

[0258] Next, refer to Figure 13A via V forming process for filling via holes VH can be performed, and thus the upper outer layer circuit pattern 140 can be formed on the upper surface of the eighth insulating layer 118, and the lower outer layer circuit pattern 130 can be formed on the lower surface of the ninth insulating layer 119. In this case, in the embodiment, the lower outer layer circuit pattern 130 is illustrated as a general circuit pattern rather than a fine circuit pattern, but the embodiment is not limited to this, and the lower outer layer circuit pattern 130 together with the second outer layer circuit pattern can be a fine circuit pattern. Therefore, when the lower outer layer circuit pattern 130 is a general circuit pattern, the primer layer 150 between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 can be omitted.

[0259] The upper outer layer circuit pattern 140 is disposed on the upper surface of the eighth insulating layer 118. In this case, the upper outer layer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 may include portions disposed in the opening regions R1 and R2 of the first protective layer 170 and portions disposed in the disposed region R3 of the first protective layer 170. Furthermore, traces and pads for wiring lines used for signal transmission may be disposed in each of regions R1, R2, and R3.

[0260] Specifically, trace 141 and first pad 142 can be set in the first region R1. The first pad 142 can be a mounting pad on which a device is to be mounted.

[0261] Furthermore, a second pad 143 can be provided in the second region R2. The second pad 143 can be a BGA pad or a core pad. In particular, the second pad 143 can have a width greater than that of the first pad 142. Therefore, the second pad 143 is not significantly affected by the development resolution, and thus, a solder resist 170 with a shape different from that provided in the first region R1 can be provided.

[0262] Next, refer to Figure 14 Solder resist is applied to the primer layer 150 to cover the upper outer layer circuit pattern 140. The solder resist formed at this time can be applied to all regions of the first region R1, the second region R2, and the third region R3, and can be formed to have a height greater than the height of the upper outer layer circuit pattern 140.

[0263] Next, refer to Figure 15 The initial exposure process can be performed. The initial exposure process can be performed to reduce the thickness of the solder resist 170 to a specific level or less.

[0264] The initial exposure can be performed relative to the area excluding the opening R2-2 in the first region R1 and the second region R2. Preferably, the initial exposure can be performed relative to the area R2-1 in the third region and the second region R2, excluding the opening R2-2.

[0265] Here, the portion exposed by the initial exposure is solidified and not thinned in the subsequent development process.

[0266] Next, refer to Figure 16 This allows for the initial development process to be performed on portions that were not cured during the initial exposure process. In this case, the solder resist 170 formed in the initially developed portion can have a third height H3.

[0267] Primary development processes may include a thinning process performed on unexposed areas using an organic basic compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0268] Next, refer to Figure 17 A secondary exposure process can be performed. A secondary exposure process can be performed to reduce the thickness of a portion of the solder resist 170 exposed in the initial exposure to a specific level or less.

[0269] A second exposure can be performed on the first sub-region R1-1 within the first region R1. In other words, a second exposure process can be performed only on the first sub-region R1-1, which was not exposed in the initial exposure process.

[0270] That is, a secondary exposure process can be performed on the area in the second region R2 excluding the opening R2-2 and the area in the second sub-region R1-2 where the first pad 142 is formed.

[0271] Next, refer to Figure 18 A secondary development process can be performed on the portions that were not exposed in the secondary exposure process. In this case, the secondary development process can be performed by removing only a portion of the solder resist 170 through thickness control, without completely removing the solder resist 170 from the unexposed portions. Preferably, based on the height of the first pad 142, the secondary development process can be performed by thinning the solder resist 170 so that it has a height lower than the upper surface of the first pad 142 and a height higher than the lower surface of the first pad 142.

[0272] In a secondary development process, a thinning process may be performed on unexposed areas using an organic basic compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0273] Next, refer to Figure 19The process of forming the second protective layer 175 can be performed. In this case, the second protective layer 175 can be formed together with the solder resist 170 corresponding to the first protective layer.

[0274] Meanwhile, in the embodiments, the above-described circuit board can be used to manufacture the packaging substrate.

[0275] For example, an adhesive portion (not shown) may be provided on the first pad 142 of the circuit board. Furthermore, a chip may be provided on the adhesive portion.

[0276] For example, a plurality of first pads 142 may be formed to be spaced apart in the width direction, and a plurality of chips may be mounted on the plurality of first pads.

[0277] For example, any one of the following chips can be mounted on pad 142: a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller.

[0278] For example, at least two different chips among a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller can be mounted on the pads.

[0279] The circuit board in this embodiment is a multilayer circuit board with eight or more layers and includes an outer layer circuit pattern. The outer layer circuit pattern is disposed on an outer insulating layer positioned at the top of the multilayer and protrudes above the surface of the outer insulating layer. In this case, the outer layer circuit pattern includes a first outer layer circuit pattern positioned in first and second regions without solder resist and a second outer layer circuit pattern positioned in a third region with solder resist. In this case, the second outer layer circuit pattern can be supported and protected by solder resist, but the first outer layer circuit pattern does not have a support layer capable of supporting it, and therefore there is a problem that the first outer layer circuit pattern may easily collapse due to various factors.

[0280] Therefore, in the embodiments, the solder resist in the first and second regions is not completely removed and is retained, thereby supporting and protecting the first outer layer circuit pattern. Thus, in the embodiments, problems such as collapse or friction of the first outer layer circuit pattern in the first and second regions can be addressed by refining the outer layer circuit pattern, thereby improving product reliability. Specifically, in the embodiments, problems such as collapse or friction of traces included in the first outer layer circuit pattern in the first region can be addressed, thereby improving product reliability.

[0281] Meanwhile, the solder resist according to the embodiment includes a first portion disposed in a first region, a second portion disposed in a second region, and a third portion disposed in a third region. Furthermore, the second portion may have an opening and have the same height as the third portion. Additionally, the first portion includes a first sub-part having a height lower than the heights of the second and third portions, and a sub-part having a height lower than the height of the first sub-part. The first sub-part may be formed to cover the surface of the traces of the first outer layer circuit pattern disposed in the first region. Furthermore, the second sub-part may have a height lower than the height of the first pad while exposing the surface of the first pad of the first outer layer circuit pattern disposed in the first region. That is, in the embodiment, the first sub-part, second sub-part, second portion, and third portion are formed by exposing and developing the solder resist in two steps. Therefore, in the embodiment, the exposure resolution can be improved. Additionally, in the embodiment, the surface of the traces can be stably protected by the first sub-part in the first region, thereby improving product reliability.

[0282] Furthermore, in this embodiment, the surfaces of the insulating layer and the primer layer have a structure covered by solder resist, thus resolving reliability issues caused by exposure of the surface of the insulating layer or a portion of the primer layer. Specifically, exposure of the surface of the insulating layer or a portion of the primer layer refers to a specific space existing between the outer circuit pattern and the solder resist. Additionally, when such a space exists, residual solution, such as adhesive components, may remain within it, or voids may be created due to this residual solution, leading to reliability problems. On the other hand, in this embodiment, the solder resist can be used to fill the space, thereby resolving the reliability issue.

[0283] Additionally, in this embodiment, a second sub-part of the solder resist is disposed around the first pad, and a first sub-part is disposed around the second sub-part. Furthermore, the first sub-part prevents movement of the adhesive member (e.g., solder ball) to be disposed on the first pad. That is, the first sub-part acts as a barrier that can fix the position of the adhesive member. Therefore, in this embodiment, reliability problems such as short circuits caused by a portion of the adhesive member flowing downwards can be solved.

[0284] Furthermore, in this embodiment, exposure and development methods are used instead of sandblasting or plasma methods for removing the solder resist. In this case, when removing the solder resist by sandblasting or plasma methods, deformation of the outer layer circuit pattern may occur, and in some cases, the cross-section of the outer layer circuit pattern may have a triangular shape. Moreover, when the cross-section of the outer layer circuit pattern is triangular, the adhesive member may not be stably mounted on the outer layer circuit pattern, leading to reliability issues. Conversely, in this embodiment, the solder resist can be removed without deforming the outer layer circuit pattern, thereby improving reliability.

[0285] Furthermore, the circuit board of the embodiment can be applied to 5G communication systems, and therefore, can minimize high-frequency transmission losses, thereby further improving reliability. Specifically, the circuit board of the embodiment can be used at high frequencies and can reduce wave loss.

[0286] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, those skilled in the art can combine or modify the features, structures, and effects described in each embodiment with respect to other embodiments. Therefore, content related to such combinations and modifications should be understood as being included within the scope of the embodiments.

[0287] The embodiments have been largely described above, but these embodiments are merely examples and do not limit the embodiments. Those skilled in the art will appreciate that various changes and applications not mentioned above can be made without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be varied. Furthermore, it should be understood that differences associated with such changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Insulating layer; A circuit layer disposed on the insulating layer; as well as A protective layer is disposed on the insulating layer and the circuit layer. The protective layer includes: A first part, the first part being disposed circumferentially around the side surface of the circuit layer and having a second height, the second height being less than the first height of the circuit layer; and The second part is configured to surround the first part and have a third height, the third height being greater than the first height of the circuit layer and the second height of the first part. The first portion of the protective layer is in direct contact with the side surface of the circuit layer, and The first portion of the protective layer includes a first width and a second width that are different from each other along the circumferential direction between the side surface of the circuit layer and the second portion of the protective layer.

2. The circuit board according to claim 1, wherein, The surface roughness of the upper surface of the first part is the same as the surface roughness of the upper surface of the second part.

3. The circuit board according to claim 1, wherein, The circuit layer includes a first pad, and The first portion of the protective layer is configured as a side surface surrounding the first pad.

4. The circuit board according to claim 3, wherein, The circuit layer includes a circuit section disposed adjacent to the first pad, and The second part of the protective layer covers at least a portion of the upper surface of the circuit section.

5. The circuit board according to claim 3, wherein, The circuit layer includes a second pad. The protective layer includes a third portion, which is disposed on the second pad and has a fourth height greater than the third height. The third part of the protective layer covers at least a portion of the upper surface of the second pad.

6. The circuit board according to claim 5, wherein, The third portion of the protective layer includes an opening that overlaps perpendicularly with the upper surface of the second pad.

7. The circuit board according to claim 5, wherein, The width of the first pad in the horizontal direction is smaller than the width of the second pad in the horizontal direction.

8. The circuit board according to claim 4, wherein, The first portion of the protective layer includes: a first sub-portion disposed on one side of the first pad; and a second sub-portion disposed on the other side of the first pad, different from the first side. The first sub-part has the first width, and the second sub-part has the second width.

9. The circuit board according to claim 8, wherein, The sum of the first width and the second width is in the range of 20 μm to 24 μm.

10. The circuit board according to claim 8, wherein, The side surface of the first pad includes a first portion and a second portion. The first portion is in direct contact with the first portion of the protective layer, and the second portion is disposed on the first portion and overlaps with the second portion of the protective layer along the horizontal direction without contacting the first portion of the protective layer.

11. The circuit board according to claim 8, wherein, The circuit section includes a first circuit section on the side closest to the first pad, and The distance between the first circuit portion and the first pad is greater than the first width of the first sub-part of the protective layer.

12. The circuit board according to claim 1, wherein, The second height of the first portion of the protective layer satisfies 70% to 90% of the first height of the circuit layer.

13. The circuit board according to claim 5, wherein, The vertical distance from the upper surface of the third part of the protective layer to the upper surface of the circuit layer is in the range of 7 μm to 17 μm.

14. The circuit board according to claim 11, wherein, The circuit section includes a second circuit section on the other side closest to the first pad, and The spacing between the second circuit portion and the first pad is greater than the second width of the first sub-part of the protective layer.

15. The circuit board according to claim 5, wherein, The surface roughness Ra of the centerline of at least one of the upper surfaces of the first and second portions of the protective layer is greater than the surface roughness Ra of the centerline of the upper surface of the third portion.

16. The circuit board according to claim 15, wherein, The surface roughness Ra of the centerline of the upper surface of the third part of the protective layer satisfies the range of 0.01 μm to 0.1 μm.

17. The circuit board according to claim 16, wherein, The surface roughness Ra of the centerline of at least one of the upper surfaces of the first and second portions of the protective layer is 1.0 μm or greater.

18. The circuit board according to claim 2, wherein, The insulating layer comprises multiple layers, and The circuit layer is disposed on the uppermost insulating layer among the plurality of layers.

19. The circuit board according to claim 14, wherein, The spacing between the first pad and the first circuit portion is different from the spacing between the first pad and the second circuit portion.

20. The circuit board according to claim 14, wherein, At least a portion of the second part of the protective layer is disposed between the first pad and the first circuit portion and between the first pad and the second circuit portion.

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