Display Panel, Display Device, and Control Method

Abstract

A display panel has a display area, and the display area includes a light-transmitting area, at least one first area, and a second area. The display panel includes a plurality of sub-pixels disposed in at least one first area and the second area, a plurality of second light-emitting devices disposed in the light-transmitting area, a plurality of data lines, and a first transistor. The plurality of data lines include a first data line and a second data line; the first data line is electrically connected to a pixel driving circuit in a column of sub-pixels including virtual sub-pixels; the second data line is electrically connected to a pixel driving circuit in a column of sub-pixels in the same column as a column of second light-emitting devices; one second light-emitting device in the column of second light-emitting devices is electrically connected to a pixel driving circuit in one virtual sub-pixel connected to the first data line. The first data line and the second data line are electrically connected through the first transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel, a display device, and a control method. Background Art

[0002] Currently, the display screens for electronic devices are developing towards larger and full-screen sizes to provide users with a better visual experience. With the development and progress of technologies, more and more research has been conducted on under-screen camera technologies. An under-screen camera is to dispose a camera of an electronic device under a display screen to take pictures, and the area corresponding to the under-screen camera on the display screen can be displayed, thereby achieving a full-screen display. Summary of the Invention

[0003] On the one hand, a display panel is provided, which has a display area. The display area includes a light-transmitting area, at least one first area, and a second area, and the at least one first area is at least located on one side of the light-transmitting area. The display panel includes a plurality of sub-pixels disposed in the at least one first area and the second area, a plurality of second light-emitting devices disposed in the light-transmitting area, a plurality of data lines, and a first transistor. The plurality of sub-pixels are arranged in multiple rows and multiple columns; the plurality of sub-pixels include a plurality of effective sub-pixels and a plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are disposed in the at least one first area; each sub-pixel includes a pixel driving circuit, and each effective sub-pixel further includes a first light-emitting device electrically connected to the pixel driving circuit; the plurality of second light-emitting devices are arranged in multiple columns of second light-emitting devices, and each column of second light-emitting devices and a column of sub-pixels are arranged in a column. The pixel driving circuits in a column of sub-pixels are electrically connected to one data line; the plurality of data lines include a first data line and a second data line; the first data line is electrically connected to the pixel driving circuits in a column of sub-pixels including virtual sub-pixels; the second data line is electrically connected to the pixel driving circuits in a column of sub-pixels in the same column as a column of second light-emitting devices; one second light-emitting device in the column of second light-emitting devices is electrically connected to the pixel driving circuit in one virtual sub-pixel connected to the first data line. The first data line and the second data line are electrically connected through the first transistor.

[0004] In some embodiments, among the column of sub-pixels electrically connected to the first data line, the sub-pixels located in the first area are all virtual sub-pixels.

[0005] In some embodiments, the effective sub-pixels located in the first area among the plurality of effective sub-pixels are evenly arranged.

[0006] In some embodiments, the display panel further includes: a first connection line and / or a second connection line. The first connection line is disposed on a side of the first region away from the signal input end of the first data line; one end of the first connection line is electrically connected to the first pole of the first transistor, and the other end of the first connection line is electrically connected to the first data line; the second connection line is disposed on a side of the first region away from the signal input end of the first data line; one end of the second connection line is electrically connected to the second pole of the first transistor, and the other end of the second connection line is electrically connected to the second data line.

[0007] In some embodiments, the display panel further includes at least one second transistor; the at least one second transistor is configured to connect the first data line into one body when turned on; and when turned off, disconnect a part of the first data line located in the first region from a part located in the second region and electrically connect it to the second data line.

[0008] In some embodiments, the light-transmitting region is located in the middle of the display region; the first data line includes a first part, and second and third parts located on both sides of the first part, the first part is located in the first region, and the second and third parts are located in the second region; the second part is closer to the signal input end of the first data line than the third part; the at least one second transistor includes one second transistor; the first part and the second part are electrically connected through the second transistor; or, the at least one second transistor includes two second transistors, the first part and the second part are electrically connected through one of the second transistors, and the first part and the third part are electrically connected through the other second transistor.

[0009] In some embodiments, the display panel further includes a capacitor; a first storage electrode of the capacitor is electrically connected to the first pole of the first transistor, and a second storage electrode of the capacitor is electrically connected to the second pole of the first transistor.

[0010] In some embodiments, the distance between any two adjacent second light-emitting devices in each row of second light-emitting devices is equal; in a row of sub-pixels including virtual sub-pixels and effective sub-pixels, the distance between any two adjacent effective sub-pixels is equal to the distance between the two adjacent second light-emitting devices.

[0011] In some embodiments, three of the virtual sub-pixels are provided between any two adjacent effective sub-pixels in a row of sub-pixels including virtual sub-pixels and effective sub-pixels.

[0012] In some embodiments, the at least one first region includes one first region, and this first region is located on one side of the light-transmitting region along the direction of the vertical data line.

[0013] In some embodiments, the at least one first region includes two first regions, which are respectively located on both sides of the light-transmitting region along the direction of the vertical data line.

[0014] In some embodiments, the at least one first region includes two first regions, one first region is located on one side of the light-transmitting region along the direction of the vertical data line, and the other first region is located on one side of the light-transmitting region along the direction of the data line.

[0015] In some embodiments, the display panel further includes a plurality of gate lines and a plurality of scan signal connection lines. At least the effective sub-pixels in one row of pixels are electrically connected to one gate line; one end of the scan signal connection line is electrically connected to the gate line electrically connected to the effective sub-pixels in the same row as a second light-emitting device, and the other end of the scan signal connection line is electrically connected to the pixel data driving circuit of the virtual sub-pixel electrically connected to the second light-emitting device, and the pixel data driving circuit of the virtual sub-pixel is insulated from the gate line electrically connected to the effective sub-pixels in the same row as the virtual sub-pixel.

[0016] In some embodiments, both the first light-emitting device and the second light-emitting device are OLEDs.

[0017] On the other hand, a display device is provided, including the display panel of any of the above embodiments and an image sensor located in the light-transmitting region.

[0018] In yet another aspect, a method for controlling a display panel is provided, including: inputting a gate scan signal to multiple rows of sub-pixels row by row; when inputting a gate scan signal to the pixel driving circuit electrically connected to any second light-emitting device in the light-transmitting region, also inputting a control signal to the first transistor to turn on the first transistor; inputting a data signal to each row of sub-pixels through the multiple data lines; when the first transistor is turned on, the second data signal from the signal input end of the second data line is transmitted through the first data line to the pixel driving circuit electrically connected to the second light-emitting device. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual size of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0020] Figure 1 Schematic diagram of a display device according to some embodiments;

[0021] Figure 2A A plan view of a display panel according to some embodiments;

[0022] Figure 2B Another plan view of a display panel according to some embodiments;

[0023] Figure 3A A schematic diagram of a display panel according to some embodiments;

[0024] Figure 3B Another schematic diagram of a display panel according to some embodiments;

[0025] Figure 4A Yet another schematic diagram of a display panel according to some embodiments;

[0026] Figure 4B Yet another schematic diagram of a display panel according to some embodiments;

[0027] Figure 4C Yet another schematic diagram of a display panel according to some embodiments;

[0028] Figure 5A A signal timing diagram of a display panel according to some embodiments;

[0029] Figure 5B Another signal timing diagram of a display panel according to some embodiments;

[0030] Figure 6A Yet another signal timing diagram of a display panel according to some embodiments;

[0031] Figure 6B Yet another signal timing diagram of a display panel according to some embodiments;

[0032] Figure 7 A simulation waveform diagram of a second data signal according to some embodiments;

[0033] Figure 8 Yet another schematic diagram of a display panel according to some embodiments;

[0034] Figure 9 Yet another schematic diagram of a display panel according to some embodiments;

[0035] Figure 10A An equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0036] Figure 10B Another equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0037] Figure 11According to some embodiments, a kind of based on Figure 8 is a cross-sectional view taken along the B-B' direction in Detailed implementation manners

[0038] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0039] As used herein, the singular form "a" also includes the plural form, unless the context clearly indicates otherwise. Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0040] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0041] In describing some embodiments, the term "connected" and its derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. Another example is that in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "connected" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0042] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0043] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0044] As used herein, depending on the context, the term "if" is optionally interpreted to mean "when" or "at the time of" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" is optionally interpreted to mean "when it is determined that..." or "in response to determining..." or "at the time of detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]".

[0045] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0046] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond the stated ones.

[0047] As used herein, "about" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0048] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. The exemplary embodiments of the present disclosure should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] Some embodiments of the present disclosure provide a display device, which can be used as a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, etc. The embodiments of the present disclosure do not impose special restrictions on the uses of the display device.

[0050] As Figure 1 shown, the display device includes a display panel 100, a frame 200, a cover plate 300, a circuit board 400, and other electronic accessories including an image sensor 500, etc. For example, the longitudinal cross-section of the frame 200 is U-shaped, and the display panel 100, the circuit board 400, the image sensor 500, etc. are disposed in a cavity formed by the frame 200 and the cover plate 300. The circuit board 400 is disposed on a side of the display panel 100 facing away from the cover plate 300.

[0051] In some examples, the image sensor 500 is a camera. For example, the camera is disposed on a side of the display panel 100 facing away from the cover plate 300.

[0052] In some examples, the circuit board 400 is configured to provide signals required for display to the display panel 100. For example, the circuit board 400 is a Printed Circuit Board Assembly (PCBA), and the PCBA includes a Printed Circuit Board (PCB) and a Timing Controller (TCON), a Power Management IC (PMIC), and other ICs or circuits, etc. disposed on the PCB.

[0053] Some embodiments of the present disclosure provide a display panel 100, as Figure 2A and Figure 2B shown, the display panel has a display area 1, and the display area 1 includes a light-transmitting area 11, at least one first area 12, and a second area 13. For example, as Figure 2A shown, the first area 12 is disposed on one side of the light-transmitting area 11. Another example is, as Figure 2BAs shown, the first region 12 is disposed around the light-transmitting region 11.

[0054] In some examples, as Figure 1 shown, the light-transmitting region 11 is a region corresponding to the installation position of the image sensor in a direction perpendicular to the thickness of the display device. On the basis of enabling the camera to collect images, the light-transmitting region 11 can also display images, so that the display panel 100 can achieve a full-screen display.

[0055] Exemplarily, as Figure 2A and Figure 2B shown, the shape of the light-transmitting region 11 is circular. In another example, the shape of the light-transmitting region 11 is rectangular. In yet another example, the shape of the first region 12 is rectangular. Of course, the shapes of the light-transmitting region 11 and the first region 12 in the embodiments of the present disclosure are not limited and can be reasonably adjusted according to actual situations.

[0056] The display panel 100 includes a plurality of sub-pixels disposed in the first region 12 and the second region 13, and the plurality of sub-pixels are arranged in multiple rows and multiple columns. Exemplarily, as Figure 3A and Figure 3B shown, the plurality of sub-pixels are arranged in 8 rows and 24 columns, and are sequentially the 1st column to the 24th column along the X direction and sequentially the 1st row to the 8th row along the Y direction. The number of sub-pixels in each column of sub-pixels is equal, and the number of sub-pixels in each row of sub-pixels is also equal. Of course, the number of sub-pixels in the display panel 100, the number of rows in which the plurality of sub-pixels are arranged and the number of columns in which they are arranged, as well as the number of sub-pixels in each row of sub-pixels and the number of sub-pixels in each column of sub-pixels are related to the resolution of the display panel, Figure 3A and Figure 3B shown, the plurality of sub-pixels shown are a part of the sub-pixels in the display panel 100, and it is only a schematic diagram of an arrangement manner in which the plurality of sub-pixels are arranged in multiple rows and multiple columns. The embodiments of the present disclosure do not limit the number of sub-pixels and the specific manner in which the plurality of sub-pixels are arranged in multiple rows and multiple columns, as long as the plurality of sub-pixels can be arranged in multiple rows and multiple columns.

[0057] As Figure 3A and Figure 3B shown, the plurality of sub-pixels include a plurality of effective sub-pixels P and a plurality of virtual sub-pixels D; the plurality of effective sub-pixels P are disposed in the first region 12 and the second region 12, and the plurality of virtual sub-pixels D are disposed in the first region 12.

[0058] Each effective sub-pixel P includes a pixel driving circuit and a first light-emitting device electrically connected to the pixel driving circuit, and each virtual sub-pixel D only includes a pixel driving circuit. Exemplarily, the circuit structures of the pixel driving circuits in each effective sub-pixel P and each virtual sub-pixel D are the same.

[0059] As Figure 3A and Figure 3BAs shown, the display panel further includes a plurality of second light-emitting devices A disposed in the light-transmissive area 11. The plurality of second light-emitting devices A are arranged in multiple columns of second light-emitting devices A, and each column of second light-emitting devices A is arranged in a column with a column of sub-pixels.

[0060] In the present disclosure, a plurality of sub-pixels electrically connected to one signal line are defined as a column of sub-pixels. Here, the signal line is the data line in the present disclosure. A plurality of second light-emitting devices A arranged along at least a part of the sub-pixels in a column of sub-pixels in the same direction are defined as a column of second light-emitting devices A. A plurality of sub-pixels arranged along the extension direction of another signal line are defined as a row of sub-pixels. Here, the other signal line is the gate line in the following text. A plurality of second light-emitting devices A arranged along at least a part of the sub-pixels in a row of sub-pixels in the same direction are defined as a row of second light-emitting devices A.

[0061] Exemplarily, the plurality of second light-emitting devices A are arranged in 4 rows and 3 columns as shown in Figure 2A and 2B shown. Along the X direction, they are the 1st column to the 3rd column in sequence, and along the Y direction, they are the 1st row to the 4th row in sequence. The number of second light-emitting devices A in each column of second light-emitting devices A is equal, and the number of second light-emitting devices A in each row of second light-emitting devices A is also equal. Of course, the number of second light-emitting devices A in the light-transmissive area 11, the number of rows and columns in which the plurality of second light-emitting devices A are arranged in rows and columns, as well as the number of second light-emitting devices A in each row of second light-emitting devices A and the number of second light-emitting devices A in each column of second light-emitting devices A are related to the size and resolution of the light-transmissive area 11, Figure 3A and Figure 3B shown. The arrangement manner of the plurality of second light-emitting devices A shown is only an illustration, and the present disclosure embodiment does not limit the number of second light-emitting devices A and the manner in which the plurality of second light-emitting devices A are arranged in multiple columns.

[0062] Here, only a plurality of second light-emitting devices A are provided in the light-transmissive area 11, and the plurality of second light-emitting devices A are arranged at uniform intervals, which can increase the light transmittance of the light-transmissive area 11 and enable the light-transmissive area to have a good display effect.

[0063] Exemplarily, referring to Figure 3A and Figure 3B , the first column of second light-emitting devices A in the light-transmissive area 11 is arranged in a column with the 13th column of sub-pixels in the display area 1. Another example is that the second column of second light-emitting devices A in the light-transmissive area 11 is arranged in a column with the 15th column of sub-pixels.

[0064] In some examples, the plurality of first light-emitting devices include a plurality of first light-emitting devices configured to emit red light, a plurality of first light-emitting devices configured to emit green light, and a plurality of first light-emitting devices configured to emit blue light.

[0065] In some examples, the multiple second light-emitting devices A include multiple second light-emitting devices A configured to emit red light, multiple second light-emitting devices A configured to emit green light, and multiple second light-emitting devices A that emit blue light.

[0066] Of course, the multiple first light-emitting devices may also include first light-emitting devices that emit white light. The multiple second light-emitting devices A may also include second light-emitting devices A that emit white light.

[0067] In some examples, the first light-emitting device is an Organic Light-Emitting Diode (OLED).

[0068] In some examples, the second light-emitting device A is an OLED.

[0069] As Figure 3A and Figure 3B shown, the display panel 100 further includes multiple data lines 14, and the pixel driving circuits in a column of sub-pixels are electrically connected to one data line 14. The multiple data lines 14 include a first data line 141 and a second data line 142. For example, the first data line 141 is multiple first data lines 141, and the second data line 142 is multiple second data lines 142.

[0070] For example, the multiple data lines 14 are arranged on the same layer. Another example is that at least some of the multiple data lines 14 are arranged on the same layer. The multiple data lines 14 arranged on the same layer are formed synchronously through a patterning process.

[0071] In the present disclosure, Figure 3A and Figure 3B only some of the data lines are shown. Substantially, each column of sub-pixels is electrically connected to one data line.

[0072] The first data line 141 is electrically connected to the pixel driving circuit in a column of sub-pixels including virtual sub-pixels D. For example, as Figure 3A shown, the first column of sub-pixels includes virtual sub-pixels D, and the first data line 141-1 is electrically connected to the pixel driving circuit in the sub-pixels located in the first column. Another example is that, as Figure 3A shown, the second column of sub-pixels includes virtual sub-pixels D and effective sub-pixels P, and the first data line 141-2 is electrically connected to the pixel driving circuit in the sub-pixels located in the second column.

[0073] The second data line 142 is electrically connected to the pixel driving circuit in a column of sub-pixels that is in the same column as a column of second light-emitting devices A; one of the second light-emitting devices A in the column of second light-emitting devices A is electrically connected to the pixel driving circuit in one virtual sub-pixel D connected to the first data line. For example, as Figure 3AAs shown, the second light-emitting device A in the first column of the light-transmitting area 11 is in the same column as the sub-pixels in the 13th column, and the second data line 142-1 is electrically connected to the pixel driving circuit in the sub-pixels in the 13th column. Another example is, as Figure 3A shown, the second light-emitting device A in the second column of the light-transmitting area 11 is in the same column as the sub-pixels in the 15th column, and the second data line 142-2 is electrically connected to the pixel driving circuit in the sub-pixels in the 15th column.

[0074] Each second data line 142 has a first winding portion that is routed around the light-transmitting area 11, which can prevent the second data line 142 from passing through the light-transmitting area 11 to avoid affecting the light transmittance of the light-transmitting area 11.

[0075] In some examples, as Figure 3A shown, the multiple data lines 14 further include a third data line 143. For example, the third data line 143 is multiple third data lines 143. The third data line 143 is only electrically connected to the pixel driving circuit in the sub-pixels that are in a different column from the second light-emitting device A in any column and all of which in a column are valid sub-pixels P. That is, the third data line 143 is only electrically connected to the pixel driving circuit of a column of valid sub-pixels P that are in a different column from the second light-emitting device A in any column and are located in the second area 13.

[0076] For example, as Figure 3A shown, the valid sub-pixels P in the 24th column are in a different column from the second light-emitting device A in any column, and multiple valid sub-pixels P in the 24th column are all located in the second area 13. The third data line 143-1 is electrically connected to the pixel driving circuit of the valid sub-pixels P in the 24th column.

[0077] Another example is, as Figure 3A shown, the valid sub-pixels P in the 22nd column are in a different column from the second light-emitting device A in any column, and multiple valid sub-pixels P in the 22nd column are all located in the second area 13. The third data line 143-2 is electrically connected to the pixel driving circuit of the valid sub-pixels P in the 22nd column. The third data line 143-2 has a second winding portion that is routed around the light-transmitting area 11, which can prevent the third data line 143-2 from passing through the light-transmitting area 11 to avoid affecting the light transmittance of the light-transmitting area 11. That is to say, if the valid sub-pixels P electrically connected to the third data line 143 are on one side of the light-transmitting area in the direction of the data line 14, a second winding portion needs to be provided for the third data line.

[0078] In some examples, the second light-emitting device A in the first row and first column of the light-transmitting area 11 is electrically connected to the pixel driving circuit in the virtual sub-pixel D in the first row and third column of the first column. For example, as Figure 3A and Figure 3BAs shown, a second light-emitting device A and a pixel driving circuit in a virtual sub-pixel D are connected by an auxiliary connection line 15.

[0079] Here, Figure 3A and Figure 3B are only for illustration. Although Figure 3A and Figure 3B only some of the second light-emitting devices A in the light-transmitting region 11 are connected to the pixel driving circuit in the virtual sub-pixel D by the auxiliary connection line 15, it does not mean that only some of the second light-emitting devices A in the light-transmitting region 11 are electrically connected to the pixel driving circuit in the virtual sub-pixel D. Substantially, each second light-emitting device A in the light-transmitting region 11 is electrically connected to the pixel driving circuit in the corresponding virtual sub-pixel D.

[0080] Exemplarily, the material of the auxiliary connection line 15 is indium tin oxide (ITO). ITO is transparent when in a thin film state. Therefore, the auxiliary connection line made of ITO is in a transparent state, so that the auxiliary connection line has almost no influence on the light transmittance of the light-transmitting region 11. Exemplarily, multiple auxiliary connection lines 15 are arranged in the same layer. Also exemplarily, multiple auxiliary connection lines 15 and multiple data lines 14 are at least partially arranged in the same layer. The multiple auxiliary connection lines 15 arranged in the same layer are formed synchronously by a patterning process.

[0081] In some examples, as Figure 10A shown, the pixel driving circuit 30 includes a driving transistor Td, a third transistor T3, and a first storage capacitor Cst. Those skilled in the art should understand that in the pixel driving circuit 30, the width-to-length ratio of the channel of the driving transistor Td is greater than that of other transistors (such as the third transistor T3) that act as switches. That is, the circuit structure of the pixel driving circuit 30 is a 2T1C circuit structure.

[0082] As Figure 10A shown, the gate of the third transistor T3 is electrically connected to the scan signal line GL, the first pole of the third transistor T3 is electrically connected to the data line DL (i.e., the data line 14 in the above display panel 100), and the second pole of the third transistor T3 is electrically connected to the gate of the driving transistor Td. The first pole of the driving transistor Td is electrically connected to the first power supply line VDD, the second pole of the driving transistor Td is electrically connected to the anode of the light-emitting device L (i.e., the first light-emitting device or the second light-emitting device A of the above display panel). The cathode of the light-emitting device L is electrically connected to the second power supply line VSS. One end of the first storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other end of the first storage capacitor Cst is electrically connected to the second pole of the driving transistor Td. Exemplarily, the first power supply line VDD is configured to provide a high voltage signal, and the second power supply line VSS is configured to provide a low voltage signal.

[0083] In some other examples, such as Figure 10B shown, the pixel driving circuit 30 includes a driving transistor Td, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a first storage capacitor Cst. That is, the circuit structure of the pixel driving circuit is a 7T1C circuit structure.

[0084] Such as Figure 10B shown, the gate of the eighth transistor T8 is electrically connected to the scan signal line GL, the first pole of the eighth transistor T8 is electrically connected to the data signal line DL (i.e., the data line 14 in the above display panel), and the second pole of the eighth transistor T8 is electrically connected to the first pole of the driving transistor Td. The gate of the ninth transistor T9 is electrically connected to the scan signal line GL, and the first and second poles of the ninth transistor T9 are respectively electrically connected to the second pole and the gate of the driving transistor Td. The gate of the fourth transistor T4 is electrically connected to the enable signal line EM, the first pole of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second pole of the fourth transistor T4 is electrically connected to the first pole of the driving transistor Td. The gate of the fifth transistor T5 is electrically connected to the enable signal line EM, the first pole of the fifth transistor T5 is electrically connected to the second pole of the driving transistor Td, and the second pole of the fifth transistor T5 is electrically connected to the anode of the light-emitting device L. The gate of the sixth transistor T6 is electrically connected to the reset signal line RST(N), the first pole of the sixth transistor T6 is electrically connected to the initialization signal line VIN, and the second pole of the sixth transistor T6 is electrically connected to the gate of the driving transistor Td. The gate of the seventh transistor T7 is electrically connected to the reset signal line RST(N + 1) connected to the sixth transistor T6 in the pixel driving circuit 30 of the next row, the first pole of the seventh transistor T7 is electrically connected to the initialization signal line VIN, and the second pole of the seventh transistor T7 is electrically connected to the anode of the light-emitting device L (i.e., the first light-emitting device or the second light-emitting device A of the above display panel). One end of the first storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other end of the first storage capacitor Cst is electrically connected to the first power supply line VDD. The cathode of the light-emitting device L is electrically connected to the second power supply line VSS. Exemplarily, the first power supply line VDD is configured to provide a high-voltage signal, and the second power supply line VSS is configured to provide a low-voltage signal.

[0085] The above is only an illustrative example of the pixel driving circuit 30. The circuit structure of the pixel driving circuit 30 is not limited to the above two structures, and it can also be other types of circuit structures, which will not be listed one by one here. However, it should be understood that no matter what circuit structure the pixel driving circuit 30 is, it includes at least one driving transistor, one transistor acting as a switch, and one first storage capacitor.

[0086] In the present disclosure, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetric in structure, there may be no difference in structure between its source and drain. That is to say, the first and second electrodes of the transistor in the embodiments of the present disclosure may have no difference in structure. By way of example, for a P-type transistor, the second electrode is referred to as the drain, and the first electrode is referred to as the source. By way of another example, for an N-type transistor, the first electrode is referred to as the drain, and the second electrode is referred to as the source.

[0087] In addition, according to the different conduction modes of the transistor, the transistor can be divided into an enhancement-mode transistor and a depletion-mode transistor. Each transistor in the embodiments of the present disclosure can be an enhancement-mode transistor or a depletion-mode transistor, and there is no limitation thereto.

[0088] By way of example, the pixel driving circuit 30 in each sub-pixel is the same. The pixel driving circuits 30 in multiple sub-pixels are synchronously formed by a patterning process.

[0089] The display panel 100 further includes a plurality of first transistors. Refer to Figure 3A 、 3B 、and Figure 4A , a first data line 141 and a second data line 142 are connected by a first transistor T1. The first transistor T1 is configured to connect the first data line 141 and the second data line 142 as a whole when it is turned on; and disconnect the first data line 141 and the second data line 142 when it is turned off.

[0090] By way of example, the plurality of first transistors T1 are synchronously formed by a patterning process.

[0091] In some examples, the gate of the first transistor T1 is connected to a first control terminal through a first control line 16. The first control signal from the first control terminal is transmitted to the first transistor T1 through the first control line 16 to control the turning on or off of the first transistor T1. For example, the first transistor T1 is an N-type transistor. In response to the first control signal from the first control terminal being a high-level signal, the first transistor T1 is turned on. By way of another example, the first transistor T1 is a P-type transistor. In response to the first control signal from the first control terminal being a low-level signal, the first transistor T1 is turned off.

[0092] In the present disclosure, when the first transistor T1 is turned on, the first data line 141 and the second data line 142 are connected as a whole. The second data signal from the signal input end of the second data line 142 is transmitted through the connected second data line 142 and first data line 141 to the pixel driving circuit electrically connected to the second light-emitting device A to control the second light-emitting device A to emit light, so that the light-transmitting area 11 of the display panel displays an image.

[0093] It should be noted that when the first transistor T1 is turned on, the first signal line 141 may not transmit the first data signal to the pixel driving circuit in the virtual sub-pixel D electrically connected to the second light-emitting device A, so as to prevent interference between the first data signal and the second data signal. For example, the processor can be controlled such that when the first transistor T1 is turned on, the signal input end of the first data line 141 does not output the first data signal, or does not output the data signal that can cause the second light-emitting device A to emit light, that is, the processor can control the signal input end of the first signal line 141 to output a virtual first data signal; alternatively, by controlling a switch (such as the second transistor T2 below), the first data line 141 is disconnected to prevent the first data signal from the signal input end of the first data line 141 from being transmitted to the pixel driving circuit electrically connected to the second light-emitting device A.

[0094] When the first transistor T1 is turned off, the first data line 141 and the second data line 142 are not connected, and the first data signal from the signal input end of the first data line 141 is transmitted to the pixel data circuit electrically connected to the first data line 141, so that a column of effective sub-pixels P electrically connected to the first data line 141 can be normally displayed.

[0095] In this way, compared with the case where the first data line 141 and the second data line 142 are directly electrically connected through a connection line and the light-transmitting area can only be located at the topmost end of the display area 1, the embodiment of the present disclosure can make the light-transmitting area 11 be located at any position of the display area 1 without affecting the normal display of the second area 13.

[0096] In the present disclosure, the spacing between the sub-pixels in each row of the display panel 100 is equal, and the spacing between the sub-pixels in each column is also equal, so that the display panel 100 has a good display effect. Figure 3A and 3B The spacing between the second row of sub-pixels and the third row of sub-pixels, the spacing between the 6th row and the 7th row, and the spacing between the 23rd column and the 24th column in [reference] are only for illustration. In order to more clearly illustrate the connection between the first data line 141 and the second data line 142 and the wiring manner of each data line, they do not represent the actual spacing between the sub-pixels in the display panel.

[0097] In some embodiments, the first transistor T1 is a thin film transistor (Thin Film Transistor, abbreviated as TFT).

[0098] In some examples, referring to Figure 11 , the display panel 100 includes a substrate 101, and the pixel driving circuit in each sub-pixel is disposed on the substrate 101. For example, the substrate 101 is a glass substrate.

[0099] Each driving transistor Td in each pixel driving circuit includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer, and the source electrode and the drain electrode are in contact with the active layer respectively.

[0100] Exemplarily, the material of the active layer 2113 includes one of amorphous indium gallium zinc oxide (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc.

[0101] Reference Figure 11 , the first light-emitting device 210 in each effective sub-pixel P includes an anode 212, a light-emitting functional layer 213, and a cathode 214. Each second light-emitting device A also includes an anode 212, a light-emitting functional layer 213, and a cathode 214.

[0102] Exemplarily, the light-emitting functional layer 213 only includes a light-emitting layer. Also exemplarily, in addition to the light-emitting layer, the light-emitting functional layer 213 further includes one or more of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0103] In some examples, the anode 212 of the first light-emitting device 210 and the second light-emitting device A close to the substrate 101 is opaque, and the cathode 214 far from the substrate 101 is transparent or semi-transparent.

[0104] In other examples, the anode 212 of the first light-emitting device 210 and the second light-emitting device A close to the substrate 101 is transparent or semi-transparent, and the cathode 214 far from the substrate 101 is opaque.

[0105] In some examples, as Figure 11 shown, the display panel 100 further includes a pixel defining layer 215, and the pixel defining layer 215 includes a plurality of opening regions. A first light-emitting device 210 is disposed in one opening region, and a second light-emitting device A is disposed in one opening region.

[0106] In still other examples, as Figure 11As shown, the display panel 100 further includes a planarization layer 216 disposed between the pixel driving circuit and the anode 212 of the first light-emitting device corresponding to the pixel driving circuit. The anode of the first light-emitting device 210 is electrically connected to the second pole of the driving transistor Td in the pixel driving circuit through a via hole disposed on the planarization layer 216. The anode of the second light-emitting device A is electrically connected to the auxiliary connection line 15 through a via hole disposed on the planarization layer 216 ( Figure 11 not shown in the figure).

[0107] Exemplarily, the material of the planarization layer 50 includes but is not limited to polysiloxane-based, acrylic-based, or polyimide-based materials.

[0108] In some other examples, as Figure 11 shown, the display panel 100 further includes a packaging layer 217.

[0109] In some embodiments, as Figure 3B shown, among the sub-pixels in a column electrically connected to the first data line 141, the sub-pixels located in the first region 12 are all virtual sub-pixels D.

[0110] In the scanning stage of a frame period, the pixel driving circuits in each row of sub-pixels are scanned row by row. That is, starting from the pixel driving circuit in the first row of sub-pixels located in the display area 1, scanning is performed row by row, and the corresponding data signals are input to each pixel driving circuit in each row of sub-pixels in turn until the data signals are input to each pixel driving circuit in the last row of sub-pixels located in the display area 1.

[0111] Based on this, during the process of scanning the pixel rows where each second light-emitting device A in the light-transmitting area 11 is located, the first transistor T1 can be kept turned on until all the pixel driving circuits electrically connected to the second light-emitting devices A in the last row of the light-transmitting area 11 are scanned.

[0112] Exemplarily, referring to Figure 3B, when the processor inputs a gate scan signal to the pixel driving circuit of the third row (i.e., the pixel row where the second light-emitting device A in the first row of the light-transmitting area 11 is located), it also inputs a first control signal to the first transistor to turn on the first transistor T1. The first data line 141 and the second data line 142 are connected as a whole through the turned-on first transistor T1, and the second data signal is transmitted to the pixel driving circuit of the virtual sub-pixel D located in the third row and electrically connected to the first data line 141, so that the second light-emitting device A located in the first row of the light-transmitting area 11 and electrically connected to the virtual sub-pixel D emits light; when the scan signal received by the pixel driving circuit of the fourth row is input by the processor, the second data signal is transmitted to the pixel driving circuit of the virtual sub-pixel D located in the fourth row and electrically connected to the first data line 141, so that the second light-emitting device A located in the second row of the light-transmitting area 11 and electrically connected to the virtual sub-pixel D emits light. Until the second data signal is transmitted to the pixel driving circuit of the virtual sub-pixel D located in the sixth row and electrically connected to the first data line 141, so that the second light-emitting device A located in the fourth row of the light-transmitting area 11 (i.e., the pixel row where the second light-emitting device A in the last row of the light-transmitting area 11 is located) and electrically connected to the virtual sub-pixel D emits light, that is, the scanning of all the pixel rows where the second light-emitting devices A in the light-transmitting area 11 are located is completed. The processor inputs a first control signal to the gate of the first transistor T1 to turn off the first transistor T1.

[0113] In some other embodiments, as Figure 3A shown, among the sub-pixels in a column electrically connected to the first data line 141, the sub-pixels located in the first area 12 include virtual sub-pixels D and effective sub-pixels P.

[0114] Based on this, during the process of scanning the pixel row where a second light-emitting device A in the light-transmitting area 11 is located, if the sub-pixel electrically connected to the first data line 141 is an effective sub-pixel P, the first transistor T1 electrically connected to the first data line 141 is turned off. If the sub-pixel electrically connected to the first data line 141 is a virtual sub-pixel P, and the virtual sub-pixel D is electrically connected to a second light-emitting device A in the second row of the light-transmitting area 11, the first transistor T1 electrically connected to the first data line 141 is turned on. [[ID=⑨]] [[ID=⑩]]

[0115] [[ID=⑪]]Exemplarily, referring to [[ID=⑫]] Figure 3A, when the processor inputs a gate scan signal to the pixel driving circuit of the third row (i.e., the pixel row where the second light-emitting device A in the first row of the light-transmitting area 11 is located), the processor also inputs a first control signal to the first transistor T1 electrically connected to the first data line 141-2 to turn off the first transistor T1. Since the sub-pixel electrically connected to the first data line 141-2 in the fourth row of sub-pixels is a virtual sub-pixel D, and this virtual sub-pixel D is electrically connected to a second light-emitting device A in the second row of the light-transmitting area 11, when the processor inputs a gate scan signal to the pixel driving circuit of the fourth row (i.e., the pixel row where the second light-emitting device A in the second row of the light-transmitting area 11 is located), the processor also inputs a first control signal to the first transistor T1 electrically connected to the first data line 141-2 to turn on the first transistor T1.

[0116] In some embodiments, as Figure 3A and 3B shown, the active sub-pixels P located in the first area 12 among the plurality of active sub-pixels P are uniformly arranged. In this way, the first area 12 can have a good display effect.

[0117] In some embodiments, the display panel 100 further includes a first connection line. The first connection line is disposed on a side of the first area 12 away from the signal input end of the data line 14. One end of the first connection line is electrically connected to the first pole of the first transistor T1, the other end of the first connection line is electrically connected to the first data line 141, and the second pole of the first transistor T1 is electrically connected to the second data line 142.

[0118] In some other embodiments, the display panel 100 further includes a second connection line. The second connection line is disposed on a side of the first area 12 away from the signal input end of the data line 14; one end of the second connection line is electrically connected to the second pole of the first transistor T1, and the first pole of the first transistor T1 is electrically connected to the first data line 141.

[0119] In still some other embodiments, as Figure 3A and 3B , and Figure 4A - Figure 4C shown, the display panel 100 further includes a first connection line 17 and a second connection line 18. Both the first connection line 17 and the second connection line 18 are disposed on a side of the first area 12 away from the signal input end of the data line 14. By way of example, both the first connection line 17 and the second connection line 18 are disposed in the pixel row where the virtual sub-pixel D electrically connected to the second light-emitting device A in the first row of the light-transmitting area 11 is located. For example, both the first connection line 17 and the second connection line 18 are disposed in Figure 3BThe region corresponding to the third sub-pixel in

[0120] One end of the first connection line 17 is electrically connected to the first pole of the first transistor T1, and the other end of the first connection line 17 is electrically connected to the first data line 141. One end of the second connection line 18 is electrically connected to the second pole of the first transistor T1, and the other end of the second connection line 18 is electrically connected to the second data line 142.

[0121] In some embodiments, such as Figure 4B and Figure 4C As shown, the display panel 100 further includes at least one second transistor T2; at least one second transistor T2 is configured to connect the first data line 141 together when turned on; when turned off, disconnect the part of the first data line 141 located in the first area 12 from the part located in the second area 13, and electrically connect it to the second data line 142.

[0122] Exemplarily, the second transistor T2 is a thin film transistor TFT.

[0123] Exemplarily, multiple second transistors T2 are at least partially arranged on the same layer. Additionally, multiple second transistors T2 are at least partially arranged on the same layer as the first data line 141. The second transistors T2 arranged on the same layer are formed synchronously through a patterning process.

[0124] In some examples, such as Figure 4B As shown, the light-transmitting area 11 is located in the middle of the display area 1; the first data line 141 includes a first part 1411, and second parts 1412 and 1413 located on both sides of the first part 1411. The first part 1411 is located in the first area 12, and the second parts 1412 and 1413 are located in the second area 13; the second part 1412 is closer to the signal input end of the first data line 141 than the third part 1413.

[0125] The display panel 100 includes one second transistor T2; the first part 1411 and the second part 1412 of the first data line 141 are electrically connected through the second transistor T2. That is, the first pole of the second transistor T2 is electrically connected to the first part 1411 of the first data line 141, and the second pole of the second transistor T2 is electrically connected to the second part 1412 of the first data line 141. The gate of the second transistor T2 is connected to the second control end through the second control signal line 21 to control the turning on or off of the second transistor T2.

[0126] Exemplarily, the second transistor T2 is disposed on a side close to the signal input end of the first data line 141. For example, it is located in the area of the last pixel row of the display area 1.

[0127] Reference Figure 3B 、 Figure 4B 、 Figure 5A And Figure 5B Taking the first transistor T1, the second transistor T2, and each transistor in the pixel driving circuit as P-type transistors as an example.

[0128] As Figure 3B 、 Figure 4B And Figure 5A As shown in, when the processor inputs a gate scan signal G1 to the pixel driving circuit electrically connected to any one of the second light-emitting devices A in the light-transmitting area 11, it also inputs a first control signal K1 to the first transistor T1. The first control signal K1 is a low-level signal, and the first transistor T1 is turned on. The first data line 141 and the second data line 142 are connected as one body. The second data signal from the data signal input end of the second data signal line 142 is transmitted to the pixel driving circuit electrically connected to the second light-emitting device A through the first data line 141, so that the pixel driving circuit drives the second light-emitting device A to emit light according to the second data signal. At this time, the second control signal K2 is a high-level signal, and the second transistor T2 is turned off, so that the first part 1411 and the second part 1412 of the first data line 141 are disconnected to prevent the first data signal from the signal input end of the first data line 141 from being transmitted to the pixel driving circuit electrically connected to the second light-emitting device A.

[0129] As Figure 3B 、 Figure 4C And Figure 5B As shown in, when the processor inputs a gate scan signal G2 to any row of pixel driving circuits in the second area 13, it inputs a first control signal K1 to the first transistor T1. The first control signal K1 is a high-level signal, and the first transistor T1 is turned off. The first data line 141 and the second data line 142 are not connected. At this time, the second control signal K2 is a low-level signal, and the second transistor T2 is turned on. The first part 1411 and the second part 1412 of the first data line 141 are connected as one body, so that the first data signal from the signal input end of the first data line 141 is transmitted to the pixel driving circuit of this row through the first data line 141, so that the first light-emitting device in the effective sub-pixel P electrically connected to the pixel driving circuit of this row emits light; the second data signal from the data signal input end of the second data line 142 is transmitted to the pixel driving circuit of this row through the second data line 142, so that the first light-emitting device in the effective sub-pixel P electrically connected to the pixel driving circuit of this row emits light.

[0130] In some other examples, asFigure 4C As shown, the light-transmitting region 11 is located in the middle of the display region 1. The display panel includes two second transistors T2. The first part 1411 and the second part 1412 are electrically connected through one of the second transistors T21, and the first part 1411 and the third part 1413 are electrically connected through the other second transistor T22.

[0131] Exemplarily, the second transistor T22 is disposed on a side close to the signal input end of the first data line 141. For example, it is located in the area of the last pixel row of the display region 1. The second transistor T21 is disposed at the position of a row of sub-pixels in the second region 13 closest to the first region 12.

[0132] In this way, when the first transistor T1 is turned on, the second transistor T2 connecting the first part 1411 and the second part 1412 is turned off to prevent the first data signal from the signal input end of the first data line 141 from being transmitted to the pixel driving circuit electrically connected to the second light-emitting device A. Turning off the second transistor T2 connecting the first part 1411 and the third part 1413 can prevent the second data signal from the second data line 142 from being transmitted to the third part 1413 of the first data line 141 while being transmitted to the first part 1411 of the first data line 141.

[0133] Taking the first transistor T1, the second transistor T2, and each transistor in the pixel driving circuit as P-type transistors as an example.

[0134] As Figure 3B 、 Figure 4B and Figure 6A shown, when the processor inputs a gate scan signal G1 to the pixel driving circuit electrically connected to any one of the second light-emitting devices A in the light-transmitting region 11, it also inputs a first control signal K1 to the first transistor T1. The first control signal K1 is a low-level signal, and the first transistor T1 is turned on. The first data line 141 and the second data line 142 are connected as a whole. The second data signal from the data signal input end of the second data signal line 142 is transmitted to the pixel driving circuit electrically connected to the second light-emitting device A through the first data line 141, so that the pixel driving circuit drives the second light-emitting device A to emit light according to the second data signal. At this time, both the second control signals K21 and K22 are high-level signals, and both the second transistor T21 and the second transistor T22 are turned off, disconnecting the first part 1411 and the second part 1412 of the first data line 141 to prevent the first data signal from the signal input end of the first data line 141 from being transmitted to the pixel driving circuit electrically connected to the second light-emitting device A.

[0135] As Figure 3B 、 Figure 4B and Figure 6BAs shown, when the processor inputs a gate scan signal G1 to the pixel driving circuit of any row of sub-pixels in the second region 12 (i.e., Figure 2B the first row, the second row, the seventh row, or the eighth row in ), a first control signal K1 is input to the first transistor T1. The first control signal K1 is a high-level signal, and the first transistor T1 is turned off. The first data line 141 and the second data line 142 are not connected. At this time, both the second control signals K21 and K22 are low-level signals, and the second transistor T21 and the second transistor T22 are turned on. The first part 1411, the second part 1412, and the third part 1413 of the first data line 141 are connected as a whole, so that the first data signal from the signal input end of the first data line 141 is transmitted through the first data line 141 to the pixel driving circuit of this row, so that the first light-emitting device in the effective sub-pixel P electrically connected to the pixel driving circuit of this row emits light; the second data signal from the signal input end of the second data line 142 is transmitted through the second data line 142 to the pixel driving circuit of this row, so that the first light-emitting device in the effective sub-pixel P electrically connected to the pixel driving circuit of this row emits light.

[0136] In some embodiments, as Figure 4C shown, the display panel further includes a capacitor C. To distinguish it from the first storage capacitor Cst in the above driving circuit, the capacitor C will be hereinafter referred to as the second storage capacitor C2.

[0137] The first storage electrode of the second storage capacitor C2 is electrically connected to the first pole of the first transistor T1, and the second storage electrode of the second storage capacitor C2 is electrically connected to the second pole of the first transistor T1. In this way, the second data signal from the signal input end of the second data line 142 is transmitted to the second storage electrode of the second storage capacitor C2, so that the voltage of the second storage electrode of the second storage capacitor C2 is the voltage of the second data signal (denoted as V2), and the voltage of the first storage electrode of the second storage capacitor C2 is the voltage of the first data signal from the signal input end of the first data line 141 (denoted as V1). In this way, the first transistor T1 is turned on. According to the charge retention law of the capacitor, the voltage of the first storage electrode of the second storage capacitor C2 jumps from V1 to V2, so that the voltages of the first pole and the second pole of the first transistor T1 reach the same in a short time, reducing the voltage drop, and the influence of the first transistor T1 on the transmission of the second data signal can be reduced (refer to Figure 7 ), improving the brightness uniformity of the display panel. Figure 7The figure shows a signal simulation waveform diagram of the second data signal transmitted from the second data line to the first data line. Among them, Q1 is the signal simulation waveform diagram of the second data signal transmitted from the second data line to the first data line after electrically connecting the second storage capacitor C2 between the first pole and the second pole of the first transistor T1; Q2 is the signal simulation waveform diagram of the second data signal transmitted from the second data line to the first data line without electrically connecting the second storage capacitor C2 between the first pole and the second pole of the first transistor T1.

[0138] In some embodiments, the distance between any two adjacent second light-emitting devices A in each row of the second light-emitting devices A is equal. In a row of sub-pixels including the virtual sub-pixel D and the like, the distance between any two adjacent effective sub-pixels P is equal to the distance between two adjacent second light-emitting devices A. In this way, the display resolutions of the light-transmitting region 11 and the first region 12 are equal, improving the display effect of the display panel.

[0139] In some examples, such as Figure 3A and Figure 3B as shown, in a row of sub-pixels P including the virtual sub-pixel D and the effective sub-pixel, three virtual sub-pixels D are provided between any two adjacent effective sub-pixels P. Here, since only the effective sub-pixel P is included in the second region 13, the resolution of the second region 13 is higher than the resolutions of the first region 12 and the light-transmitting region 11.

[0140] In some embodiments, such as Figure 3A and Figure 3B as shown, the display region 1 includes a first region 12, and the first region 12 is located on one side of the light-transmitting region 11 along the direction of the vertical data line.

[0141] In some embodiments, such as Figure 8 as shown, the display region 1 includes two first regions 12, and the two first regions 12 are respectively located on both sides of the light-transmitting region 11 along the direction of the vertical data line. The light-transmitting region 11 is located in the middle of the display region 1. In this way, a plurality of virtual sub-pixels D in the first regions 12 on both sides of the light-transmitting region 11 are respectively electrically connected to the second light-emitting devices A in the light-transmitting region 11, which can make the wiring positions of the plurality of auxiliary connection lines 15 and the plurality of data lines in the display panel more uniform.

[0142] In some embodiments, such as Figure 9 as shown, the display region 1 includes two first regions 12, one first region 12 is located on one side of the light-transmitting region 11 along the direction of the vertical data line, and the other first region 12 is located on one side of the light-transmitting region 11 along the direction of the data line. The light-transmitting region 11 is located in the middle of the display region 1. Figure 7 The plurality of sub-pixels shown are arranged in 12 rows and 18 columns, sequentially the 1st column to the 18th column along the X direction, and sequentially the 1st row to the 12th row along the Y direction.

[0143] In some examples, the display panel 100 further includes a plurality of gate lines 19 and a plurality of scan signal connection lines 20. At least the effective sub-pixels P in one row of pixels are electrically connected to one gate line. For example, as Figure 9 shown, one gate line 19 is electrically connected to the sub-pixels in the pixels of the 9th row, and the sub-pixels in this row include effective sub-pixels P and virtual sub-pixels D. Another example is, as Figure 7 shown, one gate line 19 is electrically connected to the sub-pixels in the pixels of the 2nd row, and only effective sub-pixels P are included in the sub-pixels in this row.

[0144] One end of each scan signal connection line 20 is electrically connected to the gate line 19 that is electrically connected to the effective sub-pixel P in the same row as a second light-emitting device A, and the other end of the scan signal connection line 20 is electrically connected to the pixel data driving circuit of the virtual sub-pixel D that is electrically connected to the second light-emitting device A, and the pixel data driving circuit of the virtual sub-pixel D is insulated from the gate line 20 that is electrically connected to the effective sub-pixel P in the same row as the virtual sub-pixel D.

[0145] For example, as Figure 9 shown, the first data line 141-3 is electrically connected to the pixel driving circuit in the sub-pixels located in the 4th column. The second light-emitting device A in the 1st column in the light-transmitting area 11 and the sub-pixels in the 8th column are in the same column. The second data line 142-3 is electrically connected to the pixel driving circuit in the sub-pixels located in the 8th column; the second light-emitting device A in the 1st row and 1st column in the light-transmitting area 11 is electrically connected to the pixel data driving circuit of the virtual sub-pixel D in the same row through the auxiliary connection line 15; the first data line 141-3 and the second data line 142-3 are electrically connected through the first transistor T1.

[0146] In this way, when the first transistor T1 is turned on, the first data line 141-3 and the second data line 142-3 are connected as a whole, and the second data signal from the signal input end of the second data line 142-3 is transmitted to the pixel data driving circuit of the virtual sub-pixel D that is electrically connected to the second light-emitting device A through the first data line 141-3, so that the second light-emitting device A emits light.

[0147] When the first transistor T1 is turned off, the first data line 141-3 and the second data line 142-3 are not connected, and the first data signal from the signal input end of the first data line 141-3 is transmitted to the pixel data circuit that is electrically connected to the first data line 141-3, so that a column of effective sub-pixels P that are electrically connected to the first data line 141-3 can be normally displayed.

[0148] Another example is, as Figure 9As shown, the second light-emitting device A in the third column of the light-transmitting region 11 is in the same column as the sub-pixels in the 12th column, and the second data line 142-4 is electrically connected to the pixel driving circuit in the sub-pixels in the 12th column; the first data line 141-4 is electrically connected to the pixel driving circuit in the sub-pixels in the 11th column; the second light-emitting device A in the third row of the third column in the light-transmitting region 11 is electrically connected to the pixel data driving circuit of the virtual sub-pixel D in the same column through the auxiliary connection line 15; the first data line 141-4 and the second data line 142-4 are electrically connected through the first transistor T1; one end of the scan signal connection line 20 is electrically connected to the gate line 19-1 electrically connected to the effective sub-pixel P in the same row (i.e., the 9th row) as the second light-emitting device A, and the other end of the scan signal connection line 20 is electrically connected to the pixel data driving circuit of the virtual sub-pixel D electrically connected to the second light-emitting device A, and the pixel data driving circuit of the virtual sub-pixel D is insulated from the gate line 19-2 electrically connected to the effective sub-pixel P in the same row (i.e., the 5th row) as the virtual sub-pixel D.

[0149] In this way, when the first transistor T1 is turned on, the first data line 141-2 and the second data line 142-4 are connected as a whole, and the second data signal from the signal input end of the second data line 142-4 is transmitted through the first data line 141-4 to the pixel data driving circuit of the virtual sub-pixel D electrically connected to the second light-emitting device A, and the gate line scan signal from the gate line 19-1 is transmitted through the scan signal connection line 20 to the pixel data driving circuit of the virtual sub-pixel D electrically connected to the second light-emitting device A, so that the second light-emitting device A emits light normally.

[0150] When the first transistor T1 is turned off, the first data line 141-4 and the second data line 142-4 are not connected, and the first data signal from the signal input end of the first data line 141-4 is transmitted to the pixel data circuit electrically connected to the first data line 142, so that a column of effective sub-pixels P electrically connected to the first data line 141-4 can be normally displayed; the second data signal from the signal input end of the second data line 142-4 is transmitted to the pixel data circuit electrically connected to the second data line 142-4, so that a column of effective sub-pixels P electrically connected to the second data line 142-4 can be normally displayed.

[0151] In addition, as Figure 9 shown, a first region 12 is provided on one side of the light-transmitting region 11 along the data line direction, increasing the number of virtual sub-pixels D, so that the number of second light-emitting devices A in the light-transmitting region increases, and the area of the light-transmitting region 11 is enlarged.

[0152] Some embodiments of the present disclosure provide a control method for a display panel, including S100-S300.

[0153] S100. The processor inputs a gate scan signal to multiple rows of sub-pixels row by row.

[0154] S200. When the processor inputs a gate scan signal to the pixel driving circuit electrically connected to any second light-emitting device A in the light-transmitting area 11, it also inputs a control signal to the first transistor T1 to turn on the first transistor T1.

[0155] S300. The processor inputs data signals to each row of sub-pixels through multiple data lines 14; when the first transistor T1 is turned on, the second data signal from the signal input end of the second data line 142 is transmitted to the pixel driving circuit electrically connected to the second light-emitting device A through the first data line 141.

[0156] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, It has a display area, and the display area includes a light-transmitting area, at least one first area, and a second area, and the at least one first area is at least located on one side of the light-transmitting area; The display panel includes: A plurality of sub-pixels provided in the at least one first area and the second area, and the plurality of sub-pixels are arranged in multiple rows and multiple columns; the plurality of sub-pixels include a plurality of effective sub-pixels and a plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are provided in the at least one first area; each sub-pixel includes a pixel driving circuit, and each effective sub-pixel further includes a first light-emitting device electrically connected to the pixel driving circuit; A plurality of second light-emitting devices provided in the light-transmitting area, and the plurality of second light-emitting devices are arranged in multiple columns of second light-emitting devices, and each column of second light-emitting devices and a column of sub-pixels are arranged in a column; A plurality of data lines, and the pixel driving circuits in a column of sub-pixels are electrically connected to one data line; the plurality of data lines include a first data line and a second data line; the first data line is electrically connected to the pixel driving circuits in a column of sub-pixels including virtual sub-pixels; the second data line is electrically connected to the pixel driving circuits in a column of sub-pixels located in the same column as a column of second light-emitting devices; one second light-emitting device in the column of second light-emitting devices is electrically connected to the pixel driving circuit in one virtual sub-pixel connected to the first data line; A first transistor, and the first data line and the second data line are electrically connected through the first transistor.

2. The display panel according to claim 1, wherein In a column of sub-pixels electrically connected to the first data line, the sub-pixels located in the first area are all virtual sub-pixels.

3. The display panel according to claim 1, wherein The effective sub-pixels located in the first area among the plurality of effective sub-pixels are uniformly arranged.

4. The display panel according to claim 1, characterized in that, It further includes: A first connection line provided on a side of the first area away from the signal input end of the first data line; one end of the first connection line is electrically connected to the first pole of the first transistor, and the other end of the first connection line is electrically connected to the first data line; and / or, A second connection line provided on a side of the first area away from the signal input end of the first data line; one end of the second connection line is electrically connected to the second pole of the first transistor, and the other end of the second connection line is electrically connected to the second data line.

5. The display panel according to claim 1, wherein It further includes: At least one second transistor; the at least one second transistor is configured to connect the first data line as a whole when it is turned on; when it is turned off, the part of the first data line located in the first area is disconnected from the part located in the second area and is electrically connected to the second data line.

6. The display panel according to claim 5, characterized in that, The light-transmitting area is located in the middle of the display area; The first data line includes a first part, and second parts and third parts located on both sides of the first part, the first part is located in the first area, and the second part and the third part are located in the second area; the second part is closer to the signal input end of the first data line than the third part; The at least one second transistor includes one second transistor; the first part and the second part are electrically connected through the second transistor; alternatively, the at least one second transistor includes two second transistors, the first part and the second part are electrically connected through one of the second transistors, and the first part and the third part are electrically connected through the other second transistor.

7. The display panel according to claim 1, wherein Further included is: A capacitor; a first storage electrode of the capacitor is electrically connected to a first pole of the first transistor, and a second storage electrode of the capacitor is electrically connected to a second pole of the first transistor.

8. The display panel according to claim 1, wherein The pitch between any two adjacent second light-emitting devices in each row of second light-emitting devices is equal; In a row of sub-pixels including virtual sub-pixels and effective sub-pixels, the pitch between any two adjacent effective sub-pixels is equal to the pitch between the two adjacent second light-emitting devices.

9. The display panel according to claim 8, wherein In a row of sub-pixels including virtual sub-pixels and effective sub-pixels, three of the virtual sub-pixels are provided between any two adjacent effective sub-pixels.

10. The display panel according to claim 1, wherein The at least one first region includes one first region, and this first region is located on one side of the light-transmitting region along the direction of the vertical data line.

11. The display panel according to claim 1, characterized in that The at least one first region includes two first regions, and these two first regions are respectively located on both sides of the light-transmitting region along the direction of the vertical data line.

12. The display panel according to claim 1, wherein The at least one first region includes two first regions, one first region is located on one side of the light-transmitting region along the direction of the vertical data line, and the other first region is located on one side of the light-transmitting region along the direction of the data line.

13. The display panel according to claim 12, wherein Further included is: Multiple gate lines, and at least the effective sub-pixels in one row of pixels are electrically connected to one gate line; Multiple scan signal connection lines; one end of a scan signal connection line is electrically connected to the gate line electrically connected to the effective sub-pixels in the same row as a second light-emitting device, the other end of the scan signal connection line is electrically connected to the pixel data driving circuit of the virtual sub-pixel electrically connected to the second light-emitting device, and the pixel data driving circuit of this virtual sub-pixel is insulated from the gate line electrically connected to the effective sub-pixels in the same row as this virtual sub-pixel.

14. The display panel according to any one of claims 1-13, characterized in that, Both the first light-emitting device and the second light-emitting device are OLEDs.

15. A display device, characterized in that, Included is: The display panel according to any one of claims 1-14; An image sensor located in the light-transmitting region.

16. A control method for a display panel as described in claim 1, characterized in that, Included is: Inputting a gate scan signal to multiple rows of sub-pixels row by row; When inputting a gate scan signal to the pixel driving circuit electrically connected to any second light-emitting device in the light-transmitting region, also inputting a control signal to the first transistor to turn on the first transistor; Inputting a data signal to each row of sub-pixels through the multiple data lines; when the first transistor is turned on, the second data signal from the signal input end of the second data line is transmitted through the first data line to the pixel driving circuit electrically connected to the second light-emitting device.

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