A high-g MEMS inertial micro-module and preparation method thereof

Abstract

The present invention discloses an anti-high-overload MEMS inertial micro-module and a preparation method thereof. The MEMS inertial micro-module performs a double-sided PAD process on the ASIC chip, separately leads out two types of interconnection signals of the ASIC on the upper and lower surfaces. The top surface PAD of the ASIC chip is designed as an interconnection signal interface with the MEMS sensitive structure chip, and the bottom surface PAD is designed as an output signal interface for interconnection with the package shell. The ASIC chip and the MEMS sensitive structure chip are stacked. In the present invention, the MEMS sensitive structure chip is placed above the ASIC chip, which can reduce the stress transmission caused by high-overload impact to a certain extent and improve the overall anti-high-overload ability of the MEMS inertial micro-module. At the same time, placing the ASIC chip under the MEMS sensitive structure can directly connect the output signal to the package shell by means of micro-ball welding, reducing the additional signal interconnection form, lowering the process assembly complexity, and enhancing the reliability under high-overload environments.

Description

Technical Field

[0001] The invention relates to a high overload resistant MEMS inertial micromodule and a preparation method thereof, belonging to the technical field of inertial microsystems. Background Art

[0002] With the emergence of micro-electromechanical systems (MEMS), vertical interconnection, 3D integration and other process technologies, traditional gold wire bonding and two-piece adhesive assembly of MEMS inertial sensors will gradually be replaced by MEMS inertial micro-modules using advanced packaging technology. Since MEMS inertial micro-modules use vertical signal interconnection and chip stacking through micro-balls (u-bumps), they can reduce the structure size, reduce system power consumption, and improve interconnection reliability, and have great application potential in precision-guided weapons.

[0003] like Figure 1 As shown, the existing inertial micromodule mainly includes a MEMS sensitive structure chip, a TSV silicon adapter board 1 and an ASIC chip 4. It adopts a 2.5D integrated design, and the MEMS sensitive structure chip is stacked on the TSV silicon adapter board by planting balls. The ASIC chip and the TSV silicon adapter board are stacked by using micro balls (u-bump) through flip chip technology. The TSV silicon adapter board is used as a carrier to realize the signal interconnection between the MEMS sensitive structure chip and the ASIC chip. Finally, a large ball is planted around the ASIC chip on the bottom surface of the TSV silicon adapter board to realize the external signal extraction. The overall inertial micromodule is a sandwich-like stacking structure.

[0004] Since the TSV silicon transfer board is only a few hundred microns thick, increasing the thickness will cause difficulties in the TSV process and cause defects in TSV metal filling. Therefore, the thickness of the TSV silicon transfer board is usually 200~500um, and the horizontal size is several thousand um, so the TSV silicon transfer board is a very thin plate structure. The existing design only welds the implant ball around the ASIC chip for external signal output. When subjected to high overload impact, the stress distribution of the TSV silicon transfer board is relatively concentrated, which has caused cracks in the TSV silicon transfer board and even caused it to break and fail.

[0005] In addition, due to the high overload impact during the launch of precision-guided weapons, it is easy to cause the micro-module interconnection structure micro-ball (u-bump) to break, fall off, and even cause chip stress damage. Therefore, it is necessary to improve the micro-module chip stacking method, optimize the chip signal interconnection structure, increase the stress attenuation design, and improve the micro-module's ability to resist high overload. The existing technology does not involve research on advanced packaging of inertial micro-modules that resist high overload. Summary of the invention

[0006] The object of the present invention is to provide a high-g MEMS inertial micromodule and a preparation method thereof, which adopts an ASIC chip with double-sided PADs, removes the silicon interposer in the existing 2.5D integration method, reduces the volume while realizing the advanced packaging of the high-g MEMS inertial micromodule, and improves the system integration degree.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] On the one hand, the present invention provides a preparation method of a high-g MEMS inertial micromodule, including:

[0009] S1. Perform double-sided processing of pads on the ASIC chip;

[0010] S2. Stack and interconnect the ASIC chip with double-sided processed pads and the MEMS sensitive structure chip, and weld them inside the package housing;

[0011] S3. Fill the stacked chips in the package housing with potting glue.

[0012] Further, the double-sided processing of pads on the ASIC chip includes:

[0013] S11. Increase an insulating substrate around the ASIC chip by means of deposition growth or organic material injection molding to form a cavity structure;

[0014] S12. Form a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip by deposition, which is called the second top surface insulating layer, and expose the original PADs of the ASIC chip by etching;

[0015] S13. According to the shape of the wiring metal layers on the upper and lower surfaces of the ASIC chip, perform blind hole etching on the substrate at the interconnection position, and obtain vias through back thinning of the chip;

[0016] S14. Sequentially increase a top surface seed layer and a top surface metal layer on the entire top surface of the ASIC chip by electroplating, and perform metallization filling on the vias;

[0017] S15. According to the PAD ball mounting positions of the MEMS sensitive structure chip, perform patterning processing on the top surface metal layer of the ASIC chip by etching, and remove the redundant metal to form a top surface wiring metal layer;

[0018] S16. Form a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip by deposition, which is called the first top surface insulating layer;

[0019] S17. Etch the top surface PAD position to remove the insulating layer and expose the top surface PADs required for ball mounting;

[0020] S18. Sequentially deposit a bottom seed layer and a bottom metal layer on the entire bottom surface of the ASIC chip by electroplating, and pattern the bottom metal layer according to the PAD ball placement positions to remove the excess metal, forming a bottom wiring metal layer;

[0021] S19. Form a layer of silicon dioxide insulating layer on the entire bottom surface of the ASIC chip by deposition, which is called the bottom insulating layer; and expose the bottom PADs of the required ball placements by etching.

[0022] Further, the insulating substrate is an organic material or glass.

[0023] Further, the process of stacking and interconnecting the ASIC chip with double-sided processed pads and the MEMS sensitive structure chip and welding them inside the package housing includes:

[0024] S21. Make the PAD spatial positions of the MEMS sensitive structure chip correspond one by one with the top surface PADs of the ASIC chip, and perform integrated stacking by ball placement welding;

[0025] S22. Invert the stacked chips, and perform ball placement welding on the bottom surface PADs of the ASIC chip;

[0026] S23. Weld the stacked chips with balls to the inside of the package housing.

[0027] Further, the process temperature that the balls placed on the top surface PADs of the ASIC chip can withstand in the first step is higher than the process temperature that the balls placed in the later step can withstand.

[0028] Further, the process of filling the stacked chips in the package housing with potting glue includes:

[0029] Adopt the method of injecting glue around the perimeter to fill the stacked chips in the package housing with potting glue.

[0030] Further, the height of the potting glue does not exceed the ASIC chip.

[0031] On the other hand, the present invention provides a high-g MEMS inertial micro-module, which is prepared by using the preparation method of the high-g MEMS inertial micro-module described above. The high-g MEMS inertial micro-module includes a package housing, and stacked chips welded inside the package housing;

[0032] The stacked chips are formed by ball placement welding of a MEMS sensitive structure chip and an ASIC chip;

[0033] The ASIC chip is an ASIC chip with double-sided processed pads.

[0034] Further, the top surface PAD of the ASIC chip is an interconnection signal interface with the MEMS sensitive structure chip, and the bottom surface PAD of the ASIC chip is an output signal interface for interconnection with the package case.

[0035] Further, the microsphere gap between the ASIC chip with double-sided processed pads and the package case, and the area around the ASIC chip with double-sided processed pads are filled with potting glue.

[0036] The beneficial effects of the present invention are as follows:

[0037] The present invention provides a packaged MEMS inertial micro-module. After completing chip stacking and interconnection with the package case, the microsphere (u-bump) gap between the ASIC chip and the package case and the area around the ASIC are filled with potting glue, optimizing the interconnection form of the stacked chips and the package case from being integrated only by welding of microspheres (u-bumps) to a hybrid integration of microspheres (u-bumps) and glue. After potting glue filling, not only the contact and fixing area between the stacked chips and the package case is increased, but also due to the viscoelasticity of the glue, when the MEMS inertial micro-module is subjected to high overload impact, stress can be attenuated and released, further improving the reliability of the MEMS inertial micro-module in a high overload environment.

[0038] The present invention removes the silicon interposer in the existing 2.5D integration method, reducing the volume and improving the system integration while achieving advanced packaging of the MEMS inertial micro-module against high overload. Description of the Drawings

[0039] Figure 1 Schematic diagram of an existing 2.5D integrated MEMS inertial micro-module;

[0040] Figure 2 Schematic diagram of an advanced packaged MEMS inertial micro-module against high overload provided by an embodiment of the present invention;

[0041] Figure 3 Process sectional view of the double-sided PAD ASIC chip structure provided by an embodiment of the present invention;

[0042] Wherein: 1. TSV silicon interposer; 2. Package case; 3. Ball planting; 4. ASIC chip; 5. MEMS sensitive structure chip; 6. Potting glue; 7. ASIC chip with double-sided PADs; 8. Top surface wiring metal layer; 9. Top surface seed layer; 10. Original PAD of the ASIC chip; 11. Metallized TSV (through-silicon via); 12. Bottom surface seed layer; 13. Bottom surface wiring metal layer; 14. Bottom surface PAD; 15. Top surface PAD; 16. First top surface insulation layer; 17. Second top surface insulation layer; 18. Substrate; 19. Bottom surface insulation layer. Detailed Embodiments

[0043] Example 1

[0044] This example provides a method for fabricating a high-g MEMS inertial micro-module, including:

[0045] S1. Perform double-sided processing of pads (referred to as PAD) on the ASIC chip;

[0046] S2. Stack and interconnect the ASIC chip with double-sided processed pads and the MEMS sensitive structure chip, and weld them inside the package housing;

[0047] S3. Fill the stacked chips in the package housing with glue.

[0048] In this example, double-sided processing of pads is performed on the ASIC chip to form a double-sided PAD ASIC chip structure, as Figure 3 shown. The specific implementation process is as follows:

[0049] S11. Increase the insulating substrate 18 around the ASIC chip 4 by deposition growth or organic material injection molding to form a cavity structure. The cavity depth is the same as the ASIC thickness, serving as the basic structure for subsequent metallization vias and through-hole metal wiring.

[0050] S12. Deposit a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip, called the second top surface insulating layer 17, and expose the original PAD10 of the ASIC chip by etching.

[0051] It should be noted that the thickness of the second top surface insulating layer is about 2um.

[0052] S13. For the MEMS inertial micro-module interconnection solution, according to the shape of the upper and lower surface wiring metal layers, perform blind via etching on the substrate 18 at the interconnection position, and obtain vias through back thinning of the chip.

[0053] S14. Sequentially deposit a top surface seed layer 9 and a top surface metal layer on the entire top surface of the ASIC chip by electroplating, and metallize and fill the vias, i.e., metallize the TSV11;

[0054] It should be noted that the thickness of the top surface seed layer is usually 200nm, and the thickness of the top surface metal layer is 3um.

[0055] S15. According to the PAD ball placement position of the MEMS sensitive structure chip, perform patterning processing on the top surface metal layer of the ASIC chip by etching to remove the excess metal and form the top surface wiring metal layer 8.

[0056] S16. Deposit a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip by deposition, called the first top surface insulating layer 16, to protect the top surface metal wiring.

[0057] It should be noted that the thickness of the first top surface insulating layer 16 is generally 3 - 5 μm.

[0058] S17. Etch the position of the top surface PAD to remove the insulating layer and expose the top surface PAD 15 of the ball to be implanted, thus completing the production of the top surface PAD.

[0059] S18. For the signals that need to be led out externally from the ASIC chip, according to the ball implantation design scheme, use the same method as the top surface to form the bottom surface seed layer 12 and the top and bottom surface metal layers on the bottom surface, and perform patterning processing on the bottom surface metal layer to remove the redundant metal, thus forming the bottom surface wiring metal layer 13.

[0060] S19. Form a layer of silicon dioxide insulating layer on the entire bottom surface of the ASIC chip by deposition, which is called the bottom surface insulating layer 19 to protect the bottom surface metal wiring, and expose the bottom surface PAD 14 of the ball to be implanted through etching, thus completing the production of the bottom surface PAD.

[0061] It should be noted that in this embodiment, the original single - layer PAD surface of the ASIC chip is defaulted as the top surface. Since there are fewer interconnection signals between the ASIC chip and the MEMS sensitive structure chip, and more interconnection signals with the package housing, in order to reduce the process difficulty, the PAD that needs to add metallized vias is designed as the interconnection signal interface with the MEMS sensitive structure chip.

[0062] It should be noted that an insulating substrate is added around the ASIC chip, and the insulating substrate can be an organic material, glass, etc.

[0063] In this embodiment, the ASIC chip with double - sided processed pads and the MEMS sensitive structure chip are stacked and interconnected. The specific implementation process is as follows.

[0064] S21. Make the PAD spatial positions of the MEMS sensitive structure chip correspond one - to - one with the PADs on the top surface of the ASIC chip, and use ball implantation welding for integrated stacking.

[0065] S22. Invert the stacked chips, and perform ball implantation welding on the PADs on the bottom surface of the ASIC chip.

[0066] S23. Weld the stacked chips with balls to the inside of the package housing.

[0067] As a preferred implementation method, due to the existence of two ball implantation and package welding processes, the temperature gradient of ball implantation needs to be considered. The process temperature that the top surface PAD of the ASIC chip and the MEMS sensitive structure chip can withstand for the first ball implantation should be higher than that of the subsequent ball implantation, to prevent the already completed implanted balls from melting during the subsequent ball implantation process, resulting in reliability problems of the stacked chips.

[0068] As a preferred embodiment, since the gap of the micro-balls (u-bumps) connecting the ASIC chip and the packaging shell is small, it is necessary to select a potting adhesive with good fluidity. At the same time, during the filling process, the method of injecting glue from all around is adopted to fully fill the bottom of the stacked chips with the potting adhesive.

[0069] It should be noted that since the MEMS sensitive structure chip is sensitive to stress, during the potting filling process, it is necessary to control the height of the potting glue not to exceed the ASIC chip to avoid the potting adhesive coating the MEMS sensitive structure chip, resulting in stress generated after the colloid solidifies and affecting the performance of the MEMS inertial micro-module.

[0070] The preparation method of the high-g overload resistant MEMS inertial micro-module provided in this embodiment realizes the stacking with the MEMS sensitive structure chip and the interconnection with the packaging shell by preparing the ASIC chip with double-sided PADs. After completing the chip stacking and the interconnection with the packaging shell, the gap of the micro-balls (u-bumps) between the ASIC chip and the packaging shell and the area around the ASIC are filled with potting glue. The interconnection form of the stacked chips and the packaging shell is optimized from the welding integration relying only on the micro-balls (u-bumps) to the hybrid integration of the micro-balls (u-bumps) / glue. After the potting filling, not only the contact and fixing area between the stacked chips and the packaging shell is increased, but also because the glue has certain viscoelasticity, when the MEMS inertial micro-module bears high-g overload impact, the stress can be attenuated and released, further improving the reliability of the MEMS inertial micro-module in a high-g overload environment.

[0071] Embodiment 2

[0072] This embodiment provides a high-g overload resistant MEMS inertial micro-module, which is prepared by using the preparation method of Embodiment 1. Refer to Figure 2 , the high-g overload resistant MEMS inertial micro-module includes a packaging shell 2 and stacked chips welded inside the packaging shell.

[0073] The stacked chips are formed by welding the MEMS sensitive structure chip 5 and the ASIC chip 7 with double-sided PADs through ball planting 3.

[0074] The ASIC chip with double-sided PADs is prepared by using the method disclosed in Embodiment 1.

[0075] In this embodiment, the gap of the micro-balls (u-bumps) between the ASIC chip with double-sided PADs and the packaging shell 2 and the area around the ASIC chip with double-sided PADs are filled with potting glue 6.

[0076] In this embodiment, the top PAD of the ASIC chip is the signal interface for interconnection with the MEMS sensitive structure chip, and the bottom PAD is the lead-out signal interface for interconnection with the packaging shell.

[0077] For the anti-high-overload MEMS inertial micro-module prepared in this embodiment, placing the MEMS sensitive structure chip above the ASIC chip can, to a certain extent, reduce the stress transmission caused by high-overload impact and improve the overall anti-high-overload ability of the MEMS inertial micro-module. At the same time, placing the ASIC chip below the MEMS sensitive structure chip can directly connect the output signals to the package shell by means of u-bump soldering, reducing the additional signal interconnection form, lowering the process assembly complexity, and enhancing the reliability.

[0078] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A preparation method of a high-overload-resistant MEMS inertial micro-module, characterized in that, Including: S1. Double-sided processing of pads for the ASIC chip, including: S11. Adding an insulating substrate around the ASIC chip by means of deposition growth or injection molding of organic materials to form a cavity structure; S12. Forming a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip by deposition, called the second top surface insulating layer, and exposing the original PAD of the ASIC chip by etching; S13. According to the shape of the wiring metal layers on the upper and lower surfaces of the ASIC chip, performing blind hole etching on the substrate at the interconnection position, and obtaining vias through back thinning of the chip; S14. Sequentially adding a top surface seed layer and a top surface metal layer on the entire top surface of the ASIC chip by electroplating, and metallizing and filling the vias; S15. According to the PAD ball mounting positions of the MEMS sensitive structure chip, performing patterning processing on the top surface metal layer of the ASIC chip by etching to remove the redundant metal and form the top surface wiring metal layer; S16. Forming a layer of silicon dioxide insulating layer on the entire top surface of the ASIC chip by deposition, called the first top surface insulating layer; S17. Etching the top surface PAD position to remove the insulating layer and expose the top surface PAD for the required ball mounting; S18. Sequentially adding a bottom surface seed layer and a bottom surface metal layer on the entire bottom surface of the ASIC chip by electroplating, and performing patterning processing on the bottom surface metal layer according to the PAD ball mounting positions to remove the redundant metal and form the bottom surface wiring metal layer; S19. Forming a layer of silicon dioxide insulating layer on the entire bottom surface of the ASIC chip by deposition, called the bottom surface insulating layer; and exposing the bottom surface PAD for the required ball mounting by etching; S2. Stacking and interconnecting the ASIC chip with double-sided processed pads and the MEMS sensitive structure chip, and welding them inside the package shell; S3. Filling the stacked chips in the package shell with potting glue.

2. The preparation method of a high-g MEMS inertial micro-module according to claim 1, characterized in that The insulating substrate is an organic material or glass.

3. The preparation method of a high-g MEMS inertial micro-module according to claim 1, characterized in that, The stacking and interconnecting of the ASIC chip with double-sided processed pads and the MEMS sensitive structure chip, and welding them inside the package shell includes: S21. Making the PAD spatial positions of the MEMS sensitive structure chip correspond one by one to the top surface PADs of the ASIC chip, and performing integrated stacking by ball mounting welding; S22. Inverting the stacked chips, and performing ball mounting welding on the bottom surface PADs of the ASIC chip; S23. Welding the stacked chips with ball mounting to the inside of the package shell.

4. The preparation method of a high-g MEMS inertial micro-module according to claim 3, characterized in that The process temperature that the ball mounting between the top surface PAD of the ASIC chip and the MEMS sensitive structure chip can withstand first is higher than the process temperature that the subsequent ball mounting can withstand.

5. The preparation method of a high-g MEMS inertial micro-module according to claim 1, characterized in that The filling of the stacked chips in the package shell with potting glue includes: Adopting the method of injecting glue around the perimeter to fill the stacked chips in the package shell with potting glue.

6. The preparation method of a high-g MEMS inertial micro-module according to claim 5, characterized in that, The height of the potting glue does not exceed the ASIC chip.

7. A high-g MEMS inertial micro-module, characterized in that, Prepared by using the preparation method of the high-g MEMS inertial micro-module according to any one of claims 1 to 6, the high-g MEMS inertial micro-module includes a package shell, and stacked chips welded inside the package shell; The stacked chip is formed by ball bonding a MEMS sensitive structure chip and an ASIC chip; The ASIC chip is an ASIC chip with pads processed on both sides.

8. An anti-high-overload MEMS inertial micro-module according to claim 7, characterized in that, The top surface PAD of the ASIC chip is an interconnection signal interface with the MEMS sensitive structure chip, and the bottom surface PAD of the ASIC chip is an output signal interface for interconnection with the package housing.

9. The anti-high-overload MEMS inertial micromodule according to claim 7, characterized in that, The microsphere gap between the ASIC chip with pads processed on both sides and the package housing and the area around the ASIC chip with pads processed on both sides are filled with potting glue.

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