An SRAM access device for realizing SSD master control RAID

Abstract

The present invention discloses an SRAM access device for implementing RAID in an SSD master control. The device comprises two single-port SRAMs and a logic control circuit connected to the single-port SRAMs. The logic control circuit controls the two single-port SRAMs to perform read or write operations in the same clock cycle. The two single-port SRAMs alternately function as odd-address SRAMs, reading or writing odd-address data when functioning as odd-address SRAMs and reading or writing even-address data when functioning as even-address SRAMs. The logic control circuit includes a parity flag logic circuit, an enable logic circuit, a write enable logic circuit, an address multiplexer, a read data multiplexer, and a read data cache circuit. The present invention utilizes two SPSRAMs and a corresponding control logic circuit to reduce chip area, lower power consumption, and increase frequency while ensuring functionality.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to an SRAM access device for realizing an SSD master control RAID. Background Art

[0002] As shown in Table 1, based on the datasheet statistics for 12nm on-chip SRAM (4KB and 8KB), the following conclusions can be drawn: In terms of area, SPSRAM (single-port SRAM) is much smaller than DPSRAM (dual-port SRAM) of the same size. Using DPSRAM nearly doubles the chip area, resulting in a very low cost-performance ratio. In terms of timing, SPSRAM's minimum clock cycle is shorter than DPSRAM, meaning it can support higher-frequency data access. In terms of power consumption, SPSRAM's static current is also much lower than that of DPSRAM of the same size.

[0003]

[0004] Table 1

[0005] One way to implement SSD master RAID is to frequently read and write SRAM. The timing requirements are: perform an XOR operation on the data read from SRAM in the previous cycle with external data and write the data to the read address of SRAM in the previous cycle; perform an XOR operation on the data read from SRAM in the current cycle with external data and write the data to the read address of SRAM in the next cycle. That is, each cycle has read and write operations on two consecutive addresses of SRAM. When external data continuously enters, SRAM can continuously write and read the intermediate parity to ensure pipeline efficiency. A simple implementation method is to use DPSRAM, because it has two sets of read and write addresses and data interfaces, which can support both reading and writing to SRAM within one clock cycle.

[0006] For the operation of dpsram, please refer to Table 2:

[0007]

[0008] Table 2

[0009] In the above table, A0 refers to the 0th address of the dpsram with a total of n entries, A(n-1) refers to the n-1th address of the dpsram), D(n-1) wr Indicates the write data of address n-1, D(n-1) rd Indicates the read data of the n-1th address.

[0010] However, this method consumes a lot of SRAM area and power, and the maximum frequency is limited, which in turn affects the chip cost and performance. Summary of the Invention

[0011] To address the shortcomings of existing dual-port SRAM in implementing RAID, such as large area and power consumption and limited maximum frequency, the present invention provides an SRAM access device for implementing SSD master RAID. It uses two SPSRAMs and corresponding control logic circuits to reduce chip area, lower power consumption, and increase frequency while ensuring functionality.

[0012] In order to solve the above technical problems, the technical solution adopted by the present invention is: an SRAM access device for realizing RAID in an SSD master control, comprising two single-port SRAMs and a logic control circuit connected to the single-port SRAMs, wherein the logic control circuit controls the two single-port SRAMs to perform read or write operations in the same clock cycle, and the two single-port SRAMs alternately serve as odd-address SRAMs, reading or writing odd-address data when serving as odd-address SRAMs, and reading or writing even-address data when serving as even-address SRAMs;

[0013] The logic control circuit includes a parity flag logic circuit, an enable logic circuit, a write enable logic circuit, an address multiplexer, a read data multiplexer and a read data cache circuit;

[0014] The parity flag logic circuit is used to mark whether the single-port SRAM is used as an even address SRAM or an odd address SRAM. The input end of the parity flag logic circuit is connected to the start signal and the init signal. It is triggered to flip by the start signal and adjusts the flag according to whether it is init data. The output end of the parity flag logic circuit is connected to the enable logic circuit.

[0015] The input end of the enable logic circuit is connected to the output signal of the parity flag logic circuit, the system en signal, and the start signal. The output end of the enable logic circuit is connected to the enable port of the single-port SRAM, and is used to determine whether to enable the single-port SRAM based on the system en signal, the start signal, and the parity flag;

[0016] The input end of the write enable logic circuit is connected to the output signal of the parity flag logic circuit, the lowest bit signal of the write address, and the write enable signal. The output end of the write enable logic circuit is connected to the write enable port of the single-port SRAM, and is used to select whether to enable write to the single-port SRAM based on the parity flag and whether it is the first carry;

[0017] The address multiplexer is used to select the system write address or the system read address as the address signal of the SRAM according to the write enable signal;

[0018] The read data cache circuit is connected to the read data output terminal of the single-port SRAM and is used to cache data read from the single-port SRAM;

[0019] The read data multiplexer is connected to the read data output terminals of the two single-port SRAMs and the output terminals of the read data cache circuit. It is used to select one data output from the single-port SRAM read data and the single-port SRAM read data cache. This data is the result of the previous round of data verification calculation (tempor parity) corresponding to the current system address.

[0020] Furthermore, the parity flag logic circuit has two paths, which are used to mark whether the two single-port SRAMs are used as even address SRAMs or odd address SRAMs;

[0021] A parity flag logic circuit includes a two-way selector MUX00, a two-way selector MUX01, a parity flag register SRAM0_FLAG, and a two-way selector MUX02. The input terminal X0 of the two-way selector MUX00 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX00 is grounded, the selection signal terminal Sel of the two-way selector MUX00 is connected to the init signal, the output terminal of the two-way selector MUX00 is connected to the input terminal X1 of the two-way selector MUX01, the input terminal X0 of the two-way selector MUX01 is connected to the output terminal of the two-way selector MUX02, the selection signal terminal Sel of the two-way selector MUX01 is connected to the start signal start, the output terminal of the two-way selector MUX01 is connected to the input terminal of the parity flag register SRAM0_FLAG, the output terminal Q of the parity flag register SRAM0_FLAG is connected to the input terminal X0 of the two-way selector MUX02 and the write enable logic circuit, and the output terminal of the parity flag register SRAM0_FLAG is connected to the write enable logic circuit. Connected to the input terminal X1 of the two-way selector MUX02 and the enable logic circuit, the selection signal terminal Sel of the two-way selector MUX02 is connected to the end signal finish;

[0022] Another parity flag logic circuit includes a two-way selector MUX10, a two-way selector MUX11, a parity flag register SRAM1_FLAG, and a two-way selector MUX12. The input terminal X0 of the two-way selector MUX10 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX10 is grounded, the selection signal terminal Sel of the two-way selector MUX10 is connected to the init signal, the output terminal of the two-way selector MUX10 is connected to the input terminal X1 of the two-way selector MUX11, the input terminal X0 of the two-way selector MUX11 is connected to the output terminal of the two-way selector MUX12, the selection signal terminal Sel of the two-way selector MUX11 is connected to the start signal start, the output terminal of the two-way selector MUX11 is connected to the input terminal of the parity flag register SRAM1_FLAG, the output terminal Q of the parity flag register SRAM1_FLAG is connected to the enable logic circuit, the write enable logic circuit and the input terminal X0 of the two-way selector MUX12, and the output terminal of the parity flag register SRAM1_FLAG is connected to the enable logic circuit, the write enable logic circuit and the input terminal X0 of the two-way selector MUX12. It is connected to the input terminal X1 of the two-way selector MUX12, and the selection signal terminal Sel of the two-way selector MUX12 is connected to the end signal finish.

[0023] Furthermore, there are two enabling logic circuits, which are used to enable two single-port SRAMs respectively. The two enabling logic circuits are implemented by AND gate AND00 and OR gate OR00, AND gate AND10 and OR gate OR10. One input end of AND gate AND00 is connected to the output end of parity flag register SRAM0_FLAG. Connection, one input end of the AND gate AND10 is connected to the output end Q of the parity flag register SRAM1_FLAG, the other input ends of the AND gate AND00 and the AND gate AND10 are both connected to the start signal start, the output end of the AND gate AND00 is connected to one input end of the OR gate OR00, the output end of the AND gate AND10 is connected to one input end of the OR gate OR10, the other input ends of the OR gate OR00 and the OR gate OR10 are both connected to the enable signal en, the output end of the OR gate OR00 is connected to the enable port of the single-port SRAM0, and the output end of the OR gate OR10 is connected to the enable port of the single-port SRAM1.

[0024] Furthermore, there are two write enable logic circuits, each used to write enable two single-port SRAMs. One write enable logic circuit includes an exclusive-OR gate XOR0 and an AND gate AND01. One input of the exclusive-OR gate XOR0 is connected to the lowest bit of the write address signal, the other input of the exclusive-OR gate XOR0 is connected to the output Q of the parity flag register SRAM0_FLAG, the output of the exclusive-OR gate XOR0 is connected to one input of the AND gate AND01, the other input of the AND gate AND01 is connected to the system write enable signal, and the output of the AND gate AND01 is connected to the write enable port of the single-port SRAM0.

[0025] Another write enable logic circuit includes an XNOR gate XNOR1 and an AND gate AND11. One input end of the XNOR gate XNOR1 is connected to the lowest bit of the write address signal, and the other input end of the XNOR gate XNOR1 is connected to the output end Q of the parity flag register SRAM1_FLAG. The output end of the XNOR gate XNOR1 is connected to one input end of the AND gate AND11, and the other input end of the AND gate AND11 is connected to the system write enable signal. The output end of the AND gate AND11 is connected to the write enable port of the single-port SRAM1.

[0026] Furthermore, there are two address multiplexers for determining the address signals of two single-port SRAMs. The two address multiplexers are a two-way selector MUX03 and a two-way selector MUX13. The two input ends of the two-way selector MUX03 are respectively connected to the write address and the read address, the selection signal end Sel of the two-way selector MUX03 is connected to the output of one write enable circuit, and the output end of the two-way selector MUX03 is connected to the address input port of SRAM0; the two input ends of the two-way selector MUX13 are respectively connected to the write address and the read address, the selection signal end Sel of the two-way selector MUX13 is connected to the output of another write enable circuit, and the output end of the two-way selector MUX13 is connected to the address input port of SRAM1.

[0027] Furthermore, there are two read data cache circuits, which are used to cache the read data of two single-port SRAMs respectively. The two read data cache circuits are composed of a read data register SRAM0_RDATA_R and a read data register SRAM1_RDATA_R. The read data register SRAM0_RDATA_R is connected to the read data output port of the single-port SRAM0 and is used to cache the read data of the single-port SRAM0. The read data register SRAM1_RDATA_R is connected to the read data output port of the single-port SRAM1 and is used to cache the read data of the single-port SRAM1.

[0028] Furthermore, the read data multiplexer includes a two-way selector MUX04 and a selection logic circuit thereof, a two-way selector MUX05 and a logic selection circuit thereof, a two-way selector MUX14 and a selection logic circuit thereof, and a two-way selector MUX15 and a selection logic circuit thereof;

[0029] The selection logic circuit of the two-way selector MUX04 includes an AND gate AND02, a first-pen-even address identification register EVEN_1st, and an OR gate OR01. The input ends of the AND gate AND02 are respectively connected to the write enable signal of SRAM0 and the inverted write enable signal of SRAM1, the output end of the AND gate AND02 is connected to the input end of the first-pen-even address identification register EVEN_1st, the output end Q of the first-pen-even address identification register EVEN_1st is connected to one input end of the OR gate OR01, and the other input end of the OR gate OR01 is connected to the system write enable signal;

[0030] The selection logic circuit of the two-way selector MUX05 includes a read address lowest bit register RDADDR_LSB_R0 and an exclusive OR gate XNOR0, wherein the input end of the read address lowest bit register RDADDR_LSB_R0 is connected to the lowest bit of the read address, the output end Q of the read address lowest bit register RDADDR_LSB_R0 is connected to one input end of the exclusive OR gate XNOR0, and the other input end of the exclusive OR gate XNOR0 is connected to the parity flag signal SRAM0_FLAG / Q;

[0031] The selection logic circuit of the two-way selector MUX14 includes an AND gate AND12, a first odd address identification register ODD_1st, and an OR gate OR11. The input ends of the AND gate AND12 are respectively connected to the inverted write enable signal of SRAM0 and the write enable signal of SRAM1, the output end of the AND gate AND12 is connected to the input end of the first odd address identification register ODD_1st, the output end Q of the first odd address identification register ODD_1st is connected to one input end of the OR gate OR11, and the other input end of the OR gate OR11 is connected to the system write enable signal;

[0032] The selection logic circuit of the two-way selector MUX14 includes a read address lowest bit register RDADDR_LSB_R1 and an exclusive OR gate XOR1. The input end of the read address lowest bit register RDADDR_LSB_R1 is connected to the lowest bit of the read address, the output end Q of the read address lowest bit register RDADDR_LSB_R1 is connected to one input end of the exclusive OR gate XOR1, and the other input end of the exclusive OR gate XOR1 is connected to the parity flag signal SRAM1_FLAG / Q;

[0033] An input terminal X1 of the two-way selector MUX04 is connected to the data output port sram0_rdata of SRAM0, an input terminal X0 of the two-way selector MUX04 is connected to the output terminal of the read data register SRAM0_RDATA_R, and a signal selection terminal Sel of the two-way selector MUX04 is connected to the output terminal of the OR gate OR01; an output terminal of the two-way selector MUX04 is connected to an input terminal X1 of the two-way selector MUX05, an input terminal X0 of the two-way selector MUX05 is grounded, and a signal selection terminal Sel of the two-way selector MUX05 is connected to the output terminal of the XNOR gate XNOR0;

[0034] An input terminal X1 of the two-way selector MUX14 is connected to the data output port sram1_rdata of SRAM1, an input terminal X0 of the two-way selector MUX14 is connected to the output terminal Q of the read data register SRAM1_RDATA_R, and a signal selection terminal Sel of the two-way selector MUX14 is connected to the output terminal of the OR gate OR11; the output terminal of the two-way selector MUX14 is connected to the input terminal X1 of the two-way selector MUX15, an input terminal X0 of the two-way selector MUX15 is grounded, and the signal selection terminal Sel of the two-way selector MUX15 is connected to the output terminal of the XOR gate XOR1;

[0035] The output ends of the two-way selectors MUX05 and MUX15 are respectively connected to the input ends of the OR gate RDDATA_OR. The output of the OR gate RDDATA_OR corresponds to the read data of the current system read address (the temp parity calculation result of the previous data verification).

[0036] The present invention achieves the following beneficial effects: It replaces the original dual-port SRAM with two single-port SRAMs and adds hardware control logic to enable SRAM access for RAID functionality. This control logic, comprised of a small number of registers and multiplexers, significantly reduces the area difference between DPSRAM and SPSRAM of the same size. This demonstrates the significant overall advantages of reducing chip area, lowering power consumption, and increasing frequency, while maintaining functionality. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Circuit for this SRAM access device Figure 1 ;

[0038] Figure 2 Circuit for this SRAM access device Figure 2 ;

[0039] Figure 3 Circuit for this SRAM access device Figure 3 . DETAILED DESCRIPTION

[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0041] Example 1

[0042] This embodiment discloses an SRAM access device for realizing SSD master control RAID. Figure 1 、 2 The circuit shown in 3 includes two single-port SRAMs and a logic control circuit connected to the single-port SRAMs. The two single-port SRAMs are hereinafter referred to as SRAM0 and SRAM1. The logic control circuit controls the two single-port SRAMs to perform read or write operations in the same clock cycle, and the two single-port SRAMs alternately serve as parity address SRAMs. When serving as odd address SRAMs, they read or write odd address data, and when serving as even address SRAMs, they read or write even address data, thereby realizing the access and use of SRAMs in the RAID function.

[0043] The logic control circuit includes a parity flag logic circuit, an enable logic circuit, a write enable logic circuit, an address multiplexer, a read data multiplexer and a read data cache circuit.

[0044] The parity flag logic circuit is used to mark whether the single-port SRAM is used as an even address SRAM or an odd address SRAM. The input end of the parity flag logic circuit is connected to the start signal and the init signal. It is triggered to flip by the start signal and adjusts the flag according to whether it is init data. The init signal indicates whether it is the first round. The first round is just the number of rounds, that is, the operation on the SRAM is only writing but not reading. The output end of the parity flag logic circuit is connected to the enable logic circuit.

[0045] The input end of the enable logic circuit is connected to the output signal of the parity flag logic circuit, the system enable signal en, and the start signal start. The output end of the enable logic circuit is connected to the enable port of the single-port SRAM, and is used to decide whether to enable the single-port SRAM based on the system enable signal en, the start signal start and the parity flag.

[0046] The input end of the write enable logic circuit is connected to the output signal of the parity flag logic circuit, the lowest bit signal of the write address, and the write enable signal. The output end of the write enable logic circuit is connected to the write enable port of the single-port SRAM, and is used to select whether to enable write to the single-port SRAM based on the parity flag and whether it is the first carry.

[0047] The address multiplexer is used to select the system write address or the system read address as the address signal of the SRAM according to the write enable signal.

[0048] The read data cache circuit is connected to the read data output terminal of the single-port SRAM and is used for caching data read from the single-port SRAM.

[0049] The read data multiplexer is connected to the read data output terminals of the two single-port SRAMs and the output terminals of the read data cache circuit. It is used to select one data output from the single-port SRAM read data and the single-port SRAM read data cache. This data is the result of the previous round of data verification calculation (tempor parity) corresponding to the current system address.

[0050] like Figure 1 As shown, there are two parity flag logic circuits, which are used to mark whether SRAM0 and SRAM1 are used as even address SRAM or odd address SRAM respectively.

[0051] A parity flag logic circuit includes a two-way selector MUX00, a two-way selector MUX01, a parity flag register SRAM0_FLAG, and a two-way selector MUX02. The input terminal X0 of the two-way selector MUX00 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX00 is grounded, the selection signal terminal Sel of the two-way selector MUX00 is connected to the init signal, the output terminal of the two-way selector MUX00 is connected to the input terminal X1 of the two-way selector MUX01, the input terminal X0 of the two-way selector MUX01 is connected to the output terminal of the two-way selector MUX02, the selection signal terminal Sel of the two-way selector MUX01 is connected to the start signal start, the output terminal of the two-way selector MUX01 is connected to the input terminal of the parity flag register SRAM0_FLAG, the output terminal Q of the parity flag register SRAM0_FLAG is connected to the input terminal X0 of the two-way selector MUX02 and the write enable logic circuit of SRAM0, and the output terminal of the parity flag register SRAM0_FLAG is connected to the write enable logic circuit of SRAM0. The input terminal X1 of the two-way selector MUX02 and the enable logic circuit of SRAM0 are connected, and the selection signal terminal Sel of the two-way selector MUX02 is connected to the end signal finish.

[0052] Another parity flag logic circuit includes a two-way selector MUX10, a two-way selector MUX11, a parity flag register SRAM1_FLAG, and a two-way selector MUX12. The input terminal X0 of the two-way selector MUX10 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX10 is grounded, the selection signal terminal Sel of the two-way selector MUX10 is connected to an init signal, the output terminal of the two-way selector MUX10 is connected to the input terminal X1 of the two-way selector MUX11, and the input terminal of the two-way selector MUX11 is connected to the init signal. The terminal X0 is connected to the output terminal of the two-way selector MUX12, the selection signal terminal Sel of the two-way selector MUX11 is connected to the start signal start, the output terminal of the two-way selector MUX11 is connected to the input terminal of the parity flag register SRAM1_FLAG, the output terminal Q of the parity flag register SRAM1_FLAG is connected to the input terminal X0 of the two-way selector MUX12, the write enable logic circuit of SRAM1 and the enable logic circuit of SRAM1, the output terminal of the parity flag register SRAM1_FLAG The selection signal terminal Sel of the two-way selector MUX12 is connected to the input terminal X1 of the two-way selector MUX12, and the end signal finish is connected to the selection signal terminal Sel of the two-way selector MUX12.

[0053] like Figure 1As shown, there are two enabling logic circuits, which are used to enable SRAM0 and SRAM1 respectively. The two enabling logic circuits are realized by AND gate AND00 and OR gate OR00, AND gate AND10 and OR gate OR10. One input of AND gate AND00 is connected to the output of parity flag register SRAM0_FLAG. Connection, one input end of the AND gate AND10 is connected to the output end Q of the parity flag register SRAM1_FLAG, the other input ends of the AND gate AND00 and the AND gate AND10 are both connected to the start signal start, the output end of the AND gate AND00 is connected to one input end of the OR gate OR00, the output end of the AND gate AND10 is connected to one input end of the OR gate OR10, the other input ends of the OR gate OR00 and the OR gate OR10 are both connected to the enable signal en, the output end of the OR gate OR00 is connected to the enable port sram0_en of the single-port SRAM0, and the output end of the OR gate OR10 is connected to the enable port sram1_en of the single-port SRAM1.

[0054] like Figure 1 、 2 As shown, there are two write enable logic circuits, one for write enabling SRAM0 and the other for SRAM1. One write enable logic circuit includes an XOR gate XOR0 and an AND gate AND01. One input of the XOR gate XOR0 is connected to the lowest bit of the write address signal, and the other input of the XOR gate XOR0 is connected to the output Q of the parity flag register SRAM0_FLAG, that is, the signal SRAM0_FLAG / Q. The output of the XOR gate XOR0 is connected to one input of the AND gate AND01, and the other input of the AND gate AND01 is connected to the system write enable signal wr_en. The output of the AND gate AND01 is connected to the write enable of the single-port SRAM0. Port sram0_wr_en; another write enable logic circuit includes an exclusive-OR gate XNOR1 and an AND gate AND11, one input end of the exclusive-OR gate XNOR1 is connected to the lowest bit of the write address signal, and the other input end of the exclusive-OR gate XNOR1 is connected to the output end Q of the parity flag register SRAM1_FLAG, that is, the signal SRAM1_FLAG / Q,, the output end of the exclusive-OR gate XNOR1 is connected to one input end of the AND gate AND11, the other input end of the AND gate AND11 is connected to the system write enable signal wr_en, and the output end of the AND gate AND11 is connected to the write enable port sram1_wr_en of the single-port SRAM1.

[0055] like Figure 2As shown, there are two address multiplexers for determining the address signals of SRAM0 and SRAM1. The two address multiplexers are a two-way selector MUX03 and a two-way selector MUX13. The two input ends of the two-way selector MUX03 are connected to the write address and the read address respectively, the selection signal end Sel of the two-way selector MUX03 is connected to the output of a write enable circuit, namely, the AND gate AND01, and the output end of the two-way selector MUX03 is connected to the address input port sram0_addr of SRAM0; the two input ends of the two-way selector MUX13 are connected to the write address and the read address respectively, the selection signal end Sel of the two-way selector MUX13 is connected to the output of another write enable circuit, namely, the AND gate AND11, and the output end of the two-way selector MUX13 is connected to the address input port sram1_addr of SRAM1.

[0056] like Figure 2 、 3 As shown, there are two read data cache circuits, which are used to cache the read data of SRAM0 and SRAM1 respectively. The two read data cache circuits are composed of a read data register SRAM0_RDATA_R and a read data register SRAM1_RDATA_R. The read data register SRAM0_RDATA_R is connected to the read data output port sram0_rdata of the single-port SRAM0 and is used to cache the read data of the single-port SRAM0. The read data register SRAM1_RDATA_R is connected to the read data output port sram1_rdata of the single-port SRAM1 and is used to cache the read data of the single-port SRAM1.

[0057] like Figure 2 、 3 As shown, the read data multiplexer includes two-way selector MUX04 and its selection logic circuit, two-way selector MUX05 and its logic selection circuit, two-way selector MUX14 and its selection logic circuit, and two-way selector MUX15 and its selection logic circuit.

[0058] The selection logic circuit of the two-way selector MUX04 includes an AND gate AND02, a first-pen-even address identification register EVEN_1st and an OR gate OR01. The input ends of the AND gate AND02 are respectively connected to the write enable signal of SRAM0 and the inverted write enable signal of SRAM1, and the output end of the AND gate AND02 is connected to the input end of the first-pen-even address identification register EVEN_1st. The output end Q of the first-pen-even address identification register EVEN_1st is connected to one input end of the OR gate OR01, and the other input end of the OR gate OR01 is connected to the system write enable signal.

[0059] The selection logic circuit of the two-way selector MUX05 includes a read address lowest bit register RDADDR_LSB_R0 and an exclusive OR gate XNOR0. The input end of the read address lowest bit register RDADDR_LSB_R0 is connected to the lowest bit in the read address, the output end Q of the read address lowest bit register RDADDR_LSB_R0 is connected to one input end of the exclusive OR gate XNOR0, and the other input end of the exclusive OR gate XNOR0 is connected to the parity flag signal SRAM0_FLAG / Q.

[0060] The selection logic circuit of the two-way selector MUX14 includes an AND gate AND12, a first odd address identification register ODD_1st, and an OR gate OR11. The input ends of the AND gate AND12 are respectively connected to the inverted write enable signal of SRAM0 and the write enable signal of SRAM1, and the output end of the AND gate AND12 is connected to the input end of the first odd address identification register ODD_1st. The output end Q of the first odd address identification register ODD_1st is connected to one input end of the OR gate OR11, and the other input end of the OR gate OR11 is connected to the system write enable signal.

[0061] The selection logic circuit of the two-way selector MUX15 includes a read address lowest bit register RDADDR_LSB_R1 and an exclusive OR gate XOR1. The input end of the read address lowest bit register RDADDR_LSB_R1 is connected to the lowest bit in the read address, and the output end Q of the read address lowest bit register RDADDR_LSB_R1 is connected to one input end of the exclusive OR gate XOR1. The other input end of the exclusive OR gate XOR1 is connected to the parity flag signal SRAM1_FLAG / Q.

[0062] The input terminal X1 of the two-way selector MUX04 is connected to the data output port sram0_rdata of SRAM0, the input terminal X0 of the two-way selector MUX04 is connected to the output terminal of the read data register SRAM0_RDATA_R, and the signal selection terminal Sel of the two-way selector MUX04 is connected to the output terminal of the OR gate OR01; the output terminal of the two-way selector MUX04 is connected to the input terminal X1 of the two-way selector MUX05, the input terminal X0 of the two-way selector MUX05 is grounded, and the signal selection terminal Sel of the two-way selector MUX05 is connected to the output terminal of the XNOR gate XNOR0.

[0063] An input terminal X1 of the two-way selector MUX14 is connected to the data output port sram1_rdata of SRAM1, an input terminal X0 of the two-way selector MUX14 is connected to the output terminal Q of the read data register SRAM1_RDATA_R, and a signal selection terminal Sel of the two-way selector MUX14 is connected to the output terminal of the OR gate OR11; the output terminal of the two-way selector MUX14 is connected to the input terminal X1 of the two-way selector MUX15, an input terminal X0 of the two-way selector MUX15 is grounded, and the signal selection terminal Sel of the two-way selector MUX15 is connected to the output terminal of the XOR gate XOR1;

[0064] The output ends of the two-way selectors MUX05 and MUX15 are respectively connected to the input ends of the OR gate RDDATA_OR. The output of the OR gate RDDATA_OR corresponds to the read data of the current system read address (the temp parity calculation result of the previous data verification).

[0065] The read data multiplexer selects one data path from the four SRAM0 read data / SRAM0 read data cache / SRAM1 read data / SRAM1 read data cache to provide to the system as temporary parity (data check calculation result) for the current system address. Because SRAM0 and SRAM1 alternately function as even-odd SRAM addresses, this can also be described as: selecting one data path from the four SRAM odd-address read data / odd-address SRAM read data cache / even-address SRAM read data / even-address SRAM read data cache to provide to the system as temporary parity (data check calculation result) for the current system address.

[0066] The solution for implementing RAID access to spsram in SSD storage based on this access device is as follows:

[0067] First, the two SPSRAMs are mixed and cross-addressed in the system, that is, the least significant bit (LSB) of the system address is used to distinguish between odd-address SRAM and even-address SRAM. The A0, A1, etc. mentioned below are the actual addresses of a SPSRAM after removing the LSB of the system address.

[0068] Secondly, for the same system address, a read command is first issued to read the old temp parity (the result of the previous data checksum calculation), followed by a write command to write the new temp parity (the result of the new data checksum calculation) by XORing the read data with the external data. Read and write commands for the same address are separated by one clock cycle (because SRAM write commands and write data occur in the same clock cycle, while read data is valid only in the next clock cycle after the read command). For any address in odd or even SRAM, a read must be performed before a write; otherwise, the previous temp parity will be overwritten, causing a functional error. When the system accesses two SRAMs simultaneously, the operation is 1R1W (one read, one write) to ensure continuous data reading and writing. The read and write sequences for even and odd SRAMs differ as follows: For even-address SRAMs, a read command for address 0 is issued in the first clock cycle. In the second clock cycle, the data at address 0 is read and temporarily stored in the read data buffer. Starting in the third clock cycle, read and write commands are interleaved. For odd-address SRAMs, the first clock cycle is idle, and read and write commands are interleaved starting in the second clock cycle. The final implementation is that data with the same address (not looking at LSB) is read from the odd address SRAM, XORed, and written to the even address SRAM. Conversely, data with the same address (not looking at LSB) is read from the even address SRAM, XORed, and written to the odd address SRAM. There is one clock cycle between reading and writing.

[0069] After updating the data in both SRAMs, the system addresses of the two SRAMs are swapped before the next round of RAID operations (this is equivalent to placing the new temp parity at the exact same system address as the old tempparity). The swap is accomplished by pulling the finish signal high, causing the parity registers of each to flip. The original odd-address SRAM becomes an even-address SRAM, and the original even-address SRAM becomes an odd-address SRAM. The system then controls each SRAM based on the parity registers for a new round of read and write operations.

[0070] When init is 1, it means that the first round of data enters SRAM. At this time, only SRAM needs to be written, not read.

[0071] The specific timing information is shown in Table 3, that is, after the data at a certain address of the odd-address SRAM is read out, the XOR result thereof with the external data is written to the same address of the even-address SRAM (as indicated by the curved arrow), and vice versa.

[0072]

[0073] Table 3

[0074] e0 and o0 refer to the 0 address of the even address SRAM and the 0 address of the odd address SRAM respectively;

[0075] D(0) wr ~D(2m) wr It is the write data corresponding to the system address 0~2m (the temporary parity newly calculated in the raid);

[0076] D(0) rd ~D(2m) rd It is the read data corresponding to the system address 0~2m (the last temporary parity in the raid).

[0077] Compared to the DPSRAM timing diagram (Table 2), with n=2m, the DPSRAM size is n, and both SPSRAMs are size m. The former completes one EMP parity refresh in n+3 clock cycles, while the latter completes one temp parity refresh in 2m+3 clock cycles, identical to the former. This means this device has no impact on SSD RAID efficiency.

[0078] The present invention replaces DP SRAM with SP SRAM and adds a small amount of hardware control logic. This achieves significant overall improvements in chip size, power consumption, and frequency while ensuring functionality. This represents a significant breakthrough in RAID implementation in SSD controllers.

[0079] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. An SRAM access device for implementing RAID in an SSD master controller, characterized by: The invention comprises two single-port SRAMs and a logic control circuit connected to the single-port SRAMs. The logic control circuit controls the two single-port SRAMs to perform read or write operations in the same clock cycle. The two single-port SRAMs alternately serve as odd-address SRAMs. When serving as odd-address SRAMs, the two single-port SRAMs read or write odd-address data. When serving as even-address SRAMs, the two single-port SRAMs read or write even-address data. The logic control circuit includes a parity flag logic circuit, an enable logic circuit, a write enable logic circuit, an address multiplexer, a read data multiplexer and a read data cache circuit; The parity flag logic circuit is used to mark whether the single-port SRAM is used as an even-address SRAM or an odd-address SRAM. The input end of the parity flag logic circuit is connected to the start signal and the init signal. It is triggered to flip by the start signal and adjusts the flag according to whether it is init data. The output end of the parity flag logic circuit is connected to the enable logic circuit; the input end of the enable logic circuit is connected to the output signal of the parity flag logic circuit, the system en signal, and the start signal. The output end of the enable logic circuit is connected to the enable port of the single-port SRAM and is used to determine whether to enable the single-port SRAM based on the system en signal, the start signal, and the parity flag. The input end of the write enable logic circuit is connected to the output signal of the parity flag logic circuit, the lowest bit signal of the write address, and the write enable signal. The output end of the write enable logic circuit is connected to the write enable port of the single-port SRAM, and is used to select whether to enable write to the single-port SRAM based on the parity flag and whether it is the first carry; The address multiplexer is used to select the system write address or the system read address as the address signal of the SRAM according to the write enable signal; The read data cache circuit is connected to the read data output terminal of the single-port SRAM and is used to cache data read from the single-port SRAM; The read data multiplexer is connected to the read data output terminals of the two single-port SRAMs and the output terminals of the read data cache circuit. It is used to select one data output from the single-port SRAM read data and the single-port SRAM read data cache. This data is the result of the previous round of data verification calculation corresponding to the current system address.

2. The SRAM access device for implementing RAID in an SSD master controller according to claim 1, wherein: There are two parity flag logic circuits, one for marking whether the two single-port SRAMs are used as even address SRAMs or odd address SRAMs; A parity flag logic circuit includes a two-way selector MUX00, a two-way selector MUX01, a parity flag register SRAM0_FLAG, and a two-way selector MUX02. The input terminal X0 of the two-way selector MUX00 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX00 is grounded, the selection signal terminal Sel of the two-way selector MUX00 is connected to the init signal, the output terminal of the two-way selector MUX00 is connected to the input terminal X1 of the two-way selector MUX01, the input terminal X0 of the two-way selector MUX01 is connected to the output terminal of the two-way selector MUX02, the selection signal terminal Sel of the two-way selector MUX01 is connected to the start signal start, the output terminal of the two-way selector MUX01 is connected to the input terminal of the parity flag register SRAM0_FLAG, the output terminal Q of the parity flag register SRAM0_FLAG is connected to the input terminal X0 of the two-way selector MUX02 and the write enable logic circuit, and the output terminal of the parity flag register SRAM0_FLAG is connected to the write enable logic circuit. Connected to the input terminal X1 of the two-way selector MUX02 and the enable logic circuit, the selection signal terminal Sel of the two-way selector MUX02 is connected to the end signal finish; Another parity flag logic circuit includes a two-way selector MUX10, a two-way selector MUX11, a parity flag register SRAM1_FLAG, and a two-way selector MUX12. The input terminal X0 of the two-way selector MUX10 is connected to a pull-up power supply, the input terminal X1 of the two-way selector MUX10 is grounded, the selection signal terminal Sel of the two-way selector MUX10 is connected to the init signal, the output terminal of the two-way selector MUX10 is connected to the input terminal X1 of the two-way selector MUX11, the input terminal X0 of the two-way selector MUX11 is connected to the output terminal of the two-way selector MUX12, the selection signal terminal Sel of the two-way selector MUX11 is connected to the start signal start, the output terminal of the two-way selector MUX11 is connected to the input terminal of the parity flag register SRAM1_FLAG, the output terminal Q of the parity flag register SRAM1_FLAG is connected to the enable logic circuit, the write enable logic circuit, and the input terminal X0 of the two-way selector MUX12, and the output terminal The selection signal terminal Sel of the two-way selector MUX12 is connected to the input terminal X1 of the two-way selector MUX12, and the end signal finish is connected to the selection signal terminal Sel of the two-way selector MUX12.

3. The SRAM access device for implementing RAID in an SSD master controller according to claim 2, wherein: There are two enable logic circuits, one for enabling two single-port SRAMs. The two enable logic circuits are implemented by AND gate AND00 and OR gate OR00, AND gate AND10 and OR gate OR10. One input of AND gate AND00 is connected to the output of parity flag register SRAM0_FLAG. Connection, one input end of the AND gate AND10 is connected to the output end Q of the parity flag register SRAM1_FLAG, the other input ends of the AND gate AND00 and the AND gate AND10 are both connected to the start signal start, the output end of the AND gate AND00 is connected to one input end of the OR gate OR00, the output end of the AND gate AND10 is connected to one input end of the OR gate OR10, the other input ends of the OR gate OR00 and the OR gate OR10 are both connected to the enable signal en, the output end of the OR gate OR00 is connected to the enable port of the single-port SRAM0, and the output end of the OR gate OR10 is connected to the enable port of the single-port SRAM1.

4. The SRAM access device for implementing RAID in an SSD master controller according to claim 2, wherein: There are two write enable logic circuits, each used to write enable two single-port SRAMs. One write enable logic circuit includes an exclusive OR gate XOR0 and an AND gate AND01. One input of the exclusive OR gate XOR0 is connected to the lowest bit of the write address signal, and the other input of the exclusive OR gate XOR0 is connected to the output Q of the parity flag register SRAM0_FLAG. The output of the exclusive OR gate XOR0 is connected to one input of the AND gate AND01, and the other input of the AND gate AND01 is connected to the system write enable signal. The output of the AND gate AND01 is connected to the write enable port of the single-port SRAM0. Another write enable logic circuit includes an XNOR gate XNOR1 and an AND gate AND11. One input end of the XNOR gate XNOR1 is connected to the lowest bit of the write address signal, and the other input end of the XNOR gate XNOR1 is connected to the output end Q of the parity flag register SRAM1_FLAG. The output end of the XNOR gate XNOR1 is connected to one input end of the AND gate AND11, and the other input end of the AND gate AND11 is connected to the system write enable signal. The output end of the AND gate AND11 is connected to the write enable port of the single-port SRAM1.

5. The SRAM access device for implementing RAID in an SSD master controller according to claim 2, wherein: There are two address multiplexers, which are used to determine the address signals of two single-port SRAMs. The two address multiplexers are two-way selector MUX03 and two-way selector MUX13. The two input ends of the two-way selector MUX03 are connected to the write address and the read address respectively, the selection signal end Sel of the two-way selector MUX03 is connected to the output of one write enable circuit, and the output end of the two-way selector MUX03 is connected to the address input port of SRAM0; the two input ends of the two-way selector MUX13 are connected to the write address and the read address respectively, the selection signal end Sel of the two-way selector MUX13 is connected to the output of another write enable circuit, and the output end of the two-way selector MUX13 is connected to the address input port of SRAM1.

6. The SRAM access device for implementing RAID in an SSD master controller according to claim 1 or 2, characterized in that: There are two read data cache circuits, which are used to cache the read data of two single-port SRAMs respectively. The two read data cache circuits are composed of read data register SRAM0_RDATA_R and read data register SRAM1_RDATA_R. Read data register SRAM0_RDATA_R is connected to the read data output port of single-port SRAM0 and is used to cache the read data of single-port SRAM0. Read data register SRAM1_RDATA_R is connected to the read data output port of single-port SRAM1 and is used to cache the read data of single-port SRAM1.

7. The SRAM access device for implementing RAID in an SSD master controller according to claim 6, wherein: The read data multiplexer includes a two-way selector MUX04 and its selection logic circuit, a two-way selector MUX05 and its logic selection circuit, a two-way selector MUX14 and its selection logic circuit, and a two-way selector MUX15 and its selection logic circuit; The selection logic circuit of the two-way selector MUX04 includes an AND gate AND02, a first-pen-even address identification register EVEN_1st, and an OR gate OR01. The input ends of the AND gate AND02 are respectively connected to the write enable signal of SRAM0 and the inverted write enable signal of SRAM1, the output end of the AND gate AND02 is connected to the input end of the first-pen-even address identification register EVEN_1st, the output end Q of the first-pen-even address identification register EVEN_1st is connected to one input end of the OR gate OR01, and the other input end of the OR gate OR01 is connected to the system write enable signal; The selection logic circuit of the two-way selector MUX05 includes a read address lowest bit register RDADDR_LSB_R0 and an exclusive OR gate XNOR0, wherein the input end of the read address lowest bit register RDADDR_LSB_R0 is connected to the lowest bit of the read address, the output end Q of the read address lowest bit register RDADDR_LSB_R0 is connected to one input end of the exclusive OR gate XNOR0, and the other input end of the exclusive OR gate XNOR0 is connected to the parity flag signal SRAM0_FLAG / Q; The selection logic circuit of the two-way selector MUX14 includes an AND gate AND12, a first odd address identification register ODD_1st, and an OR gate OR11. The input ends of the AND gate AND12 are respectively connected to the inverted write enable signal of SRAM0 and the write enable signal of SRAM1, the output end of the AND gate AND12 is connected to the input end of the first odd address identification register ODD_1st, the output end Q of the first odd address identification register ODD_1st is connected to one input end of the OR gate OR11, and the other input end of the OR gate OR11 is connected to the system write enable signal; The selection logic circuit of the two-way selector MUX14 includes a read address lowest bit register RDADDR_LSB_R1 and an exclusive OR gate XOR1. The input end of the read address lowest bit register RDADDR_LSB_R1 is connected to the lowest bit in the read address, the output end Q of the read address lowest bit register RDADDR_LSB_R1 is connected to one input end of the exclusive OR gate XOR1, and the other input end of the exclusive OR gate XOR1 is connected to the parity flag signal SRAM1_FLAG / Q; the input end X1 of the two-way selector MUX04 is connected to Connected to the data output port sram0_rdata of SRAM0, the input terminal X0 of the two-way selector MUX04 is connected to the output terminal of the read data register SRAM0_RDATA_R, and the signal selection terminal Sel of the two-way selector MUX04 is connected to the output terminal of the OR gate OR01; the output terminal of the two-way selector MUX04 is connected to the input terminal X1 of the two-way selector MUX05, the input terminal X0 of the two-way selector MUX05 is grounded, and the signal selection terminal Sel of the two-way selector MUX05 is connected to the output terminal of the XNOR gate XNOR0; An input terminal X1 of the two-way selector MUX14 is connected to the data output port sram1_rdata of SRAM1, an input terminal X0 of the two-way selector MUX14 is connected to the output terminal Q of the read data register SRAM1_RDATA_R, and a signal selection terminal Sel of the two-way selector MUX14 is connected to the output terminal of the OR gate OR11; the output terminal of the two-way selector MUX14 is connected to the input terminal X1 of the two-way selector MUX15, an input terminal X0 of the two-way selector MUX15 is grounded, and the signal selection terminal Sel of the two-way selector MUX15 is connected to the output terminal of the XOR gate XOR1; The output ends of the two-way selectors MUX05 and MUX15 are respectively connected to the input ends of the OR gate RDDATA_OR. The output of the OR gate RDDATA_OR corresponds to the read data of the current system read address.

Images