Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology, so as to simplify the manufacturing process of CFET devices and reduce the difficulty of manufacturing CFET devices. The method for manufacturing a semiconductor device includes: sequentially forming an isolation layer and a doped semiconductor layer on a semiconductor substrate. The doping type and doping concentration of each region of the doped semiconductor layer are the same. Repeat the above operation until at least one first stack and at least one second stack located on the at least one first stack are formed on the semiconductor substrate. At least one first stack and at least one second stack are patterned to form a fin structure. Along the length direction of the fin structure, at least the edge region of at least one second stack is selectively etched so that the length of each doped semiconductor layer is less than the length of another doped semiconductor layer located below it, and the length of each isolation layer is less than the length of the doped semiconductor layer located below it.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0003] However, the manufacturing process of existing CFET devices is relatively complicated and has high requirements for manufacturing technology, which makes the integration of CFET devices more difficult. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device, which is used to simplify the manufacturing process of a CFET device and reduce the difficulty of manufacturing the CFET device.

[0005] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] An isolation layer and a doped semiconductor layer are sequentially formed on the semiconductor substrate, wherein the doping type and doping concentration of each region of the doped semiconductor layer are the same.

[0007] The above operation is repeated until at least one first stack and at least one second stack located on the at least one first stack are formed on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, each second stack and each first stack includes an isolation layer and a doped semiconductor layer located on the isolation layer. The doping type of the doped semiconductor layer included in the first stack is opposite to that of the doped semiconductor layer included in the second stack.

[0008] At least one first stacked layer and at least one second stacked layer are patterned to form a fin structure on the semiconductor substrate.

[0009] Along the length direction of the fin structure, at least the edge area of ​​at least one second stack is selectively etched so that the length of each doped semiconductor layer is smaller than the length of another doped semiconductor layer located below it, and the length of each isolation layer is smaller than the length of the doped semiconductor layer located below it.

[0010] A first junction-less transistor is manufactured based on at least one first stacked layer, and a second junction-less transistor is manufactured based on at least one second stacked layer.

[0011] Compared to the prior art, the semiconductor device manufacturing method provided by the present invention features a second stack positioned above the first stack, and the doping types of the doped semiconductor layers included in the first stack and the second stack are opposite. Furthermore, a first junctionless transistor is fabricated based on at least one layer of the first stack, and a second junctionless transistor is fabricated based on at least one layer of the second stack. Therefore, the semiconductor device manufactured by the manufacturing method provided by the present invention is a CFET device.

[0012] Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to sequentially form an isolation layer and a doped semiconductor layer on the semiconductor substrate. The above operation is then repeated until at least one first stack and at least one second stack are formed on the semiconductor substrate. Based on this, since the doped semiconductor layer included in the first stack is used to manufacture the first source / drain region and the first channel region included in the first junctionless transistor, and the doped semiconductor layer included in the second stack is used to manufacture the second source / drain region and the second channel region included in the second junctionless transistor, and the doping type and doping concentration of each region of the doped semiconductor layer are the same, after forming the intrinsic semiconductor material for manufacturing the corresponding doped semiconductor layer on each isolation layer, there is no need to form a corresponding mask layer, and each part of the intrinsic semiconductor material can be directly doped with impurities, thereby simplifying the manufacturing process of the first source / drain region and the second source / drain region with opposite conductivity types, and reducing the manufacturing difficulty of the CFET device.

[0013] Furthermore, after patterning at least one first stack and at least one second stack to form a fin structure, selective etching is performed on the edge region of at least one second stack along the length of the fin structure, so that the length of each doped semiconductor layer is shorter than the length of the other doped semiconductor layer located below it, and the length of each isolation layer is shorter than the length of the doped semiconductor layer located below it. In this case, the first source / drain region and the second source / drain region are arranged in a stepped manner, so that the edge regions of all active portions included in the first source / drain region and the second source / drain region are exposed from bottom to top, facilitating the connection of each active portion with the corresponding contact electrode, reducing the difficulty of leading out the contact electrode, and further reducing the difficulty of manufacturing the CFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0015] Figure 1A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0016] Figure 2 Schematic diagram of a structure after at least one first stacked layer and at least one second stacked layer are formed on a semiconductor substrate in an embodiment of the present invention;

[0017] Figure 3 Schematic diagram of a structure after at least one first stacked layer, at least one second stacked layer and a dielectric protection layer are formed on a semiconductor substrate in an embodiment of the present invention;

[0018] Figure 4 Schematic diagram of the structure after fins are formed on a semiconductor substrate in an embodiment of the present invention;

[0019] Figure 5 Schematic diagram of the structure after the shallow trench isolation structure and the fin structure are formed in an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of the structure after forming a sacrificial gate in an embodiment of the present invention;

[0021] Figure 7 Schematic diagram of the structure behind the gate sidewall in an embodiment of the present invention;

[0022] Figure 8 A schematic cross-sectional view of the structure along the length direction of the fin structure after the gate spacer is formed in an embodiment of the present invention;

[0023] Figure 9 is a schematic cross-sectional view of the structure along the length direction of the fin structure after forming the corresponding mask layer in an embodiment of the present invention;

[0024] Figure 10 is a schematic cross-sectional view of the structure along the length direction of the fin structure after the dielectric protection layer is selectively etched in an embodiment of the present invention;

[0025] Figure 11 is a schematic cross-sectional view of the structure along the length direction of the fin structure after etching the second stacked layer located on the top layer under the masking action of the corresponding mask layer in an embodiment of the present invention;

[0026] Figure 12 It is a schematic longitudinal cross-sectional view of the structure after the first source / drain region and the second source / drain region are formed in an embodiment of the present invention;

[0027] Figure 13 is a schematic longitudinal cross-sectional view of the structure after the dielectric layer is formed in an embodiment of the present invention;

[0028] Figure 14 A schematic longitudinal cross-sectional view of the structure after removing the sacrificial gate in an embodiment of the present invention;

[0029] Figure 15is a schematic longitudinal cross-sectional view of the structure after the first channel region and the second channel region are formed in an embodiment of the present invention;

[0030] Figure 16 1 is a schematic longitudinal cross-sectional view of the structure after the first junctionless transistor and the second junctionless transistor are formed in an embodiment of the present invention.

[0031] Figure numerals: 11 is a semiconductor substrate, 12 is an isolation layer, 13 is a doped semiconductor layer, 14 is a first stack, 15 is a second stack, 16 is a dielectric protection layer, 17 is a shallow trench isolation structure, 18 is a fin structure, 181 is a first region, 182 is a second region, 183 is a third region, 19 is a sacrificial gate, 20 is a gate sidewall, 21 is a first source / drain region, 22 is a second source / drain region, 23 is a dielectric layer, 24 is a first channel region, 25 is a second channel region, and 26 is a gate stack structure. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0036] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0037] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0038] However, the manufacturing process of existing CFET devices is relatively complex and has high requirements for manufacturing technology, which makes it difficult to integrate NMOS transistors and PMOS transistors in CFET devices. Among them, the existing manufacturing methods of CFET devices mainly have the following two integration schemes:

[0039] The first method: using a monolithic method to manufacture CFET devices. Specifically, taking the NMOS transistor and the PMOS transistor as ring-gate transistors, and the PMOS transistor being located above the NMOS transistor as an example, the process of manufacturing CFET devices using the existing manufacturing method is described: First, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer, and a channel layer located on the sacrificial layer. Then, a sacrificial gate and sidewalls are formed across the fin structure. The sacrificial gate and sidewalls are used as masks to selectively etch the fin structure to remove the portion of the fin structure exposed outside the sacrificial gate and sidewalls. Then, a first semiconductor material for manufacturing the source and drain regions included in the NMOS transistor is formed on the semiconductor substrate. At this time, the remaining portions of the sacrificial layer and the channel layer corresponding to the NMOS transistor and the PMOS transistor are exposed after being etched. They can all serve as seed layers for the epitaxial growth of the first semiconductor material, so the first semiconductor material is formed not only on both sides of the remaining portion after the sacrificial layer and the channel layer corresponding to the NMOS transistor are etched, but also on both sides of the remaining portion after the sacrificial layer and the channel layer corresponding to the PMOS transistor are etched. Next, it is necessary to remove the first semiconductor material on both sides of the remaining portion after the sacrificial layer and the channel layer corresponding to the PMOS transistor are etched, and the remaining portion of the first semiconductor material forms the source region and the drain region included in the NMOS transistor. Then, an epitaxial isolation layer is formed covering the source region and the drain region included in the NMOS transistor away from the substrate surface. An epitaxial growth process is used to form the source region and the drain region of the PMOS transistor on the epitaxial isolation layer. Finally, the sacrificial gate and the portion of the sacrificial layer located in the gate formation area are removed, and a gate stack structure surrounding the periphery of the channel area is formed to obtain a CFET device.

[0040] The second method uses a sequential approach to fabricating CFET devices. This involves forming the underlying transistors using conventional semiconductor manufacturing processes. After forming the corresponding contact electrodes for the underlying transistors, a semiconductor layer is deposited on top of the underlying transistors using wafer-to-wafer bonding technology and wafer transfer. The top transistor is then integrated onto this semiconductor layer, and the top and bottom gates are connected to form a CFET transistor.

[0041] As can be seen from the manufacturing process of the first method mentioned above, in order to isolate the source, drain, and channel regions of the bottom and top transistors, the vertical distance between the two transistors is relatively large. Therefore, this method has a relatively high aspect ratio vertical structure, which leads to significant technical challenges in the subsequent patterning of fins, sacrificial gates, gate sidewalls, and source and drain electrodes. In addition, the corresponding CFET device manufacturing process of this method is relatively complex. The manufacturing process of the second method for manufacturing CFET devices is also relatively complex and has high process requirements, resulting in greater difficulty in manufacturing CFET devices.

[0042] In order to solve the above technical problems, Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The semiconductor device manufactured by the manufacturing method includes a semiconductor substrate, a first junctionless transistor and a second junctionless transistor. Figure 16 As shown, the first junctionless transistor is located on the semiconductor substrate 11, and the second junctionless transistor is located on the first junctionless transistor. Moreover, the conductivity types of the second junctionless transistor and the first junctionless transistor are opposite. It can be seen that the semiconductor device manufactured by the manufacturing method provided in the embodiment of the present invention is a CFET device. Specifically, the specific conductivity types of the first junctionless transistor and the second junctionless transistor can be set according to actual needs. For example: the first junctionless transistor can be an N-type transistor, and the second junctionless transistor can be a P-type transistor. At this time, the P-type transistor included in the CFET device is located on the N-type transistor. For another example: the first junctionless transistor can also be a P-type transistor, and the second junctionless transistor can be an N-type transistor. At this time, the N-type transistor included in the CFET device is located on the P-type transistor.

[0043] In addition, the first channel region of the first junction-less transistor may have only one first channel portion. There is a gap between the first channel portion and the semiconductor substrate. Alternatively, Figure 16 As shown, along the thickness direction of the semiconductor substrate 11 , the first channel region 24 may also include at least two first channel portions spaced apart from each other, and a gap exists between the first channel portion at the bottom layer and the semiconductor substrate 11 .

[0044] As for the second channel region included in the second junction-less transistor, it can have only one layer of the second channel portion. There is a gap between the second channel portion and the first channel region. Alternatively, Figure 16 As shown, along the thickness direction of the semiconductor substrate 11 , the second channel region 25 may also include at least two second channel portions spaced apart from each other, and a gap exists between the second channel portion at the bottom layer and the first channel region 24 .

[0045] like Figure 16 As shown, the semiconductor device includes a gate stack structure 26 that surrounds the periphery of the first channel region 24 and the second channel region 25 through the above-mentioned gap. The gate stack structure 26 may include a gate dielectric layer and a gate located on the gate dielectric layer.

[0046] The following will be based on Figures 2 to 16 The manufacturing process is described by using a perspective view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes:

[0047] First, an isolation layer and a doped semiconductor layer are sequentially formed on a semiconductor substrate. The doping type and doping concentration of each region of the doped semiconductor layer are the same. Figure 2 As shown, the above operation is repeated until at least one first stack 14 and at least one second stack 15 located on the at least one first stack 14 are formed on the semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, each second stack 15 and each first stack 14 includes an isolation layer 12 and a doped semiconductor layer 13 located on the isolation layer 12. The doping types of the doped semiconductor layer 13 included in the first stack 14 and the doped semiconductor layer 13 included in the second stack 15 are opposite.

[0048] Specifically, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario. For example: the semiconductor substrate can be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate, etc. on which no other structure is formed. For another example: if the manufacturing method provided in the embodiment of the present invention is used to manufacture the second or higher layer semiconductor devices included in the integrated circuit, the semiconductor substrate can at least include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of the various parts included in the semiconductor substrate can be set according to actual needs, as long as they can be applied to the manufacturing method of the semiconductor device provided in the embodiment of the present invention.

[0049] For the above-mentioned isolation layer, the isolation layer located at the bottom layer is at least used to form a gap between the first channel region and the semiconductor substrate. The isolation layer located between the first junction-less transistor and the second junction-less transistor is used to form a gap between the first channel region and the second channel region. In addition, in the case where the second channel region includes at least two layers of second channel portions, the corresponding isolation layer is also used to form a gap between two adjacent layers of second channel portions. In the case where the first channel region includes at least two layers of first channel portions, the corresponding isolation layer is also used to form a gap between two adjacent layers of first channel portions. Based on this, the thickness of each isolation layer can be set according to the specifications of the gate stack structure included in the semiconductor device and actual needs. Exemplarily, among all the isolation layers, the thickness of the isolation layer located at the bottom layer can be 30nm to 200nm, and the thickness of the remaining isolation layers can be 10nm to 50nm. In this case, the thickness range of the isolation layer located at the bottom layer is larger. When the bottom isolation layer has a large thickness, while meeting the requirement that the gate stack structure is normally filled between the first channel region and the semiconductor substrate, the remaining part of the bottom isolation layer between the gate stack structure and the semiconductor substrate can also isolate the two, suppress leakage, and improve the electrical characteristics of the first junction-less transistor.

[0050] The isolation layer can be made of an insulating material such as silicon oxide or silicon nitride. Because the isolation layer is a non-conductive film, it can also isolate the first source / drain region of the first junctionless transistor from the semiconductor substrate, and the first source / drain region from the second source / drain region of the second junctionless transistor, thereby preventing leakage and improving the electrical characteristics of the resulting semiconductor device.

[0051] Regarding the doped semiconductor layer, the lower doped semiconductor layer is used to form the first channel region and the first source / drain region, while the upper doped semiconductor layer is used to form the second channel region and the second source / drain region. Based on this, the material, thickness, impurity doping type, and doping concentration of the corresponding doped semiconductor layer can be set according to the requirements of the actual application scenario for the material, thickness, and impurity doping type and doping concentration of the first channel region, the first source / drain region, the second channel region, and the second source / drain region. For example, the thickness of the doped semiconductor layer can be 6 nm to 15 nm. The doped semiconductor layer can be made of a semiconductor material such as silicon, silicon germanium, or germanium. When the doped semiconductor layer is made of silicon, the doped semiconductor layer is a doped silicon layer. In this case, the crystal orientation of the doped silicon layer can be polycrystalline and / or single crystalline. Based on this, with other factors being equal, a doped silicon layer with a polycrystalline and / or single crystalline orientation has higher conductivity than amorphous silicon, which helps improve the carrier mobility in the first and second channel regions, further enhancing the driving performance of the semiconductor device.

[0052] In actual application, chemical vapor deposition and other processes can be used to sequentially form an isolation layer and a doped semiconductor layer on a semiconductor substrate. Among them, when the thickness of the underlying isolation layer is large, a high-temperature deposition method can be used to form the underlying isolation layer to improve the compactness of the underlying isolation layer, thereby improving the isolation performance of the underlying isolation layer. Specifically, the deposition temperature of the high-temperature deposition method is 800°C to 1050°C. Of course, when the thickness of the underlying isolation layer is small, a low-temperature deposition method can be used. In addition, because the thickness of the remaining isolation layers is relatively small, they can be manufactured and formed by a low-temperature deposition method to reduce the thermal plan for manufacturing semiconductor devices, which is conducive to the use of the manufacturing method provided in the embodiment of the present invention to manufacture upper-layer devices in integrated circuits. Specifically, the deposition temperature of the low-temperature deposition method is greater than 0°C and less than or equal to 600°C.

[0053] Secondly, when the doped semiconductor layer is a doped silicon layer, the formation temperature of the doped silicon layer can be greater than 0°C and less than or equal to 600°C, that is, the doped silicon layer can be formed by a relatively low temperature deposition method, further reducing the thermal plan for manufacturing semiconductor devices.

[0054] Of course, the doped semiconductor layer can also be manufactured at a relatively high formation temperature. The specific formation process of the doped semiconductor layer can be set according to the material, crystal orientation, and actual needs of the doped semiconductor layer. The following will take the doped semiconductor layer as an example to illustrate the specific formation process of forming the doped semiconductor layer on the isolation layer:

[0055] For example, if the doped silicon layer is only polycrystalline, a low-temperature deposition process can be used to directly form the doped silicon layer on the isolation layer. The deposition temperature range of the low-temperature deposition process can be found in the previous text and will not be described in detail here.

[0056] For another example, the aforementioned step of forming a doped silicon layer on the isolation layer may also include the steps of forming an amorphous silicon layer on the isolation layer using a process such as low-pressure chemical vapor deposition. The amorphous silicon layer is then annealed and doped with impurities to form a doped silicon layer on the isolation layer. In this case, the doped silicon layer may have a polycrystalline and / or single-crystalline orientation.

[0057] A low-temperature deposition process can be used to form an amorphous silicon layer on the isolation layer to reduce the thermal requirements of semiconductor device manufacturing. The deposition temperature of this low-temperature deposition process is greater than 0°C and less than 600°C. Of course, the amorphous silicon layer can also be formed at a relatively high temperature.

[0058] In addition, the type and processing conditions of the above-mentioned annealing treatment can be determined according to the crystal orientation of the doped silicon layer to be formed. Specifically, when the crystal orientation of the doped silicon layer is only polycrystalline silicon, the above-mentioned annealing treatment is a low-temperature annealing treatment, the processing temperature of which is greater than 0°C and less than 600°C, and the processing time of the low-temperature annealing treatment is 10 hours to 36 hours.

[0059] In the case where the crystal orientation of the doped silicon layer is only single crystal silicon, the annealing treatment method can be only laser annealing treatment. At this time, the portion of the amorphous silicon layer corresponding to the first source / drain region and the first channel portion can be directly subjected to laser annealing treatment. The processing temperature of the laser annealing treatment can be 1200°C to 1500°C. The processing time of the laser annealing treatment can be 10ns to 10ms. Alternatively, in this case, the annealing treatment method can also include low-temperature annealing treatment and laser annealing treatment. At this time, the processing conditions described above can be used to perform low-temperature annealing treatment and laser annealing treatment on the entire amorphous silicon layer in sequence to form a single crystal silicon layer from the polycrystalline silicon layer.

[0060] When the crystal orientation of the doped silicon layer includes polycrystalline and single crystal, the annealing method may include low-temperature annealing and laser annealing. In this case, the processing conditions described above can be used to first perform a low-temperature annealing treatment on the entire amorphous silicon layer to transform the amorphous silicon layer into a polycrystalline silicon layer. Then, laser annealing treatment is performed on the portion of the polycrystalline silicon layer corresponding to the first source / drain region and the first channel portion (or corresponding to the second source / drain region and the second channel portion) in a targeted manner to make the crystal orientation of the processed portion of the polycrystalline silicon layer single crystal.

[0061] After forming an isolation layer and a doped semiconductor layer on the isolation layer in the above manner, the number of repetitions of the above operation can be determined based on the number of first channel portions included in the first channel region and the number of second channel portions included in the second channel region. Figure 16 As shown, in the case where the first channel region 24 includes two layers of first channel portions, and the second channel region 25 includes two layers of second channel portions, as shown in FIG. Figure 2 As shown, the above operation needs to be performed four times to form two first stacked layers 14 and two second stacked layers 15 on the semiconductor substrate 11 .

[0062] In one example, after forming the at least one first stack and the at least one second stack located on the at least one first stack on the semiconductor substrate, and before performing subsequent operations, the method for manufacturing the semiconductor device may further include the following steps: Figure 3 As shown, a dielectric protection layer 16 can be formed on at least one second stack 15 using a process such as atomic layer deposition or plasma-enhanced chemical vapor deposition. The dielectric protection layer 16 can protect the doped semiconductor layer 13 located below it from subsequent patterning and selective etching operations, thereby improving the quality of the corresponding second channel portion formed based on the doped semiconductor layer 13. Specifically, the material and thickness of the dielectric protection layer 16 can refer to the material and thickness of the isolation layer 12 between adjacent doped semiconductor layers 13, and will not be described in detail here.

[0063] It should be noted that, in actual application, if subsequent operations have little impact on the top doped semiconductor layer and meet the manufacturing requirements of the semiconductor substrate, the above-mentioned dielectric protection layer may not be formed.

[0064] like Figure 5 As shown, at least one first stack layer and at least one second stack layer are patterned to form a fin structure 18 on the semiconductor substrate 11 .

[0065] In actual application, processes such as photolithography and dry etching can be used to pattern at least one first stack and at least one second stack to form a fin structure on the semiconductor substrate. The objects of the above patterning process can be divided into the following three types:

[0066] First, if the underlying isolation layer is relatively thick and no dielectric protection layer is formed, only the at least one first stack and the at least one second stack can be patterned. In this case, the subsequently formed first junction-less transistor can be isolated from other adjacent conductive structures formed on the semiconductor substrate by the relatively thick isolation layer.

[0067] Second method: If the thickness of the underlying isolation layer is relatively small and no dielectric protection layer is formed, the at least one second stack, the at least one first stack, and a portion of the semiconductor substrate can be patterned from top to bottom. The semiconductor substrate etching depth can be adjusted based on the thickness of the subsequently formed shallow trench isolation structure and is not specifically limited here.

[0068] The third type: Figure 4 As shown, when the thickness of the bottom isolation layer is small and a dielectric protection layer is formed, the dielectric protection layer, the at least one second stack layer, the at least one first stack layer and part of the semiconductor substrate 11 can be patterned from top to bottom.

[0069] It should be noted that in the second and third cases, after patterning, e.g. Figure 5 As shown, it is also necessary to form a shallow trench isolation structure 17 on the semiconductor substrate 11 by using processes such as chemical vapor deposition and etching. The above-mentioned fin structure 18 is exposed outside the shallow trench isolation structure 17. In addition, as shown in FIG. Figure 5 As shown, along the length direction of the fin structure 18 , the fin structure 18 includes a first region 181 , a second region 182 , and a third region 183 located between the first region 181 and the second region 182 .

[0070] In actual application, a gate stack structure included in a semiconductor device is usually formed using a replacement gate process to improve the formation quality of the manufactured gate stack structure. In this case, after the fin structure is formed on the semiconductor substrate and before subsequent operations are performed, the manufacturing method of the semiconductor device further includes: Figures 6 to 8 As shown, chemical vapor deposition and etching processes can be used to sequentially form a sacrificial gate 19 and a gate spacer 20 across the third region 183. The gate spacer 20 is located at least on both sides of the sacrificial gate 19 along the length direction. The materials and specifications of the sacrificial gate 19 and the gate spacer 20 can be set according to actual needs, as long as they can be applied to the semiconductor device manufacturing method provided in the embodiment of the present invention.

[0071] like Figure 12As shown, after the above operations are performed, the edge area of ​​at least one layer of the second stack is selectively etched along the length direction of the fin structure, so that the length of each doped semiconductor layer 13 is smaller than the length of another doped semiconductor layer 13 located below it, and the length of each isolation layer 12 is smaller than the length of the doped semiconductor layer 13 located below it.

[0072] Specifically, after the selective etching, the length difference between each doped semiconductor layer and the other doped semiconductor layer located below it, as well as the length difference between each isolation layer and the doped semiconductor layer located below it, can be set according to the actual application scenario, as long as it can facilitate the extraction of each active portion included in the first source / drain region and the second source / drain region. In addition, after the selective etching, the length of each isolation layer can be equal to the length of the doped semiconductor layer located below it, or it can be less than or slightly greater than the length of the doped semiconductor layer located below it.

[0073] In actual application, when no dielectric protection layer is formed, it is necessary to selectively etch at least the edge region of at least one second stack along the length direction of the fin structure. Figure 12 As shown, when the dielectric protection layer 16 is formed, it is necessary to selectively etch at least the edge region of the dielectric protection layer 16 and the edge region of at least one second stacked layer along the length direction of the fin structure.

[0074] In addition, in the fin structure, whether each layer of the first stack and each layer of the second stack needs to be selectively etched, and the length of the selective etching can be determined based on the number of layers of the first stack and the second stack in the fin structure, and the specifications of each active portion included in the above-mentioned first source / drain region and the second source / drain region.

[0075] For example, in a fin structure comprising only a first stack and a second stack, selective etching can be performed sequentially along the length of the fin structure using the masking of the corresponding mask layer, sequentially along the edge region of the doped semiconductor layer included in the second stack and the edge region of the isolation layer included in the second stack. After the selective etching, the edge region of the second stack is etched away, exposing the doped semiconductor layer included in the first stack. Furthermore, because the doped semiconductor layer included in the second stack is located on the top layer, the edge region of the remaining doped semiconductor layer included in the second stack is also exposed.

[0076] For another example, in the case where the fin structure includes two first stacked layers, two second stacked layers and a dielectric protection layer, as shown in FIG. Figure 9 As shown in FIG, a first mask layer can be formed on the dielectric protection layer 16 by using a process such as photolithography. Figure 10As shown, then, under the masking action of the first mask layer, the edge area of ​​the dielectric protection layer 16 is selectively etched along the length direction of the fin structure. Then, the first mask layer is removed and a second mask layer is formed. Figure 11 As shown, under the masking effect of the second mask layer, the edge area of ​​the top second stack 15 is selectively etched along the length direction of the fin structure. Figure 12 As shown, the above operation is repeated until the length of each doped semiconductor layer 13 is smaller than the length of another doped semiconductor layer 13 located thereunder, and the length of each isolation layer 12 is smaller than the length of the doped semiconductor layer 13 located thereunder.

[0077] It should be noted that the selective etching described above can be performed in a variety of ways. How to perform the selective etching is not a key feature of the present invention. Therefore, this specification only briefly describes the method so that those skilled in the art can easily implement the present invention. Those skilled in the art can readily devise other methods to ensure that the length of each doped semiconductor layer is shorter than the length of the underlying doped semiconductor layer, and that the length of each isolation layer is shorter than the length of the underlying doped semiconductor layer.

[0078] In one example, after performing the above selective etching and before performing subsequent operations, the method for manufacturing the semiconductor device may further include the following steps: Figure 13 As shown, a dielectric layer 23 covering the semiconductor substrate 11 can be formed by chemical vapor deposition and chemical mechanical polishing. The top of the dielectric layer 23 is flush with the top of the sacrificial gate 19. The material of the dielectric layer 23 can be an insulating material such as silicon oxide or silicon nitride. Figure 14 As shown, the sacrificial gate can be removed by using a dry etching process or a wet etching process.

[0079] like Figure 16 As shown, a first junction-less transistor is manufactured based on at least one first stacked layer, and a second junction-less transistor is manufactured based on at least one second stacked layer.

[0080] In actual application, if a dielectric protection layer is not formed, a process such as dry etching or wet etching can be used to selectively remove only the portion of each isolation layer located in the third region, so that the portion of the doped semiconductor layer included in at least one first stack located in the third region forms the first channel region included in the first junction-less transistor, and the portion of the doped semiconductor layer included in at least one second stack located in the third region forms the second channel region included in the second junction-less transistor. Finally, a gate stack structure surrounding the first channel region and the second channel region can be formed by a process such as atomic deposition. The material of the gate dielectric layer included in the gate stack structure can be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate included in the gate stack structure can be a conductive material such as TiN, TaN or TiSiN.

[0081] like Figure 15 As shown, if the above-mentioned dielectric protection layer is formed, it is necessary to use a dry etching or wet etching process to selectively remove the portion of the dielectric protection layer located in the third region and the portion of each isolation layer located in the third region to form the first channel region 24 and the second channel region 25. Finally, as shown in FIG. Figure 16 As shown, a gate stack structure 26 surrounding the first channel region 24 and the second channel region 25 may be formed by using processes such as atomic deposition.

[0082] From the above manufacturing process, it can be seen that Figures 2 to 16 As shown, the semiconductor device manufactured by the embodiment of the present invention is a CFET device. Secondly, in the actual manufacturing process, a process such as chemical vapor deposition can be used to sequentially form an isolation layer 12 and a doped semiconductor layer 13 on a semiconductor substrate 11. The above operations are then repeated until at least one first stack 14 and at least one second stack 15 are formed on the semiconductor substrate. Based on this, since the doped semiconductor layer 13 included in the first stack 14 is used to manufacture the first source / drain region 21 and the first channel region 24 included in the first junctionless transistor, and the doped semiconductor layer 13 included in the second stack 15 is used to manufacture the second source / drain region 22 and the second channel region 25 included in the second junctionless transistor, and the doping type and doping concentration of each region of the doped semiconductor layer 13 are the same, after forming the intrinsic semiconductor material used to manufacture the doped semiconductor layer 13 on the isolation layer 12, there is no need to form a corresponding mask layer. Impurity doping can be directly performed on each portion of the intrinsic semiconductor material, simplifying the manufacturing process of the first source / drain region 21 and the second source / drain region 22 of opposite conductivity types, thereby reducing the manufacturing difficulty of the CFET device.

[0083] Furthermore, if Figures 12 to 16As shown, after patterning at least one first stack layer and at least one second stack layer to form a fin structure, selective etching is performed on the edge region of at least one second stack layer along the length direction of the fin structure, so that the length of each doped semiconductor layer 13 is shorter than the length of the other doped semiconductor layer 13 located below it, and the length of each isolation layer 12 is shorter than the length of the doped semiconductor layer 13 located below it. At this time, the first source / drain region 21 and the second source / drain region 22 are distributed in a stepped manner, so that the edge regions of all active portions included in the first source / drain region 21 and the second source / drain region 22 are exposed from bottom to top, which facilitates the connection of each active portion with the corresponding contact electrode, reduces the difficulty of leading out the contact electrode, and further reduces the difficulty of manufacturing the CFET device.

[0084] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0085] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming an isolation layer and a doped semiconductor layer in sequence on a semiconductor substrate; The doping type and doping concentration of each region of the doped semiconductor layer are the same; Repeating the above operation until at least one first stack and at least one second stack located on the at least one first stack are formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, each second stack and each first stack includes the isolation layer and the doped semiconductor layer located on the isolation layer; the doping types of the doped semiconductor layer included in the first stack and the doped semiconductor layer included in the second stack are opposite; performing a patterning process on at least the at least one first stacked layer and the at least one second stacked layer to form a fin structure on the semiconductor substrate; Selectively etching at least an edge region of the at least one second stack along a length direction of the fin structure so that a length of each doped semiconductor layer is shorter than a length of another doped semiconductor layer located thereunder, and a length of each isolation layer is shorter than a length of the doped semiconductor layer located thereunder; A first junctionless transistor is manufactured based on the at least one first stack, and a second junctionless transistor is manufactured based on the at least one second stack; the length direction of the isolation layer and the length direction of the doped semiconductor layer are both parallel to the length direction of the gate stack structure included in the first junctionless transistor and the junctionless transistor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The doped semiconductor layer is a doped silicon layer, and the crystal orientation of the doped silicon layer is polycrystalline and / or single crystal.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The doped silicon layer is formed at a temperature greater than 0° C. and less than or equal to 600° C.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: In a case where the crystal orientation of the doped silicon layer is polycrystalline, the doped silicon layer is directly formed on the isolation layer by using a low temperature deposition process.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: Forming the doped silicon layer on the isolation layer comprises: forming an amorphous silicon layer on the isolation layer; The amorphous silicon layer is subjected to annealing treatment and impurity doping treatment to form the doped silicon layer on the isolation layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The amorphous silicon layer is formed on the isolation layer by a low temperature deposition process; the deposition temperature of the low temperature deposition process is greater than 0° C. and less than 600° C.; and / or, The annealing treatment includes low-temperature annealing treatment and / or laser annealing treatment; wherein, the treatment temperature of the low-temperature annealing treatment is greater than 0°C and less than 600°C, and the treatment time of the low-temperature annealing treatment is 10h to 36h; the treatment temperature of the laser annealing treatment is 1200°C to 1500°C; and the treatment time of the laser annealing treatment is 10ns to 10ms.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the isolation layer is silicon oxide or silicon nitride; and / or, Among all the isolation layers, the thickness of the isolation layer located at the bottom layer is 30 nm to 200 nm, and the thickness of the remaining isolation layers is 10 nm to 50 nm.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: Along the length direction of the fin-shaped structure, the fin-shaped structure includes a first region, a second region, and a third region located between the first region and the second region; The manufacturing of a first junctionless transistor based on the at least one first stacked layer, and the manufacturing of a second junctionless transistor based on the at least one second stacked layer, comprises: selectively removing at least a portion of each isolation layer located in the third region, so that a portion of the doped semiconductor layer included in the at least one first stack located in the third region forms a first channel region of the first junctionless transistor, and a portion of the doped semiconductor layer included in the at least one second stack located in the third region forms a second channel region of the second junctionless transistor; A gate stack structure is formed surrounding the first channel region and the second channel region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The above operations are repeated until at least one first stack and at least one second stack located on the at least one first stack are formed on the semiconductor substrate, and before the at least one first stack and the at least one second stack are patterned to form a fin structure on the semiconductor substrate, the method for manufacturing a semiconductor device further includes: forming a dielectric protection layer on the at least one second stack; The patterning process is performed on at least the at least one first stack and the at least one second stack, comprising: performing the patterning process on the at least one first stack, the at least one second stack and the dielectric protection layer; The selectively etching at least an edge region of the at least one second stack along the length direction of the fin structure comprises: selectively etching at least an edge region of the dielectric protection layer and an edge region of the at least one second stack along the length direction of the fin structure; The selectively removing at least the portion of each isolation layer located in the third region includes: selectively removing the portion of the dielectric protection layer located in the third region and the portion of each isolation layer located in the third region.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: After patterning at least the at least one first stack and the at least one second stack to form a fin structure on the semiconductor substrate, and before selectively etching at least an edge region of the at least one second stack along the length direction of the fin structure, the method for manufacturing a semiconductor device further comprises: forming a sacrificial gate and a gate sidewall across the third region; the gate sidewall is located at least on both sides of the sacrificial gate along the length direction; After selectively etching at least the edge area of ​​the at least one second stack along the length direction of the fin structure, and before selectively removing at least the portion of each isolation layer located in the third area, the method for manufacturing the semiconductor device further includes: forming a dielectric layer covering the semiconductor substrate; the top of the dielectric layer is flush with the top of the sacrificial gate; and removing the sacrificial gate.

Images