Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The formation method includes: forming a first interlayer dielectric layer on a substrate on the side of a polysilicon gate layer, the first interlayer dielectric layer covering the sidewall of the polysilicon gate layer; forming a capping dielectric layer on top of the first interlayer dielectric layer and the polysilicon gate layer; etching the capping dielectric layer on top of the polysilicon gate layer in a first device region to form an opening in the capping dielectric layer exposing the polysilicon gate layer; forming a metal silicide layer on top of the polysilicon gate layer exposed by the opening; removing the remaining capping dielectric layer; forming a second interlayer dielectric layer on top of the first interlayer dielectric layer and the polysilicon gate layer; and forming a gate plug penetrating the second interlayer dielectric layer on top of the polysilicon gate layer in the first device region, the gate plug being connected to the metal silicide. This reduces the probability of a height difference between the first interlayer dielectric layer on the substrate of the first device region and the first interlayer dielectric layer on other regions of the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of highly integrated semiconductor devices, the gate length of metal-oxide-semiconductor devices is being reduced proportionally to smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also being continuously improved to meet people's requirements for device performance.

[0003] Currently, devices with higher operating voltages are typically integrated with devices with lower operating voltages (i.e., logic platform devices) in integrated circuit manufacturing. In order to reduce the contact resistance between the added devices with higher operating voltages and the contact plugs, a process for forming metal silicides needs to be added after the metal gate structure is formed during the manufacturing process of the original logic platform device. This can have an adverse effect on other structures of the semiconductor device. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first device region for forming a first device; a polysilicon gate layer located on the substrate of the first device region; a first interlayer dielectric layer located on the substrate at the side of the polysilicon gate layer, the first interlayer dielectric layer covering the sidewall of the polysilicon gate layer, and the top of the first interlayer dielectric layer being flush with the top of the polysilicon gate layer; a metal silicide layer located on the polysilicon gate layer of the first device region; a second interlayer dielectric layer located on top of the first interlayer dielectric layer and the polysilicon gate layer, the second interlayer dielectric layer covering the metal silicide layer; and a gate plug located in the first device region and penetrating the second interlayer dielectric layer located on top of the polysilicon gate layer, the gate plug being connected to the metal silicide layer.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region for forming a first device, wherein a polysilicon gate layer is formed on the substrate; forming a first interlayer dielectric layer on the substrate at the side of the polysilicon gate layer, the first interlayer dielectric layer covering the sidewall of the polysilicon gate layer, and the top of the first interlayer dielectric layer being flush with the top of the polysilicon gate layer; forming a capping dielectric layer on top of the first interlayer dielectric layer and the polysilicon gate layer; and etching the polysilicon gate in the first device region. The cap dielectric layer at the top of the electrode layer has an opening formed in it to expose the polysilicon gate layer; a metal silicide layer is formed on top of the polysilicon gate layer exposed by the opening; after forming the metal silicide layer, the remaining cap dielectric layer is removed; after removing the remaining cap dielectric layer, a second interlayer dielectric layer is formed on top of the first interlayer dielectric layer and the polysilicon gate layer; in the first device region, a gate plug penetrating the second interlayer dielectric layer is formed on top of the polysilicon gate layer, and the gate plug is connected to the metal silicide.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the formation method provided by this embodiment of the invention, a capping dielectric layer is formed on top of the first interlayer dielectric layer and the polysilicon gate layer; in the first device region, the capping dielectric layer on top of the polysilicon gate layer is etched to form an opening in the capping dielectric layer exposing the polysilicon gate layer. Compared with the current scheme that completely removes the capping dielectric layer of the first device region, exposing the top of the polysilicon gate layer and the first interlayer dielectric layer of the first device region, this embodiment of the invention only etches and removes the capping dielectric layer above the polysilicon gate layer, that is, the remaining capping dielectric layer still covers the top of the first interlayer dielectric layer of the first device region. Correspondingly, while completely removing the capping dielectric layer above the polysilicon gate layer, the remaining capping dielectric layer protects the top of the first interlayer dielectric layer of the first device region, reducing the probability of damage to the first interlayer dielectric layer on the side of the polysilicon gate layer, thus improving the performance of the metal silicide process. The top of the first interlayer dielectric layer remains flush with the top of the polysilicon gate layer. This improves the flatness of the top surface of the first interlayer dielectric layer and reduces the probability of a height difference between the first interlayer dielectric layer on the first device region substrate and the first interlayer dielectric layer on other region substrates. Therefore, after removing the remaining cap dielectric layer and forming the second interlayer dielectric layer, the flatness of the top surface of the second interlayer dielectric layer is correspondingly improved. This reduces the probability of defocusing during the photolithography process when forming the gate plug, and also reduces the probability of conductive material used to form the gate plug remaining on the top of the second interlayer dielectric layer, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 8 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this need to improve performance using a semiconductor structure formation method as an example.

[0013] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 A substrate is provided, the substrate 10 including a first device region 10A for forming a first device and a second device region 10B for forming a second device, the channel length of the second device being less than the channel length of the first device, a polysilicon gate structure 18 being formed on the substrate 10 of the first device region 10A, a metal gate structure 17 being formed on the substrate 10 of the second device region 10B, and a first interlayer dielectric layer 16 being formed on the substrate 10, the first interlayer dielectric layer 16 covering the sidewalls of the polysilicon gate structure 18 and the sidewalls of the metal gate structure 17.

[0015] A high-k gate dielectric layer (not shown) and a metal barrier layer (not shown) are formed between the polysilicon gate structure 18 and the substrate 10.

[0016] refer to Figure 2 A capping dielectric layer 20 is formed on top of the first interlayer dielectric layer 16, the polysilicon gate structure 18, and the metal gate structure 17.

[0017] refer to Figure 3 Remove the capping dielectric layer 20 in the first device region 10A to expose the top surface of the polysilicon gate structure 18 and the top surface of the first interlayer dielectric layer 16; after removing the capping dielectric layer 20 in the first device region 10A, form a metal silicide layer 19 on the top surface of the polysilicon gate structure 18.

[0018] refer to Figure 4A second interlayer dielectric layer 21 is formed on top of the first interlayer dielectric layer 16, the cap dielectric layer 20, the metal silicide layer 19, and the polysilicon gate structure 18.

[0019] refer to Figure 5 The metal silicide layer 19 and the second interlayer dielectric layer 21 and cap dielectric layer 20 on top of the metal gate structure 17 are etched away.

[0020] A gate contact hole (not shown) is formed to expose the top of the metal silicide layer 19 and the metal gate structure 17; a gate plug material layer 22 is formed in the gate contact hole.

[0021] refer to Figure 6 Taking the top of the second interlayer dielectric layer 21 as the stopping position, the gate plug material layer 22 above the top of the second interlayer dielectric layer 21 is removed, and the remaining gate plug material layer serves as the gate plug 23.

[0022] However, during the removal of the capping dielectric layer 20 in the first device region 10A, in order to completely remove the capping dielectric layer 20 on top of the polysilicon gate structure 18 in the first device region 10A, it is easy to cause over-etching of the first interlayer dielectric layer 16 on both sides of the polysilicon gate structure 18 (e.g., Figure 3 As shown in the dashed circle, this creates a height difference between the top surfaces of the first interlayer dielectric layer 16 of the first device region 10A and the second device region 10B. Simultaneously, after the metal silicide layer 19 is formed on the top surface of the polysilicon gate structure 18, the cap dielectric layer 20 remains on top of the first interlayer dielectric layer 16 of the second device region 10B, further increasing the height difference between the top surfaces of the first device region 10A and the second device region 10B. Consequently, during the formation of the gate contact hole (not shown), the height difference between the top surfaces of the second interlayer dielectric layer 21 of the first device region 10A and the second device region 10B makes it highly susceptible to defocusing during photolithography, leading to pattern exposure loss. Therefore, during the formation of the gate plug 23, after planarizing the gate plug material layer 22 above the top of the second interlayer dielectric layer 21 with the top of the second interlayer dielectric layer 21 as the stopping position, a portion of the gate plug material layer 22 may remain at the junction of the first device region 10A and the second device region 10B (e.g., Figure 6 (As shown in the dashed coil in the middle), thus affecting the performance of the semiconductor structure.

[0023] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region for forming a first device, and forming a polysilicon gate layer on the substrate; forming a first interlayer dielectric layer on the substrate at a side of the polysilicon gate layer, the first interlayer dielectric layer covering the sidewall of the polysilicon gate layer, and the top of the first interlayer dielectric layer being flush with the top of the polysilicon gate layer; forming a capping dielectric layer on top of the first interlayer dielectric layer and the polysilicon gate layer; and etching the polysilicon gate layer in the first device region. The capping dielectric layer on top of the polysilicon gate layer forms an opening in the capping dielectric layer that exposes the polysilicon gate layer; a metal silicide layer is formed on top of the polysilicon gate layer exposed by the opening; after forming the metal silicide layer, the remaining capping dielectric layer is removed; after removing the remaining capping dielectric layer, a second interlayer dielectric layer is formed on top of the first interlayer dielectric layer and the polysilicon gate layer; in the first device region, a gate plug penetrating the second interlayer dielectric layer is formed on top of the polysilicon gate layer, and the gate plug is connected to the metal silicide.

[0024] In the formation method provided by this embodiment of the invention, only the capping dielectric layer above the polysilicon gate layer is etched away. That is, the remaining capping dielectric layer still covers the top of the first interlayer dielectric layer in the first device region. Correspondingly, while completely removing the capping dielectric layer above the polysilicon gate layer, the remaining capping dielectric layer protects the top of the first interlayer dielectric layer in the first device region, reducing the probability of damage to the first interlayer dielectric layer on the side of the polysilicon gate layer. This makes the top of the first interlayer dielectric layer flush with the top of the polysilicon gate layer, which improves the flatness of the top surface of the first interlayer dielectric layer and reduces the probability of a height difference between the first interlayer dielectric layer on the substrate of the first device region and the first interlayer dielectric layer on the substrate of other regions. Therefore, after removing the remaining capping dielectric layer and forming the second interlayer dielectric layer, the flatness of the top surface of the second interlayer dielectric layer is correspondingly improved. In the subsequent formation of the gate plug, the probability of defocusing during the photolithography process is reduced, and the probability of the conductive material used to form the gate plug remaining on the top of the second interlayer dielectric layer is reduced, thereby improving the performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0027] The semiconductor structure includes: a substrate, the substrate including a first device region 200A for forming a first device; a polysilicon gate layer 212 located on the substrate of the first device region 200A; a first interlayer dielectric layer 216 located on the substrate on the side of the polysilicon gate layer 212, the first interlayer dielectric layer 216 covering the sidewall of the polysilicon gate layer 212, and the top of the first interlayer dielectric layer 216 being flush with the top of the polysilicon gate layer 212; and a metal silicide layer 220. The first device region 200A has a polysilicon gate layer 212 located on top of the first interlayer dielectric layer 216 and the polysilicon gate layer 212, and the second interlayer dielectric layer 230 covers the metal silicide layer 220; the gate plug 221 is located in the first device region 200A and penetrates the second interlayer dielectric layer 230 located on top of the polysilicon gate layer 212, and the gate plug 221 is connected to the metal silicide layer 220.

[0028] In this embodiment, during the formation process of the metal silicide layer 220, in order to selectively form the metal silicide layer 220 on top of the polysilicon gate layer 212 in the first device region 200A, a capping dielectric layer (not shown) covering the first interlayer dielectric layer 216 and the polysilicon gate layer 212 is typically formed first. This is achieved by etching away only the capping dielectric layer above the polysilicon gate layer 212, meaning the remaining capping dielectric layer still covers the top of the first interlayer dielectric layer 216 in the first device region 100A. After forming the metal silicide layer 220, the capping dielectric layer is removed. Correspondingly, while completely removing the capping dielectric layer above the polysilicon gate layer 212, the remaining capping dielectric layer protects the top of the first interlayer dielectric layer 216 in the first device region 200A, reducing the probability of damage to the first interlayer dielectric layer 216 on the side of the polysilicon gate layer 212, thus protecting the first interlayer dielectric layer 216. The top of the first interlayer dielectric layer 216 is flush with the top of the polysilicon gate layer 212, which improves the top surface flatness of the first interlayer dielectric layer 216 and reduces the probability of a height difference between the first interlayer dielectric layer 216 on the first device region 200A substrate and the first interlayer dielectric layer 216 on other region substrates. Therefore, after removing the remaining cap dielectric layer and forming the second interlayer dielectric layer 230, the top surface flatness of the second interlayer dielectric layer 230 is correspondingly improved. When forming the gate plug 221, the probability of defocusing during the photolithography process is reduced, and the probability of the conductive material used to form the gate plug 221 remaining on the top of the second interlayer dielectric layer 230 is reduced, thereby improving the performance of the semiconductor structure.

[0029] The substrate provides the technological basis for the formation of the semiconductor structure.

[0030] In this embodiment, the substrate is used to form a planar transistor; therefore, the substrate includes a substrate 200. In other embodiments, when the substrate is used to form a fin field-effect transistor (FinFET), the substrate also includes fins protruding from the substrate.

[0031] In this embodiment, 200 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0032] In this embodiment, the semiconductor structure further includes an isolation layer 202 located in the substrate 200. Specifically, the top of the isolation layer 202 is flush with the top of the substrate 200.

[0033] The isolation layer 202 is used to isolate adjacent devices. The material of the isolation layer 202 may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0034] In this embodiment, the substrate includes a first device region 200A for forming a first device and a second device region 200B for forming a second device, wherein the channel length of the second device is less than the channel length of the first device.

[0035] As an example, the operating voltage of the first device is greater than that of the second device, such that the channel length of the first device is greater than that of the second device.

[0036] In this embodiment, the first device includes one or both of medium-voltage and high-voltage devices, and the second device is a low-voltage device. The operating voltages of the low-voltage, medium-voltage, and high-voltage devices increase sequentially. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0037] In the step of providing the substrate, the polysilicon gate layer 212 located in the first device region 200A includes a bottom gate layer 209 and a plurality of top gate layers 210 protruding on the bottom gate layer 209, with adjacent top gate layers 210 and bottom gate layers 209 forming a groove (not shown).

[0038] Since the channel length of the first device is relatively long, in the polysilicon gate layer 212 in the first device region 200A, the adjacent top gate layer 210 and bottom gate layer 209 form a groove 207. The linewidth dimension of the top gate layer 210 and the spacing between adjacent top gate layers 210 (i.e., the linewidth dimension of the groove 207) are both small, thereby reducing the probability of dishing defects occurring at the top of the polysilicon gate layer 212 during the planarization process used to form the semiconductor structure.

[0039] In this embodiment, the semiconductor structure further includes a metal gate layer 217 located on the substrate of the second device region 200B.

[0040] The metal gate layer 217 serves as the metal gate structure for the second device region 200B. Since the channel length of the second device is relatively short, the short-channel effect is improved by employing a metal gate structure.

[0041] In this embodiment, the material of the metal gate layer 217 includes W. In other embodiments, the material of the metal gate layer may also be TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, or TiAlC, etc.

[0042] In this embodiment, the semiconductor structure further includes a high-k gate dielectric layer 203 and a metal barrier layer 204 located on the high-k gate dielectric layer 203. The stacked structure formed by the high-k gate dielectric layer 203 and the metal barrier layer 204 is located between the polysilicon gate layer 212 and the substrate in the first device region 200A, and between the metal gate layer 217 and the substrate in the second device region 200B.

[0043] The high-k gate dielectric layer 203 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 230 is HfO2.

[0044] The metal barrier layer 204 is used to isolate the high-k gate dielectric layer 203 and the metal gate layer 217 to protect the high-k gate dielectric layer 203. In addition, the metal barrier layer 204 is also used to prevent easily diffusible ions (e.g., Al ions) in the metal gate layer 217 from diffusing into the high-k gate dielectric layer 203.

[0045] Specifically, the material of the metal barrier layer 204 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). As an example, the material of the metal barrier layer 204 is titanium nitride.

[0046] In this embodiment, the semiconductor structure further includes a gate hard mask layer 211 located in the groove.

[0047] The gate hard mask layer 211 is used as an etching mask for forming the polysilicon gate layer 212. At the same time, in the formation process of the first interlayer dielectric layer 216, the top of the gate hard mask layer 211 is also used as the stop position for the planarization process, thereby reducing the probability of a depression defect occurring on the top of the polysilicon gate layer 212 during the planarization process.

[0048] In this embodiment, the gate hard mask layer 211 fills the groove. In other embodiments, depending on the depth of the groove and the thickness of the gate hard mask layer, the gate hard mask layer may also be located at the bottom and sidewalls of the groove, and a first interlayer dielectric layer is formed in the remaining space of the groove.

[0049] In this embodiment, the semiconductor structure further includes a sidewall 215 located on the sidewall of the polysilicon gate layer 212 and the metal gate layer 217.

[0050] The sidewall 215 is used to protect the sidewall of the polysilicon gate layer 212. At the same time, in the planarization process with the top of the gate hard mask layer 211 in the groove 207 as the stop position, the sidewall 215 helps to reduce the probability of the top of the top gate layer 210 having a recess defect.

[0051] The sidewall 215 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 215 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall 215 is a single-layer structure, and the material of the sidewall 215 is silicon nitride.

[0052] In this embodiment, the semiconductor structure further includes a first source / drain doped region 262, located in the substrate on both sides of the polysilicon gate layer 212 of the first device region 200A.

[0053] The first source / drain doped region 262 is used as the source or drain region of the first device. When the first device is an NMOS device, the first source / drain doped region 262 is N-type doped; when the first device is a PMOS device, the first source / drain doped region 262 is P-type doped.

[0054] In this embodiment, the semiconductor structure further includes a second source / drain doped region 261, located in the substrate on both sides of the metal gate layer 217 of the second device region 200B.

[0055] The second source / drain doped region 261 is used as the source or drain region of the second device. When the second device is an NMOS device, the second source / drain doped region 261 is N-type doped; when the second device is a PMOS device, the second source / drain doped region 261 is P-type doped.

[0056] In this embodiment, the semiconductor structure further includes a source / drain silicide layer 260, located on the top surface of the first source / drain doped region 262 and the second source / drain doped region 261.

[0057] The source / drain silicide layer 260 is used to reduce the contact resistance between the first source / drain doped region 262 and the second source / drain doped region 261 and the corresponding source / drain contact plugs. In this embodiment, the material of the source / drain silicide layer 260 can be a nickel-silicon compound, a cobalt-silicon compound, or a titanium-silicon compound.

[0058] The first interlayer dielectric layer 216 serves to isolate adjacent devices.

[0059] In this embodiment, the material of the first interlayer dielectric layer 216 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0060] In this embodiment, the top of the first interlayer dielectric layer 216 is flush with the top of the top gate layer 210.

[0061] The top of the first interlayer dielectric layer 216 is flush with the top of the top gate layer 210, which improves the flatness of the top surface of the first device.

[0062] In this embodiment, the first interlayer dielectric layer 216 also covers the sidewall of the metal gate layer 217, and the top of the first interlayer dielectric layer 216 is flush with the top of the metal gate layer 217.

[0063] The top of the first interlayer dielectric layer 216 is flush with the top of the metal gate layer 217, which improves the flatness of the top surface of the second device.

[0064] In this embodiment, the metal gate layer 217 is flush with the top of the top gate layer 210. Therefore, the top of the first interlayer dielectric layer 216 is flush with the top of the top gate layer 210 and the top of the metal gate layer 217, resulting in a high degree of flatness on the top surface of the first interlayer dielectric layer 216.

[0065] Since the contact resistance of the polysilicon gate layer 212 in the first device region 200A is relatively large, a metal silicide layer 220 needs to be formed on the top of the polysilicon gate layer 212 to reduce the contact resistance. At the same time, the metal silicide layer 220 serves as an external terminal of the polysilicon gate layer 212 and is used to achieve electrical connection with the gate plug formed on the top of the polysilicon gate layer 212.

[0066] In this embodiment, the material of the metal silicide layer 220 includes one or more of nickel silicon compound, cobalt silicon compound, and titanium silicon compound. Nickel silicon compound, cobalt silicon compound, and titanium silicon compound have high conductivity, which can reduce the contact resistance between the gate plug 221 and the polysilicon gate layer 212.

[0067] The second interlayer dielectric layer 230 serves as an isolation layer for the gate plug 221 that penetrates the second interlayer dielectric layer 230.

[0068] In this embodiment, the second interlayer dielectric layer 230 is in contact with the first interlayer dielectric layer 216.

[0069] It should be noted that the thickness of the second interlayer dielectric layer 230 should not be too large or too small. If the thickness of the second interlayer dielectric layer 230 is too large, it increases the difficulty of filling the conductive material in the gate contact hole during the formation process of the gate plug 221, thereby affecting the conductivity of the gate plug 221. If the thickness of the second interlayer dielectric layer 230 is too small, it is easy to result in the effective height of the gate plug 221 formed in the second interlayer dielectric layer 230 being too small, thereby affecting the conductivity of the gate plug 221. Therefore, in this embodiment, the thickness of the second interlayer dielectric layer 230 is 800 angstroms to 1800 angstroms.

[0070] In this embodiment, the material of the second interlayer dielectric layer 230 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. Silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbonitride are all insulating materials that can isolate the gate plug 221.

[0071] In this embodiment, the second interlayer dielectric layer 230 also covers the top of the metal gate layer 217.

[0072] The gate plug 221 in the first device region 200A is used to realize the electrical connection between the polysilicon gate layer 212 and external circuits or other interconnect structures.

[0073] In this embodiment, the gate plug 221 is also located in the second device region 200B and penetrates the second interlayer dielectric layer 230 located on top of the metal gate layer 217, and the bottom of the gate plug 221 is connected to the top of the metal gate layer 217.

[0074] The gate plug 221 in the second device region 200B is used to realize the electrical connection between the metal gate layer 217 and external circuits or other interconnect structures.

[0075] In this embodiment, the gate plug 221 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the gate plug 221, thereby reducing power consumption. In other embodiments, the conductive plug can also be made of cobalt or ruthenium.

[0076] In this embodiment, the gate plug 221 is also located in the second device region 200B and penetrates the second interlayer dielectric layer 230 located on top of the metal gate layer 217, and the bottom of the gate plug 221 is connected to the top of the metal gate layer 217.

[0077] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0078] Figures 8 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0079] refer to Figures 8 to 11 A substrate is provided, the substrate including a first device region 100A for forming a first device, and a polysilicon gate layer 112 is formed on the substrate.

[0080] The substrate provides the technological basis for the formation of the semiconductor structure.

[0081] In this embodiment, the substrate is used to form a planar transistor; therefore, the substrate includes a substrate 100. In other embodiments, when the substrate is used to form a fin field-effect transistor (FinFET), the substrate also includes fins protruding from the substrate.

[0082] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0083] In this embodiment, the method for forming the semiconductor structure further includes forming an isolation layer 102 in the substrate 100, wherein the top of the isolation layer 102 is flush with the top of the substrate 100. In other embodiments, depending on device requirements and process requirements, the top of the isolation layer and the top of the substrate may not be flush.

[0084] The isolation layer 102 is used to isolate adjacent devices. The material of the isolation layer 102 may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.

[0085] In this embodiment, the substrate includes a first device region 100A for forming a first device and a second device region 100B for forming a second device, wherein the channel length of the second device is less than the channel length of the first device. As an example, the operating voltage of the first device is greater than the operating voltage of the second device, such that the channel length of the first device is greater than the channel length of the second device.

[0086] In this embodiment, the first device includes one or both of medium-voltage and high-voltage devices, and the second device is a low-voltage device. The operating voltages of the low-voltage, medium-voltage, and high-voltage devices increase sequentially. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0087] like Figure 11 As shown, in the step of providing the substrate, the polysilicon gate layer 112 located in the first device region 100A includes a bottom gate layer 109 and a plurality of top gate layers 110 protruding on the bottom gate layer 109, with adjacent top gate layers 110 and bottom gate layers 109 forming a groove 107.

[0088] Since the channel length of the first device is relatively long, in the polysilicon gate layer 112 in the first device region 100A, the adjacent top gate layer 110 and bottom gate layer 109 form a groove 107. The linewidth dimension of the top gate layer 110 and the spacing between adjacent top gate layers 110 (i.e., the linewidth dimension of the groove 107) are both small, thereby reducing the probability of dishing defects occurring at the top of the polysilicon gate layer 112 in the planarization process used to form the semiconductor structure.

[0089] In this embodiment, the polysilicon gate layer 112 is formed on the substrate 100 of the first device region 100A and the second device region 100B, respectively.

[0090] The polysilicon gate layer 112 in the second device region 100B is used to occupy space for the subsequent formation of a metal gate layer.

[0091] Therefore, in this embodiment, a high-k gate dielectric layer 103 and a metal barrier layer 104 located on the high-k gate dielectric layer 103 are also formed between the polysilicon gate layer 112 and the substrate.

[0092] The high-k gate dielectric layer 103 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 103 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 103 is HfO2.

[0093] The metal barrier layer 104 is used to isolate the high-k gate dielectric layer 103 and the subsequently formed metal gate layer to protect the high-k gate dielectric layer 103. In addition, the metal barrier layer 104 is also used to prevent easily diffusing ions (e.g., Al ions) in the metal gate layer from diffusing into the high-k gate dielectric layer 103.

[0094] Specifically, the material of the metal barrier layer 104 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). As an example, the material of the metal barrier layer 104 is titanium nitride.

[0095] In this embodiment, by forming a high-k gate dielectric layer 103 and a metal barrier layer 104 on the substrate 100 of the first device region 100A and the second device region 100B, it is beneficial to simplify the process steps and reduce the process complexity.

[0096] refer to Figure 11 In the step of providing the substrate, a gate hard mask layer 111 is formed on the top of the top gate layer 110, and the gate hard mask layer 111 also extends to cover the bottom and sidewalls of the recess 107.

[0097] The gate hard mask layer 111 is used as an etching mask for forming the polysilicon gate layer 112. At the same time, in the subsequent process of forming the first interlayer dielectric layer, the top of the gate hard mask layer 111 is also used as a stop position for planarization, thereby reducing the probability of the top of the polysilicon gate layer 112 having a depression defect and the over-grinding of the top of the polysilicon gate layer 112 during the planarization process.

[0098] In this embodiment, the gate hard mask layer 111 fills the groove 107. In other embodiments, depending on the depth of the groove and the thickness of the gate hard mask layer, the gate hard mask layer may also be located at the bottom and sidewalls of the groove, and a first interlayer dielectric layer is formed in the remaining space of the groove.

[0099] Combination Figures 8 to 11 The steps for forming the polysilicon gate layer 112 and the gate hard mask layer 111 are described in detail.

[0100] refer to Figure 8 A polycrystalline silicon gate material layer 105 is formed on the substrate.

[0101] The polysilicon material layer 105 is used to prepare for the formation of a plurality of polysilicon gate layers 112 on the substrate.

[0102] Accordingly, before forming the polysilicon gate material layer 105, a high-k gate dielectric layer 103 covering the substrate and a metal barrier layer 104 covering the high-k gate dielectric layer 103 are formed on the substrate.

[0103] refer to Figure 9 A groove 107 is formed in the polysilicon gate material layer 105 of the first device region 100A, the groove 107 being located in the polysilicon gate material layer 105 of a certain thickness.

[0104] By forming the groove 107, the polysilicon gate layer 112 subsequently formed in the first device region 100A includes a bottom gate layer 109 and a plurality of top gate layers 110 protruding from the bottom gate layer 109. That is, the remaining polysilicon gate material layer 105 at the bottom of the groove 107 is used to form the bottom gate layer 109, and a portion of the polysilicon material layer 105 outside the groove 107 is used to form the top gate layer 110.

[0105] Specifically, before forming the groove 107, the method further includes forming a patterned layer 106 on the polysilicon gate material layer 105, wherein the patterned layer 106 exposes a portion of the top of the polysilicon gate material layer 105.

[0106] The pattern layer 106 serves as an etching mask for forming the groove 107.

[0107] In this embodiment, the material of the pattern layer 106 includes photoresist.

[0108] In this embodiment, the step of forming the groove 107 includes: using the patterned layer 106 as a mask, removing a portion of the polysilicon gate material layer 105 exposed by the patterned layer 106.

[0109] It should be noted that after forming the groove 107, the process also includes removing the graphic layer 106.

[0110] refer to Figure 10 A gate hard mask material layer 108 is formed on the polysilicon gate material layer 105, and the gate hard mask material layer 108 covers the top of the polysilicon gate material layer 105 and the bottom and sidewalls of the groove 107.

[0111] The gate hard mask material layer 108 provides the process basis for forming the gate hard mask layer 111.

[0112] In this embodiment, after the groove 107 is formed, a gate hard mask material layer 108 is formed so that after the polysilicon gate layer 112 located in the first device region 100A is subsequently formed, the gate hard mask layer 111 can cover the bottom and sidewalls of the groove 107.

[0113] refer to Figure 11 Remove a portion of the gate hard mask material layer 108 outside the groove 107 to form a gate hard mask layer 111 that covers the bottom and sidewalls of the groove 107 and extends to cover a portion of the top of the polysilicon gate material layer 108.

[0114] The gate hard mask layer 111 serves as a mask for subsequent etching of the polysilicon gate material layer 108.

[0115] Continue to refer to Figure 11 Remove the polysilicon gate material layer 108 exposed by the gate hard mask layer 111 to form a polysilicon gate layer 112.

[0116] The polysilicon gate material layer 108 is removed by using the gate hard mask layer 111 as an etching mask. In the same step, a polysilicon gate layer 112 is formed on the substrate 100 of the first device region 100A and the second device region 100B, which simplifies the process steps and saves process costs.

[0117] In this embodiment, after forming the polysilicon gate layer 112, the process further includes removing the exposed high-k gate dielectric layer 103 and metal barrier layer 104 from the polysilicon gate layer 112. Therefore, it is not necessary to separately form the high-k gate dielectric layer 103 and metal barrier layer 104 in the second device region 100B, simplifying the process steps.

[0118] refer to Figures 12 to 13 Sidewalls 115 are formed on the sidewalls of the polysilicon gate layer 112 and the gate hard mask layer 111.

[0119] The sidewall 115 is used to protect the sidewall of the polysilicon gate layer 112. At the same time, the sidewall 115 also covers the sidewall of the gate hard mask layer 111. In the subsequent planarization process with the top of the gate hard mask layer 111 in the groove 107 as the stop position, the sidewall 115 in the groove 107 also helps to reduce the probability of a depression defect occurring at the top of the top gate layer 110.

[0120] In this embodiment, the steps for forming the sidewall 115 include: as follows Figure 12 As shown, a sidewall material layer 113 is formed on top of the substrate, covering the top and sidewalls of the polysilicon gate layer 112, the bottom and sidewalls of the recess 107, and the top of the substrate where the polysilicon gate layer 112 is exposed; as Figure 13 As shown, the sidewall material layer 113 at the top of the polysilicon gate layer 112 and the top of the substrate exposed by the polysilicon gate layer 112, as well as the sidewall material layer 113 at the bottom of the groove 107, are removed, and the remaining sidewall material layer 113 serves as the sidewall 115.

[0121] The sidewall 115 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 115 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall 115 is a single-layer structure, and the material of the sidewall 115 is silicon nitride.

[0122] Continue to refer to Figure 13 In this embodiment, after forming the sidewall 115, the method for forming the semiconductor structure further includes: forming a first source / drain doped region 162 in the substrate on both sides of the polysilicon gate layer 112 of the first device region 100A; and forming a second source / drain doped region 161 in the substrate on both sides of the metal gate layer 217 of the second device region 100B.

[0123] The first source / drain doped region 162 is used as the source or drain region of the first device. When the first device is an NMOS device, the first source / drain doped region 162 is N-type doped; when the first device is a PMOS device, the first source / drain doped region 162 is P-type doped.

[0124] The second source / drain doped region 161 is used as the source or drain region of the second device. When the second device is an NMOS device, the second source / drain doped region 161 is N-type doped; when the second device is a PMOS device, the second source / drain doped region 161 is P-type doped.

[0125] In this embodiment, after forming the first source / drain doped region 162 and the second source / drain doped region 161, the semiconductor structure further includes a source / drain silicide layer 160 located on the top surface of the first source / drain doped region 162 and the second source / drain doped region 161.

[0126] The source / drain silicide layer 160 is used to reduce the contact resistance between the first source / drain doped region 162 and the second source / drain doped region 161 and the corresponding source / drain contact plugs. In this embodiment, the material of the source / drain silicide layer 160 can be a nickel silicon compound, a cobalt silicon compound, or a titanium silicon compound.

[0127] refer to Figure 14 A first interlayer dielectric layer 116 is formed on the substrate on the side of the polysilicon gate layer 112. The first interlayer dielectric layer 116 covers the sidewall of the polysilicon gate layer 112, and the top of the first interlayer dielectric layer 116 is flush with the top of the polysilicon gate layer 112.

[0128] The first interlayer dielectric layer 116 serves to isolate adjacent devices.

[0129] In this embodiment, the material of the first interlayer dielectric layer 116 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0130] In this embodiment, the step of forming a first interlayer dielectric layer 116 on the substrate on the side of the polysilicon gate layer 112 includes: forming a first interlayer dielectric material layer (not shown) covering the sidewall of the polysilicon gate layer 112 and the top of the gate hard mask layer 111 on the substrate on the side of the polysilicon gate layer 112; taking the top of the gate hard mask layer 111 in the groove 107 as the stop position, performing planarization on the first interlayer dielectric material layer above the top of the gate hard mask layer 111, and retaining the remaining first interlayer dielectric material layer covering the sidewall of the polysilicon gate layer 112 as the first interlayer dielectric layer 116.

[0131] It should be noted that, taking the top of the gate hard mask layer 111 in the groove 107 as the stop position, the first interlayer dielectric material layer above the top of the gate hard mask layer 111 is planarized, so that the top surface of the first interlayer dielectric layer 116 has a high flatness, which provides a good process basis for the subsequent formation of the cap dielectric layer.

[0132] It should also be noted that, in this embodiment, during the formation of the first interlayer dielectric layer 116, the gate hard mask layer 111 located on the top gate layer 110 is removed to expose the top of the top gate layer 110.

[0133] Specifically, the gate hard mask layer 111 located on the top gate layer 110 is removed to expose the top of the top gate layer 110, in preparation for the subsequent formation of a metal silicide layer on the top of the top gate layer 110 in the first device region 100A and the removal of the polysilicon gate layer 112 in the second device region 100B.

[0134] In this embodiment, during the formation of the first interlayer dielectric layer 116, the sidewall 115 located on the sidewall of the gate hard mask layer 111 is also removed.

[0135] Removing the sidewall 115 located on the sidewall of the gate hard mask layer 111 improves the top surface flatness of the first interlayer dielectric layer 116.

[0136] refer to Figure 15 Remove the polysilicon gate layer 112 of the second device region 100B, and form a gate opening (not shown) in the first interlayer dielectric layer 116; form a metal gate layer 117 in the gate opening.

[0137] The metal gate layer 117 serves as the metal gate structure for the second device region 100B. Since the channel length of the second device is relatively short, the short-channel effect is improved by employing a metal gate structure.

[0138] In this embodiment, the metal gate layer 117 is made of Al. In other embodiments, the metal gate layer may also be made of TiN, TaN, Ta, Ti, TiAl, W, TiSiN, or TiAlC.

[0139] refer to Figure 16 A capping dielectric layer 118 is formed on top of the first interlayer dielectric layer 116 and the polysilicon gate layer 112.

[0140] The cap dielectric layer 118 provides a process basis for the subsequent formation of a metal silicide layer on top of the top gate layer 110 in the first device region 100A.

[0141] In the subsequent process of forming a metal silicide layer on top of the top gate layer 110 in the first device region 100A, in order to avoid forming a metal silicide layer on top of the metal gate layer 117 in the second device region 100B, the capping dielectric layer 118 also covers the top of the metal gate layer 117.

[0142] The cap dielectric layer 118 is made of a dielectric material, thus ensuring compatibility with the subsequent process of forming a metal silicide layer.

[0143] In this embodiment, the material of the capping dielectric layer 118 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0144] Silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride are all insulating materials that can isolate adjacent devices and also protect the top of the metal gate layer 117 in the second device region 100B.

[0145] refer to Figure 17 In the first device region 100A, the cap dielectric layer 118 on top of the polysilicon gate layer 112 is etched, and an opening 119 is formed in the cap dielectric layer 118 to expose the polysilicon gate layer 112.

[0146] In this embodiment, only the capping dielectric layer 118 above the polysilicon gate layer 112 is etched away. That is, the remaining capping dielectric layer 118 still covers the top of the first interlayer dielectric layer 116 of the first device region 100A. Correspondingly, while completely removing the capping dielectric layer 118 above the polysilicon gate layer 112, the remaining capping dielectric layer 118 protects the top of the first interlayer dielectric layer 116 of the first device region 100A, reducing the probability of damage to the first interlayer dielectric layer 116 on the side of the polysilicon gate layer 112. This makes the top of the first interlayer dielectric layer 116 flush with the top of the polysilicon gate layer 112, which improves the flatness of the top surface of the first interlayer dielectric layer 116 and also reduces the probability of a height difference between the first interlayer dielectric layer 116 on the substrate of the first device region 100A and the first interlayer dielectric layer 116 on other regions of the substrate.

[0147] The opening 119 provides space for the subsequent formation of a metal silicide layer.

[0148] In this embodiment, the process of forming an opening 119 in the cap dielectric layer 118 to expose the polysilicon gate layer 112 in the first device region 100A includes a dry etching process.

[0149] The dry etching process has anisotropic etching characteristics, which provides a large etching selectivity for the polysilicon gate layer 112 and the gate hard mask layer 111. It can retain the polysilicon gate layer 112 and the gate hard mask layer 111 while removing the cap dielectric layer 118 on top of the polysilicon gate layer 112. At the same time, the dry etching is more directional and can obtain a fairly accurate pattern transformation, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the opening 119.

[0150] refer to Figure 18 A metal silicide layer 120 is formed on top of the polysilicon gate layer 112 exposed by the opening 119.

[0151] Since the contact resistance of the polysilicon gate layer 112 in the first device region 100A is relatively large, a metal silicide layer 120 needs to be formed on top of the polysilicon gate layer 112 to reduce the contact resistance. At the same time, the metal silicide layer 120 serves as an external terminal of the polysilicon gate layer 112, and is used to achieve electrical connection with the gate plug subsequently formed on top of the polysilicon gate layer 112.

[0152] In this embodiment, the material of the metal silicide layer 120 includes one or more of nickel silicon compound, cobalt silicon compound, and titanium silicon compound. Nickel silicon compound, cobalt silicon compound, and titanium silicon compound have high conductivity, which can reduce the contact resistance between the subsequently formed gate plug and the polysilicon gate layer 112.

[0153] refer to Figure 19 After forming the metal silicide layer 120, the remaining cap dielectric layer 118 is removed.

[0154] Removing the remaining cap dielectric layer 118 results in a high degree of flatness on the top surfaces of the first and second devices, providing a good process foundation for the subsequent formation of the second interlayer dielectric layer.

[0155] In this embodiment, the process for removing the remaining cap dielectric layer 118 includes a plasma dry etching process.

[0156] Specifically, in the process of removing the remaining cap dielectric layer 118, a plasma dry etching process is directly used to physically react with the remaining cap dielectric layer 118, thereby removing the remaining cap dielectric layer 118.

[0157] Because the material selected for the capping dielectric layer 118 has an etching selectivity ratio with the material selected for the first interlayer dielectric layer 116, the top of the first interlayer dielectric layer 116 is less damaged during the removal of the capping dielectric layer 118.

[0158] In this embodiment, the etching gas in the plasma dry etching process includes one or more of CF4, N2, CHF3, He, and Ar.

[0159] refer to Figure 20 After removing the remaining cap dielectric layer 118, a second interlayer dielectric layer 130 is formed on top of the first interlayer dielectric layer 116 and the polysilicon gate layer 112.

[0160] The second interlayer dielectric layer 130 provides the process basis for the subsequent formation of a gate plug that penetrates the second interlayer dielectric layer 130.

[0161] In this embodiment, the second interlayer dielectric layer 130 is in contact with the first interlayer dielectric layer 116.

[0162] It should be noted that the thickness of the second interlayer dielectric layer 130 should not be too large or too small. If the thickness of the second interlayer dielectric layer 130 is too large, it will increase the difficulty of filling the conductive material in the gate contact hole during the subsequent formation of the gate plug, thereby affecting the conductivity of the gate plug. If the thickness of the second interlayer dielectric layer 130 is too small, it will easily lead to the effective height of the gate plug formed in the second interlayer dielectric layer 130 being too small, thereby affecting the conductivity of the gate plug. Therefore, in this embodiment, the thickness of the second interlayer dielectric layer 130 is 800 angstroms to 1800 angstroms.

[0163] In this embodiment, the material of the second interlayer dielectric layer 130 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0164] Silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride are all insulating materials that can isolate the gate plugs formed subsequently.

[0165] refer to Figure 21 In the first device region 100A, a gate plug 121 is formed on top of the polysilicon gate layer 112, penetrating the second interlayer dielectric layer 130, and the gate plug 121 is connected to the metal silicide layer 120.

[0166] The gate plug 221 in the first device region 200A is used to realize the electrical connection between the polysilicon gate layer 212 and external circuits or other interconnect structures.

[0167] In this embodiment, in the step of forming a gate plug 121 penetrating the second interlayer dielectric layer 130 on the top of the polysilicon gate layer 112, the gate plug 121 is also formed in the second device region 100B. The gate plug 121 in the second device region 100B penetrates the second interlayer dielectric layer 130 on the top of the metal gate layer 117, and the bottom of the gate plug 121 is connected to the top of the metal gate layer 117.

[0168] The gate plug 121 in the second device region 100B is used to realize the electrical connection between the metal gate layer 117 and external circuits or other interconnect structures.

[0169] In this embodiment, the step of forming the gate plug 121 includes: etching away the metal silicide layer 120 and the second interlayer dielectric layer 130 on top of the metal gate layer 117 to form a gate contact hole (not shown) exposing the top of the metal silicide layer 120 and the metal gate layer 117; forming a gate plug material layer (not shown) in the gate contact hole; and planarizing the gate plug material layer above the top of the second interlayer dielectric layer 130, with the top of the second interlayer dielectric layer 130 as the stop position, and the remaining gate plug material layer serving as the gate plug 121.

[0170] In this embodiment, since the top surface flatness of the second interlayer dielectric layer 130 is relatively high, the probability of defocusing during the photolithography process is reduced when forming the gate plug 121. Furthermore, during the planarization of the gate plug material layer above the top of the second interlayer dielectric layer 130, the probability of the gate plug material layer remaining on the top of the second interlayer dielectric layer 130 is reduced, thereby improving the performance of the semiconductor structure.

[0171] In this embodiment, the gate plug 121 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the gate plug 121, thereby reducing power consumption. In other embodiments, the conductive plug may also be made of cobalt or ruthenium.

[0172] It should be noted that the step of forming the gate plug 121 further includes: forming a source-drain interconnect layer (not shown) on top of the source-drain doped layer (not shown). A detailed description of the source-drain interconnect layer will not be repeated here.

[0173] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first device region for forming a first device and a second device region for forming a second device; A polysilicon gate layer is located on the substrate of the first device region; A metal gate layer is located on the substrate of the second device region; The first interlayer dielectric layer is located on the substrate on the side of the polysilicon gate layer. The first interlayer dielectric layer covers the sidewall of the polysilicon gate layer, and the top of the first interlayer dielectric layer is flush with the top of the polysilicon gate layer. The first interlayer dielectric layer also covers the sidewall of the metal gate layer, and the top of the first interlayer dielectric layer is flush with the top of the metal gate layer. A metal silicide layer is located on the polysilicon gate layer in the first device region; The second interlayer dielectric layer is located on top of the first interlayer dielectric layer and the polysilicon gate layer. The second interlayer dielectric layer covers the metal silicide layer and also covers the top of the metal gate layer. A gate plug is located in the first device region and the second device region, and penetrates the second interlayer dielectric layer located on top of the polysilicon gate layer. The gate plug is connected to the metal silicide layer and penetrates the second interlayer dielectric layer located on top of the metal gate layer. The bottom of the gate plug is connected to the top of the metal gate layer. The step of forming the metal silicide layer includes: forming a capping dielectric layer on top of the first interlayer dielectric layer and the polysilicon gate layer; etching only the capping dielectric layer on top of the polysilicon gate layer in the first device region, forming an opening in the capping dielectric layer that exposes the polysilicon gate layer; forming a metal silicide layer on top of the polysilicon gate layer exposed by the opening; and removing the remaining capping dielectric layer after forming the metal silicide layer.

2. The semiconductor structure as described in claim 1, characterized in that, The polysilicon gate layer located in the first device region includes a bottom gate layer and a plurality of top gate layers protruding from the bottom gate layer, with adjacent top gate layers and bottom gate layers forming a groove; The top of the first interlayer dielectric layer is flush with the top of the top gate layer.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes a gate hard mask layer located in the groove.

4. The semiconductor structure as described in claim 1, characterized in that, The channel length of the second device is less than that of the first device.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: sidewalls located on the sidewalls of the polysilicon gate layer and the metal gate layer.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a high-k gate dielectric layer and a metal barrier layer located on the high-k gate dielectric layer. The stacked structure formed by the high-k gate dielectric layer and the metal barrier layer is located between the polysilicon gate layer and the substrate in the first device region and between the metal gate layer and the substrate in the second device region.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the metal gate layer includes one or more of TiN, TaN, Ta, Ti, W, TiAl, Al, TiSiN, and TiAlC.

8. The semiconductor structure as described in claim 6, characterized in that, The material of the high-k gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and Al2O3.

9. The semiconductor structure as described in claim 6, characterized in that, The material of the metal barrier layer includes one or both of titanium nitride and silicon-doped titanium nitride.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the metal silicide layer includes one or more of nickel silicon compounds, cobalt silicon compounds, and titanium silicon compounds.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region for forming a first device and a second device region for forming a second device, and a polysilicon gate layer is formed on the substrate; A first interlayer dielectric layer is formed on the substrate on the side of the polysilicon gate layer. The first interlayer dielectric layer covers the sidewall of the polysilicon gate layer, and the top of the first interlayer dielectric layer is flush with the top of the polysilicon gate layer. Remove the polysilicon gate layer of the second device region and form a gate opening in the first interlayer dielectric layer; A metal gate layer is formed in the gate opening; A capping dielectric layer is formed on top of the first interlayer dielectric layer and the polysilicon gate layer, and the capping dielectric layer also covers the top of the metal gate layer; In the first device region, only the capping dielectric layer on top of the polysilicon gate layer is etched to form an opening in the capping dielectric layer that exposes the polysilicon gate layer. A metal silicide layer is formed on top of the polysilicon gate layer exposed by the opening; After the metal silicide layer is formed, the remaining cap dielectric layer is removed; After removing the remaining cap dielectric layer, a second interlayer dielectric layer is formed on top of the first interlayer dielectric layer and the polysilicon gate layer; In the first device region, a gate plug is formed on top of the polysilicon gate layer, penetrating the second interlayer dielectric layer. The gate plug is connected to the metal silicide layer. The gate plug is formed in the second device region, penetrating the second interlayer dielectric layer on top of the metal gate layer. The bottom of the gate plug is connected to the top of the metal gate layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the polysilicon gate layer located in the first device region includes a bottom gate layer and a plurality of top gate layers protruding on the bottom gate layer, with adjacent top gate layers and bottom gate layers forming a groove.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, a gate hard mask layer is formed on top of the top gate layer, and the gate hard mask layer also extends to cover the bottom and sidewalls of the recess; During the formation of the first interlayer dielectric layer, the gate hard mask layer located on the top gate layer is removed to expose the top of the top gate layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming a first interlayer dielectric layer on a substrate on the side of the polysilicon gate layer includes: forming a first interlayer dielectric material layer on the substrate on the side of the polysilicon gate layer that covers the sidewall of the polysilicon gate layer and the top of the gate hard mask layer; taking the top of the gate hard mask layer in the groove as a stop position, performing planarization on the first interlayer dielectric material layer above the top of the gate hard mask layer, and retaining the remaining first interlayer dielectric material layer covering the sidewall of the polysilicon gate layer as the first interlayer dielectric layer.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The steps of forming the polysilicon gate layer and the gate hard mask layer include: forming a polysilicon gate material layer on the substrate; A groove is formed in the polysilicon gate material layer of the first device region, the groove being located in a portion of the thickness of the polysilicon gate material layer; A gate hard mask material layer is formed on the polysilicon gate material layer, the gate hard mask material layer covering the top of the polysilicon gate material layer and the bottom and sidewalls of the groove; Remove a portion of the gate hard mask material layer outside the groove to form a gate hard mask layer that covers the bottom and sidewalls of the groove and extends to cover a portion of the top of the polysilicon gate material layer; Remove the polysilicon gate material layer exposed by the gate hard mask layer to form a polysilicon gate layer.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the polysilicon gate layer and before forming the first interlayer dielectric layer, the method further includes: forming sidewalls on the sidewalls of the polysilicon gate layer and the gate hard mask layer; In the step of forming the first interlayer dielectric layer, the sidewalls of the gate hard mask layer sidewalls are also removed.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the channel length of the second device is less than the channel length of the first device.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, a high-k gate dielectric layer and a metal barrier layer located on the high-k gate dielectric layer are further formed between the polysilicon gate layer and the substrate.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, After the metal silicide layer is formed, the process for removing the remaining capping dielectric layer includes a plasma dry etching process.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the first device region, the process of forming an opening in the cap dielectric layer that exposes the polysilicon gate layer includes a dry etching process.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the capping dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

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