Signal processing system and signal processing method

Abstract

Embodiments of the present application provide a signal processing system and a signal processing method. The system comprises a first interpolation filtering module and an up-conversion module. The first interpolation filtering module is configured to perform k times interpolation and anti-aliasing filtering on a baseband I signal and a baseband Q signal respectively, to obtain k parallel filtered I signals and k parallel filtered Q signals. The processing clock rate of the k times interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal. The up-conversion module is configured to perform up-conversion on the k parallel filtered I signals and the k parallel filtered Q signals, and output k intermediate frequency real signals. The system realizes wideband signal high-speed interpolation, high-speed anti-aliasing filtering and high-speed up-conversion based on the existing FPGA chip capability.

Description

[Technical Field]

[0001] This application relates to the field of signal generation technology in the field of wireless communication, and in particular to a signal processing system and signal processing method. [Background Technology]

[0002] The conventional interpolation upmixing process in the existing technology includes: the baseband IQ modulation signal is first interpolated to become a high sampling rate IQ modulation signal, the image frequency component is filtered out by anti-aliasing filter, the filtered baseband signal is upmixed, and one intermediate frequency real signal is output after upmixing. The intermediate frequency real signal after upmixing is converted from serial to parallel to form 8 parallel data, which is sent to the high-speed DA for digital-to-analog conversion through a high-speed bus.

[0003] In certain specific application scenarios, it is necessary to further interpolate, anti-aliasing filter and upmix the high-speed sampled broadband signal. However, the sampling rate of the broadband signal after interpolation is much higher than the current processing capability of FPGA. Therefore, the interpolation and upmixing of broadband signals cannot be performed based on the current processing capability of FPGA. [Summary of the Invention]

[0004] This application provides a signal processing system and method to achieve high-speed interpolation, high-speed anti-aliasing filtering, and high-speed up-conversion of broadband signals based on existing PFGA processing capabilities.

[0005] In a first aspect, this application provides a signal processing system, including a first interpolation filtering module and an up-conversion module. The first interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the baseband I signal and the baseband Q signal respectively, to obtain k parallel filtered I signals and k parallel filtered Q signals. The clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4. The up-conversion module is used to up-convert the k parallel filtered I signals and the k parallel filtered Q signals to output k intermediate frequency real signals.

[0006] The first benefit is that it enables high-speed interpolation of broadband signals, high-speed anti-aliasing filtering, and high-speed up-conversion based on the capabilities of existing FPGA chips.

[0007] In one possible implementation, the first interpolation filtering module includes two identical interpolation filtering units, each comprising k parallel sub-filters. The processing clock rate of each sub-filter is equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients. The step of performing k-fold interpolation and anti-aliasing filtering on the baseband I signal and the baseband Q signal respectively includes: the first interpolation filtering unit generating k parallel baseband I signals from the baseband I signal, and then convolving the i-th baseband I signal with the filtering coefficients of its i-th sub-filter to achieve anti-aliasing filtering of the i-th baseband I signal, where i takes values ​​of 1, 2, ..., k; the second interpolation filtering unit generating k parallel baseband Q signals from the baseband Q signal, and then convolving the i-th baseband Q signal with the filtering coefficients of its i-th sub-filter to achieve anti-aliasing filtering of the i-th baseband Q signal, where i takes values ​​of 1, 2, ..., k.

[0008] In one possible implementation, the method for generating the filter coefficients of the k sub-filters of the interpolation filter unit includes: based on the sampling rate f of the baseband I signal and the baseband Q signal. s Signal width 2B, interpolation factor k, sampling rate f after interpolation s ′=k*f s An anti-aliasing filter h = {b(0), b(1), b(2), ..., b(L)} is generated, where b(0), b(1), b(2), ..., b(L) are the coefficients of the anti-aliasing filter, and the coefficients of the anti-aliasing filter satisfy the sampling rate f = f s ′, passband frequency f pass ≥B, passband cutoff frequency B <f stop ≤f s -B, the order L of the anti-aliasing filter is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; the anti-aliasing filter h={b(0),b(1),b(2)…...b(L)} is divided into k equal-length sub-filters, and the filter coefficients of each sub-filter are as follows: h i-1 = {b(i-1), b(1*i+i-1), b(2*i+i-1), ..., b(L-1)}, where i takes the values ​​1, 2, ..., k, and the processing clock of each sub-filter is... The order L′ = L / k, where L is the order of the anti-aliasing filter.

[0009] In one possible implementation, the upconversion module includes a signal sorting unit and a signal processing unit, upconverting the k parallel filtered I signals and the k parallel filtered Q signals. This includes: the signal sorting unit acquiring the odd-numbered filtered I signals from the k parallel filtered I signals, where the odd-numbered filtered I signals include the m-th filtered I signal, where m takes values ​​of 1, 3, ..., k-1; and acquiring the even-numbered filtered Q signals from the k parallel filtered Q signals. The even-numbered filtered Q signals include the nth filtered Q signal, where n takes the value 2, 4, ..., k. The odd-numbered filtered I signals and the even-numbered filtered Q signals are combined in their original sequence to form k parallel filtered signals. The signal calculation unit divides the parallel k filtered signals into groups of eight consecutive filtered signals. In each group, the first, fourth, fifth, and eighth filtered signals are passed through D flip-flops, and the second, third, sixth, and seventh filtered signals are passed through inverting flip-flops to obtain k intermediate frequency real signals.

[0010] Secondly, this application provides a signal processing system, including a signal preprocessing module and a second interpolation filtering module. The signal preprocessing module is used to sort and preprocess baseband I signals and baseband Q signals to obtain k parallel preprocessed signals. The second interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals to output k intermediate frequency real signals. The clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signals and baseband Q signals, and k is an integer multiple of 4.

[0011] In one possible implementation, the signal preprocessing module includes a signal sorting unit and a signal processing unit. The step of sorting and preprocessing the baseband I signal and the baseband Q signal includes: the signal sorting unit dividing the baseband I signal into f parallel baseband I signals and the baseband Q signal into f parallel baseband Q signals, wherein the f parallel baseband I signals and the f parallel baseband Q signals constitute k parallel initial signals, wherein the odd-numbered initial signals in the k parallel initial signals are the baseband I signals and the even-numbered initial signals are the baseband Q signals, and f = k / 2; the signal processing unit groups the k parallel initial signals into groups of eight consecutive initial signals, and the first, fourth, fifth, and eighth initial signals in each group are passed through D flip-flops, and the second, third, sixth, and seventh initial signals in each group are passed through inverting flip-flops to obtain k parallel preprocessed signals.

[0012] In one possible implementation, the second interpolation filtering module includes k parallel sub-filters, each of which has a processing clock rate equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients. The step of performing k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals includes: the second interpolation filtering module performing convolution operation on the i-th preprocessed signal and the filtering coefficients of its i-th sub-filter to achieve anti-aliasing filtering on the i-th preprocessed signal, where i takes the values ​​1, 2, ..., k.

[0013] In one possible implementation, the method for generating the filter coefficients of the k sub-filters of the second interpolation filtering module includes: based on the sampling rate f of the baseband I signal and the baseband Q signal... s Signal width 2B, interpolation factor k, sampling rate f after interpolation s ′=k*f s An anti-aliasing filter h = {b(0), b(1), b(2), ..., b(L)} is generated, where b(0), b(1), b(2), ..., b(L) are the coefficients of the anti-aliasing filter, and the coefficients of the anti-aliasing filter satisfy the sampling rate f = f s ′, passband frequency f pass ≥B, passband cutoff frequency B <f stop ≤f s -B, the order L of the anti-aliasing filter is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; the anti-aliasing filter h={b(0),b(1),b(2)……b(L)} is divided into k sub-filters of equal length, and the filter coefficients of each sub-filter are as follows: h i-1 = {b(i-1), b(1*i+i-1), b(2*i+i-1), ..., b(L-1)}, where i takes the values ​​1, 2, ..., k, and the processing clock of each sub-filter is... The order L′ = L / k, where L is the order of the anti-aliasing filter.

[0014] Thirdly, embodiments of this application provide a signal processing method, comprising: performing k-fold interpolation and anti-aliasing filtering on baseband I signals and baseband Q signals respectively to obtain k parallel filtered I signals and k parallel filtered Q signals, wherein the processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signals and baseband Q signals, and k is an integer multiple of 4; up-converting the k parallel filtered I signals and the k parallel filtered Q signals to output k intermediate frequency real signals.

[0015] Fourthly, embodiments of this application provide a signal processing method, comprising: sorting and preprocessing baseband I signals and baseband Q signals to obtain k parallel preprocessed signals; performing k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals to output k intermediate frequency real signals; wherein the clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signals and baseband Q signals, and k is an integer multiple of 4.

[0016] It should be understood that the second to fourth aspects of the embodiments of this application are consistent with the technical solutions of the first aspect of the embodiments of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be described again. [Attached Image Description]

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a conventional interpolation upmixing process provided for an embodiment of this application;

[0019] Figure 2 This application provides a structural diagram of a signal processing system according to an embodiment of the present application.

[0020] Figure 3a A block diagram illustrating the principle of an inverse polynomial interpolation anti-aliasing filter provided in this application embodiment;

[0021] Figure 3b A schematic diagram illustrating the filtering operation principle of an interpolation filtering unit provided in an embodiment of this application;

[0022] Figure 4a A waveform diagram of the pre-interpolation monotone signal provided in an embodiment of this application;

[0023] Figure 4b This is a schematic diagram of the spectrum of the pre-interpolation single-tone IQ signal provided in an embodiment of this application;

[0024] Figure 4c This is a schematic diagram of the waveform after interpolation and filtering of a single-tone signal provided in an embodiment of this application;

[0025] Figure 4d This is a schematic diagram of the spectrum of a single-tone signal after interpolation and filtering, provided in an embodiment of this application.

[0026] Figure 5 A schematic diagram illustrating the principle of frequency conversion operation of an upconversion module provided in an embodiment of this application;

[0027] Figure 6 This is a structural diagram of another signal processing system provided in an embodiment of this application;

[0028] Figure 7 This is a schematic diagram illustrating the operational principle of the signal processing system provided in an embodiment of this application;

[0029] Figure 8 This application provides a schematic diagram of the structure of an FPGA-implemented signal processing system according to an embodiment of the present application.

[0030] Figure 9 A schematic diagram illustrating the frequency amplitude and phase response of an anti-aliasing filter provided in an embodiment of this application;

[0031] Figure 10a This is a schematic diagram of the time-domain waveform of the baseband IQ signal before interpolation provided in an embodiment of this application.

[0032] Figure 10b This is a schematic diagram of the baseband IQ signal spectrum before interpolation provided in an embodiment of this application;

[0033] Figure 10c This is a schematic diagram of the time-domain waveform after anti-aliasing filtering based on inverse polynomial structure interpolation provided in an embodiment of this application;

[0034] Figure 10d This is a schematic diagram of the real signal spectrum after anti-aliasing filtering based on inverse polynomial structure interpolation provided in an embodiment of this application;

[0035] Figure 11 A schematic flowchart of a signal processing method provided in this application;

[0036] Figure 12 A flowchart illustrating another signal processing method provided in this application.

Detailed Implementation Methods

[0037] To better understand the technical solutions in this specification, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0038] It should be understood that the described embodiments are merely some, not all, of the embodiments in this specification. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without inventive effort are within the scope of protection of this specification.

[0039] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0040] Figure 1 This application provides a schematic diagram of a conventional interpolation upmixing process, as shown in the embodiments of this application. Figure 1 As shown, in existing related technologies, the conventional interpolation upmixing process is as follows: the baseband IQ modulation signal is first interpolated to become a high sampling rate IQ modulation signal. The image frequency component is filtered out by an anti-aliasing filter. The filtered baseband signal is then upmixed. After upmixing, one intermediate frequency real signal is output. The upmixed intermediate frequency real signal is then converted from serial to parallel to form 8 parallel data channels, which are sent to a high-speed DA converter for digital-to-analog conversion via a high-speed bus.

[0041] The anti-aliasing filter filters the interpolated signal data. Traditional anti-aliasing filters must have a processing speed greater than or equal to the data rate. When the original IQ baseband signal sampling rate is 240MHz and the symbol interpolation factor k=8, the decimated sampling rate is 1920MHz. The minimum processing speed of the anti-aliasing filter is 1920MHz, far exceeding the processing capabilities of current FPGAs, making it impossible to implement in an FPGA. Upmixing, when implemented in an FPGA, typically consists of a DDS and a complex multiplier. When the input high-speed sampled IQ data has a sampling rate of 1920MHz, the calculation clock of the DDS and complex multiplier must also reach a corresponding 1920MHz, which is clearly impractical.

[0042] Therefore, in certain specific application scenarios, it is necessary to further interpolate, anti-aliasing filter and upmix the high-speed sampled signal. However, the sampling rate after interpolation is much higher than the current processing capability of FPGA, and signal processing cannot be performed under existing technology.

[0043] Based on the above problems, this application provides a signal processing system and signal processing method to achieve high-speed interpolation of broadband signals, high-speed anti-aliasing filtering, and high-speed up-conversion on existing mainstream FPGA chips.

[0044] Figure 2 A structural diagram of a signal processing system provided in an embodiment of this application is shown below. Figure 2As shown, the signal processing system may include: a first interpolation filtering module and an up-conversion module. The first interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the baseband I signal and the baseband Q signal respectively, to obtain k parallel filtered I signals and k parallel filtered Q signals. The processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4. The up-conversion module is used to up-convert the k parallel filtered I signals and the k parallel filtered Q signals to output k intermediate frequency real signals.

[0045] It should be noted that the first interpolation filtering module uses an inverse polynomial structure interpolation anti-aliasing filter to achieve interpolation and anti-aliasing filtering of baseband IQ data. After the I and Q signals are interpolated and anti-aliasing filtered by the first interpolation filtering module, k parallel samples are output, namely I′(n,i) (i=0,1,2,……,k-1) and Q'(n,i) (i=0,1,2,……,k-1). The up-conversion module is used to perform up-conversion, outputting 8 intermediate frequency real signals y(n,i) (i=0,1,2,……,k-1), where n is the number of the sample currently participating in the calculation.

[0046] The signal processing system provided in this application, which can be applied to existing mainstream FPGA chips for high-speed interpolation of broadband signals, high-speed anti-aliasing filtering, and high-speed up-conversion, can overcome the shortcomings of existing technologies, such as high resource consumption and computational processing requirements that are far higher than the processing capabilities of current mainstream FPGAs.

[0047] In some embodiments, the design idea of ​​the first interpolation filtering module is to design a filter bank, wherein the processing clock rate of each sub-filter in the filter bank is the sampling rate of the original IQ data before interpolation. While ensuring filtering performance, the processing clock rate is reduced, and the high-speed filtering operation is converted into a low-speed filter bank filtering operation.

[0048] For example, the first interpolation filtering module may include two identical interpolation filtering units. Each interpolation filtering unit includes k parallel sub-filters. The processing clock rate of each sub-filter is equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients. The step of performing k-fold interpolation and anti-aliasing filtering on the baseband I signal and the baseband Q signal may include: the first interpolation filtering unit generates k parallel baseband I signals from the baseband I signal, and then performs convolution operation on the i-th baseband I signal and the filtering coefficient of its i-th sub-filter to achieve anti-aliasing filtering on the i-th baseband I signal, where i takes the value 1, 2, ..., k; the second interpolation filtering unit generates k parallel baseband Q signals from the baseband Q signal, and then performs convolution operation on the i-th baseband Q signal and the filtering coefficient of its i-th sub-filter to achieve anti-aliasing filtering on the i-th baseband Q signal, where i takes the value 1, 2, ..., k.

[0049] Figure 3a A block diagram of an inverse polynomial interpolation anti-aliasing filter provided in this application embodiment is shown below. Figure 3a As shown, the input data x(n) is simultaneously fed into k sub-filters for convolution operations to achieve anti-aliasing filtering of the i-th preprocessed signal, forming k filtered data y(n,0), y(n,1), y(n,2), y(n,3), y(n,4), ..., y(n,k-1), which are the output results of x(n) after k interpolations and anti-aliasing filtering.

[0050] For example, the filtering calculations for y(n,0), y(n,1), y(n,2), y(n,3), y(n,4), ..., y(n,k-1) are as follows:

[0051] y(n,0)=h0*^x=b(0)*x(n)+b(k*1)*x(n-1)+…b(k*(L′-1)+0)*x(nL′+1);

[0052] y(n,1)=h1*^x=b(1)*x(n)+b(k*1+1)*x(n-1)+…b(k*(L′-1)+1)*x(nL′+1);

[0053] y(n,2)=h2*^x=b(2)*x(n)+b(k*1+2)*x(n-1)+…b(k*(L′-1)+2)*x(nL′+1);

[0054] y(n, k-1) = h k-1 *^x=b(k-1)*x(n)+b(k*1+k-1)*x(n-1)+…b(k*(L′-1)+k-1)*x(nL′+1).

[0055] In the above formulas, *^ represents the convolution symbol.

[0056] Figure 3b This is a schematic diagram illustrating the filtering operation principle of an interpolation filtering unit provided in an embodiment of this application, as shown below. Figure 3b As shown, two interpolation filter units with identical structure and coefficients are used to implement interpolation and anti-aliasing filtering for the I and Q signals. I′(n,0), I′(n,1), I′(n,2)...I′(n,k-1) are the k interpolated samples of the I-channel filter output when the current input is I(n). Q'(n,0), Q'(n,1), Q'(n,2),...Q'(n,k-1) are the k interpolated samples of the Q-channel filter output when the current input is Q(n).

[0057] For example, a single-tone signal can be used for verification. Let's assume the signal sampling rate is f before multi-stage filtering. s =240MHz, the center frequency of the baseband IQ signal is 40MHz, and there are 6 sampling points in one cycle of the single tone signal.

[0058] Let the interpolation factor k = 8, and the original anti-aliasing filter sampling rate f. s ′=8*f s =1920MHz, channel bandwidth B is 200MHz, passband frequency is set to f pass =110MHz, filter order 168 is selected, resulting in an FIR filter f stop =140MHz≤f s -B / 2 = 140MHz.

[0059] The anti-aliasing filter is divided into eight sub-filters, forming the first interpolation filtering module. Each sub-filter has an order of 168 / 8 = 21. The baseband IQ data of the single-tone signal is simultaneously fed into two interpolation filtering units, which output parallel eight-channel I and Q data after interpolation filtering. After parallel-to-serial conversion, the parallel data is converted into 1920MHz baseband IQ data, realizing the synchronous operation of data interpolation and anti-aliasing filtering. The FPGA operation clock remains constant at 240MHz.

[0060] Figure 4a A waveform diagram of the pre-interpolation monotone signal provided in an embodiment of this application; Figure 4b This is a schematic diagram of the spectrum of the pre-interpolation single-tone IQ signal provided in an embodiment of this application; Figure 4c This is a schematic diagram of the waveform after interpolation and filtering of a single-tone signal provided in an embodiment of this application; Figure 4d This is a schematic diagram of the spectrum of a single-tone signal after interpolation and filtering, provided in an embodiment of this application. According to... Figures 4a-4dAs can be seen, the baseband data passes through the first interpolation filter module. After being filtered by the first interpolation filter module, the data is interpolated, and out-of-band signals are suppressed. The proposed scheme simplifies the calculation while reducing the clock requirements for the calculation process.

[0061] Furthermore, the method for generating the filter coefficients of the k sub-filters of the interpolation filter unit includes: based on the sampling rate f of the baseband I signal and the baseband Q signal. s Signal width 2B, interpolation factor k, sampling rate f after interpolation s ′=k*f s An anti-aliasing filter h = {b(0), b(1), b(2), ..., b(L)} is generated, where b(0), b(1), b(2), ..., b(L) are the coefficients of the anti-aliasing filter, and the coefficients of the anti-aliasing filter satisfy the sampling rate f = f s ′, passband frequency f pass ≥B, passband cutoff frequency B < f stop ≤f s -B, the order L of the anti-aliasing filter is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; the anti-aliasing filter h = {b(0), b(1), b(2)......b(L)} is divided into k equal-length sub-filters, and the filter coefficients of each sub-filter are as follows: h i-1 = {b(i-1), b(1*i+i-1), b(2*i+i-1), ..., b(L-1)}, where i takes the values ​​1, 2, ..., k, and the processing clock of each sub-filter is... The order L′ = L / k, where L is the order of the anti-aliasing filter.

[0062] It should be noted that the original signal sampling rate is f. s The signal bandwidth is 2B, the interpolation factor is k, and the sampling rate after interpolation is f. s ′=k*f s Anti-aliasing filters can be designed using MATLAB Toolbox, with parameters set to satisfy the sampling rate f = f s ′, passband frequency f pass ≥B, passband cutoff frequency B < f stop ≤f s -B, the filter order is selected as an integer multiple of the decimation factor k, and the filter window type can be a Hamming window, resulting in filter h={b(0), b(1), b(2)......b(L)}, where L is an integer multiple of k.

[0063] For example, for a sampling rate f s′=1920MHz, channel bandwidth B is a 200MHz wideband signal, the filter window type is a Hamming window, and the passband frequency is set to f pass =110MHz, cutoff frequency f stop =140MHz, interpolation factor is 8, filter order is selected as 168 (an integer multiple of 8), where the passband normalized angular frequency is... Normalized cutoff angular frequency w in the passband stop =π*f stop / (f s ′ / 2)=π*140 / 960=0.1458π.

[0064] The anti-aliasing filter h = {b(0), b(1), b(2), ..., b(L)} is divided into k sub-filters of equal length, and the processing clock of each sub-filter is... This forms a filter bank, with each sub-filter having an order of L′ = L / k, where L is the original order of the anti-aliasing filter. The coefficients of each sub-filter are as follows:

[0065] h0={b(0), b(1*k), b(2*k)...b(Lk-1)};

[0066] h1={b(1), b(1*k+1), b(2*k+1)...b(Lk)};

[0067] h2={b(2), b(1*k+2), b(2*k+2)...b(L-k+1)};

[0068] h3={b(3), b(1*k+3), b(2*k+3)...b(L-k+2)};

[0069] h4={b(4), b(1*k+4), b(2*k+4)..., b(L-k+3)};

[0070] h5={b(5), b(1*k+5), b(2*k+5)..., b(L-k+4)};

[0071] h6={b(6), b(1*k+6), b(2*k+6)..., b(L-k+5)};

[0072] ...;

[0073] h k-1 ={b(k-1), b(1*k+k-1), b(2*k+k-1)..., b(L-1)}.

[0074] In some embodiments, the upconversion module includes a signal sorting unit and a signal processing unit. Upconverting the k parallel filtered I signals and the k parallel filtered Q signals may include: the signal sorting unit acquiring the odd-numbered filtered I signals from the k parallel filtered I signals, where the odd-numbered filtered I signals include the m-th filtered I signal, where m takes the value 1, 3, ..., k-1; and acquiring the even-numbered filtered Q signals from the k parallel filtered Q signals, where the even-numbered filtered Q signals include the n-th filtered Q signal, where n takes the value 2, 4, ..., k; combining the odd-numbered filtered I signals and the even-numbered filtered Q signals according to their original sequence number to form k parallel filtered signals; and the signal calculation unit grouping the parallel k filtered signals into sets of eight consecutive filtered signals, where the first, fourth, fifth, and eighth filtered signals in each set are processed by D flip-flops, and the second, third, sixth, and seventh filtered signals in each set are processed by inverting flip-flops to obtain k intermediate frequency real signals.

[0075] It should be noted that the upconversion module uses a mixer-free upmixer to achieve upconversion of the baseband I and Q signals. The upconversion module is suitable for upconverting baseband I and Q signals to f... s In the case of ′ / 4, we first simplify the DDS, and we can see that the center frequency of the two output channels of the DDS is f. c The single-tone signals are sin(2πf) c t) and cos(2πf c Discretize the time parameter t of the two single-tone signals: t = n * τ = n / f s ′,(τ is the time period of the discrete sample points, τ=1 / f s The two single-tone signals become:

[0076] Formula 1:

[0077] Formula 2:

[0078] Substituting n = 0, 1, 2, 3... into equations 1) and 2) yields:

[0079] Equation 3: sin(2πf) c t)={0,1,0,-1,0,1,0,-1,...};

[0080] Equation 4: cos(2πf) c t)={1,0,-1,0,1,0,-1,0,...};

[0081] As can be seen, sin(2πf) c After expansion, t) is a discrete sequence with a period of 0, 1, 0, -1, cos(2πf)c After expansion, t) is a discrete sequence with periods of 1, 0, -1, and 0. As shown in Equation 1, the upmixing operation of the signal is to multiply the input signal by the complex number of the local oscillator signal and take the real part, i.e., y = real((I + j * Q) * (cos(2πf)). c t)+j*sin(2πf c t)))=I*cos(2πf c t)-Q*sin(2πf c t).

[0082] Figure 5 This application provides a schematic diagram illustrating the principle of frequency conversion operation of an upconversion module, as shown in the embodiment. Figure 5 As shown, the upconversion module selects odd-numbered interpolated samples from the k interpolated samples output by the I-channel filter and even-numbered interpolated samples from the k interpolated samples output by the Q-channel filter, combining them into k parallel filtered signals. Then, each group consists of eight consecutive filtered signals. The first, fourth, fifth, and eighth filtered signals in each group are processed by D flip-flops, and the second, third, sixth, and seventh filtered signals in each group are processed by inverting flip-flops to obtain k intermediate frequency real signals.

[0083] It should be noted that the output of the upconversion module is obtained by sorting the input I and Q sequences. The odd-numbered parts of the k parallel data of the output y are the corresponding input baseband data I, and "+" and "-" alternate. The even-numbered parts of the k parallel data of the output y are the corresponding input baseband data Q, and "-" and "+" alternate. Overall, the output y is continuously phased with a period of {I′(n,j), -Q′(n,j+1), -I′(n,j+2), Q′(n,j+3)}.

[0084] Substituting the output results I′(n,0), I′(n,1), I′(n,2)……I′(n,k-1) after interpolation filtering of I-channel and the output results Q′(n,0), Q′(n,1), Q′(n,2),……、Q′(n,k-1) after interpolation filtering of Q-channel into equations 3) and 4), we get: y(n,0)=I′(n,0); y(n,1)=-Q′(n,1); y(n,2)=-I′(n,2); y(n,3)=Q′(n,3); y(n,4)=I′(n,4); y(n,5)=-Q′(n,5); y(n,6)=-I′(n,6); y(n,7)=Q′(n,7).

[0085] Therefore, in order to ensure the continuity of the output, when using a mixer-free upconverter, the interpolation factor k of the signal should be an integer multiple of 4. In this way, the upmixer does not need to use a complex multiplier for calculation, nor does it need to use DDS to generate sine and cosine mixing signals, saving resources. At the same time, the k channels of IQ data of the interpolation and anti-aliasing output can be calculated in parallel, reducing the calculation clock rate requirement.

[0086] Figure 6 A structural diagram of another signal processing system provided in this application embodiment is shown below. Figure 6 As shown, the signal processing system includes a signal preprocessing module and a second interpolation filtering module. The signal preprocessing module is used to sort and preprocess the baseband I signal and the baseband Q signal to obtain k parallel preprocessed signals. The second interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals to output k intermediate frequency real signals. The clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4.

[0087] In some embodiments, the signal preprocessing module includes a signal sorting unit and a signal processing unit. The step of sorting and preprocessing the baseband I signal and the baseband Q signal may include: the signal sorting unit dividing the baseband I signal into f parallel baseband I signals and the baseband Q signal into f parallel baseband Q signals, wherein the f parallel baseband I signals and the f parallel baseband Q signals constitute k parallel initial signals, wherein the odd-numbered initial signals in the k parallel initial signals are the baseband I signals and the even-numbered initial signals are the baseband Q signals, and f = k / 2; the signal processing unit groups the k parallel initial signals into groups of eight consecutive initial signals, and the first, fourth, fifth, and eighth initial signals in each group are passed through D flip-flops, and the second, third, sixth, and seventh initial signals in each group are passed through inverting flip-flops to obtain k parallel preprocessed signals.

[0088] Furthermore, the second interpolation filtering module includes k parallel sub-filters, each of which has a processing clock rate equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients. The step of performing k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals may include: the second interpolation filtering module performing convolution operation on the i-th preprocessed signal and the filtering coefficients of its i-th sub-filter to achieve anti-aliasing filtering on the i-th preprocessed signal, where i takes the values ​​1, 2, ..., k.

[0089] It should be noted that the output y of the mixer-free up-converter is obtained by sorting the input I and Q sequences.

[0090] A simplified calculation process involving interpolation, anti-aliasing filtering, and up-mixing of the I and Q baseband signals:

[0091] y(n, 0) = I′ (n，0) =h0*^I=h0*^(+I);

[0092] y(n,1)=-Q'(n,1)=-h1*^Q=h1*^(-Q);

[0093] y(n, 2) = -I′ (n，2) =-h2*^I=h2*^(-I);

[0094] y(n,3)=Q′(n,3)=h3*^Q=h3*^(+Q);

[0095] ...

[0096] y(n, k-4)=I′ (n，k-4) =h k-4 *^I=h k-4 *^(+I);

[0097] y(n,k-3)=-Q′(n,k-3)=-h k-3 *^Q=h k-3 *^(-Q);

[0098] y(n, k-2) = -I′ (n，k-2) =-h k-2 *^I=h k-2 *^(-I);

[0099] y(n, k-1) = Q'(n, k-1) = h k-1 *^Q=h k-1 *^(+Q).

[0100] Figure 7 This is a schematic diagram illustrating the operational principle of the signal processing system provided in the embodiments of this application, such as... Figure 7 As shown, the signal processing system consists of a k-channel sub-filter, a D flip-flop, and an inverting flip-flop, where h0, h1, ..., h k-1 The coefficients of the transfer functions of the k-way sub-filters are given, and the coefficient allocation method of each transfer function is the same as in the previous embodiment. "D" is a delay trigger, and "~" is an inverting trigger. The inputs of the first, third, fifth, and seventh odd-numbered sub-filters are I-channel input data I(n), and the inputs of the second, fourth, sixth, and eighth even-numbered sub-filters are Q-channel inputs Q(n).

[0101] It can be seen that only one signal preprocessing module and one second interpolation filtering module are needed to achieve the functions of signal interpolation, anti-aliasing filtering and up-conversion. The total filter order of the signal preprocessing module and the second interpolation filtering module has not changed compared with the original anti-aliasing filter. Compared with the existing technology system, it reduces one set of anti-aliasing filters, one DDS and one complex multiplier. More importantly, due to the use of parallel operation, there is no need to increase the processing clock, which greatly reduces the processing capability requirements of the FPGA.

[0102] Furthermore, the method for generating the filter coefficients of the k sub-filters of the second interpolation filtering module includes: based on the sampling rate f of the baseband I signal and the baseband Q signal. s Signal width 2B, interpolation factor k, sampling rate f after interpolation s ′=k*f s An anti-aliasing filter h = {b(0), b(1), b(2), ..., b(L)} is generated, where b(0), b(1), b(2), ..., b(L) are the coefficients of the anti-aliasing filter, and the coefficients of the anti-aliasing filter satisfy the sampling rate f = f s ′, passband frequency f pass ≥B, passband cutoff frequency B < f stop ≤f s -B, the order L of the anti-aliasing filter is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; the anti-aliasing filter h = {b(0), b(1), b(2)......b(L)} is divided into k equal-length sub-filters, and the filter coefficients of each sub-filter are as follows: h i-1 = {b(i-1), b(1*i+i-1), b(2*i+i-1), ..., b(L-1)}, where i takes the values ​​1, 2, ..., k, and the processing clock of each sub-filter is... The order L′ = L / k, where L is the order of the anti-aliasing filter.

[0103] It should be noted that the method for generating the filter coefficients of the k sub-filters is the same as that in the previous embodiment, and can be described in the previous embodiment, so it will not be repeated here.

[0104] Figure 8 This is a schematic diagram of the structure of an FPGA implementation of a signal processing system provided in an embodiment of this application, as shown below. Figure 8 As shown, the interpolation factor of the signal processing system is k, and the up-conversion center frequency is f. s ′ / 4 (where f) sb(kL′-1) are the signal sampling rate after interpolation (b′ / 4), b(0), b(1), b(2), ..., b(kL′-1) are the transmission coefficients of the anti-aliasing filter, and the order of the sub-filter of the anti-aliasing filter with inverse polynomial structure interpolation is L′, L′ = L / k, where L is the order of the anti-aliasing filter.

[0105] The following is an example: In a certain spaceborne broadband communication project, the high-speed DA clock is 1920MHz, the FPGA processing clock is 240MHz, the bandwidth is limited to 200MHz, and there are multiple signals in the band. One of the baseband signals has a symbol rate of 120Msps and a frequency deviation of 40MHz from 0. Since it is necessary to adopt a common design with other communication projects, the baseband signal sampling rate must be interpolated to 1920MHz with an interpolation factor of 8, and the signal center frequency must be up-mixed to 480MHz. Finally, the resulting 8 parallel intermediate frequency real signals are fed into the high-speed DA for digital-to-analog conversion.

[0106] The solution employs a signal processing system based on an inverse polynomial structure. First, an anti-aliasing filter is constructed with a passband frequency of 110MHz, an order of 168, and a haming window. Figure 9 This application provides a schematic diagram of the frequency amplitude response and phase response of an anti-aliasing filter. An anti-aliasing filter based on an inverse polynomial structure is constructed, with each sub-filter assigned corresponding coefficients. The baseband I and Q signals are passed through the constructed anti-aliasing filter. The signal, time-domain waveforms, and spectrum graphs before and after filtering are shown below. Figures 10a-10d As shown, where, Figure 10a This is a schematic diagram of the time-domain waveform of the baseband IQ signal I-channel before interpolation provided in an embodiment of this application. Figure 10b This is a schematic diagram of the baseband IQ signal spectrum before interpolation provided in an embodiment of this application; Figure 10c This is a schematic diagram of the time-domain waveform after anti-aliasing filtering based on inverse polynomial structure interpolation provided in an embodiment of this application; Figure 10d A schematic diagram of the real signal spectrum after anti-aliasing filtering based on inverse polynomial interpolation provided in an embodiment of this application.

[0107] The anti-aliasing filter uses a 240MHz clock. After passing through this anti-aliasing filter, the out-of-band image frequency component is suppressed, and eight parallel interpolated data channels y(n,0), y(n,1), y(n,2), y(n,3), y(n,4), y(n,5), y(n,6), and y(n,7) are output. The data bit width is 2B, the data rate of each channel is 240M*2B, and the total data rate is 1920M*2B. The data is transmitted to the DA converter via a high-speed bus for digital-to-analog conversion.

[0108] This application also provides a signal processing method. Figure 11A flowchart illustrating a signal processing method provided in this application is shown below. Figure 11 As shown, the signal processing method includes:

[0109] S101: The baseband I signal and the baseband Q signal are subjected to k times interpolation and anti-aliasing filtering respectively to obtain k parallel filtered I signals and k parallel filtered Q signals, wherein the processing clock rate of the k times interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4.

[0110] S102: Upconvert the k parallel filtered I signals and the k parallel filtered Q signals to output k intermediate frequency real signals.

[0111] Figure 11 The signal processing method provided in the illustrated embodiments can be used to perform this specification. Figure 2 The implementation principle and technical effects of the system embodiment shown can be further described in the relevant descriptions in the method embodiment.

[0112] This application also provides another signal processing method. Figure 12 A flowchart illustrating another signal processing method provided in this application is shown below. Figure 12 As shown, the signal processing method includes:

[0113] S201: Perform signal sorting and preprocessing on the baseband I signal and baseband Q signal to obtain k parallel preprocessed signals;

[0114] S202: Perform k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals to output k intermediate frequency real signals; wherein, the processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4.

[0115] Figure 12 The signal processing method provided in the illustrated embodiments can be used to perform this specification. Figure 6 The implementation principle and technical effects of the system embodiment shown can be further described in the relevant descriptions in the method embodiment.

[0116] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0117] In the description of the embodiments of the present invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0118] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this specification, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0119] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this specification includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which the embodiments of this specification pertain.

[0120] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0121] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0122] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0123] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0124] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A signal processing system, characterized in that, It includes a first interpolation filter module and an up-conversion module, wherein, The first interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the baseband I signal and the baseband Q signal respectively to obtain k parallel filtered I signals and k parallel filtered Q signals, wherein the processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4. The upconversion module is used to upconvert the k parallel filtered I signals and the k parallel filtered Q signals to output k intermediate frequency real signals. The first interpolation filtering module includes two identical interpolation filtering units, each interpolation filtering unit includes k parallel sub-filters, the processing clock rate of each sub-filter is equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter is provided with filtering coefficients; The method for generating the filter coefficients of the k sub-filters of the interpolation filter unit includes: Based on the sampling rates of the baseband I signal and the baseband Q signal Signal width 2B, interpolation factor k, sampling rate after interpolation Generate anti-aliasing filter ,in, The coefficients of the anti-aliasing filter satisfy the sampling rate... passband frequency passband cutoff frequency The order of the anti-aliasing filter The interpolation factor k is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; The anti-aliasing filter Divide into k sub-filters of equal length, and the filter coefficients of each sub-filter are as follows: The value of i is 1, 2, ..., k, where the processing clock of each sub-filter is... order , Let be the order of the anti-aliasing filter.

2. The system according to claim 1, characterized in that, The step of performing k-fold interpolation and anti-aliasing filtering on the baseband I signal and baseband Q signal respectively includes: The first interpolation filtering unit generates k parallel baseband I signals from the baseband I signal, and then performs convolution operation on the i-th baseband I signal and the filtering coefficient of its i-th sub-filter to achieve anti-aliasing filtering of the i-th baseband I signal. The value of i is 1, 2, ..., k. The second interpolation filtering unit generates k parallel baseband Q signals from the baseband Q signal, and then performs convolution operation on the i-th baseband Q signal and the filtering coefficient of its i-th sub-filter to achieve anti-aliasing filtering of the i-th baseband Q signal, where i takes the values ​​1, 2, ..., k.

3. The system according to claim 1, characterized in that, The upconversion module includes a signal sorting unit and a signal processing unit, which upconverts the k parallel filtered I signals and the k parallel filtered Q signals, including: The signal sorting unit acquires the odd-numbered filtered I signals from the k parallel filtered I signals, the odd-numbered filtered I signals including the m-th filtered I signal, where m takes the value 1, 3, ..., k-1; and acquires the even-numbered filtered Q signals from the k parallel filtered Q signals, the even-numbered filtered Q signals including the n-th filtered Q signal, where n takes the value 2, 4, ..., k; and combines the odd-numbered filtered I signals and the even-numbered filtered Q signals in their original sequence number order to form k parallel filtered signals. The signal processing unit divides the parallel k-channel filtered signals into groups of eight consecutive filtered signals. In each group, the first, fourth, fifth, and eighth filtered signals are processed by D flip-flops, and the second, third, sixth, and seventh filtered signals are processed by inverting flip-flops to obtain k-channel intermediate frequency real signals.

4. A signal processing system, characterized in that, It includes a signal preprocessing module and a second interpolation filtering module, wherein, The signal preprocessing module is used to sort and preprocess the baseband I signal and the baseband Q signal to obtain k parallel preprocessed signals. The second interpolation filtering module is used to perform k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals and output k intermediate frequency real signals; wherein, the processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4; The second interpolation filtering module includes k parallel sub-filters, each of which has a processing clock rate equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients. The method for generating the filter coefficients of the k sub-filters in the second interpolation filtering module includes: Based on the sampling rates of the baseband I signal and the baseband Q signal Given a signal width of 2 bytes, an interpolation factor of k, and a post-interpolation sampling rate, generate an anti-aliasing filter. ,in, The coefficients of the anti-aliasing filter satisfy the sampling rate... passband frequency passband cutoff frequency The order of the anti-aliasing filter The interpolation factor k is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; The anti-aliasing filter Divide into k sub-filters of equal length, and the filter coefficients of each sub-filter are as follows: The value of i is 1, 2, ..., k, where the processing clock of each sub-filter is... order , Let be the order of the anti-aliasing filter.

5. The system according to claim 4, characterized in that, The signal preprocessing module includes a signal sorting unit and a signal processing unit. The step of sorting and preprocessing the baseband I signal and baseband Q signal includes: The signal sorting unit divides the baseband I signal into f parallel baseband I signals and the baseband Q signal into f parallel baseband Q signals. The f parallel baseband I signals and the f parallel baseband Q signals constitute k parallel initial signals. Among the k parallel initial signals, the odd-numbered initial signals are the baseband I signals, and the even-numbered initial signals are the baseband Q signals, where f = k / 2. The signal processing unit divides the k parallel initial signals into groups of eight consecutive initial signals. The first, fourth, fifth, and eighth initial signals in each group are processed by D flip-flops, and the second, third, sixth, and seventh initial signals in each group are processed by inverting flip-flops to obtain the k parallel preprocessed signals.

6. The system according to claim 4, characterized in that, The step of performing k-fold interpolation and anti-aliasing filtering on the k parallel preprocessed signals includes: The second interpolation filtering module performs convolution operation on the i-th preprocessed signal and the filtering coefficients of its i-th sub-filter to achieve anti-aliasing filtering of the i-th preprocessed signal, where i takes the values ​​1, 2, ..., k.

7. A signal processing method, characterized in that, include: The baseband I signal and the baseband Q signal are subjected to k times interpolation and anti-aliasing filtering respectively to obtain k parallel filtered I signals and k parallel filtered Q signals. The processing clock rate of the k times interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4. The k parallel filtered I signals and the k parallel filtered Q signals are up-converted to output k intermediate frequency real signals. The step of performing k-fold interpolation and anti-aliasing filtering on the baseband I signal and baseband Q signal respectively to obtain k parallel filtered I signals and k parallel filtered Q signals includes: k parallel sub-filters, each of which has a processing clock rate equal to the sampling rate of the baseband I signal and the baseband Q signal, and each of which has filtering coefficients; The method for generating the filter coefficients of the k sub-filters includes: Based on the sampling rates of the baseband I signal and the baseband Q signal Signal width 2B, interpolation factor k, sampling rate after interpolation Generate anti-aliasing filter ,in, The coefficients of the anti-aliasing filter satisfy the sampling rate... passband frequency passband cutoff frequency The order of the anti-aliasing filter The interpolation factor k is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; The anti-aliasing filter Divide into k sub-filters of equal length, and the filter coefficients of each sub-filter are as follows: The value of i is 1, 2, ..., k, where the processing clock of each sub-filter is... order , Let be the order of the anti-aliasing filter.

8. A signal processing method, characterized in that, include: The baseband I signal and baseband Q signal are sorted and preprocessed to obtain k parallel preprocessed signals; The k parallel preprocessed signals are subjected to k-fold interpolation and anti-aliasing filtering to output k intermediate frequency real signals; wherein, the processing clock rate of the k-fold interpolation and anti-aliasing filtering is equal to the sampling rate of the baseband I signal and the baseband Q signal, and k is an integer multiple of 4; The step of sorting and preprocessing the baseband I and Q signals to obtain k parallel preprocessed signals includes: k parallel sub-filters, each of which has a processing clock rate equal to the sampling rate of the baseband I signal and the baseband Q signal, and each sub-filter has filtering coefficients; Methods for generating the filter coefficients of k sub-filters include: Based on the sampling rates of the baseband I signal and the baseband Q signal Signal width 2B, interpolation factor k, sampling rate after interpolation Generate anti-aliasing filter ,in, The coefficients of the anti-aliasing filter satisfy the sampling rate... passband frequency passband cutoff frequency The order of the anti-aliasing filter The interpolation factor k is an integer multiple of the interpolation factor k, and the window type of the anti-aliasing filter is a Hamming window; The anti-aliasing filter Divide into k sub-filters of equal length, and the filter coefficients of each sub-filter are as follows: The value of i is 1, 2, ..., k, where the processing clock of each sub-filter is... order , Let be the order of the anti-aliasing filter.

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